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SuperH™ Family E10A-USB Emulator Section 2 Software Specifications when Using the SH7265 and SH7205 Table 2.20 Measurement Item Selected Name Option Disabled None Elapsed time AC (The number of execution cycles (Iφ)). Branch instruction counts BT Number of execution instructions I Number of execution 32bit-instructions I32 Exception/interrupt counts EA Interrupt counts INT Data cache-miss counts DC Instruction cache-miss counts IC All area access counts ARN All area instruction access counts ARIN All area data access counts ARND Cacheable area access counts CDN (data access) Cacheable area instruction access counts CIN Non cacheable area data access counts NCN URAM area access counts UN URAM area instruction access counts UIN URAM area data access counts UDN Internal I/O area data access counts IODN All area access cycle ARC All area instruction access cycle ARIC All area data access cycle ARDC All area access stall ARS All area instruction access stall ARIS All area data access stall ARDS Note: Selected names are displayed for CONDITION in the [Performance Analysis] window. Options are parameters for <mode> of the PERFORMANCE_SET command. Note: In the non-realtime trace mode of the AUD trace, normal counting cannot be performed because the generation state of the stall or the execution cycle is changed. R20UT0366EJ0300 Rev. 3.00 Nov 18, 2010 Page 48 of 50
