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INTERRUPT STRUCTURE
S3C80A4/C80A8/C80A5/C80B4/C80B8/C80B5
INTERRUPT PROCESSING CONTROL POINTS
Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The
system-level control points in the interrupt structure are, therefore:
— Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 )
— Interrupt level enable/disable settings (IMR register)
— Interrupt level priority settings (IPR register)
— Interrupt source enable/disable settings in the corresponding peripheral control registers
NOTE
When writing the part of your application program that handles interrupt processing, be sure to include the
necessary register file address (register pointer) information.
EI
S
RESET
R
Q
Interrupt Request
Register (Read-only)
Polling
Cycle
IRQ0, IRQ1,
IRQ4 and IRQ6- IRQ7
Interrupts
Interrupt Priority
Register
Vector
Interrupt
Cycle
Interrupt Mask
Register
Global Interrupt Control
(EI, DI, or SYM.0
manipulation)
Figure 5-4. Interrupt Function Diagram
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