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EM8500
1.
OVERVIEW
The architecture of the EMEVB8500 is based on the following block diagram
S1
J2A
J1
LX1
User
HRV
VDD_LTS
VDD_HRV
EM8500
H3
Miscs
STS
VDD_USB
I2C pull
J6A-J6B
H2
Com
Ctrl
WAKE-UP
CONFiG
Push-button
JA4-J4B
J5A-J5B
VDD_STS
VSS
VSS_DCDC
I2C - SPI
BAT_LOW
HRV_LOW
WAKE_UP
VAUX_GND2
VAUX_GND1
VAUX_GND0
VSUP
VAUX2
VAUX1
VAUX0
J2B
J3
S2
Supercap
User
LTS
S3 STS
User
STS
UserH1STS
STS
Supply
User extension connector
User extension screw terminal block
Configuration area
Figure 1-1 EMEVB8500 System Architecture
Copyright 2015, EM Microelectronic-Marin SA
EMEBV8500-MN01, Version 1.0, 28-Sep-15
2
PRELIMINARY
www.emmicroelectronic.com
420005-A01, 2.0