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ATS962x Coprocessor FPGA Development Kit - User's Guide
v1.0.2
Book I Contents
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Book I - Introduction .................................................................................................. 7
2.1
Overview of the FPGA Development Kit........................................................... 7
2.2
Software Requirements....................................................................................... 7
2.3
Quick Start Guide ............................................................................................... 7
2.4
What is provided in the FPGA Development Kit ............................................... 7
2.5
Hardware Overview ............................................................................................ 8
2.5.1
Coprocessor FPGA (CPF) Device Information .......................................... 8
2.6
Development Framework Overview................................................................... 9
2.6.1
Coprocessor FPGA Design Framework...................................................... 9
2.6.2
Sample User Design.................................................................................... 9
2.6.3
Quartus FPGA project............................................................................... 10
2.6.4
Simulation Framework and Testbench ..................................................... 10
2.6.5
Development Environment Facilitators .................................................... 10
2.7
Pre-requisites..................................................................................................... 10
2.7.1
FPGA Design Expertise............................................................................ 11
2.7.2
Tools, Licenses and Equipment ................................................................ 11
2.7.3
Design Responsibility ............................................................................... 12
2.8
Contacting us .................................................................................................... 12
3
Quick Start Guide ..................................................................................................... 13
3.1
Installing the ATS962x Coprocessor FDK ....................................................... 13
3.2
Implementing your Design ............................................................................... 13
3.2.1
Where to insert your design ...................................................................... 13
3.3
Simulating the Design....................................................................................... 13
3.4
Compiling the Design and Producing a Downloadable File............................. 16
3.5
Downloading the FPGA to the Board............................................................... 18
3.5.1
FPGA Download using AlazarTech DSO Software................................. 18
3.5.2
FPGA Download using JTAG and Signal Tap II ..................................... 20
3.5.3
FPGA Download through software (ATS-SDK)...................................... 21
3.6
Testing the User Design on a board.................................................................. 22
3.7
Design Modification Reminders ....................................................................... 23
4
Design Description.................................................................................................... 24
4.1
Architecture....................................................................................................... 24
4.1.1
ATS9625 Waveform Digitizer Board....................................................... 24
4.1.2
Coprocessor FPGA ................................................................................... 25
4.1.3
File Folder Hierarchy................................................................................ 25
4.2
Scope of Design Provided................................................................................. 26
4.2.1
User's Responsibility................................................................................. 26
4.3
Port Description - User Interface (user_top_level.vhd).................................... 26
4.4
Datapath Functional Description ...................................................................... 28
4.4.1
Datapath/Trigger/Aux Latency Matching Considerations........................ 29
4.4.2
Trigger Pulse Requirements...................................................................... 30
4.4.3
Data Format .............................................................................................. 30
4.4.4
Out-Of-Range (OOR) ............................................................................... 30
4.5
Trigger Signals.................................................................................................. 31
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