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SIGNALS REFERENCE
Both of these signals must be software configured by programming the APIC register space to
be used either as NMI/INTR or LINT[1:0] in the BIOS. Because APIC is enabled after reset,
LINT[1:0] is the default configuration.
A.1.37. LOCK# (I/O)
The LOCK# signal is the Arbitration group bus lock signal. For a locked sequence of transactions, LOCK# is asserted from the first transaction’s Request Phase through the last transaction’s
Response Phase. A locked operation can be prematurely aborted (and LOCK# deasserted) if
AERR# or DEFER# is asserted during the first bus transaction of the sequence. The sequence
can also be prematurely aborted if a hard error (such as a hard failure response or AERR# assertion beyond the retry limit) occurs on any one of the transactions during the locked operation.
When the priority agent asserts BPRI# to arbitrate for bus ownership, it waits until it observes
LOCK# deasserted. This enables symmetric agents to retain bus ownership throughout the bus
locked operation and guarantee the atomicity of lock. If AERR# is asserted up to the retry limit
during an ongoing locked operation, the arbitration protocol ensures that the lock owner receives
the bus ownership after arbitration logic is reset. This result is accomplished by requiring the
lock owner to reactivate its arbitration request one clock ahead of other agents’ arbitration request. LOCK# is kept asserted throughout the arbitration reset sequence.
A.1.38. NMI (I)
The NMI signal is the Non-maskable Interrupt signal. It is the state of the LINT1 signal when
APIC is disabled. Asserting NMI causes an interrupt with an internally supplied vector value of
2. An external interrupt-acknowledge transaction is not generated. If NMI is asserted during the
execution of an NMI service routine, it remains pending and is recognized after the IRET is executed by the NMI service routine. At most, one assertion of NMI is held pending.
NMI is rising-edge sensitive. Recognition of NMI is guaranteed in a specific clock if it is asserted synchronously and meets the setup and hold times. If asserted asynchronously, active and inactive pulse widths must be a minimum of two clocks. In FRC mode, NMI must be synchronous
to BCLK.
A.1.39. PICCLK (I)
The PICCLK signal is the Execution Control group APIC Clock signal. It is an input clock to
the Pentium Pro processor for synchronous operation of the APIC bus. PICCLK must be synchronous to BCLK in FRC mode.
A.1.40. PICD[1:0] (I/O)
The PICD[1:0] signals are the Execution Control group APIC Data signals. They are used for
bidirectional serial message passing on the APIC bus.
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