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UM10800
Chapter 19: LPC82x Multi-Rate Timer (MRT)
Rev. 1 — 18 September 2014
User manual
19.1 How to read this chapter
The MRT is available on all LPC82x parts.
19.2 Features
• 31-bit interrupt timer
• Four channels independently counting down from individually set values
• Repeat, bus-stall, and one-shot interrupt modes
19.3 Basic configuration
Configure the MRT using the following registers:
• In the SYSAHBCLKCTRL register, set bit 10 (Table 35) to enable the clock to the
register interface.
• Clear the MRT reset using the PRESETCTRL register (Table 23).
• The global MRT interrupt is connected to interrupt #10 in the NVIC.
MRT
SYSCON
MRT_PCLK
system clock
TIMER[0:3]
SYSAHBCLKCTRL[10]
(MRT clock enable)
Fig 49. MRT clocking
19.4 Pin description
The MRT has no configurable pins.
19.5 General description
The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each
channel can be programmed with an independent time interval.
Each channel operates independently from the other channels in one of the following
modes:
• Repeat interrupt mode. See Section 19.5.1.
UM10800
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 18 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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