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UM10850
NXP Semiconductors
Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4)
14.7 Register description
Each Timer/Counter contains the registers shown in Table 242 ("Reset Value" refers to the
data stored in used bits only; it does not include reserved bits content). More detailed
descriptions follow.
Table 242. Register overview: Timer0/1/2/3 (register base addresses 0x400B 4000 (TIMER0), 0x400B 8000 (TIMER1),
0x4000 4000 (TIMER2), 0x4000 8000 (TIMER3), 0x4000 C000 (TIMER4))
Name
Access
Address
offset
Description
IR
R/W
0x00
Interrupt Register. The IR can be written to clear interrupts. The IR can 0
be read to identify which of eight possible interrupt sources are
pending.
Table 244
TCR
R/W
0x04
Timer Control Register. The TCR is used to control the Timer Counter 0
functions. The Timer Counter can be disabled or reset through the
TCR.
Table 246
TC
R/W
0x08
Timer Counter. The 32 bit TC is incremented every PR+1 cycles of
PCLK. The TC is controlled through the TCR.
0
Table 248
PR
R/W
0x0C
Prescale Register. When the Prescale Counter (PC) is equal to this
value, the next clock increments the TC and clears the PC.
0
Table 250
PC
R/W
0x10
Prescale Counter. The 32 bit PC is a counter which is incremented to
the value stored in PR. When the value in PR is reached, the TC is
incremented and the PC is cleared. The PC is observable and
controllable through the bus interface.
0
Table 252
MCR
R/W
0x14
Match Control Register. The MCR is used to control if an interrupt is
generated and if the TC is reset when a Match occurs.
0
Table 254
MR0
R/W
0x18
Match Register 0. MR0 can be enabled through the MCR to reset the 0
TC, stop both the TC and PC, and/or generate an interrupt every time
MR0 matches the TC.
Table 256
MR1
R/W
0x1C
Match Register 1. See MR0 description.
0
Table 256
MR2
R/W
0x20
Match Register 2. See MR0 description.
0
Table 256
MR3
R/W
0x24
Match Register 3. See MR0 description.
0
Table 256
CCR
R/W
0x28
Capture Control Register. The CCR controls which edges of the
0
capture inputs are used to load the Capture Registers and whether or
not an interrupt is generated when a capture takes place.
Table 258
CR0
RO
0x2C
Capture Register 0. CR0 is loaded with the value of TC when there is
an event on the CAPn.0 input.
0
Table 260
CR1
RO
0x30
Capture Register 1. See CR0 description.
0
Table 260
CR2
RO
0x34
Capture Register 2. See CR0 description.
0
Table 260
CR3
RO
0x38
Capture Register 3. See CR0 description.
0
Table 260
EMR
R/W
0x3C
External Match Register. The EMR controls the match function and the 0
external match pins.
Table 262
CTCR
R/W
0x70
Count Control Register. The CTCR selects between Timer and
0
Counter mode, and in Counter mode selects the signal and edge(s) for
counting.
Table 264
PWMC
R/W
0x74
PWM Control Register. The PWMCON enables PWM mode for the
external match pins.
Table 266
[1]
Reset
Refervalue[1] ence
0
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
UM10850
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 5 November 2014
© NXP B.V. 2014. All rights reserved.
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