Download Technical Data Sheet

MC56F8367EVM User Manual, Rev. 2
1
2
3
4
A
A
P_RESET
R23
47K
25
24
23
22
21
20
19
18
17
16
15
14
5.1K
R48
13
12
11
10
9
8
7
6
5
4
3
2
1
Q1
2N2222A
/J_RESET
R42
5.1K
+3.3V
B
PORT_CONNECT
PORT_PU
PORT_TDO
PORT_VCC
PORT_DE
/PORT_TRST
PORT_TDI
PORT_TCK
PORT_TMS
PORT_RESET
51 Ohm
R50
51 Ohm
R51
+5.0V
+3.3V
5.1K
R43
3
1
2
3
5
20
/J_TRST
/POR
/J_RESET
JG19 +Vsel
13
11
8
6
4
2
GND
2G
1G
2A4
2A3
2Y2
2Y1
1Y4
1Y3
1Y2
1Y1
PORT_PU
74AC00
R94
C
1K
DNP
R95
1K
74AC00
+Vsel
10
U7C
U7B
0 Ohm
R77
0 Ohm
R75
0 Ohm
R73
JG3
+3.3V
0 Ohm
R76
0 Ohm
R74
/CCEN
1
8
6
B
Size
Title
R46
5.1K
20
1
19
3
5
7
11
8
6
4
2
GND
2A4
2A3
2A2
2Y1
1Y4
1Y3
1Y2
1Y1
TCK
TDO
TDI
+3.3V
MC74LCX244DW
VCC
1G
2G
2Y4
2Y3
2Y2
2A1
1A4
1A3
1A2
1A1
U9
D
/DE
PWR
TDO
P_DE
14
12
10
8
6
4
2
KEY
/J_TRST
TMS
P_DE
/J_TRST
/DE
PWR
TDO
MC56F8367EVM.DSN
D
Date: Thursday, September 02, 2004
Document
Number
5.1K
R47
47K
R27
47K
R26
47K
R25
47K
R24
+3.3V
(512) 895-7215
Designer: DSCO Design
E
Sheet
11 of
14
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
1.0
Rev.
Digital Signal Controller Operation
JTAG Connector
13
11
9
7
5
3
1
J3
/J_TRST
TDI
TCK
TMS
P_RESET
/J_RESET
10
17
15
13
9
12
14
16
18
E
PARALLEL JTAG HOST TARGET INTERFACE AND JTAG CONNECTOR
/TRST
/RESET
On-Board
Host Target Interface
Disable
R45
5.1K
74AC00
9
5
4
R44
5.1K
U7D
11
3
1
74AC00
U7A
10
19
1
17
15
7
9
12
14
16
18
PORT_CONNECT
13
12
2
1
MC74HC244DW
2Y4
2Y3
VCC
2A2
2A1
1A4
1A3
1A2
1A1
U8
Parallel JTAG Interface
C
Figure A-11. Parallel JTAG Host Target Interface and JTAG Connector
P1
PORT_IDENT
B
2
1
Appendix A-12
Freescale Semiconductor
Preliminary
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