Download T-Engine SH7760 Development Kit User Manual

REJ10J0782-0100Z
R0P7760TH001TRK
User’s Manual
SH7760 T-Engine Development Kit
Rev.1.00
August 23, 2004
www.renesas.com
Cautions
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more
reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may
lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures
such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corporation product best suited to the customer's application; they do not convey any license under
any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third
party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's
rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application
examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms
represents information on products at the time of publication of these materials, and are subject to change by
Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore
recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology
Corporation product distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from
these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various means,
including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts,
programs, and algorithms, please be sure to evaluate all information as a total system before making a final
decision on the applicability of the information and products. Renesas Technology Corporation assumes no
responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact Renesas
Technology Corporation or an authorized Renesas Technology Corporation product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or
in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported
under a license from the Japanese government and cannot be imported into a country other than the approved
destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of
destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products contained
therein.
R0P7760TH001TRK User’s Manual
Precautions for Safety
Precautions for Safety
Definitions of Signal Words
In both the user’s manual and on the product itself, several icons are used to insure proper handling of this product
and also to prevent injuries to you or other persons, or damage to your properties.
This chapter describes the precautions which should be taken in order to use this product safely and properly. Be
sure to read this chapter before using this product.
This symbol represents a warning about safety. It is used to arouse caution about a
potential danger that will possibly inflict an injury on persons. To avoid a possible
injury or death, please be sure to observe the safety message that follows this
symbol.
DANGER
DANGER indicates an imminently dangerous situation that will cause death or heavy
wound unless it is avoided. However, there are no instances of such danger for the
product presented in this manual.
WARNING
WARNING indicates a potentially dangerous situation that will cause death or heavy
wound unless it is avoided.
CAUTION
CAUTION indicates a potentially dangerous situation that will cause a slight injury or
a medium-degree injury unless it is avoided.
CAUTION
CAUTION with no safety warning symbols attached indicates a potentially dangerous
situation that will cause property damage unless it is avoided.
IMPORTANT
This is used in operation procedures or explanatory descriptions to convey
exceptional conditions or cautions to the user.
In addition to the five above, the following are also used as appropriate.
means WARNING or CAUTION.
Example:
CAUTION AGAINST AN ELECTRIC SHOCK
means PROHIBITION.
Example:
DISASSEMBLY PROHIBITED
means A FORCIBLE ACTION.
Example:
UNPLUG THE POWER CABLE FROM THE RECEPTACLE.
R0P7760TH001TRK User’s Manual
Precautions for Safety
WARNING
Warnings for AC Power Supply:
l If the attached AC power cable does not fit the receptacle, do not alter the AC power cable and do not
plug it forcibly. Failure to comply may cause electric shock and/or fire.
l Use an AC power cable which complies with the safety standard of the country.
l Do not touch the plug of the AC power cable when your hands are wet. This may cause electric
shock.
l This product is connected signal ground with frame ground. If your developing product is
transformless (not having isolation transformer of AC power), this may cause electric shock. Also, this
may give an unrepairable damage to this product and your developing one.
While developing, connect AC power of the product to commercial power through isolation
transformer in order to avoid these dangers.
l If other equipment is connected to the same branch circuit, care should be taken not to overload the
circuit.
l When installing this equipment, insure that a reliable ground connection is maintained.
l If you smell a strange odor, hear an unusual sound, or see smoke coming from this product, then
disconnect power immediately by unplugging the AC power cable from the outlet.
Do not use this as it is because of the danger of electric shock and/or fire. In this case, contact your
local distributor.
l Before setting up this product and connecting it to other devices, turn off power or remove a power
cable to prevent injury or product damage.
Warnings to Be Taken for This Product:
l Do not disassemble or modify this product. Personal injury due to electric shock may occur if this
product is disassembled and modified. Disassembling and modifying the product will void your
warranty.
l Make sure nothing falls into the cooling fan on the top panel, especially liquids, metal objects, or
anything combustible.
Warning for Installation:
l Do not set this product in water or areas of high humidity. Make sure that the product does not get
wet. Spilling water or some other liquid into the product may cause unrepairable damage.
Warning for Use Environment:
l This equipment is to be used in an environment with a maximum ambient temperature of 35°C. Care
should be taken that this temperature is not exceeded.
R0P7760TH001TRK User’s Manual
Precautions for Safety
CAUTION
Note on Connecting the Power Supply:
l Do not use any power cable other than the one that is included with the product.
l The power cable included with the product has its positive and negative poles color-coded by red and
black, respectively.
l Pay attention to the polarities of the power supply. If its positive and negative poles are connected in
reverse, the internal circuit may be broken.
l Do not apply any voltages exceeding the product’s rated power supply voltage (5.0 V ±5%). Extreme
voltages may cause a burn due to abnormal heat or cause the internal circuit to break down.
Cautions to Be Taken for Handling This Product:
l Use caution when handling the main unit. Be careful not to apply a mechanical shock.
l Do not touch the connector pins of the product main unit and the target MCU connector pins directly.
Static electricity may damage the internal circuits.
l Excessive flexing or force of the flexible cable for connecting this product to the emulation probe may
break connector.
Cautions to Be Taken for System Malfunctions:
l If the product malfunctions because of interference like external noise, do the following to remedy the
trouble.
(1) Press the RESET button on the board.
(2) If normal operation is not restored after step (1), shut OFF the product once and then reactivate it.
R0P7760TH001TRK User’s Manual
Contents
Content
Precautions for Safety....................................................................................................................................... 1
User Registration.............................................................................................................................................. 8
1. Outline ......................................................................................................................................................... 9
1.1 Package Components .......................................................................................................................... 9
1.2 System Configuration ......................................................................................................................... 10
1.2.1 T-Engine Features .................................................................................................................... 10
1.2.2 T-Engine Configuration ............................................................................................................. 10
1.3 T-Engine Appearance......................................................................................................................... 12
1.4 T-Engine Specifications ...................................................................................................................... 16
2. Installation.................................................................................................................................................. 18
2.1 Host System Connection .................................................................................................................... 18
2.2 AC Adapter Connection ...................................................................................................................... 19
2.3 Turning ON or OFF the T-Engine Board .............................................................................................. 20
2.4 Using the Debug Board ...................................................................................................................... 20
2.4.1 Debug Board Function .............................................................................................................. 20
2.4.2 Debug Board Connection .......................................................................................................... 21
2.4.3 Debug Board Jumper Switches .................................................................................................. 22
2.4.4 8-bit LEDs on the Debug Board ............................................................................................... 22
2.4.5 16-bit SWs on the Debug Board .............................................................................................. 22
2.4.6 H-UDI Debugger Connection ..................................................................................................... 23
3. Switches .................................................................................................................................................... 24
3.1 CPU Board Switches .......................................................................................................................... 24
3.2 LCD Board Switch.............................................................................................................................. 26
4. Memory Map .............................................................................................................................................. 27
4.1 Memory Map for the T-Engine Board................................................................................................... 27
4.2 Memory Map during Debug Board Connection ..................................................................................... 28
5. Functional Blocks........................................................................................................................................ 30
5.1 PCMCIA ............................................................................................................................................ 30
5.1.1 Block Description ...................................................................................................................... 30
5.1.2 Connector Pins ......................................................................................................................... 31
5.1.3 Register Map............................................................................................................................ 33
5.2 USB Host .......................................................................................................................................... 34
5.2.1 Block Description ...................................................................................................................... 34
5.2.2 Connector Pins ......................................................................................................................... 35
5.2.3 Register Map............................................................................................................................ 35
5.3 UART................................................................................................................................................ 36
5.3.1 Block Description ...................................................................................................................... 36
5.3.2 Connector Pins ......................................................................................................................... 37
5.3.3 Register Map............................................................................................................................ 38
5.4 LCD .................................................................................................................................................. 39
5.4.1 Block Description ...................................................................................................................... 39
5.4.2 Connector Pins ......................................................................................................................... 40
5.4.3 Register Map............................................................................................................................ 41
5.5 Sound Generator ............................................................................................................................... 42
5.5.1 Block Description ...................................................................................................................... 42
5.5.2 Connector Pins ......................................................................................................................... 43
5.5.3 Register Map............................................................................................................................ 44
5.6 eTRON Interface................................................................................................................................ 45
5.6.1 Block Description ...................................................................................................................... 45
5.6.2 Connector Pins ......................................................................................................................... 46
5.6.3 Register Map............................................................................................................................ 47
5.7 I/O Board.................................................................................................................................................. 48
5.7.1 Block Description ...................................................................................................................... 48
5.7.2 Connector (Through-Hole) Pin Assignments ............................................................................... 49
R0P7760TH001TRK User’s Manual
Contents
6. Power Supply Controller.............................................................................................................................. 51
6.1. Power Supply Controller Functions ..................................................................................................... 51
6.2 Serial Communications between SH7760 and the Power Supply Controller ........................................... 52
6.2.1 Serial Format ............................................................................................................................ 52
6.2.2 Power Supply Control Register Read Procedure......................................................................... 52
6.2.3 Read Command........................................................................................................................ 53
6.2.4 Normal Response during a Read Operation................................................................................ 54
6.2.5 Error Response during a read Operation .................................................................................... 54
6.2.6 Power Supply Control Register Write Procedure ......................................................................... 55
6.2.7 Write Command........................................................................................................................ 55
6.2.8 Normal Response during a Write Operation ................................................................................ 56
6.2.9 Error Response during a Write Operation ................................................................................... 57
6.3 RTC (Real-time Clock) Functions ........................................................................................................ 58
6.3.1 RTC Control Register (RTCCR) ................................................................................................. 59
6.3.2 RTC Status Register (RTCSR)................................................................................................... 60
6.3.3 Second Counter (SECCNT) ....................................................................................................... 61
6.3.4 Minute Counter (MINCNT) ......................................................................................................... 61
6.3.5 Hour Counter (HRCNT) ............................................................................................................. 61
6.3.6 Day -of-the-Week Counter (WKCNT) .......................................................................................... 62
6.3.7 Day Counter (DAYCNT) ............................................................................................................ 62
6.3.8 Month Counter (MONCNT) ........................................................................................................ 62
6.3.9 Year Counter (YRCNT) ............................................................................................................. 63
6.3.10 Alarm Register..................................................................................................................... 63
6.3.11 Second Alarm Register (SECAR).......................................................................................... 63
6.3.12 Minute Alarm Register (MINAR)............................................................................................ 63
6.3.13 Hour Alarm Register (HRAR) ................................................................................................ 64
6.3.14 Day-of-the-Week Alarm Register (WKAR) ............................................................................. 64
6.3.15 Day Alarm Register (DAYAR) ............................................................................................... 65
6.3.16 Month Alarm Register (MONAR) ........................................................................................... 65
6.3.17 RTC/Touch Panel/Key Input/Power Supply Status Register (RTKISR)..................................... 65
6.4 Touch Panel Functions ....................................................................................................................... 66
6.4.1 Touch Panel Control Register (TPLCR)...................................................................................... 68
6.4.2 Touch Panel Status Register (TPLSR) ....................................................................................... 69
6.4.3 Touch panel Sampling Control Register (TPLSCR) ..................................................................... 70
6.4.4 X Position A/D Register (XPAR)................................................................................................. 70
6.4.5 Y Position A/D Register (YPAR)................................................................................................. 71
6.4.6 X Position Dot Register (XPDR)................................................................................................. 71
6.4.7 Y Position Dot Register (YPDR)................................................................................................. 71
6.4.8 XA Position Dot Register (XAPDR) ............................................................................................ 72
6.4.9 YA Position Dot Register (YAPDR) ............................................................................................ 72
6.4.10 XB Position Dot Register (XBPDR)........................................................................................... 72
6.4.11 YB Position Dot Register (YBPDR)........................................................................................... 73
6.4.12 XC Position Dot Register (XCPDR) .......................................................................................... 73
6.4.13 YC Position Dot Register (YCPDR) .......................................................................................... 73
6.4.14 XA Position A/D Register (XAPAR) .......................................................................................... 74
6.4.15 YA Position A/D Register (YAPAR) .......................................................................................... 74
6.4.16 XB Position A/D Register (XBPAR) .......................................................................................... 74
6.4.17 YB Position A/D Register (YBPAR) .......................................................................................... 75
6.4.18 XC Position A/D Register (XCPAR) .......................................................................................... 75
6.4.19 YC Position A/D Register (YCPAR) .......................................................................................... 75
6.4.20 DX Dot Register (DXDR) ......................................................................................................... 76
6.4.21 DY Dot Register (DYDR) ......................................................................................................... 76
6.4.22 X Position Dot Calculation A/D Value (XPARDOT) .................................................................. 77
6.4.23 X Position Dot Calculation A/D Value 1 (XPARDOT1)................................................................ 77
6.4.24 X Position Dot Calculation A/D Value 2 (XPARDOT2)................................................................ 77
6.4.25 X Position Dot Calculation A/D Value 3 (XPARDOT3)................................................................ 78
6.4.26 X Position Dot Calculation A/D value 4 (XPARDOT4) ................................................................ 78
R0P7760TH001TRK User’s Manual
Contents
6.4.27 Y Position Dot Calculation A/D Value (YPARDOT) .................................................................... 79
6.4.28 Y Position Dot Calculation A/D Value 1 (YPARDOT1) ............................................................ 79
6.4.29 Y Position Dot Calculation A/D Value 2 (YPARDOT2) ............................................................ 79
6.4.30 Y Position Dot Calculation A/D Value 3 (YPARDOT3)................................................................ 80
6.4.31 Y Position Dot Calculation A/D Value 4 (YPARDOT4)................................................................ 80
6.4.32 RTC/Touch Panel/Key Input/Power Supply Status Register (RTKISR) ........................................ 80
6.4.33 Touch Panel Calibration Method (2-point System)..................................................................... 81
6.5 Key Switch Control ............................................................................................................................. 83
6.5.1 CPU Board Switch Control ........................................................................................................ 84
6.5.2 LCD Board Switch Control (Application Switch)........................................................................... 84
6.5.3 Key Switch Registers ................................................................................................................ 84
6.5.4 Key Control Register (KEYCR) .................................................................................................. 85
6.5.5 Key Auto Repeat Time Register (KATIMER)............................................................................... 86
6.5.6 Key Bit Pattern Register (KBIPR) ............................................................................................... 86
6.5.7 Key Input Status Register (KEYSR)............................................................................................ 87
6.5.8 RTC/Touch Panel/Key Input/Power Supply Status Register (RTKISR).......................................... 89
6.6 Power Supply Control ......................................................................................................................... 89
6.6.1 System Power Control Register 1 (SPOWCR1) .......................................................................... 90
6.6.2 System Power Control Register 2 (SPOWCR2) .......................................................................... 90
6.6.3 RTC/Touch Panel/Key Input/Power Supply Status Register (RTKISR).......................................... 90
6.7 LCD Front Light Control ...................................................................................................................... 91
6.7.1 LCD Front Light Register (LCDR)............................................................................................... 91
6.8 Reset Control..................................................................................................................................... 92
6.8.1 RESTCR Register (RESTCR) .................................................................................................... 92
6.9 Infrared Remote Control ..................................................................................................................... 93
6.9.1 Infrared Remote Control Register (IRRCR)................................................................................. 94
6.9.2 Infrared Remote Control Status Register (IRRSR) ....................................................................... 95
6.9.3 Receive Data Count Register for Infrared Remote Control Signals (IRRRDNR)............................. 95
6.9.4 Transmit Data Count Register for Infrared Remote Control Signals (IRRSDNR)............................ 96
6.9.5 Receive FIFO Data Register for Infrared Remote Control Signals (IRRRFDR) .............................. 96
6.9.6 Transmit FIFO Data Register for Infrared Remote Control Signals (IRRSFDR).............................. 96
6.9.7 RTC/Touch Panel/Key Input/Power Supply Status Register (RTKISR).......................................... 97
6.9.8 Infrared Remote Control Data Structure...................................................................................... 97
6.10 Serial EEPROM Control.................................................................................................................... 99
6.10.1 EEPROM Control Register (EEPCR) ........................................................................................ 99
6.10.2 EEPROM Data Register (EEPDR)............................................................................................ 99
6.10.3 Serial EEPROM Operation Procedure .....................................................................................100
6.11 Electronic Volume Control................................................................................................................101
6.11.1 Electronic Volume Data Register for the Right Speaker (EVRDR) ..........................................101
6.11.2 Electronic Volume Data Register for the Left Speaker (EVLDR).............................................101
6.12 Power Supply Controller Initial Values ..............................................................................................102
7. External Interrupts .....................................................................................................................................105
7.1 SH7760 External Interrupts................................................................................................................105
8. T-Engine Extension Slot .............................................................................................................................106
8.1 Extension Slot Specifications .............................................................................................................106
8.2 Extension Slot Signal Assignment ......................................................................................................107
9. Daughter Board Design Guide....................................................................................................................108
9.1 Daughter Board Dimensions ..............................................................................................................108
9.2 Daughter Board Power Supply ...........................................................................................................108
9.3 Daughter Board Stack .......................................................................................................................109
9.4 Daughter Board WAIT# Output ..........................................................................................................109
9.5 Extension Slot AC Timing ..................................................................................................................110
10. Flash Memory Refresh .............................................................................................................................112
10.1 Preparation for Flash Memory Refresh .............................................................................................112
10.2 T-Engine Flash Memory ...................................................................................................................113
10.2.1 Refresh Method .....................................................................................................................113
10.3 Power Supply Controller’s Internal Flash Memory ..............................................................................115
R0P7760TH001TRK User’s Manual
Contents
10.3.1 Refresh Method .....................................................................................................................115
10.3.2 Refresh Check.......................................................................................................................118
11. Attached Documents................................................................................................................................119
11.1 T-Engine Board Parts List................................................................................................................119
11.1.1 CPU Board Parts list ..............................................................................................................119
11.1.2 LCD Board Parts List..............................................................................................................122
11.1.3 Debug Board Parts List ..........................................................................................................123
11.1.4 I/O Board Parts List .............................................................................................................123
11.2 T-Engine FPGA Logic......................................................................................................................124
11.2.1 CPU Board (U11) FPGA Logic ................................................................................................124
11.3 T-Engine Board Circuit Diagrams .....................................................................................................143
11.3.1 CPU Board Circuit Diagrams (MS7760CP01/1) ........................................................................143
11.3.2 LCD Board Circuit Diagrams (MS7760LCD01/4) ......................................................................143
11.3.3 Debug Board Circuit Diagrams (MS7760DBG01/3) ..................................................................143
11.3.4 I/O Board Circuit Diagrams .....................................................................................................143
11.4 T-Engine Board Dimensions.............................................................................................................143
11.4.1 CPU Board (MS7760CP01/3) Dimensions ...............................................................................143
11.4.2 LCD Board (MS7760LCD01/4) Dimensions .............................................................................143
11.4.3 Debug Board (MS7760DBG01/3) Dimensions ..........................................................................143
R0P7760TH001TRK User’s Manual
User Registration
User Registration
When you have purchased the product presented in this manual, please register your name and address. Your
registered information is used for only after-sale services, and not for any other purposes. Without user registration,
you will not be able to receive maintenance services such as a notification of field changes or trouble information.
So be sure to register your name and address.
To get reference information about user registration, please visit the Web site shown below.
[Renesas Tools Homepage]
http://www.renesas.com/en/tools/
[Inquiries]
[email protected]
R0P7760TH001TRK User’s Manual
Outline
1. Outline
This chapter describes the package components, the system configuration and the preparation for using this
product for the first time.
1.1 Package Components
The R0P7760TH001TRK package consists of the following items. When unpacking it, check to see if your
R0P7760TH001TRK contains all of these items.
Table 1.1 Package components
Item
T-Engine Board
ACadapter
RS-232C cable
CD-ROM
- T-Engine Board User’s Manual (This Manual)
- T-Kernel and other software and various documentation
(Personal Media Corporation)
Quantity
1
1
1
1
* Please keep the R0P7760TH001TRK’s packing box and cushion material in your place for reuse at a
later time when sending your product for repair or other purposes. Always use these packing box
and cushion material when transporting this product.
* If there is any question or doubt about the packaged product, contact your local distributor.
R0P7760TH001TRK User’s Manual
Outline
1.2 System Configuration
1.2.1 T-Engine Features
The following summarizes the main features of T-Engine.
(1) The manual covers all information about T-Engine, including the circuit diagrams, connector specifications,
and internal logic of FPGA employed on this board.
(2) The peripheral LSI chips (PCMCIA controller and sound generator chips) are commercially available.
(3) This board contains the PCMCIA controller, sound generator chip, SIM card connector, etc., so that
application systems can be developed taking advantage of them.
(4) This board contains two SH7760 buses (address bus and data bus) and one extension slot subject to control
signal output so that users can connect user-specific hardware.
1.2.2 T-Engine Configuration
Figure 1.1 shows a T-Engine Board system configuration and Figure 1.2 shows a T-Engine block diagram.
Users must prepare any user-specific devices as needed, in addition to preparing the T-Engine and its
accessories.
ATA card, etc.
RS-232C cable (accessory)
Host system
SIM card
Head
phones
USB mouse, etc.
USB
Host
Earphones
T-Engine Board
AC adapter (accessory)
Figure 1.1 System configuration
R0P7760TH001TRK User’s Manual
Outline
LCD Board interface
SIM Card HP HP/MIC LCD1
LCD2
Serial
AC adapter
5.6V
Supply voltage
generation
Sound generator
Chip UDA1342TS
RTC
H8/3048B
SROM
Power supply
control
SIM
IIS
IIC LCDC
CPU
SH7760
5V 3.3V 1.5V
UART(2Ch)
USBH CPG INTC BSC
8bit
CLK
SH Local Bus
16bit
Adress
decoder
USB
Flash
Memory
32bit
SDRAM
16bit
PCMCIA
Bus
Buffer
PC Card
Extension bus interface
Figure 1.2 T-Engine Block Diagram
R0P7760TH001TRK User’s Manual
Outline
1.3 T-Engine Appearance
T-Engine Board consists of four boards: CPU, LCD, debug, and I/O boards. Figure 1.3 is an external view of
the T-Engine. Figures 1.4 to 1.7 show the appearances of the respective boards (LCD, CPU, debug, and I/O
boards).
LCD Board
CPU Board
I/O Board
Debug Board
Figure 1.3 T-Engine - External View
R0P7760TH001TRK User’s Manual
Outline
LCD interface connector1
LCD interface connector2
Contrast control volume
LCD interface connector3
CPU board interface connector2
CN 2
CN4
CN3
CPU board interface connector1
CN1
CN5
Rear view
LCD
Infrared remote control reception
SW3
Push-button switch3
SW1
Cursor switch1
SW2
Push-button switch2
Front view
Figure 1.4 LCD Board - External View
R0P7760TH001TRK User’s Manual
Outline
System reset switch
H8/3048-ONE write connector
Infrared remote control transmission LED
SW4
Extension slot
CN15
SH 7760
CN1
CN1
SW 5
LED3
8-bit DIP switch
CN4
Serial interface connector
CN16
CN17
I/O board interface connector1
SIM card connector
I/O board interface connector2
Rear view
Earphones/microphones connection connector
Headphones connection connector
PC Card slot
CN3
CN10
CN5
CN9
CN6
LCD board interface connector1
Power-on switch
Reset switch
SW3
SW2
SW1
LCD board interface connector2
Front view
NMI switch
Note: The “CN15” connector is used to test the board prior to shipping
from the factory. NO connection must be made to this connector.
Figure 1.5 CPU Board - External View
AC adapter connection connector
USB HOST interface connector
R0P7760TH001TRK User’s Manual
Outline
Extension slot
8-bit LED
16-bit SW
EPROM
CN1
TP3
TP2
TP1
J1
EPROM connection jumper switch
H-UDI connector
CN2
Figure 1.6 Debug Board - External View
CN1
CN8
CN6
CN9
CN7
CN4
CN10
CN5
CN3
CN11
CN2
Figure 1.7 I/O Board - External View
R0P7760TH001TRK User’s Manual
Outline
1.4 T-Engine Specifications
Table 1-1 summarizes the T-Engine function specifications and Table 1-2 the power supply, dimensions,
and environmental specifications.
Table 1-1 T-Engine Function Specifications
Item
CPU
Flash memory
SDRAM
PC Card I/F
Serial I/F
Sound
USB Host
Specifications
SH7760
Model name: HD6417760BP200D
(RENESAS Technology)
Input clock: 16.6667MHz
Operating clock (Internal): 200MHz (x 12)
(External): 66MHz (x 4)
Package: 256-pin BGA
Capacity: 8MB
MBM29DL640E90TN (Fujitsu) x 1
Capacity: 64MB
EDS2516APTA-75 (ELPIDA) x 2
One slot
Controller: MR-SHPC-01 V2T (Marubun)
Package: 144pin TQFP
2ch
Controller: ST16C2550CQ48 (EXAR)
Package: 48pin TQFP
Model name: UDA1342TS (Philips)
Package: 28pin SSOP
Earphone/microphone: 1ch
Headphone output: 1ch
- Microphone input
Impedance: 2.2KΩ
Sensitivity: -51dB/Pa
- Headphone output
Impedance: 32Ω
NL2432DR22-02B (NEC)
Display color: 262,144 colors
Display area: 240(H) x 320(V)
Controller:SH7760 on-chip LCDC
Power supply controller
H8/3048F-ONE
Model name: HD64F3048BVTE25
(Renesas Technology)
Operating frequency: 7.3728MHz
Package: 100-pin TQFP
Model name: RV5C348B (RICOH)
Package: 10pin SSOP-G
Touch panel I/F
Model name: ADS7843 (TI)
Package: 16pin SSOP
Serial EEPROM
Capacity: 512 bytes
Model name: S-29391AFJA (SII)
Transmission
Model name: GL100MN0MP (SHARP)
Transmission carrier: 38KHz
Reception
Model name: GP1UC101 (SHARP)
Transmission carrier: 38KHz
Infrared remote control
ChA: H8/3048F-ONE I/F
ChB: Monitor for debugging
The SH7760 on-chip SSI is used
to transmit data.
The SH7760 on-chip IIC is used
to select the mode.
1ch
Controller: SH7760 on-chip USB Host
TFT color LCD module
RTC
Target device
The control SH7760 working
for power supply control, RTC,
or tablet interface infrared
remote control must be
interfaced via the serial chA.
Via the H8/3048F-ONE
Via the H8/3048F-ONE
(To be mounted on the LCD
board)
Via the H8/3048F-ONE
Via theH8/3048F-ONE
R0P7760TH001TRK User’s Manual
Outline
Table 1.2 Power supply, Dimensions, and Envi ronmental Specifications of the T-Engine Board
Item
Environment
Operating voltage
Dissipation current
Dimensions
Specifications
Operating conditions
- Temperature: 10-35ºC
- Humidity: 30 to 85% RH
(no dew condensation occurs)
Ambient gas: no corrosive gas
DC 5.6VDC
600mA
CPU board: 120mm x 75mm
LCD board: 120mm x 75mm
Debug board: 101mm x 75mm
I/O board: 101mm x 75mm
Table 1.3 Permissible Current Supplied Externally by T-Engine Supply Voltage
Supply voltage
5V
3.3V
l
l
l
Permissible current
250mA
250mA
Locations subject to current supply
• PCMCIA card power supply
• USB bus power
• Extension slot
• PCMCIA card power supply
• Extension slot
CAUTION
Table 1.2 shows the maximum dissipation current of T-Engine (comprising only the CPU board,
LCD board, debug board, and I/O board) without external devices.
Table 1.3 shows the sum of permissible current in all the powered devices on T-Engine.
Accordingly, when a current of 100mA is used for the PCMCIA card supply voltage (5V), the
currents of the USB bus power or extension slot is 150mA (250mA to 100mA). This is true for the
supply voltage 3.3V.
When the PCMCIA card, etc. is powered from the internal power supply of T-Engine, the current
must not exceed the permissible current of each power supply shown in Table 1.3. Otherwise,
there is a risk of electric shock, heat, or fire.
R0P7760TH001TRK User’s Manual
Installation
2. Installation
2.1 Host System Connection
To use T-monitor, connect the serial interface connector (CN1) of the T-Engine board with an RS-232C
interface cable (accessory).
Figure 2.1 shows the host system connection method. Figure 2.2 shows the
pins of the serial interface connector. Table 2.1 shows the signals of the serial interface connector.
RS-232C interface
cross cable (accessory)
Host system
Serial interface connector
(CN1)
T-Engine Board
Figure 2.1 Host System Connection
1
CN1
15
Figure 2.2 Serial Interface Connector Pins
R0P7760TH001TRK User’s Manual
Installation
Table 2.1 Serial Interface Connector Signals
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal name
GND
TxD
RxD
GND
RTS
CTS
GND
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I/O
Output
I
O
I
-
Remarks
TXB(UART)
RXB(UART)
RTSB(UART)
CTSB(UART)
ISP TCK(*)
GND(*)
ISP TMS(*)
ISP Plug(*)
ISP BScan(*)
ISP TDI(*)
ISP TDO(*)
Vcc(3.3V) (*)
*: These pins are used only to test the board when it is shipped from the factory.
Don’t use these pins for any other purpose.
2.2 AC Adapter Connection
Figure 2.3 shows an AC adapter connection method. As shown in Figure 2.3, connect the plug to the AC
adapter connector of the T-Engine board (1), then connect the adapter cord to the receptacle (2).
T-Engine Board
AC 110V
(2) Connect the adapter cord
to the receptacle.
AC adapter
AC adapter connection
(1) Connect the plug. connector (CN14)
Figure 2.3 AC Adapter Connection Cord
R0P7760TH001TRK User’s Manual
Installation
CAUTION
l
Don’t put heavy things on the AC adapter cord. To avoid the risk of electric leakage, fire, or
electric shock, don’t damage or modify the AC adapter cord.
To avoid the risk of electric shock, don’t unplug the AC adapter cord with wet hands. To avoid the
risk of cord damage, electric shock, or fire, don’t pull on the AC adapter cord; rather, grasp and pull
the plug to disconnect the AC adapter cord.
When connecting the AC adapter to the receptacle, check the polarity and connection beforehand
to avoid the risk of electric shock, fire, or fault.
l
l
2.3 Turning ON or OFF the T-Engine Board
To turn the T-Engine board ON or OFF, press the power-on switch (SW1) on the CPU board. To turn
ON the T-Engine board, press and hold the switch for 0.5 seconds or more. To turn it OFF, press and
hold this switch for 2 seconds or more while the T-Engine board is powered.
2.4 Using the Debug Board
2.4.1 Debug Board Function
When the debug board has been connected to the T-Engine, the following functions can be implemented:
(1) Run the program stored in the EPROM on the debug board to refresh the flash memory on the T-Engine
board.
The H8/3048F-One firmware can be refreshed. For details on flash memory refresh, refer to 10.
“Flash Memory Refresh.”
(2) The 8-bit LEDs on the debug board can be turned on or off from the SH7760. The software execution
state can be monitored by controlling the ON/OFF state of these LEDs.
(3) The 16-bit SWs on the debug board can be read from the SH7760. Various operating conditions can be
controlled through these SWs.
(4) The H-UDI debugger (to be connected to the H-UDI and AUD pins of the SH7760) can be used.
R0P7760TH001TRK User’s Manual
Installation
2.4.2 Debug Board Connection
Figure 2.4 shows a debug board connection method. Connect the debug board to the extension slot (CN2)
on the T-Engine board.
T-Engine Board
Extension slot (CN2)
Connection
Extension slot (CN1)
Figure 2.4 Debug Board Connection
CAUTION
Turn off the T-Engine before connecting the debug board or detaching the EPROM.
reattaching the EPROM, check the connecting direction as shown in Figure 2.5.
EPROM
EPROM
CN1
CN1
TP3
TP2
TP1
TP3
TP2
TP1
J1
J1
CN2
CN2
Figure 2.5 EPROM Connection
When
R0P7760TH001TRK User’s Manual
Installation
2.4.3 Debug Board Jumper Switches
Table 2.2 describes a method for setting the EPROM selection jumper switch (J1) on the debugger board.
For details of a memory map during debug board connection, refer to 4. “Memory Map.”
Table 2.2 Setting the EPROM Selection Jumper Switch (J1)
Jumper
switch
Setting
Description
J1
1
2
Pins 1 and 2 must be open
1
2
Pins 1 and 2 must be
short-circuited.
2.4.4
Debug board resources are assigned to area 0 on the SH7760 board as shown
below. (Factory setting)
- The flash memory on the T-Engine board is assigned to an address range
from h’00000000 to h’007FFFFF.
- The EPROM mounted on the debug board is assigned to an address range
from h’01000000 to h’011FFFFF.
- The 8-bit LEDs mounted on the debug board are assigned to an address
range from h’014000000 to h’017FFFFF.
- The 16-bit SWs mounted on the debug board are assigned to an address
range from h’01800000 to h’01BFFFFF.
Debug board resources are assigned to area 0 on the SH7760 board as shown
below.
- The EPROM mounted on the debug board is assigned to an address range
from h’00000000 to h’001FFFFF.
- The 8-bit LEDs mounted on the debug board are assigned to an address
range from h’00400000 to h’007FFFFF.
- The 16-bit SWs mounted on the debug board are assigned to an address
range from h’00800000 to h’00BFFFFF.
- The flash memory on the T-Engine board is assigned to an address range
from h’01000000 to h’017FFFFF.
8-bit LEDs on the Debug Board
The low-order 8 bits (D7 to D0) of the SH7760 data bus are connected to the 8-bit LEDs placed on the debug
board. The 8-bit LEDs can be turned on or off by writing data to an area assigned for the LEDs through D7 to
D0. When a value of 1 is written to a bit, the corresponding LED is turned off. When a value of 0 is written
to the bit, it is turned on.
2.4.5
16-bit SWs on the Debug Board
The 16 bits (D15 to D0) of the SH7760 are connected to the 16-bit SWs placed on the debug board. The 16bit SWs can be turned on or off by reading data from an area assigned for the SWs through D15 to D0.
When a value of 1 is read from a bit, the corresponding SW is turned off. When a value of 0 is read from the
bit, the corresponding SW is turned on.
R0P7760TH001TRK User’s Manual
Installation
2.4.6 H-UDI Debugger Connection
The debug board allows the H-UDI debugger to be connected to the pin 36 (CN2) of the H-UDI (Hitachi-User
Debug Interface) connector. Connect the H-UDI and AUD pins of the SH7760 board to the H-UDI connector.
Figure 2. 6 shows a method for connecting the H-UDI debugger. Connect an H-UDI debugger cable to the
H-UDI connector (CN2) of the debug board. Note that the following H-UDI debugger can be connected to
T-Engine. For details on the H-UDI debugger connection/setup procedure, refer to the pertinent manual of
the product.
- Renesas Technology Corporation
E10A-USB Emulator
Model name: HS0005KCU02H (AUD)
- Hitachi ULSI Systems Co., Ltd.
MY-ICE EZ emulator
T-Engine Board
CN2
Maker: Hirose Electric
Model name: DX10M-36SE
(36 pins)
CN2
Connection
J1
H-UDI debugger
Host system
Debug board
Figure 2.6 H-UDI Debugger Connection
CAUTION
T-Engine permits the connection of only the H-UDI debugger that uses the AUD and H-UDI pins of the SH7760
board.
R0P7760TH001TRK User’s Manual
Switches
3. Switches
3.1 CPU Board Switches
Figure 3.1 shows the location of the switches (SW1 to SW5) on the CPU board. In addition, this section
gives a brief description of each switch in (1) to (5).
LED3
SW4
System reset switch
CN15
CN 1
CN4
SH 7760
CN1
SW5
8-bit DIP switch
CN16
CN17
Rear view
CN3
CN10
SW3
SW2
SW1
CN6
CN5
CN9
Power-on switch
Reset switch
Front view
NMI switch
Figure 3.1 CPU Board Switches (SW1 to SW5)
(1)
Power on Switch (SW1)
This switch turns on or off T-Engine. To turn on T-Engine, press and hold down this switch for 0.5
seconds or more. To turn it off, press and hold down this switch for 2 seconds or more when T-Engine
is being powered.
(2)
Reset Switch (SW2)
This switch resets T-Engine. To reset devices other than the H8/3048-ONE, press this switch. To
reset and restart T-Engine, release this switch.
In this case, the values of H8/3048-ONE internal
registers are not initialized. Among the control registers, the values of those that can be accessed by
SH7760 are initialized but the others are not (i.e., their values are retained). For more details, refer to
6.13 “Initial Values of the Power Supply Controller Register.”
R0P7760TH001TRK User’s Manual
(3)
Switches
NMI Switch (SW3)
This switch controls the SH7760 NMI pin. Press this switch and the SH7760 NMI pin will go “Low.”
Release this switch, and the NMI pin will go “High.”
(4)
8-bit DIP Switch (SW5)
Figure 3.2 shows the setting of an 8-bit DIP switch. This DIP switch is connected to pins ID0 to ID5
and to MD5 of the SH7760. Be sure to turn off the power-on switch before setting the DIP switch.
(a) Switches SW5-1 to SW5-6 are connected to pins ID0 to ID5 (input pins).
ON: The input pin goes “Low.”
OFF: The input pin goes “High.” (Factory setting)
(b) The SW5-7 switch is used to set the power-on condition of T-Engine.
ON: T-Engine is powered when power supply takes place through the AC adapter.
OFF: T-Engine is powered when the power-on switch is pressed. (Factory setting)
(c) The SW5-8 switch is connected to SH7760's pin MD5. The SW5-8 switch is used to set the type of
endian for SH7760 operation.
ON: The MD5 pin goes “Low” to set the big endian for SH7760 operation.
OFF: The MD5 pin goes “High” to set the little endian for SH7760 operation. (Factory setting)
ON
1
2
3
4
5
6
7
8
SW5-n
SW5-n
[OFF setting] [ON setting]
SW5-8
SW5-1
Figure 3.2 Setting the 8-bit DIP Switch
(5)
System Reset Switch (SW4)
This switch resets the T-Engine hardware.
All T-Engine devices are reset so long as this switch is
pressed and held down. When this switch is released, T-Engine is turned off. When the power-on
switch is pressed,
T-Engine is turned on and started. In addition, if this switch is released while SW5-7 is ON, T-Engine
is also turned on.
R0P7760TH001TRK User’s Manual
Switches
3.2 LCD Board Switch
The states of the cursor switch (SW1) and push-button switches (SW2 and SW3) are signaled to the SH7760
through the power supply controller. For details, refer to 6. “Power Supply Controller.”
R0P7760TH001TRK User’s Manual
Memory Map
4. Memory Map
4.1 Memory Map for the T-Engine Board
Table 4.1 shows an SH7760 memory map for the T-Engine board without expansion board.
Table 4.1 SH7760 Memory Map for T-Engine without Expansion Board
Area No.
Area 0
Bus width
16 bits
Area 1
16 bits
Area 2
8/16/32 bits
Area 3
Area 4
Area 5
Area 6
Area 7
32 bits
8/16/32 bits
8/16/32 bits
16 bits
-
Space
h’00000000
~
h’00FFFFFF
h’00100000
~
h’03FFFFFF
h’04000000
~
h’07FFFFFF
h’08000000
~
h’0BFFFFFF
h’0C000000
~
h’0FFFFFFF
h’10000000
~
h’13FFFFFF
h’14000000
~
h’17FFFFFF
Space name
Flash memory area
-
Device
Remarks
8MB
MBM29DL640E-90TN (Fujitsu) x 1
Unused area
Board control register 16B
area
Board control register
Extension area (CS2)
64MB
Extension slot (CS2 area)
SDRAM area
64MB
EDS2516APTA-75 (ELPIDA) x 2
Extension area (CS4)
64MB
Extension slot (CS4 area)
Extension slot
CS4# asserted
Extension area (CS5)
64MB
Extension slot (CS5 area)
Extension slot
CS5# asserted
h’18000000
~
h’19FFFFFF
PCMCIA area
Card controller
Model
name:
MR-SHPC-01
V2T
(Marubun)
This device is simply called SH-PCIC.
h’1A000000
~
h’1A7FFFFF
UART area (ChA)
h’1A800000
~
h’1AFFFFFF
UART area (ChB)
h’1B000000
~
h’1BFFFFFF
h’1C000000
~
h’1FFFFFFF
ID register area
-
Extension slot
CS2# asserted
This device is
UART
used for interface
Model name: ST16C2550CQ48 (EXAR)
with H8/3048FThis device is simply called UART.
ONE.
This device is
used as an
Same as above
interface with the
host.
-
The DIP switch
settings are read.
-
Reserved
R0P7760TH001TRK User’s Manual
Memory Map
4.2 Memory Map during Debug Board Connection
Table 4.2 shows a memory map for the SH7760 when the debug board is connected to the T-Engine board
and the jumper switch (J1) on the debug board is open. Table 4.3 also shows a memory map for the SH7760
when the debug board is connected to the T-Engine board and the jumper switch (J1) on the debug board is
short-circuited.
Table 4.2 Memory Map during Debug Board Connection (J1: Open)
Area No.
Bus width
Area 0
16 bits
Area 1
16 bits
Area 2
8/16/32 bits
Area 3
32 bits
Area 4
8/16/32 bits
Area 5
8/16/32 bits
Area 6
16 bits
Area 7
-
Space
h’00000000
~
h’00FFFFFF
h’01000000
~
h’013FFFFF
h’01400000
~
h’017FFFFF
h’01800000
~
h’01BFFFFF
h’01C00000
~
h’01FFFFFF
h’02000000
~
h’03FFFFFF
h’04000000
~
h’07FFFFFF
Space name
Device
Flash memory area
8MB
MBM29DL640E-90TN (Fujitsu) x 1
EPROM area
256kB
M27C800-100F1 (STMicro) x 1
Debug LED area
1B
8-bit debug LED
2B
8-bit switch x 2
Remarks
Resources on the
debug board
Switch area
Unused area
-
Unused area
Board control
register area
16B
Board control register
Extension area
(CS2)
64MB
Extension slot (CS2 area)
SDRAM area
64MB
EDS2516APTA-75 (ELPIDA) x 2
Extension area
(CS4)
64MB
Extension slot (CS4 area)
Extension slot
CS4# asserted
Extension area
(CS5)
64MB
Extension slot (CS5 area)
Extension slot
CS5# asserted
PCMCIA area
Card controller
Model name: MR-SHPC-01 V2T(Marubun)
This device is simply called SH-PCIC.
h’1A000000
~
h’1A7FFFFF
UART area (ChA)
UART
Model name: ST16C2550CQ48(EXAR)
This device is simply called UART.
h’1A800000
~
h’1AFFFFFF
UART area (ChB)
Same as above
h’08000000
~
h’0BFFFFFF
h’0C000000
~
h’0FFFFFFF
h’10000000
~
h’13FFFFFF
h’14000000
~
h’17FFFFFF
h’18000000
~
h’19FFFFFF
h’1B000000
~
h’1BFFFFFF
ID register area
h’1C000000
~
h’1FFFFFFF
-
Extension slot
CS2# asserted
This device is
used for interface
with H8/3048FONE.
This device is
used as an
interface with the
host.
The DIP switch
settings are read.
-
Reserved
R0P7760TH001TRK User’s Manual
Memory Map
Table 4.3 Memory Map during Debug Board Connection (J1: short-circuited)
Area No. Bus width
Area 0
16 bits
Area 1
Area 2
Area 3
16 bits
8/16/32 bits
32 bits
Area 4
8/16/32 bits
Area 5
8/16/32 bits
Area 6
16 bits
Space
h’00000000
~
h’003FFFFF
h’00400000
~
h’007FFFFF
h’00800000
~
h’00BFFFFF
h’00C00000
~
h’00FFFFFF
h’01000000
~
h’01FFFFFF
h’02000000
~
h’03FFFFFF
h’04000000
~
h’07FFFFFF
h’08000000
~
h’0BFFFFFF
h’0C000000
~
h’0FFFFFFF
h’10000000
~
h’13FFFFFF
h’14000000
~
h’17FFFFFF
h’18000000
~
h’19FFFFFF
h’1A000000
~
h’1A7FFFFF
h’1A800000
~
h’1AFFFFFF
Area 7
-
h’1B000000
~
h’1BFFFFFF
h’1C000000
~
h’1FFFFFFF
Space name
Device
EPROM area
256kB
M27C800-100F1 (ST Micro) x 1
Debug LED area
1B
8-bit debug LED
Remarks
Resources on
the debug board
2B
8-bit switch x 2
Switch area
Unused area
Flash memory area
8MB
MBM29DL640E-90TN (Fujitsu) x 1
-
Unused area
Board control register 16B
area
Board control register
Extension area (CS2)
64MB
Extension slot (CS2 area)
SDRAM area
64MB
EDS2516APTA-75 (ELPIDA) x 2
Extension slot
CS2# asserted
64MB
Extension area (CS4) Extension slot (CS4 area)
Extension slot
CS4# asserted
Extension area (CS5)
64MB
Extension slot (CS5 area)
Extension slot
CS5# asserted
PCMCIA area
Card controller
Model name: MR-SHPC-01 V2T(Marubun)
This device is simply called SH-PCIC.
UART area (ChA)
UART
Model name: ST16C2550CQ48(EXAR)
This device is simply called UART.
UART area (ChB)
Same as above
The DIP switch
settings are read.
ID register area
-
This device is
used for interface
with H8/3048FONE.
This device is
used as an
interface with the
host.
-
Reserved
R0P7760TH001TRK User’s Manual
Functional Blocks
5. Functional Blocks
5.1 PCMCIA
5.1.1 Block Description
Figure 5.1 shows the PCMCIA control block. As shown in Figure 5.1, the PCMCIA control block contains a
controller (MR-SHPC-01 V2 from Marubun Corporation), a 68-pin PC card interface connector (CN3) and a
power supply controller IC (TPS2211DB from TI). This controller interfaces with the card(s) conforming to the
PC Card Standard 97 and has the following features:
• Internal memory windows (2 windows) and I/O window (one window)
• Card access timing adjustment function
• One-step read/write buffer
• Endian internal control circuit
• Support for 5.0V/3.3V cards
• External buffer not required
• Internal interrupt steering function
• Power-down function
• Internal suspend function
There are four kinds of controller interrupts (SIRQ3 to SIRQ0). n
I puts to the H7760 are made by the IRL
codes. For details, refer to Marubun’s MR-SHPC-01 V2 Manual.
Marubun Homepage: http://www.marubun.co.jp
SH7760
Marubun PCMCIA controller
System bus I/F
FPGA
/IRL3
/IRL2
/IRL1
/IRL0
MR-SHPC-01 V2T
PC Card I/F
CARD slot
Card VCC
/SIRQ3
/SIRQ2
/SIRQ1
/SIRQ0
System VCC
+3.3V
+5.0V
Power supply
control register
(TPS2211IDB)
/CVCC3
/CVCC5
CVPP0
CVPP1
CARD PW GOOD
VCC(+5.0Vv/+3.3V/0V)
VPP(+5.0Vv/+3.3V/0V)
Figure 5.1 PCMCIA Control Block
CN3
R0P7760TH001TRK User’s Manual
Functional Blocks
5.1.2 Connector Pins
Table 5.1 summarizes the pins of a 68-pin PC card interface connector (CN3).
Table 5.1(1) PC Card Interface Connector Signal Pins
Pin
Memory card
Signal name
I/O card
Signal name
I/O
1
2
GND
D3
I/O Function
I/O
Ground
Data bit 3
GND
D3
I/O
Function
Ground
Data bit 3
3
4
5
D4
D5
D6
I/O
I/O
I/O
Data bit 4
Data bit 5
Data bit 6
D4
D5
D6
I/O
I/O
I/O
Data bit 4
Data bit 5
Data bit 6
6
7
8
D7
CE1#
A10
I/O
I
I
Data bit 7
Card enable
Address bit 10
D7
CE1#
A10
I/O
I
I
Data bit 7
Card enable
Address bit 10
9
10
11
OE#
A11
A9
I
I
I
Output enable
Address bit 11
Address bit 9
OE#
A11
A9
I
I
I
Output enable
Address b it 11
Address bit 9
12
13
14
A8
A13
A14
I
I
I
Address bit 8
Address bit 13
Address bit 14
A8
A13
A14
I
I
I
Address bit 8
Address bit 13
Address bit 14
15
16
17
WE#
READY
Vcc
I
O
-
Write enable
Ready
Supply voltage
WE#
IREQ#
Vcc
I
O
-
Write enable
Interrupt request
Supply voltage
18
19
20
VPP1
A16
A15
I
I
Programmed supply voltage
Address bit 16
Address bit 15
VPP1
A16
A15
I
I
Programmed supply voltage
Address bit 16
Address bit 15
21
22
23
A12
A7
A6
I
I
I
Address bit 12
Address bit 7
Address bit 6
A12
A7
A6
I
I
I
Address bit 12
Address bit 7
Address bit 6
24
25
26
A5
A4
A3
I
I
I
Address bit 5
Address bit 4
Address bit 3
A5
A4
A3
I
I
I
Address bit 5
Address bit 4
Address bit 3
27
28
29
A2
A1
A0
I
I
I
Address bit 2
Address bit 1
Address bit 0
A2
A1
A0
I
I
I
Address bit 2
Address bit 1
Address bit 0
30
31
32
D0
D1
D2
I/O
I/O
I/O
Data bit 0
Data bit 1
Data bit 2
D0
D1
D2
I/O
I/O
I/O
Data bit 0
Data bit 1
Data bit 2
33
34
WP
GND
O
-
Write Protect
Ground
IOIS16#
GND
O
-
16bit I/O port
Ground
R0P7760TH001TRK User’s Manual
Functional Blocks
Table 5.1(2) PC Card Interface Connector Signal Pins
Pin
Memory card
Signal
name
I/O
35
GND
-
36
37
38
CD1#
D11
D12
39
40
41
I/O card
Function
Signal name
I/O
Function
Ground
GND
-
O
I/O
I/O
Card detection
Data bit 11
Data bit 12
CD1#
D11
D12
O
I/O
I/O
Card detection
Data bit 11
Data bit 12
D13
D14
D15
I/O
I/O
I/O
Data bit 13
Data bit 14
Data bit 15
D13
D14
D15
I/O
I/O
I/O
Data bit 13
Data bit 14
Data bit 15
42
43
44
CE2#
VS1#
RFU
I
O
-
Card enable
Voltage sense
Reserved
CE2#
VS1#
IORD#
I
O
I
Card enable
Voltage sense
I/O read
45
46
47
RFU
A17
A18
I
I
Reserved
Address bit 17
Address bit 18
IOWR#
A17
A18
I
I
I
I/O write
Address bit 17
Address bit 18
48
49
50
A19
A20
A21
I
I
I
Address bit 19
Address bit 20
Address bit 21
A19
A20
A21
I
I
I
Address bit 19
Address bit 20
Address bit 21
51
52
53
Vcc
VPP2
A22
I
Supply voltage
Programmed supply voltage
Address bit 22
Vcc
VPP2
A22
I
Supply voltage
Programmed supply voltage
Address bit 22
54
55
56
A23
A24
A25
I
I
I
Address bit 23
Address bit 24
Address bit 25
A23
A24
A25
I
I
I
Address bit 23
Address bit 24
Address bit 25
57
58
59
VS2#
RESET
WAIT#
O
I
O
Voltage sense
Card reset
Bus cycle extension
VS2#
RESET
WAIT#
O
I
O
Voltage sense
Card reset
Bus cycle extension
60
61
62
RFU
REG#
BVD2
I
O
Reserved
Register selection
Battery voltage detection
INPACK#
REG#
SPKR#
O
I
O
I/O port response
Register selection
Audio digital waveform
63
64
65
BVD1
D8
D9
O
I/O
I/O
Battery voltage detection
Data bit 8
Data bit 9
STSCHG#
D8
D9
O
I/O
I/O
Card status change
Data bit 8
Data bit 9
66
67
68
D10
CD2#
GND
I/O
O
-
Data bit 10
Card detection
Ground
D10
CD2#
GND
I/O
O
-
Data bit 10
Card detection
Ground
Ground
R0P7760TH001TRK User’s Manual
Functional Blocks
5.1.3 Register Map
Table 5.2 shows a map for the PCMCIP controller registers.
Each of the controller registers must be
accessed in words.
Table 5.2 PCMCIA Control Registers
Address
H’B83FFFE4
H’B83FFFE6
H’B83FFFE8
H’B83FFFEA
H’B83FFFEC
H’B83FFFEE
H’B83FFFF0
Initial value
H’0000
H’000C
H’03BF
H’0000
H’0000
H’0000
H’07FC
H’B83FFFF2
H’07FC
H’B83FFFF4
H’07FC
H’B83FFFF6
H’0000
H’B83FFFF8
H’0000
H’B83FFFFA
H’0000
H’B83FFFFC
H’B83FFFFE
H’0000
H’5333
Register name
Mode register
Option register
Card status register
Interrupt factor register
Interrupt control register
Card voltage control register
Memory window 0
Control register 1
Memory window 1
Control register 1
I/O window
Control register 1
Memory window 0
Control register 2
Memory window 1
Control register 2
I/O window
Control register 2
Card control register
Chip information register
R0P7760TH001TRK User’s Manual
Functional Blocks
5.2 USB Host
5.2.1 Block Description
Figure 5.2 shows the USB host control block. As shown in Figure 5.2, the SH7760 contains the internal USB
host controller. This internal controller supports USB Versions 1.1openHCI has the following features:
• Compatibility with the OpenHCI Version 1.0a register set
• Conforms to the USB Version 1.1
• Provides a route hub function
• Supports the low speed (1.5Mbps) and full speed (12MB) modes
• Supports an overcurrent detection function
• Supports a maximum of 127 endpoints
• Capable of using the shared memory (8K) for transfer data and descriptors
For details, refer to the pertinent SH7760 Hardware Manual.
SH7760
USB Type A connector (CN7)
USB host controller
USB_PENC
USB_OVC
USB power
supply
control
driver
+5V
GND
USB_DM
-DATA
USB_DP
+DATA
Figure 5.2 USB Host Control Block
R0P7760TH001TRK User’s Manual
Functional Blocks
5.2.2 Connector Pins
Figure 5.3 shows the pins of the USB host connector (CN7).
Pin No
1
2
3
4
CN7 USB host connector (TypeA)
Model name: 20-5041-004-100-834
Maker: Kyocera Elco
Signal name
1
VBUS
2
-DATA
3
+DATA
4
GND
Figure 5.3 USB Host Connector (CN7) Pins
5.2.3 Register Map
Table 5.3 shows a register map for the internal USB host controller of the SH7760.
Table5.3 USB Host Controller Register
Address
Initial value
H’FE340000
H’00000010
HcRevision register
Register name
H’FE340004
H’00000000
HcControl register
H’FE340008
H’00000000
HcCommandStatus register
H’FE34000C
H’00000000
HcInterruptStatus register
H’FE340010
H’00000000
HcInterruptEnable register
H’FE340014
H’00000000
HcInterruptDisable register
H’FE340018
H’00000000
HcHCCA register
H’FE34001C
H’00000000
HcPeriodCurrentED register
H’FE340020
H’00000000
HcControlHeadED register
H’FE340024
H’00000000
HcControlCurrentED register
H’FE340028
H’00000000
HcBulkHeadED register
H’FE34002C
H’00000000
HcBulkCurrentED register
H’FE340030
H’00000000
HcDonrHeadED register
H’FE340034
H’00002EDF
HcFmInterval register
H’FE340038
H’00000000
HcFrameRemaining register
H’FE34003C
H’00000000
HcFmNumber register
H’FE340040
H’00000000
HcPeriodicStart register
H’FE340044
H’00000628
HcLSThreshold register
H’FE340048
H’02001202
HcRhDescriptorA register
H’FE34004C
H’00000000
HcRhDescriptorB register
H’FE340050
H’00000000
HcRhStatus register
H’FE340054
H’00000100
HcRhPortStatus1 register
H’FE341000~
H’FE342FFF
-
Shared memory area
R0P7760TH001TRK User’s Manual
Functional Blocks
5.3 UART
5.3.1 Block Description
Figure 5.4 shows the UART control block. As shown in Figure 5.4, the UART control block contains the
controller (ST16C2550 from EXAR), RS232C interface driver, and 15-pin connector (CN1).
This controller
uses the clock pulses (7.3728MHz) supplied from the power supply controller (H8/3048F-ONE) for operations,
and determines a baud rate (transfer rate) using these pulses as reference.
This controller has been provided with a 2-channel UART device. Channel A is used to communicate with
the power supply controller (H8/3048F-ONE).
Because channel B is connected to a 15-pin RS-232C
connector (CN1), it can be used as a debug interface if it is connected to a PC.
In addition, channel A (INTA) inputs the controller interrupts to the SH7760 IRL9 and channel B (INTB) inputs
them to the SH7760 IRL11.
EXAR Homepage: http://www.exar.com
Serial controller
(ST16C2550)
SH7760
Address bus
RS-232C I/F driver
(SP3223ECY)
Chanel B
Data bus
Power supply controller
(H8/3048F-ONE)
Control signal
/IRL3
/IRL2
/IRL1
/IRL0
FPGA
Chanel B
INTB
INTA
SCI chanel 1
XTAL
CK
EXTAL
7.3728MHz
OSC2
Figure 5.4 Serial Interface Block
15 pin
Serial connector
(CN1)
R0P7760TH001TRK User’s Manual
Functional Blocks
5.3.2 Connector Pins
Figure 5.5 shows the pins of a 15-pin serial interface connector (CN1).
Pin No
1
15
CN1: 15-pin serial connector
Model name: RMC-EA15MY-OM15-MC1
Maker: Honda Tsushin kogyo
Signal name
1
GND
2
TxD
3
RxD
4
GND
5
RTS
6
CTS
7
GND
8
Reserved
9
Reserved
10
Reserved
11
Reserved
12
Reserved
13
Reserved
14
Reserved
15
Reserved
Figure 5.5 15-pin Serial Interface Connector Pins (CN1)
R0P7760TH001TRK User’s Manual
Functional Blocks
5.3.3 Register Map
Tables 5.4 and 5.5 show register maps for the serial interface controller registers. Each of the serial interface
control registers must be accessed in words. If access takes place in words, data in the low order 8 bits
(D7 to D0) will become effective.
Table 5.4 Serial Interface Controller Register Map (Channel A)
Address
H’BA000000
Initial value
-
H’BA000000
-
H’BA000002
H’00
H’BA000002
-
H’BA000004
H’01
H’BA000006
H’00
H’BA000008
H’00
H’BA00000A
H’60
H’BA00000C
H’X0
H’BA00000E
H’FF
Register name (at read)
RHR
(ReceiveHoldingRegister)
DLL
(LSB of Divisor Latch)
IER
(InterruptEnableRegister)
DLM
(MSB of Divisor Latch)
ISR
(InterruptStatusRegister)
LCR
(LineControlRegister)
MCR
(ModemControlRegister)
LSR
(LineStatusRegister)
MSR
(ModemStatusRegister)
SPR
(ScratchpadRegister)
Register name (at write)
THR
(TransferHoldingRegister)
DLL
(LSB of Divisor Latch)
IER
(InterruptEnableRegister)
DLM
(MSB of Divisor Latch)
FCR
(FIFOControlRegister)
LCR
(LineControlRegister)
MCR
(ModemControlRegister)
N.A
Remarks
LCR bit7=0
LCR bit7=1
LCR bit7=0
LCR bit7=1
N.A
SPR
(ScratchpadRegister)
Table 5.5 Serial Interface Controller Register Map (Channel B)
Address
H’BA800000
Initial value
-
H’BA800000
-
H’BA800002
H’00
H’BA800002
-
H’BA800004
H’01
H’BA800006
H’00
H’BA800008
H’00
H’BA80000A
H’60
H’BA80000C
H’X0
H’BA80000E
H’FF
Register name (at read)
RHR
(ReceiveHoldingRegister)
DLL
(LSB of Divisor Latch)
IER
(InterruptEnableRegister)
DLM
(MSB of Divisor Latch)
ISR
(InterruptStatusRegister)
LCR
(LineControlRegister)
MCR
(ModemControlRegister)
LSR
(LineStatusRegister)
MSR
(ModemStatusRegister)
SPR
(ScratchpadRegister)
Register name (at write)
THR
(TransferHoldingRegister)
DLL
(LSB of Divisor Latch)
IER
(InterruptEnableRegister)
DLM
(MSB of Divisor Latch)
FCR
(FIFOControlRegister)
LCR
(LineControlRegister)
MCR
(ModemControlRegister)
N.A
N.A
SPR
(ScratchpadRegister)
Remarks
LCR bit7=0
LCR bit7=1
LCR bit7=0
LCR bit7=1
R0P7760TH001TRK User’s Manual
Functional Blocks
5.4 LCD
5.4.1 Block Description
Figure 5.6 shows the LCD control block. As shown in Figure 5.6, the LCD control block contains an internal
LCD controller and an LCD panel (TFT liquid crystal panel) mounted on the LCD board that can display 16-bit
RGB data with a resolution of QVGA (240 x 320). In addition, the SRAM with an internal LCD controller is
used for the LCD display VRAM (Video RAM).
Display data is stored in the internal SDRAM of the LCD controller in the order of coordinates (0,0), (1,0), …
and (239, 319) from the address set in the register (LDSARU) of the LCD controller. On the LCD panel
display, data at the upper left corner is handled as data on the origin (0,0) and data at the lower right corner is
handled as data on the coordinates (239,319).
The front light on the LCD panel can be turned on or off by the power supply controller. For details on front
light control, refer to 6. “Power Supply Controller.”
In addition, refer to the pertinent SH7760 Hardware
Manual for details on the LCD controller.
LCD Board
(0,0)
(239,319)
Power supply controller
(H8/3048F-ONE)
CPU board
connection
connector (CN2)
LCD board
connection
connector (CN6)
Touch panel signal
SW2
Key switch signal
Front light control signal
SH7760
LCD
controller
LCD data bus
LCD control signal
LCD board
connection
connector (CN5)
Data bus
Video RAM
(SDRAM)
Figure 5.6 LCD Control Block
SW1
SW3
CPU board
connection
connector (CN1)
R0P7760TH001TRK User’s Manual
Functional Blocks
5.4.2 Connector Pins
Figure 5.7 shows the pins of the LCD interface connectors (CN5 and CN6). Tables 5.6 and 5.7 summarize
the signals of these interface connectors.
CN5
1
40
1
CN6
24
CN6: LCD interface connector
Model name: FH12-24S-0.5SH
Maker: Hirose Electric Co., LTD.
CN5: LCD interface connector
Model name: FH12-40S-0.5SH
Maker: Hirose Electric Co., LTD.
Figure 5.7 LCD Interface Connector (CN5/CN6) Pins
Table 5.6 LCD Interface Connector (CN5) Signals
Pin No.
Signal name
I/O
Remarks
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VBAT
VBAT
VBAT
VBAT
N.C
LCD0
LCD1
LCD2
LCD3
LCD4
LCD5
LCD6
LCD7
GND
GND
LCD8
LCD9
LCD10
LCD11
LCD12
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Power supply
Power supply
Power supply
Power supply
Unused
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
Power supply
Power supply
LCDC
LCDC
LCDC
LCDC
LCDC
Pin No. Signal name
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
LCD13
LCD14
LCD15
GND
GND
CL1
CL2
DON
M_DISP
FLM
VEPWC
VCPWC
NC
GND
GND
IR_IN
3.3V
3.3V
3.3V
3.3V
I/O
Remarks
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
-
LCDC
LCDC
LCDC
Power supply
Power supply
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
LCDC
Unused
Power supply
Power supply
Remote control
Power supply
Power supply
Power supply
Power supply
R0P7760TH001TRK User’s Manual
Functional Blocks
Table5.7 LCD Interface Connector (CN6) Signals
Pin No. Signal name
1
2
3
4
5
6
7
8
9
10
11
12
GND
GND
KEY_IN0
KEY_IN1
KEY_IN2
KEY_IN3
KEY_IN4
KEY_OUT0
KEY_OUT1
KEY_OUT2
GND
GND
I/O
Remarks
Pin No.
Signal name
I/O
Remarks
IN
IN
IN
IN
IN
OUT
OUT
OUT
-
Power supply
Power supply
KEY_I/F
KEY_I/F
KEY_I/F
KEY_I/F
KEY_I/F
KEY_I/F
KEY_I/F
KEY_I/F
Power supply
Power supply
13
14
15
16
17
18
19
20
21
22
23
24
~PAD_CS
~PAD_IRQ
PAD_DIN
PAD_DOUT
PAD_DCLK
~RESET
~LCD_FLON
~LCD_PWRDY
GND
GND
3.3VSB
3.3VSB
OUT
IN
OUT
IN
OUT
OUT
OUT
IN
-
PAD I/F
PAD_I/F
PAD_I/F
PAD_I/F
PAD_I/F
Reset
LCD power supply
LCD power supply
Power supply
Power supply
Power supply
Power supply
5.4.3 Register Map
Table 5.8 shows a register map for the LCD controller.
Table 5.8 LCD Controller Registers
Address
H’FE300C00
H’FE300C02
H’FE300C04
H’FE300C06
H’FE300C08
Initial value
H’0101
H’0109
H’000C
H’0000
H’0C000000
H’FE300C0C
H’0C000000
H’FE300C10
H’0280
H’FE300C12
H’FE300800~
H’FE300BFC
H’FE300C14
H’FE300C16
H’FE300C18
H’FE300C1A
H’FE300C1C
H’FE300C1E
H’0000
H’4F52
H’0050
H’01DF
H’01DF
H’01DF
H’000C
H’FE300C20
H’0000
H’FE300C24
H’FE300C26
H’0010
H’F606
H’FE300C28
H’0000
Register name
Input clock register
Module type register
Data format register
Scan mode register
Starting address register for fetching
upper data on the display panel
Starting address register for fetching
lower data on the display panel
Data line address offset register for
fetching display data
Palette control register
Palette data register
Horizontal character number register
Horizontal synchronization signal register
Vertical display line number register
Vertical total line number register
Vertical synchronization signal register
AC modulation signal toggle line number
register
Interrupt control register
Power management mode register
Power control sequence period register
Control register
R0P7760TH001TRK User’s Manual
Functional Blocks
5.5 Sound Generator
5.5.1 Block Description
Figure 5.8 shows the sound generator control block. As shown in Figure 5.8, this control block contains the
serial sound interface (SSI) of the SH7760 and the Audio CODE C (UDA1342TS from Philips), so that sound can
be output to headphones connected to the output mini-jack (CN9) or can be input to earphones connected to
the I/O mini-jack (CN10). In addition, headphone output takes place with the quality of stereo output while
earphone I/O takes place with the quality of monaural I/O that uses only the Rch.
The IIC interface of the SH7760 is used for the initial setting and for modification of the Audio CODEC internal
registers.
This control block is connected to an electronic volume so that sound output volume can be controlled. The
electronic volume is controlled by the power supply controller.
For details, refer to 6, “Power Supply
Controller.”
T-Engine has the following characteristics for microphone input and headphone output:
- Microphone input
Impedance: 2.2KΩ
Sensitivity: -51dB/Pa
- Headphone output
Impedance: 32Ω
For more details, refer to the SH7760 Hardware Manual or the Philips UDA1342TS Manual.
Philips Homepage: http://www.semiconductors.philips.com/
SH7760
Audio CODEC
(UDA1342TS)
IIS Ch0
DATAO
SDATA
SCK
WS
CLK
BCK
WS
DATAI Rch input
IIS Ch1
Rch
Lch
Rch output
Lch output
Amplifier
SYSCLK
SDATA
SCK
WS
CLK
I2C Ch0
SCL
SDA
L3CLOCK
L3DATA
22.5792MHz
OSC4
Electronic
volume
Power supply controller
(H8/3048F-ONE)
Figure 5.8 Sound Generator Control Block
Sound
output
mini-jack
(CN9)
Sound I/O
mini-jack
(CN10)
R0P7760TH001TRK User’s Manual
Functional Blocks
5.5.2 Connector Pins
Figure 5.9 shows the pins of the sound generator I/O mini-jack (CN9, CN10). Tables 5.9 and 5.10 list the
signals of the sound generator I/O mini-jack (CN9, CN10).
CN9,CN10: Sound generator I/O mini-jack ( 2.5)
4
1
Model name: HSJ1602-010011
Maker: Hoshiden Corporation
5
2
3
Figure 5.9 Sound Generator I/O Mini-jack (CN9, CN10) Pins
Table 5.9 Sound Generator I/O Mini-jack (CN9) Signals
Pin No
1
2
3
4
5
Signal Name
GND
R-IN
R-OUT
MIC-IN
HP_SENSE
Table 5.10 Sound Generator I/O Mini-jack (CN10) Signals
Pin No
1
2
3
4
5
Signal Name
GND
L-OUT
R-OUT
HP_SENSE
NC
R0P7760TH001TRK User’s Manual
Functional Blocks
5.5.3 Register Map
Table 5.11 shows a register map for the SH7760 SSI registers.
Table 5.11 SSI Controller Register
Resister
Abbreviation
SSICR0
SSISR0
SSITDR0
SSIRDR0
SSICR1
SSISR1
SSITDR1
SSIRDR1
Address
R/W
Initial Value
H’FE680000
H’FE680004
H’FE680008
H’FE68000C
H’FE690000
H’FE690004
H’FE690008
H’FE69000C
R/W
R/W
R
R
R/W
R/W
R
R
H’0000 0000
H’0200 0003
H’0000 0000
H’0000 0000
H’0000 0000
H’0200 0003
H’0000 0000
H’0000 0000
Access Size
32
32
32
32
32
32
32
32
R0P7760TH001TRK User’s Manual
Functional Blocks
5.6 eTRON Interface
5.6.1 Block Description
Figure 5.11 shows an eTRON interface control block. As shown in Figure 5.11, this control block contains the
SIM card module of the SH7760, the power supply/level converter (LTC1555LEGN-1.8), and the 8-pin
connector (CN4) to interact with the eTRON card inserted into the eTRON interface connector (CN4).
The eTRON card can be reset by controlling the SH7760 internal SIM card module register (SISCMR).
The control method is shown below.
“Low” output from PTE4: The reset pin of the eTRON card is set to “Low.” (Reset state)
“High” output from PTE4: The reset pin of the eTRON card is set to “High.” (Normal state)
Power supply to the eTRON card is controlled via the power supply controller (H8/3048-ONE). However, when
the T-Engine board is ON, the eTRON card is being powered. When inserting or removing the eTRON card,
be sure to turn off T-Engine in advance.
For more information, refer to the pertinent SH7760 Hardware
Manual.
SH7760
Smart card
module (SIM)
SIM card interface
connector (CN4)
SIM_CLK
SIM_D
Power supply/level
converter
SIM_RST
(LTC1555LEGN-1.8)
CLK
I/O
VCC
RST
Power supply controller
(H8/3048F-ONE)
VCC
Figure 5.11 eTRON Interface Control Block
R0P7760TH001TRK User’s Manual
Functional Blocks
5.6.2 Connector Pins
Figure 5.12 shows the pins of the SIM card interface connector (CN4). Table 5.12 summarizes the signals of
the SIM card interface connector (CN4).
CN4 : eTRON interface connector
Model name: 03-5036-006-071-862
Maker: Kyocera Elco
1
5
2
6
3
7 4
8
Figure 5.12 eTRON Interface Connector (CN4) Pins
Table 5.12 eTRON Interface Connector (CN4) Signals
Pin No
1
2
3
4
5
6
7
8
Signal Name
C1:VCC
C2:RST
C3:CLK
C4:*1
C5:GND
C6:VPP
C7:I/O
C8: *1
*1: Pins 4 and 8 are connected to the connector (CN13) for board test. Don’t use this connector for the other
purpose.
R0P7760TH001TRK User’s Manual
Functional Blocks
5.6.3 Register Map
Table 5.13 shows a register map for the SH7760 SIM card module (SIM).
Table 5.13 SIM Card Module Register Map
Address
H’FE480000
H’FE480002
H’FE480004
H’FE480006
H’FE480008
H’FE48000A
H’FE48000C
H’FE48000E
H’FE480010
H’FE480012
H’FE480014
Initial value
H’20
H’07
H’00
H’FF
H’84
H’00
H’01
H’00
H’0000
H’00
H’0173
Register name
Serial mode register
Bit rate register
Serial control register
Transmit data register
Serial status register
Receive data register
Smart card mode register
Serial control 2 register
Wait time register
Guard extension register
Sample register
R0P7760TH001TRK User’s Manual
Functional Blocks
5.7 I/O Board
5.7.1 Block Description
Figure 5.13 shows the control block of an I/O board. As shown in Figure 5.13, the SH7760 module pins output
signals to the connectors (through-holes), which provide various interfaces with the external device.
As the connector is not installed, when an external pin is to be connected, it should be directly connected to the
through-hole, or the connector should be installed.
The internal modules, which output the signals, are listed below.
Hitachi controller area network 2 (HCAN2): 2ch
Serial communication interface (SCIF): 2ch
IIC bus interface: 1ch
A/D converter: 4ch
Compare match timer (CMT)
For details on each module, refer to the pertinent SH7760 Hardware Manual.
CPU board
I/O board
CN6
SH7760
HCAN2
CAN0_RX
CAN0_TX
CAN0_NERR
CAN0_RX
CAN0_TX
CAN0_NERR
CAN1_RX
CAN1_TX
CAN1_NERR
CN7
CAN1_RX
CAN1_TX
CAN1_NERR
CN10
SCIF
SCIF0_TXD
SCIF0_RXD
SCIF0_CLK
SCIF1_TXD
SCIF1_RXD
SCIF1_CLK
SCIF1_RTS
SCIF1_CTS
C
N
1
CN
16
SCIF0_TXD
SCIF0_RXD
SCIF0_CLK
CN9
SCIF1_TXD
SCIF1_RXD
SCIF1_CLK
SCIF1_RTS
SCIF1_CTS
IIC
CN11
IIC1_SDA
IIC1_SCL
IIC1_SDA
IIC1_SCL
A/D
Avcc_ADC
Avss_ADC
AN0
AN1
AN2
AN3
ADRTG
CN5
5V
3.3V
GND
C
N
2
CN
17
Avcc_ADC
Avss_ADC
AN0
AN1
AN2
AN3
CN12
5V
CN13
3.3V
CN14
GND
Figure 5.13
I/O Board Control Block
R0P7760TH001TRK User’s Manual
Functional Blocks
5.7.2 Connector (Through-Hole) Pin Assignments
Tables 5.14 to 5.22 show the connector (through-hole) pin assignments on the I/O board.
Table 5.14 A/D Converter I/F Connector (CN5) Pin Assignments
Pin No.
1
2
3
4
5
6
Signal Name
AVcc ADC
AN3
AN2
AN1
AN0
AVss_ADC
Table 5.15 HCAN2 I/F Connector (CN6) Pin Assignments
Pin NO.
1
2
3
Signal Name
CAN0_TX
CAN0_RX
CAN0_NERR
Table 5.16 HCAN2 I/F Connector (CN7) Pin Assignments
Pin No.
1
2
3
Signal Name
CAN1_TX
CAN1_RX
CAN1_NERR
Table 5.17 CMT I/F Connector (CN8) Pin Assignments
Pin No.
1
2
3
4
Signal Name
CMT_CTR0
CMT_CTR1
CMT_CTR2
CMT_CTR3
Table 5.18 SCIF Connector (CN9) Pin Assignments
Pin NO.
1
2
3
4
5
Signal Name
SCIF1_TXD
SCIF1_RXD
SCIF1_RTS
SCIF1_CTS
SCIF1_CLK
Table 5.19 SCIF Connector (CN10) Pin Assignments
Pin No.
1
2
3
Signal Name
SCIF0_TXD
SCIF0_RXD
SCIF0_CLK
R0P7760TH001TRK User’s Manual
Functional Blocks
Table 5.20 5V Power Supply Connector (CN6) Pin Assignments
Pin No.
1
Signal Name
5V
2
5V
3
4
5V
5V
Table 5.21 3.3V Power Supply Connector (CN6) Pin Assignments
Pin NO.
1
2
3
4
Signal Name
3.3V
3.3V
3.3V
3.3V
Table 5.22 GND Connector (CN6) Pin Assignments
Pin No.
1
2
3
4
Signal Name
GND
GND
GND
GND
R0P7760TH001TRK User’s Manual
Power Supply Controller
6. Power Supply Controller
6.1. Power Supply Controller Functions
The H8/3048F-ONE power supply controller (simply called the power supply controller) provides the following
control functions with firmware stored in the internal memory.
The following functions can be controlled
through the UART ChA from the SH7760. Figure 6.1 shows a power supply controller block diagram.
(1) RTC (real-time clock) function
(2) System power supply (3.3V/5/0V) ON/OFF control function
(3) Touch panel coordinate position read function
(4) Key switch input function
(5) Infrared remote control transmission/reception function
(6) Electronic volume
(7) Serial EEPROM read/write function
These functions can be controlled through the UART chA from SH7760.
H8/3048F-ONE
1.8V ON/OFF
(Vcc)
-SH7727 CPUcore
-SH7290 CPU core 3.3V ON/OFF
(VCC3A)
-SH7727
-SDRAM (SH7727)
-FLASH (SH7727)
P40
RV5C348A(RTC)
P41
P42
3.3V ON/OFF
(VCC3B)
-UART
-PCMCIA
-USB HUB
-Sound
5V ON/OFF
(5V)
-USB power
P43
supply
-Sound generator
amplifier
-ATA card power
supply
generator IC
-SIM card
H8 reset
circuit
SH7727
/RESET
PB6
Reset signal for devices
other than H8/3048F
Reset
circuit
/RESET
P60
NMI
P61
PINT11
P62
BUS
/CTSA
/RTSA
RXA
TXA
EXTAL
Infrared remote control
ST16C2550CQ48
(UART)
LED
LCD board
P82(/IRQ2)
P27
TXD0
RXD0
CK
Transmission
TIOCA3(PB0)
TIOCA4(PB2)
TIOCB2(PA7)
/IRQ4(P94)
Receiving unit
MAX5413ECD
(Electronic volume)
/INT
CE
/IRQ1
P50
/CS
SCLK
DIN
SI
SO
CLK
29391AFJA(EEPROM)
CS
D0
D1
/SK
P52
P53
TXD1
RXD1
SCK1
LCD board
ADS7843E(Touch panel)
DIN
DOUT
DCLK
/PENIRQ
/CS
/IRQ0(P80)
P51
PA4
P22
P21
P20
P14
P13
P12
P11
P10
Cursor switch (SW1)
Push-buttonswitch
(SW2, 3)
VOUT2
VOUT1
ADP_IN
VOLT
AMP
SIGN
H8_SW2
H8_SW1
P17
P16
PA6
AN0
AN1
PA5
P25
P24
LTC1555LEGN
M0
M1
M2
P44
P45
P46
/IRQ3(P83)
PA2
PA1
P30-P37
P66
LCD
8
Power-on switch
NMI switch
Reset switch
Power supply
(battery monitoring)
eTRON socket
8bit LED
DIPSW5-8
Figure 6.1 Power Supply Control Block Diagram
CAUTION
Though the power supply controller's I/O port is connected to the /RTSA and /CTSA pins of the UART
controller (ST16C2550) through the circuit, the power supply controller does not execute hardware
control during communications with SH7760. For details of communications between SH7760 and the
power supply controller, refer to 6.2 “Serial Communications between SH7760 and the Power Supply
Controller.”
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.2 Serial Communications between SH7760 and the Power Supply Controller
This section describes how serial communications take place between SH7760 and the power supply controller.
6.2.1 Serial Format
This subsection describes a format for serial communications between SH7760 and the power supply controller.
(1) Mode: Start-stop
(2) Baud rate: 38400 bits/second
(3) Stop bit: 1 bit
(4) Start bit: 1 bit
(5) Parity bit: None
(6) LSB first
6.2.2 Power Supply Control Register Read Procedure
This subsection describes a procedure for reading the power supply control registers.
(1) SH7760 issues a read command to a power supply controller.
(2) The power supply controller returns a response to SH7760.
CAUTION
Don’t issue multiple commands continually from SH7760. Note that the next command must be
issued after a response to the preceding command has been returned from the power supply controller.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.2.3 Read Command
Figure 6.2 shows a read command format. SH7760 sends a start code, a function code and a register address,
in this order, as a read command.
(1) Start code (1 byte)
(2) Function code (1 byte or 2 bytes)
(3) Register address (2 bytes)
Figure6.2 Read Command
(1) Start code
The code is fixed at 0 x 02.
(2) Function code
• A 1-byte function code specifies the size of data to be read in the lower 4 bits when the upper 4 bits of
a function code are 1000. Figure 6.3 shows a function command where the upper 4 bits are 1000.
D7
D6
D5
D4
1
0
0
0
D3
D2
D1
D0
Size of data
Figure6.3 Function Command (1 Byte)
• A 2-byte function code specifies the size of data to be read in the lower 12 bits when the upper 4 bits
of a function code are 1001. Figure 6.4 shows a function command where the upper 4 bits are 1001.
D15
D14
D13
D12
1
0
0
1
D11
D10
D9
D8
D7
D6
D5
Size of data
Figure6.4 Function Command (2 Bytes)
(3) Register Address
The register address specifies the address of the register to be read
D4
D3
D2
D1
D0
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.2.4 Normal Response during a Read Operation
Figure 6.5 shows the response format for the read command. The power supply controller returns an
ACK code, a function code, a register address and target data, in this order, as a response.
(1) ACK code(1 byte)
(2) Function code
(1 byte or 2 bytes)
(3) Register address
(2 bytes)
(4) Data (N byte)
Figure 6.5 Normal Response during a Read Operation
(1) ACK code
The code is fixed at ACK (0x06).
(2) Function code
The same function code as for the read command returns.
(3) Register address
The address of a register subject to a read operation returns.
(4) Data
Read data returns. The size of this data is equal to the value specified in the function
code.
6.2.5 Error Response during a read Operation
Figure 6.6 shows the error response format for the read command. The power supply controller returns a NAK
code and an error code in this order as a response at error occurrence.
(1) NAK code
(1 byte)
(2) Error code
(1byte)
Figure 6.6 Error Response during a Read Operation
(1) NAK code
This code is fixed at NAK (0x15).
(2) Error code
Table 6.1 summarizes the error codes.
Table 6.1 Error Codes
Error No
Error type
0x01
Communications error
0x02
Invalid function code
0x03
Invalid register number
0x04
Register size error
0x05
Data size error
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.2.6 Power Supply Control Register Write Procedure
This subsection describes the procedure for writing to a controller control of the power supply controller from
SH7760.
(1) SH7760 issues a write command to the power supply controller.
(2) The power supply controller returns a response the SH7760.
CAUTION
Don’t issue multiple commands continually from SH7760. Note that the next command must be
issued after a response to the preceding command has been returned from the power supply controller.
6.2.7 Write Command
Figure 6.7 shows the write command format. SH7760 sends a start code, a function code, a register address
and data, in this order, as a write command.
(1) Start code
(1 byte)
(2) Function code
(1 byte or 2 byte)
(3) Register address
(2 byte)
(4) Register address (N
byte)
Figure 6.7 Read Command
(1) Start code
This code is fixed at 0x02.
(2) Function code
• A 1-byte function code specifies the size of data to be written in the lower 4 bits when the upper 4 bits
of a function code are 1100. Figure 6.8 shows a function command where the upper 4 bits are 1100.
D7
D6
D5
D4
1
1
0
0
D3
D2
D1
D0
Size of data
Figure 6.8 Function Command (1 Byte)
• A 2-byte function code specifies the size of data to be written in the lower 12 bits when the upper 4 bits
of a function code are 1101. Figure 6.9 shows a function command where the upper 4 bits are 1101.
D15
D14
D13
D12
1
1
0
1
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Size of data
Figure 6.9 Function Command (2 Bytes)
(3) Register Address
The register address specifies the address of the register to be written.
(4) Data
This field specifies the size of data to be written. This data size is equal to that specified in the function
code.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.2.8 Normal Response during a Write Operation
Figure 6.10 shows the response format for the write command. The power supply controller returns an
ACK code, a function code, a register address and target data, in this order, as a response for the write
command.
(1) ACK code
(1 byte)
(2) Function code
(1 byte or 2 byte)
(3) Register address
(2 byte)
(4) Data
(N byte)
Figure 6.10 Normal Response during a Write Operation
(1) ACK code
This code is fixed at ACK (0x06).
(2) Function code
The same code as for the write command returns.
(3) Register address
The address of a register subject to a write operation returns.
(4) Data
Write data returns. The size of this data is equal to the value specified in the function code. However,
note that no data returns for IRRSFDR subject to infrared remote control and EEPDR subject to serial
EEPROM control.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.2.9 Error Response during a Write Operation
Figure 6.11 shows an error response format for the write command at error occurrence. The power supply
controller returns a NAK code and an error code in this order as an error response.
(1) NAK code
(1 byte)
(2) Error code
(1 byte)
Figure 6.11 Error Response during a Write Operation
(1) NAK code
This code is fixed at NAK (0x15).
(2) Error code
Table 6.2 summarizes the error codes.
Table 6.2 Error Codes
Error
No.
0x01
0x02
0x03
0x04
0x05
Code
Error type
Communications error
Invalid function code
Invalid register number
Register size error
Data size error
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.3 RTC (Real-time Clock) Functions
This section describes the RTC functions.
Table 6.1 summarizes the RTC registers.
For a detailed
description of each register, refer to 6.3.1 to 6.3.17.
(1) Function for counting the seconds, minutes, hours, day of the week, month, and year (BCD code)
(2) RTC start/stop function
(3) Alarm interrupt function
(4) 1sec/0.5sec cyclic interrupt function
(5) Automatic correction function for leap years
(6) Effective range of operation from January 1, 2000 to December 31, 2099
Table 6.3 RTC Registers
Register
Abbreviation
Address
R/W
Size
RTC control register
RTC status register
Second counter
Minute counter
Hour counter
Day-of-the-week counter
Day counter
Month counter
Year counter
Second alarm counter
Minute alarm counter
Hour alarm counter
Day-of-the-week alarm counter
Day alarm counter
Month alarm counter
RTC/Touch panel/Key input/Power supply
status register
RTCCR
RTCSR
SECCNT
MINCNT
HRCNT
WKCNT
DAYCNT
MONCNT
YRCNT
SECAR
MINAR
HRAR
WKAR
DAYAR
MONAR
RTKISR
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000C
0x000D
0x000E
0x0090
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
Remarks
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.3.1 RTC Control Register (RTCCR)
Address: 0x000 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
0
R
0
R
CNTS
R/W
SECCAF
R/W
0.5secI
R/W
1secI
R/W
ARI
R/W
START
R/W
(1) START
START bit
Setting
0
RTC start (Initial value)
1
RTC stop
CAUTION
Don’t write to any counter while the START bit is set to “0.” Rewrite each counter after setting the
START bit to “1.”
(2) ARI
ARI bit
Setting
0
No alarm interrupt is generated (Initial value)
1
An alarm interrupt is generated
(3) 1secI
1secI bit
0
1
Setting
No interrupt is generated at intervals of 1 second.
(Initial value)
An interrupt is generated at intervals of 1 second.
(4) 0.5secI
0.5secI bit
0
1
Setting
No interrupt is generated at intervals of 0.5 second.
(Initial value)
An interrupt is generated at intervals of 0.5 second.
(5) SECCAF
SECCAF bit
0
1
Setting
No carry has been generated in the second counter (SECCNT).
(Initial value)
A carry has been generated in the second counter (SECCNT).
[Zero-clear condition]
The SECCAF bit is set to “1.’’
R0P7760TH001TRK User’s Manual
Power Supply Controller
(6) CNTS
CNTS bit
Setting
The setting (value) of each counter is not updated.
(Initial value)
The setting (value) of each counter is updated.
[Zero-clear condition]
Counter update is completed.
This clear
automatically performed.
0
1
operation
is
CAUTION
Don’t write to any counter while the START bit is set to “0.” Set the CNTS bit to “1” after updating
the value of each counter with the START bit set to “1.”
6.3.2 RTC Status Register (RTCSR)
Address: 0x001 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
0
R
0
R
0
R
0
R
0.5 secF
R/W
1 secF
R/W
ARF
R/W
0
R
(1) ARF
ARF bit
0
1
Setting
The setting of each alarm register with the AR bit set is not the
same as that of each counter register (Initial value)
The setting of each alarm register with the AR bit set is identical
to that of each counter register. At this time, an interrupt occurs
if the ARI bit is set to “1.’’
[Clear condition]
“0’’ is written with the ARF bit set to “1.’’
(2) 1secF
1secF bit
Setting
0
A second has not elapsed yet (Initial value)
1
A second has elapsed.
[Clear condition]
“0’’ is written with the 1secF bit set to “1.’’
(3) 0.5secF
0.5secF bit
Setting
0
A half second has not elapsed yet. (Initial value)
1
A half second has elapsed yet.
[Clear condition]
“0’’ is written with the 0.5secF bit set to “1.’’
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.3.3 Second Counter (SECCNT)
Address: 0x002 Initial value: 0xXX (Not defined)
D7
D6
D5
D4
D3
0
R
R/W
10 second
R/W
R/W
R/W
D2
D1
1 second
R/W
R/W
D0
R/W
The counter value is a BCD (Binary Coded Decimal) value. Counting takes place within a range from 00 to 59.
When the value changes from 59 to 00, a carry is generated in the minute counter.
6.3.4 Minute Counter (MINCNT)
Address: 0x0003 Initial value: 0xXX (Not defined)
D7
D6
D5
D4
D3
0
R
R/W
10 minutes
R/W
R/W
R/W
D2
D1
1 minutes
R/W
R/W
D0
R/W
The counter value is a BCD (Binary Coded Decimal) value. Counting takes place within a range from 00 to 59.
When the value changes from 59 to 00, a carry is generated in the hour counter.
6.3.5 Hour Counter (HRCNT)
Address: 0x0004 Initial value: 0xXX (Not defined)
D7
D6
0
R
0
R
D5
D4
10 hours
R/W
R/W
D3
D2
R/W
R/W
D1
1 hours
R/W
D0
R/W
The counter value is a BCD (Binary Coded Decimal) value. Counting takes place within a range from 00 to 23.
When the value changes from 23 to 00, a carry is generated in the day counter and the day-of-the-week
counter.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.3.6 Day-of-the-Week Counter (WKCNT)
Address: 0x0005 Initial Value: 0xXX (Not defined)
D7
D6
D5
D4
D3
0
R
0
R
0
R
0
R
0
R
D2
D1
D0
Septinary incremental counter
R/W
R/W
R/W
Counting takes place within a range from 0x00 to 0x06.
The following shows the correspondence between the day of the week and the value of the septinary
incremental counter.
(D2.D1.D0) = (0.0.0) →Sunday
(D2.D1.D0) = (0.0.1) →Monday
(D2.D1.D0) = (0.1.0) →Tuesday
(D2.D1.D0) = (0.1.1) →Wednesday
(D2.D1.D0) = (1.0.0) →Thursday
(D2.D1.D0) = (1.0.1) →Friday
(D2.D1.D0) = (1.1.0) →Saturday
6.3.7 Day Counter (DAYCNT)
Address: 0x0006 Initial value: 0xXX (Not defined)
D7
D6
0
R
0
R
D5
D4
10 days
R/W
R/W
D3
D2
R/W
R/W
D1
D0
R/W
R/W
1 day
The counter value is a BCD (Binary Coded Decimal) value. Counting takes place within a range from 1 to 31
(January, March, July, August, October and December), 1 to 30 (April, June, September and November), 1 to 28
(February in normal year) or 1 to 29 (February in leap year).
6.3.8 Month Counter (MONCNT)
Address: 0x0007 Initial value: 0xXX (Not defined)
D7
D6
D5
D4
D3
0
R
0
R
0
R
October
R/W
R/W
D2
D1
January
R/W
R/W
D0
R/W
The counter value is a BCD (Binary Coded Decimal) value. Counting takes place within a range from 1 to 12.
When the counter value changes from 12 to 1, a carry is generated in the year counter.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.3.9 Year Counter (YRCNT)
Address: 0x0008 Initial value: 0xXX (Not defined)
D7
D6
R/W
D5
10 years
R/W
R/W
D4
D3
D2
R/W
R/W
R/W
D1
D0
R/W
R/W
1 year
The counter value is a BCD (Binary Coded Decimal) value. Counting takes place within a range from 0 to 99.
In this range, 00, 04, ..., 92 and 96 are leap years.
6.3.10
Alarm Register
Each alarm register corresponds to the relevant counter as shown below.
If the AR bit (D7) of each alarm is set to “1,” counters will be compared with alarm registers. This comparison
is performed only for alarm registers with the AR bit (D7) set to “1” and an alarm interrupt is generated only at
correct correspondence.
• Correspondence between the alarm registers and counters
Second alarm register (BCD code): second counter
Minute alarm register (BCD code): minute counter
Hour alarm register (BCD code): Hour counter
Day-of-the-week alarm register (0x00 to 0x07): Day-of-the-week counter
Day alarm register (BCD code): Day counter
Month alarm register (BCD code): Month counter
6.3.11
Second Alarm Register (SECAR)
Address: 0x0009 Initial value: 0x00
D7
D6
D5
D4
D3
AR
R/W
R/W
10 seconds
R/W
R/W
R/W
D2
D1
1 second
R/W
R/W
D0
R/W
The alarm value must be a BCD (Binary Coded Decimal) code between 00 and 59.
6.3.12
Minute Alarm Register (MINAR)
Address: 0x000A Initial value: 0x00
D7
AR
R/W
D6
D5
R/W
10 minutes
R/W
D4
R/W
D3
R/W
D2
D1
1 minute
R/W
R/W
The alarm value must be a BCD (Binary Coded Decimal) code between 00 and 59.
D0
R/W
R0P7760TH001TRK User’s Manual
6.3.13
Power Supply Controller
Hour Alarm Register (HRAR)
Address: 0x000B Initial value: 0x00
D7
D6
AR
R/W
0
R
D5
D4
10 hours
R/W
R/W
D3
D2
R/W
R/W
D1
D0
R/W
R/W
1 hour
The alarm value must be a BCD (Binary Coded Decimal) code between 00 and 23.
6.3.14
Day-of-the-Week Alarm Register (WKAR)
Address: 0x000C Initial value: 0x00
D7
D6
D5
D4
D3
AR
R/W
0
R
0
R
0
R
0
R
D2
(D2.D1.D0) = (0.0.0) → Sunday
(D2.D1.D0) = (0.0.1) → Monday
(D2.D1.D0) = (0.1.0) → Tuesday
(D2.D1.D0) = (0.1.1) → Wednesdady
(D2.D1.D0) = (1.0.0) → Thursday
(D2.D1.D0) = (1.0.1) → Friday
(D2.D1.D0) = (1.1.0) → Saturday
D0
Septinary counter value
R/W
R/W
R/W
The alarm value must be set within a range from 0x00 to 0x06.
• Day of the week and septinary counter value
D1
R0P7760TH001TRK User’s Manual
6.3.15
Power Supply Controller
Day Alarm Register (DAYAR)
Address: 0x000D Initial value: 0x00
D7
D6
AR
R/W
0
R
D5
D4
10 days
R/W
R/W
D3
D2
R/W
R/W
D1
D0
R/W
R/W
1 day
The alarm value must be a BCD (Binary Coded Decimal) code between 1 and 31 (January, March, May, July,
August, October and December), between 1 and 30 (April, June, September and November), between 1 and 28
(February in normal year) or between 1 and 29 (February in leap year).
6.3.16
Month Alarm Register (MONAR)
Address: 0x000E Initial value: 0x00
D7
D6
D5
D4
D3
AR
R/W
0
R
0
R
October
R/W
R/W
D2
D1
January
R/W
R/W
D0
R/W
The alarm value must be a BCD (Binary Coded Decimal) code between 01 and 12.
6.3.17
RTC/Touch Panel/Key Input/Power Supply Status Register (RTKISR)
This status register indicates the RTC, touch panel or key input status.
The following is a brief
description of RTC-related status bits.
Address: 0x0090 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
0
R
0
R
0
R
IRRIF
R/W
POWERIF
R/W
KEYIF
R/W
TPIF
R/W
RTCIF
R/W
(1) RTCIF
RTCIF bit
0
1
Setting
The ARF, 1secF ad 0.5secF bits of the RTC register are all set to “0.’’
(Initial value)
One of the ARF, 1secF ad 0.5 secF bits of the RTC register is set to “1.’’
[Clear condition]
“0’’ is written with the RTCIF bit set to ‘’1.’’
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.4 Touch Panel Functions
This section describes the touch panel functions. In addition, Table 6.4 summarizes the touch panel registers.
For details of each register, refer to 6.4.1 to 6.4.32.
(1) The A/D conversion value of the X or Y position sensed by pen touch is output.
(2) Pen touch ON/OFF interrupt function
Sampling takes place at intervals of 20msec to 100msec. When the results (A/D conversion value of
the X or Y position) obtained three times from sampling are approximate to each other, a pen touch
ON interrupt is generated for SH7760. In addition, when the touch panel is turned off, a pen touch
OFF interrupt is generated.
(3) To keep the pen touch “ON,” sampling is performed at intervals of 20msec to 100msec and a pen
touch ON interrupt is generated if the results obtained from sampling are approximate to each other.
(4) Calibration function
Calibration is performed when two points on the touch panel are touched with the pen.
After completion of calibration, the X and Y positions are converted into the LCD
drawing dot positions for output.
R0P7760TH001TRK User’s Manual
Power Supply Controller
Table 6.4 Touch Panel Registers
Register
Abbreviation
Address
R/W
Size
Touch panel control register
Touch panel status register
Touch panel sampling control register
X position A/D register
Y position A/D register
X position dot register
Y position dot register
XA position dot register
YA position dot register
XB position dot register
YB position dot register
XC position dot register
YC position dot register
XA position A/D register
YA position A/D register
XB position A/D register
YB position A/D register
TPLCR
TPLSR
TPLSCR
XPAR
YPAR
XPDR
YPDR
XAPDR
YAPDR
XBPDR
YBPDR
XCPDR
YCPDR
XAPAR
YAPAR
XBPAR
YBPAR
0x0020
0x0021
0x0022
0x0024
0x0026
0x0028
0x002A
0x002C
0x002E
0x0030
0x0032
0x0034
0x0036
0x0038
0x003A
0x003C
0x003E
R/W
R/W
R/W
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1 byte
1 byte
1 byte
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
XC position A/D register
YC position A/D register
DX dot register
DY dot register
X position dot calculation A/D value
X position A/D value 1
X position A/D value 2
XCPAR
YCPAR
DXDR
DYDR
XPARDOT
XPARDOT1
XPARDOT2
0x0040
0x0042
0x0044
0x0046
0x0048
0x004A
0x004C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
X position A/D value 3
X position A/D value 4
XPARDOT3
XPARDOT4
0x004E
0x0050
R/W
R/W
2 bytes
2 bytes
Y position dot calculation A/D value
Y position A/D value 1
YPARDOT
YPARDOT1
0x0052
0x0054
R/W
R/W
2 bytes
2 bytes
Y position A/D value 2
Y position A/D value 3
YPARDOT2
YPARDOT3
0x0056
0x0058
R/W
R/W
2 bytes
2 bytes
Y position A/D value 4
RTC/Touch Panel/Key Input/Power Supply
Status Register
YPARDOT4
RTKISR
0x005A
0x0090
R/W
R/W
2 bytes
1 byte
Remarks
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.4.1 Touch Panel Control Register (TPLCR)
Address: 0x0020 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
0
R
0
R
0
R
0
R
PEN_ONRE
PEN_OFFI
R/W
PEN_ONI
R/W
TP_STR
R/W
R/W
(1) TP_STR
TP_STR bit
0
Setting
The touch panel is disabled. (Initial value)
1
The touch panel is enabled.
(2) PEN_ONI
PEN_ONI bit
Setting
0
A pen touch ON interrupt is not generated. (Initial value)
1
A pen touch ON interrupt is generated.
(3) PEN_OFFI
PEN_OFFI bit
Setting
0
A pen touch OFF interrupt is not generated. (Initial value)
1
A pen touch OFF interrupt is generated.
(4) PEN_ONRE
PEN_ ONRE bit
0
1
Setting
A pen touch ON interrupt is not generated when pen touch
continues. (Initial value)
A pen touch ON interrupt is generated when pen touch
continues.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.4.2 Touch Panel Status Register (TPLSR)
Address: 0x0021 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
0
R
0
R
0
R
0
R
0
R
PEN_OFFIF
R/W
PEN_ONIF
R/W
0
R
(1) PEN_ONIF
PEN_ONIF bit
0
1
Setting
The touch panel has not been pen-touched. (pen touch OFF.)
(Initial value)
The pen-touch state on the touch panel has been changed from
OFF to ON. The touched positions on the touch panel are output to
the X position A/D register, Y position A/D register, X position dot
register and Y position dot register. At this time, a pen touch ON
interrupt is generated if the PEN_ONI bit is set to “1.’’
[Clear condition]
“0’’ is written with the PEN_ONIF bit set to ‘’1.’’
(2) PEN_OFFIF
PEN_OFFIF bit
0
1
Setting
The touch panel has not been pen-touched. (pen touch OFF.)
(Initial value)
The pen-touch state on the touch panel has been changed from ON
to OFF. At this time, a pen touch OFF interrupt is generated if the
PEN_OFFI bit is set to “1.’’
[Clear condition]
“0’’ is written with the PEN_OFFIF bit set to ‘’1.’’
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.4.3 Touch panel Sampling Control Register (TPLSCR)
The touch panel sampling control register sets a sampling interval for the touch panel.
Address: 0x0022 Initial value: 0x01
D7
160mse
c
R/W
D6
D5
D4
D3
D2
D1
D0
140msec
120msec
100msec
80msec
60msec
40msec
20msec
R/W
R/W
R/W
R/W
R/W
R/W
R/W
A sampling interval for the touch panel can be set within a range from 20msec to 160msec (unit: 20msec).
When a bit is set to “1,” the corresponding sampling interval from 20msec to 160msec is set. Note that only
the following values can be specified.
• Correspondence between the setting values and sampling intervals
0x01: 20msec
0x02: 40msec
0x04: 60msec
0x08: 80msec
0x10: 100msec
0x20: 120msec
0x40: 140msec
0x80: 160msec
6.4.4 X Position A/D Register (XPAR)
Address: 0x0024 Initial value: 0x000
D15
D14
D13
D12
D11
D10
D9
D8
0
R
0
R
0
R
0
R
XA_D11
R
XA_D10
R
XA_D9
R
XA_D8
R
D7
D6
D5
D4
D3
D2
D1
D0
XA_D7
R
XA_D6
R
XA_D5
R
XA_D4
R
XA_D3
R
XA_D2
R
XA_D1
R
XA_D0
R
The X position A/D register indicates the A/D conversion result of a pen-touched X position on the touch panel.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.4.5 Y Position A/D Register (YPAR)
Address: 0x0026 Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R
0
R
0
R
0
R
YA_D11
R
YA_D10
R
YA_D9
R
YA_D8
R
D7
D6
D5
D4
D3
D2
D1
D0
YA_D7
R
YA_D6
R
YA_D5
R
YA_D4
R
YA_D3
R
YA_D2
R
YA_D1
R
YA_D0
R
The Y position A/D register indicates the A/D conversion result of a pen-touched Y position on the touch panel.
6.4.6 X Position Dot Register (XPDR)
Address: 0x0028 Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
XD_D15
R
XD_D14
R
XD_D13
R
XD_D12
R
XD_D11
R
XD_D10
R
XD_D9
R
XD_D8
R
D7
D6
D5
D4
D3
D2
D1
D0
XD_D7
R
XD_D6
R
XD_D5
R
XD_D4
R
XD_D3
R
XD_D2
R
XD_D1
R
XD_D0
R
The X position dot register indicates the dot position of a pen-touched X position on the touch panel. Use the
output value of this register after calibration. The output value is not settled without calibration.
6.4.7 Y Position Dot Register (YPDR)
Address: 0x002A Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
YD_D15
R
YD_D14
R
YD_D13
R
YD_D12
R
YD_D11
R
YD_D10
R
YD_D9
R
YD_D8
R
D7
D6
D5
D4
D3
D2
D1
D0
YD_D7
R
YD_D6
R
YD_D5
R
YD_D4
R
YD_D3
R
YD_D2
R
YD_D1
R
YD_D0
R
The Y position dot register indicates the dot position of a pen-touched Y position on the touch panel. Use the
output value of this register after calibration. The output value is not settled without calibration.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.4.8 XA Position Dot Register (XAPDR)
Address: 0x002C Initial value: 0x0000
D15
D14
D13
D12
D11
D10
XAD_D15
XAD_D14
XAD_D13
XAD_D12
XAD_D11
R/W
R/W
R/W
R/W
R/W
XAD_D1
0
R/W
D9
D8
XAD_D9
XAD_D8
R/W
R/W
D7
D6
D5
D4
D3
D2
D1
D0
XAD_D7
R/W
XAD_D6
R/W
XAD_D5
R/W
XAD_D4
R/W
XAD_D3
R/W
XAD_D2
R/W
XAD_D1
R/W
XAD_D0
R/W
The XA position dot register indicates the X dot position of point A when calibration takes place.
6.4.9 YA Position Dot Register (YAPDR)
Address: 0x002E Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
YAD_D15
R/W
YAD_D14
R/W
YAD_D13
R/W
YAD_D12
R/W
YAD_D11
R/W
YAD_D10
R/W
YAD_D9
R/W
YAD_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
YAD_D7
R/W
YAD_D6
R/W
YAD_D5
R/W
YAD_D4
R/W
YAD_D3
R/W
YAD_D2
R/W
YAD_D1
R/W
YAD_D0
R/W
The YA position dot register indicates the Y dot position of point A when calibration takes place.
6.4.10 XB Position Dot Register (XBPDR)
Address: 0x0030 Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
XBD_D15
R/W
XBD_D14
R/W
XBD_D13
R/W
XBD_D12
R/W
XBD_D11
R/W
XBD_D10
R/W
XBD_D9
R/W
XBD_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
XBD_D7
R/W
XBD_D6
R/W
XBD_D5
R/W
XBD_D4
R/W
XBD_D3
R/W
XBD_D2
R/W
XBD_D1
R/W
XBD_D0
R/W
The XB position dot register indicates the X dot position of point B when calibration takes place.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.4.11 YB Position Dot Register (YBPDR)
Address: 0x0032 Initial value: 0x0000
D15
YBD_D1
5
R/W
D7
YBD_D
7
R/W
D14
D13
YBD_D14
YBD_D13
R/W
R/W
D12
D11
YBD_D1
2
R/W
YBD_D1
1
R/W
D10
D9
D8
YBD_D10
YBD_D9
YBD_D8
R/W
R/W
R/W
D6
D5
D4
D3
D2
D1
D0
YBD_D6
YBD_D5
YBD_D4
YBD_D3
YBD_D2
YBD_D1
YBD_D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The YB position dot register indicates the Y dot position of point B when calibration takes place.
6.4.12 XC Position Dot Register (XCPDR)
Address: 0x0034 Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
XCD_D15
R/W
XCD_D14
R/W
XCD_D13
R/W
XCD_D12
R/W
XCD_D11
R/W
XCD_D10
R/W
XCD_D9
R/W
XCD_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
XCD_D7
R/W
XCD_D6
R/W
XCD_D5
R/W
XCD_D4
R/W
XCD_D3
R/W
XCD_D2
R/W
XCD_D1
R/W
XCD_D0
R/W
The XC position dot register indicates the X dot position of point C when calibration takes place. This register
will be functionally enhanced in future. Don’t access this register.
6.4.13 YC Position Dot Register (YCPDR)
Address: 0x0036 Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
YCD_D15
R/W
YCD_D14
R/W
YCD_D13
R/W
YCD_D12
R/W
YCD_D11
R/W
YCD_D10
R/W
YCD_D9
R/W
YCD_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
YCD_D7
R/W
YCD_D6
R/W
YCD_D5
R/W
YCD_D4
R/W
YCD_D3
R/W
YCD_D2
R/W
YCD_D1
R/W
YCD_D0
R/W
The YC position dot register indicates the Y dot position of point C where calibration takes place.
register will be functionally enhanced in future. Don’t access this register.
This
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.4.14 XA Position A/D Register (XAPAR)
Address: 0x0038 Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R
0
R
0
R
0
R
XAA_D11
R/W
XAA_D10
R/W
XAA_D9
R/W
XAA_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
XAA_D7
R/W
XAA_D6
R/W
XAA_D5
R/W
XAA_D4
R/W
XAA_D3
R/W
XAA_D2
R/W
XAA_D1
R/W
XAA_D0
R/W
The XA position A/D register indicates the X position A/D conversion result of point A subject to calibration/
6.4.15 YA Position A/D Register (YAPAR)
Address: 0x003A Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R
0
R
0
R
0
R
YAA_D11
R/W
YAA_D10
R/W
YAA_D9
R/W
YAA_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
YAA_D7
R/W
YAA_D6
R/W
YAA_D5
R/W
YAA_D4
R/W
YAA_D3
R/W
YAA_D2
R/W
YAA_D1
R/W
YAA_D0
R/W
The YA position A/D register indicates the Y position A/D conversion result of point A subject to calibration.
6.4.16 XB Position A/D Register (XBPAR)
Address: 0x003C Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R
0
R
0
R
0
R
XBA_D11
R/W
XBA_D10
R/W
XBA_D9
R/W
XBA_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
XBA_D7
R/W
XBA_D6
R/W
XBA_D5
R/W
XBA_D4
R/W
XBA_D3
R/W
XBA_D2
R/W
XBA_D1
R/W
XBA_D0
R/W
The XB position A/D register indicates the X position A/D conversion result of point B subject to calibration.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.4.17 YB Position A/D Register (YBPAR)
Address: 0x003E Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R
0
R
0
R
0
R
YBA_D11
R/W
YBA_D10
R/W
YBA_D9
R/W
YBA_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
YBA_D7
R/W
YBA_D6
R/W
YBA_D5
R/W
YBA_D4
R/W
YBA_D3
R/W
YBA_D2
R/W
YBA_D1
R/W
YBA_D0
R/W
The YB position A/D register indicates the Y position A/D conversion result of point B subject to calibration.
6.4.18 XC Position A/D Register (XCPAR)
Address: 0x0040 Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R
0
R
0
R
0
R
XCA_D11
R/W
XCA_D10
R/W
XCA_D9
R/W
XCA_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
XCA_D7
R/W
XCA_D6
R/W
XCA_D5
R/W
XCA_D4
R/W
XCA_D3
R/W
XCA_D2
R/W
XCA_D1
R/W
XCA_D0
R/W
The XC position A/D register indicates the X position A/D conversion result of point C subject to calibration.
This register will be functionally enhanced in future. Don’t access this register.
6.4.19 YC Position A/D Register (YCPAR)
Address: 0x0042 Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R
0
R
0
R
0
R
YCA_D11
R/W
YCA_D10
R/W
YCA_D9
R/W
YCA_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
YCA_D7
R/W
YCA_D6
R/W
YCA_D5
R/W
YCA_D4
R/W
YCA_D3
R/W
YCA_D2
R/W
YCA_D1
R/W
YCA_D0
R/W
The YC position A/D register indicates the Y position A/D conversion result of point C subject to calibration.
This register will be functionally enhanced in future. Don’t access this register.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.4.20 DX Dot Register (DXDR)
Address: 0x0044 Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
DX1_D15
R/W
DX1_D14
R/W
DX1_D13
R/W
DX1_D12
R/W
DX1_D11
R/W
DX1_D10
R/W
DX1_D9
R/W
DX1_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
DX1_D7
R/W
DX1_D6
R/W
DX1_D5
R/W
DX1_D4
R/W
DX1_D3
R/W
DX1_D2
R/W
DX1_D1
R/W
DX1_D0
R/W
The DX dot register holds a value obtained by multiplying the number of dots per data (X position A/D
conversion result at calibration) by 1,000.
The power supply controller outputs a dot position of the X
position to be stored in the X position dot register (XPDR) from the values set in the DX dot register (DXDR),
XA position dot register (XAPDR) and XA position A/D register (XAPAR). When the DX dot register (DXDR)
has been set to “0,” the dot position is not calculated.
6.4.21 DY Dot Register (DYDR)
Address: 0x0046 Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
DY1_D15
R/W
DY1_D14
R/W
DY1_D13
R/W
DY1_D12
R/W
DY1_D11
R/W
DY1_D10
R/W
DY1_D9
R/W
DY1_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
DY1_D7
R/W
DY1_D6
R/W
DY1_D5
R/W
DY1_D4
R/W
DY1_D3
R/W
DY1_D2
R/W
DY1_D1
R/W
DY1_D0
R/W
The DY dot register (DY1DR) holds a value obtained by multiplying the number of dots per data (Y position
A/D conversion result at calibration) by 1,000. The power supply controller outputs a dot position of the Y
position to be stored in the Y position dot register (YPDR) from the values set in the DY dot register (DYDR),
YA position dot register (YAPDR) and YA position A/D register (YAPAR). When the DY dot register (DY1DR)
has been set to “0,” the dot position is not calculated.
R0P7760TH001TRK User’s Manual
6.4.22
Power Supply Controller
X Position Dot Calculation A/D Value (XPARDOT)
Address: 0X0048 Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
XD_D9
R/W
XD_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
XD_D7
R/W
XD_D6
R/W
XD_D5
R/W
XD_D4
R/W
XD_D3
R/W
0
R/W
0
R/W
0
R/W
The X position dot calculation A/D value register (XPARDOT) holds an AD value of X position dot calculation.
This A/D value is obtained by calculating the mean of the previous four XPARDOT values and clearing the low
order 3 bits with zeros.
6.4.23 X Position Dot Calculation A/D Value 1 (XPARDOT1)
Address: 0x004A Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
XD1_D9
R/W
XD1_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
XD1_D7
R/W
XD1_D6
R/W
XD1_D5
R/W
XD1_D4
R/W
XD1_D3
R/W
0
R/W
0
R/W
0
R/W
The X position dot calculation A/D value 1 register (XPARDOT1) holds an XPARDOT value before
sampling.
6.4.24 X Position Dot Calculation A/D Value 2 (XPARDOT2)
Address: 0x004C Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
XD2_D9
R/W
XD2_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
XD2_D7
R/W
XD2_D6
R/W
XD2_D5
R/W
XD2_D4
R/W
XD2_D3
R/W
0
R/W
0
R/W
0
R/W
The X position dot calculation A/D value 2 register (XPARDOT2) holds an XPARDOT value before sampling.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.4.25 X Position Dot Calculation A/D Value 3 (XPARDOT3)
Address: 0x004E Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
XD3_D9
R/W
XD3_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
XD3_D7
R/W
XD3_D6
R/W
XD3_D5
R/W
XD3_D4
R/W
XD3_D3
R/W
0
R/W
0
R/W
0
R/W
The X position dot calculation A/D value 3 register (XPARDOT3) holds an XPARDOT value before
sampling.
6.4.26 X Position Dot Calculation A/D value 4 (XPARDOT4)
Address: 0x0050 Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
XD4_D9
R/W
XD4_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
XD4_D7
R/W
XD4_D6
R/W
XD4_D5
R/W
XD4_D4
R/W
XD4_D3
R/W
0
R/W
0
R/W
0
R/W
The X position dot calculation A/D value 4 register (XPARDOT4) holds an XPARDOT value before sampling.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.4.27 Y Position Dot Calculation A/D Value (YPARDOT)
Address: 0x0052 n
I itial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
YD_D9
R/W
YD_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
YD_D7
R/W
YD_D6
R/W
YD_D5
R/W
YD_D4
R/W
YD_D3
R/W
0
R/W
0
R/W
0
R/W
The Y position dot calculation A/D value register (YPARDOT) holds an A/D value of Y position dot calculation.
This A/D value is obtained by calculating the mean of the previous four YPARDOT values and clearing the
following 3 bits with zeros.
6.4.28
Y Position Dot Calculation A/D Value 1 (YPARDOT1)
Address: 0 x0054 Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
YD1_D9
R/W
YD1_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
YD1_D7
R/W
YD1_D6
R/W
YD1_D5
R/W
YD1_D4
R/W
YD1_D3
R/W
0
R/W
0
R/W
0
R/W
The Y position dot calculation A/D value 1 register (YPARDOT1) holds a YPARDOT value before sampling.
6.4.29
Y Position Dot Calculation A/D Value 2 (YPARDOT2)
Address: 0x0056 Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
YD2_D9
R/W
YD2_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
YD2_D7
R/W
YD2_D6
R/W
YD2_D5
R/W
YD2_D4
R/W
YD2_D3
R/W
0
R/W
0
R/W
0
R/W
The Y position dot calculation A/D value 2 register (YPARDOT2) holds a YPARDOT value before sampling.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.4.30 Y Position Dot Calculation A/D Value 3 (YPARDOT3)
Address: 0x0058 Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
YD3_D9
R/W
YD3_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
YD3_D7
R/W
YD3_D6
R/W
YD3_D5
R/W
YD3_D4
R/W
YD3_D3
R/W
0
R/W
0
R/W
0
R/W
The Y position dot calculation A/D value 3 register (YPARDOT3) holds a YPARDOT value before
sampling.
6.4.31 Y Position Dot Calculation A/D Value 4 (YPARDOT4)
Address: 0x005A Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
YD4_D9
R/W
YD4_D8
R/W
D7
D6
D5
D4
D3
D2
D1
D0
YD4_D7
R/W
YD4_D6
R/W
YD4_D5
R/W
YD4_D4
R/W
YD4_D3
R/W
0
R/W
0
R/W
0
R/W
The Y position dot calculation A/D value 4 register (YPARDOT4) holds a YPARDOT value before
sampling.
6.4.32 RTC/Touch Panel/Key Input/Power Supply Status Register (RTKISR)
This status register indicates the RTC, touch panel, or key input status. Below is a brief description of the
status bits related to the touch panel.
Address: 0x0090 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
0
R
0
R
0
R
IRRIF
R/W
POWERIF
R/W
KEYIF
R/W
TPIF
R/W
RTCIF
R/W
(1) TPIF
TPIF bit
0
1
Setting
The PEN_ONIF, PEN_OFFIF, CAIF and CAEF bits of the touch
panel status registered are all set to “0.’’ (Initial value)
One of the PEN_ONIF, PEN_OFFIF, CAIF and CAEF bits of the
touch panel status register is set to “1.’’
[Clear condition]
“0’’ is written with the TPIF bit set to “1.’’
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.4.33 Touch Panel Calibration Method (2-point System)
The power supply controller supports 2-point touch panel calibration. Figure 6.11shows the points of the
drawing coordinates and A/D conversion coordinates that are necessary for calibration.
Origin of drawing
coordinates
T-Engine Board
Drawing coordinates: x axis
Point B
A/D conversion coordinates: y axis
Drawing coordinates: y axis
LCD
Point A
A/D conversion
coordinates
A/D conversion coordinates: x axis
SW2
SW1
SW3
Figure 6.11 Points of the Drawing Coordinates and A/D Conversion Coordinates
R0P7760TH001TRK User’s Manual
Power Supply Controller
[Calibration Method]
(1)
The SH7760 writes the dot points of points A and B to the registers XAPDR, YAPDR, XBPDR, and
YBPDR.
(2)
When point A is pen-touched, it is signaled by a pen touch interrupt. The A/D conversion result of
the pen-touched point A is written to the registers XAPAR and YAPAR.
(3)
Next, when point B is pen-touched, it is signaled by a pen touch interrupt. The A/D conversion
result of the pen-touched point B is written to the registers XBPAR and YBPAR.
(4)
Calibration takes place according to data in the above steps (1) to (3).
Using the following
expression, the SH7760 calculates the number of dots per data of the X position A/D conversion
result and that of the Y position A/D conversion result.
Number of dots per data of the X position A/D conversion result (DX)
DX = (DXA – DXB) / (TXB – TXA)
Where TXA < TXB, DXA > DXB
Number of dots per data of the Y position A/D conversion result (DY)
DY = (DYA – DYB) / (TYB- TYA)
Where TYA < TYB, DYA > DYB
DXA: X position drawing dot point of point A (XAPDR)
DXB: X position drawing dot point of point B (XBPDR)
TXA: X position A/D conversion result of point A (XAPAR)
TXB: X position A/D conversion result of point B (XBPAR)
DYA: Y position drawing dot point of point A (YAPDR)
DYB: Y position drawing dot point of point B (YBPDR)
TXA: Y position A/D conversion result of point A (YAPAR)
TXB: Y position A/D conversion result of point B (YBPAR)
（5）
The above calculation results are multiplied by 1,000, their decimal places are rounded, and the
resulting integers are written to the registers DXDR and DYDR.
DX dot register (DXDR) = DX x 1,000 (rounding the decimal places)
DY dot register (DYDR) = DY x 1,000 (rounding the decimal places)
（6）
The power supply controller uses data stored in the registers DXDR, DYDR, XAPDR,
YAPDR, XAPAR, and YAPAR to calculate dot position data (XPDR, YPDR) of the pentouched point on the LCD. The power supply controller uses the following expression to
calculate dot position data.
X position dot register (XPDR)
XPDR = (DXA – (DX x (TXD – TXA)) / 1,000
Y position dot register (YPDR)
YPDR = (DYA – (DY x (TYD – TYA)) / 1,000
DXA: XA position dot register (XAPDR) data
DX: DX1 dot register (DXDR) data
TXA: XA position A/D register (XAPAR) data
TXD: X position A/D register (XPAR) data
DYA: YA position dot register (YAPDR) data
DY: DY dot register (DYDR) data
TYA: YA position A/D register (YAPAR) data
TYD: X position A/D register (YPAR) data
The power supply controller outputs data stored in the X position A/D register (XPAR) and Y
position A/D register (YPAR). When the values stored in the DX dot register (DXDR) and DY dot
register (DYDR) are not 0, the power supply controller outputs the data derived from the above
expressions to the X position dot register (XPDR) and Y position dot register (YPDR). When
either value is 0, it does not use the above expression for calculation and outputs only XPAR and
YPAR data.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.5 Key Switch Control
Figure 6.12 shows the T-Engine switches under control by the power supply controller. The power supply
controller controls the switches SW1 to SW3 on the CPU board and the switches SW1to SW3 on the LCD
board.
Power-on switch
SW1
T-Engine Board
SW1
CPU board
switch
Reset switch
SW2
LCD
SW2
NMI switch
SW3
SW2
SW2
SW1
Application switch
Figure 6.12 T-Engine Switch
SW3
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.5.1 CPU Board Switch Control
(1) Power-on switch (SW1)
l
When the SH7760 is being powered, a power-on switch interrupt occurs for the SH7760 if
the power-on switch is pressed and held for 2 seconds or more.
l
When T-Engine is OFF, it is turned ON if the power-on switch is pressed and held for 0.5
seconds or more.
l
When T-Engine is ON, it is turned OFF if the power-on switch is pressed and held for 2
seconds or more.
(2) Reset switch (SW2)
T-Engine is turned OFF when the reset switch is pressed.
(3) NMI switch (SW3)
An NMI interrupt occurs for the SH7760 when the NMI switch is pressed.
6.5.2 LCD Board Switch Control (Application Switch)
(1)
Cursor switch (SW1) and push-button switches (SW2 and SW3) on the LCD board
l
The cursor switch and push-button switches are subject to sampling at intervals of 10msec.
When consecutive three samplings indicate that the same key is being pressed, key bit pattern
data of the cursor switch and push-button switches are output.
l
If the switch is turned ON, a key ON interrupt occurs. If the switch is turned OFF, a key OFF
interrupt occurs.
l
When the same switch is pressed and held, an auto repeat interrupt occurs at intervals of 100 to
450msec (unit: 50msec).
6.5.3 Key Switch Registers
Table 6.5 summarizes the key switch registers. For details of each register, refer to 6.5.4 to 6.5.8.
Table 6.5 Key Switch Registers
Register
Abbreviation
Address
R/W
Size
Key control register
Key auto repeat time register
Key bit pattern register
Key input status register
RTC/Touch panel/key input/Power supply
status register
KEYCR
KATIMER
KBITPR
KEYSR
RTKISR
0x0060
0x0061
0x0064
0x0062
0x0090
R/W
R/W
R/W
R/W
R/W
1 byte
1 byte
2 bytes
1 byte
1 byte
Remarks
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.5.4 Key Control Register (KEYCR)
Address: 0x0060 Initial value: 0x20
D7
D6
D5
D4
0
R
0
R
NMIE
R/W
PONSWI
R/W
D3
D2
D1
D0
ARKEYI
R/W
KEY_OFFI
R/W
KEY_ONI
R/W
KEY_STR
R/W
(1) KEY_STR
KEY_STR bit
Setting
0
An application switch key input is disabled. (Initial value)
1
An application switch key input is enabled.
(2) KEY_ONI
KEY_ONI bit
Setting
0
An application switch ON interrupt is disabled. (Initial value)
1
An application switch key ON interrupt is enabled.
(3) KEY_OFFI
KEY_OFFI bit
Setting
0
An application switch OFF interrupt is disabled. (Initial value)
1
An application switch key OFF interrupt is enabled.
(4) ARKEYI
ARKEYI bit
0
1
Setting
An application switch auto repeat interrupt is disabled. (Initial
value)
An application switch auto repeat interrupt is enabled.
(5) PONSWI
PONSWI bit
0
Setting
A power-on switch interrupt is disabled. (Initial value)
1
A power-on switch interrupt is enabled.
(6) NMIE
NMIE bit
0
1
Setting
An NMI interrupt is disabled for the SH7760 even when the NM I
switch is pressed.
An NMI interrupt is disabled for the SH7760 when the NMI switch
is pressed. (Initial value)
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.5.5 Key Auto Repeat Time Register (KATIMER)
Address: 0x0061 Initial value: 0x01
D7
D6
D5
D4
450msec
R/W
400msec
R/W
350msec
R/W
300msec
R/W
D3
D2
D1
D0
250msec
R/W
200msec
R/W
150msec
R/W
100msec
R/W
This register sets the auto repeat interrupt generation time. The auto repeat interrupt generation time is set
at intervals of 100msec to 450msec (unit: 50msec). When one of the bits (100msec to 450msec) is set, the
corresponding auto repeat interrupt generation time is set.
6.5.6 Key Bit Pattern Register (KBIPR)
Address: 0x0064 Initial value: 0x0000
D15
D14
D13
D12
D11
D10
D9
D8
0
R
0
R
0
R
0
R
0
R
SW2
R
0
R
SW3
R
D7
D6
D5
D4
0
0
0
R
R
R
SW1-5
(Decided)
R
D3
SW1-4
(↓)
R
D2
D1
SW1-3
(↑)
R
SW1-2
(←)
R
D0
SW1-1
(→)
R
This register stores the bit pattern of the application switch (SW1 to SW3) key input status.
(1) SWn
SWn bit
Setting
0
Application switch key input: OFF (Initial value)
1
Application switch key input: ON
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.5.7 Key Input Status Register (KEYSR)
Address: 0x0062 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
0
R
0
R
0
R
PONSWF
R/W
ARKEYF
R/W
KEY_OFFF
R/W
KEY_ONF
R/W
0
R
(1) KEY_ONF
KEY_ONF bit
0
1
Setting
An application switch key has not been turned on (Initial value)
An application switch key has been turned on. At this time, if the
KEY_ONI bit is set to ‘’1,’’ a key ON interrupt occurs.
[Clear condition]
“0’’ is written with the KEY_ONF bit set to ‘’1.’’
(2) KEY_OFFF
KEY_OFFF bit
0
1
Setting
An application switch key is ON or OFF. (Initial value)
An application switch key has changed from ON to OFF. (Initial
value) At time, if the KEY_OFFI bit is set to “1,’’ a key OFF
interrupt occurs.
[Clear condition]
“0’’ is written with the KEY_OFFI bit set to ‘’1.’’
(3) ARKEYF
ARKEYF bit
0
1
Setting
The same application switch key is not ON for the time specified
in the key auto repeat time register (Initial value)
The same application switch key is not ON for the time specified
in the key auto repeat time register. At this time, if the ARKEYI
bit is set to ‘’1,’’ repeat interrupt occurs.
[Clear condition]
‘’0’’ is written with the ARKEYF bit set to “1.’’
(4) PONSWF
PONSWF bit
0
Setting
The power-on switch has not been turned on for 2sec or more.
on switch has been turned on for 2 sec or more.
At this time, if the PONSWI bit is set to “1,” a power-on interrupt
1
occurs.
[Clear condition]
“0” is written to the PONSWF bit set to “1.”
R0P7760TH001TRK User’s Manual
Power Supply Controller
[Supplementary description on application switch key input]
(1) When multiple keys are pressed at the same time, the corresponding bits are all set to “1,” and a
KEY_ONF interrupt occurs so long as it is enabled.
(2) If data in the key bit pattern register changes when multiple keys are pressed at the same time, a
KEY_ONF interrupt occurs so long as it is enabled.
- Example This KEY_ONF interrupt occurs when the state with switches SW1 and SW2 pressed simultaneously
changes to one with switches SW1 and SW3 pressed simultaneously.
(3) When multiple keys are released in the state with the keys pressed and held, a KEY_OFFI interrupt
occurs so long as it is enabled.
(4) When multiple keys are released, the key states immediately before key release are retained in the key
bit pattern register.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.5.8 RTC/Touch Panel/Key Input/Power Supply Status Register (RTKISR)
This status register indicates the RTC, touch panel, or key input status. Below is a brief description of the
status bits for key input.
Address: 0x0090 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
0
R
0
R
0
R
IRRIF
R/W
POWERIF
R/W
KEYIF
R/W
TPIF
R/W
RTCIF
R/W
(1) KEYIF
KEYIF bit
0
1
[Clear condition]
Setting
The PONSWF, ARKEYF, KEY_OFFF, and KEY_ONF bits of the
key input status register are all set to “0.” (Initial value)
One of the PONSWF, ARKEYF, KEY_OFFF, or KEY_ONF bits of
the key input status register is set to “1.”
“0” is written with the KEYIF bit set to “1.”
6.6 Power Supply Control
This section describes the power supply control functions. Table 6.6 summarizes the power supply control
registers. In addition, refer to 6.6.1 to 6.6.3 for details of each register.
(1) T-Engine is turned ON or OFF.
(2) When T-Engine is OFF, it is turned ON if the power-on switch is pressed for 2 seconds or more.
(3) T-Engine can be turned OFF from the SH7760.
(4) If the DIP switch (SW7) is set to ON, T-Engine is also turned ON at the same time the power supply
controller is turned ON.
Table 6.6 Power Control Registers
Register
Abbreviation
Address
R/W
Size
System power control register 1
System power control register 2
SPOWCR1
SPOWCR2
0x0070
0x0071
R/W
R/W
1 byte
1 byte
Remarks
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.6.1 System Power Control Register 1 (SPOWCR1)
Address: 0x0070 Initial value: 0x01
D7
D6
D5
D4
D3
D2
D1
D0
0
R
0
R
0
R
0
R
0
R
0
R
0
R
SPOWER
R/W
(1) SPOWER
SPOWER bit
Setting
0
System power supply: OFF
1
System power supply: ON (Initial value)
6.6.2 System Power Control Register 2 (SPOWCR2)
Address: 0x0071 Initial value: 0x01
D7
D6
D5
D4
D3
D2
D1
D0
0
R
0
R
0
R
0
R
0
R
0
R
0
R
SFPOWER
R/W
(2) SFPOWER
SFPOWER
0
1
Setting
T-Engine is turned OFF by SH7760 control.
T-Engine is turned OFF by pressing the power-on switch. (Initial value)
6.6.3 RTC/Touch Panel/Key Input/Power Supply Status Register (RTKISR)
This status register indicates the RTC, touch panel, or key input status. Below is a brief description of the
status bits for power control.
Address: 0x0090 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
0
R
0
R
0
R
IRRIF
R/W
POWERIF
R/W
KEYIF
R/W
TPIF
R/W
RTCIF
R/W
(1) POWERIF
This bit will be functionally enhanced in the future. Don’t access this register. When read, this bit is
always 0.”
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.7 LCD Front Light Control
This section describes the LCD light control functions. In addition, Table 6.7 summarizes the front light control
registers.
(1) Controlling the ON/OFF state of the LCD front light
Table 6.7 LCD front light register
Register
Abbreviatio
n
Addres
s
R/W
Size
LCD front light register
LCDR
0x00A1
R/W
1
byte
Remarks
6.7.1 LCD Front Light Register (LCDR)
Address: 0x00A1 Initial value: 0x01
D7
D6
D5
D4
D3
D2
D1
D0
0
R
0
R
0
R
0
R
0
R
0
R
0
R
FRONTL
R/W
(1) FRONTL
FRONTL bit
0
1
Setting
The LCD front light is turned ON.
The LCD front light is turned OFF. (Initial value)
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.8 Reset Control
This section describes the reset control functions. Table 6.9 summarizes the reset control registers.
(1) T-Engine reset is controlled.
Table 6.9 Reset Registers
Register
Abbreviation
Address
R/W
Size
Reset control register
RESTCR
0x00A2
R/W
1byte
6.8.1 RESTCR Register (RESTCR)
Address: 0x00A2 Initial value: 0x02
D7
D6
D5
D4
D3
D2
D1
D0
0
R
0
R
0
R
0
R
0
R
0
R
SWRES
R/W
SORES
R/W
(1) SORES
SORES bit
0
Setting
T-Engine is not restarted by reset. (Initial value)
1
T-Engine is restarted by reset.
If this bit is set to “1,” T-Engine is restarted.
(2) SWRES
SWRES bit
0
1
Setting
Devices other than the power supply controller are reset with the
reset switch (SW2).
All the devices covering the power supply controller are reset
with the reset switch (SW2). (Initial value)
Remarks
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.9 Infrared Remote Control
This section describes the infrared remote control functions.
Table 6.9 summarizes the infrared remote
control functions. For details of each register, refer to 6.9.1 to 6.9.8.
(1) Support of formats for two kinds of infrared remote control signal
• Supported format: NEC format and Home Appliance Manufacturer’s Association format
(2) Function for receiving infrared remote control signals
• A maximum of 255 bytes of the infrared remote control signal can be stored. Receive data can
be read from the receiving FIFO data register (IRRRFDR).
• Infrared remote control signals of a specified format can be received.
• When a frame signal has been received, a receiving interrupt may be generated.
(3) Function for transmitting infrared remote control signals
• A maximum of 255 bytes of the infrared remote control signal can be transmitted.
• Transmit data can be written to the transmitting FIFO data register (IRRSFDR).
• Infrared remote control signals of the specified format are transmitted.
Table 6.9 Infrared Remote Control Registers
Register
Abbreviation
Address
R/W
Size
Infrared remote control register
Infrared remote status register
Receive data count register
remote control signals
Transmit data count register
remote control signals
Receive FIFO data register
remote control signals
Transmit FIFO data register
remote control signals
IRRCR
IRRSR
0x00B0
0x00B1
R/W
R/W
1 byte
1 byte
IRRRDNR
0x00B2
R
1 byte
IRRSDNR
0x00B3
R
1 byte
IRRRFDR
0x00B4
R
1 byte
IRRSFDR
0x00B5
W
1 byte
for infrared
for infrared
for infrared
for infrared
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.9.1 Infrared Remote Control Register (IRRCR)
Address; 0x00B0 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
0
R
0
R
0
R
0
R
TDIE
R/W
RDIE
R/W
FORMAT
R/W
START
R/W
(1) START
START bit
Setting
Infrared
0 remote control is disabled. (Initial value)
Infrared
remote
control
is
1
transmission/reception.
enabled
to
start
data
(2) FORMAT
FORMAT bit
Setting
0
The NEC format is set. (Initial value)
1
The Home Appliance Manufacturer’s Association format is set.
(3) RDIE
RDIE bit
0
1
Setting
An interrupt is disabled upon completion of receiving a frame of
infrared remote control signal. (Initial value)
An interrupt is enabled upon completion of receiving a frame of
infrared remote control signal.
(4) TDIE
TDIE bit
0
1
Setting
An interrupt is disabled upon completion of transmitting a frame
of infrared remote control signal. (Initial value)
An interrupt is enabled upon completion of transmitting a frame
of infrared remote control signal.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.9.2 Infrared Remote Control Status Register (IRRSR)
Address: 0x00B1 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
TDI
RDI
0
R
R
R
R
R/W
R/W
R
D0
RDBFE
R
R/W
(1) RDBFER
RDBFER bit
Setting
A buffer full error has not occurred during a receive operation.
(Initial value)
A buffer full error has occurred during a receive operation.
0
1
(2) RDI
RDI bit
Setting
0
A frame of data has not been received. (Initial value)
1
A frame of data has been received.
[Clear condition]
“0” is written with the RDI bit set to “1.”
(3) TDI
TDI bit
Setting
A frame of data has not been transmitted.
value)
A frame of data has been transmitted.
[Clear condition]
“0” is written with the TDI bit set to “1.”
0
1
(Initial
6.9.3 Receive Data Count Register for Infrared Remote Control Signals (IRRRDNR)
Address: 0x00B2 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
IRRRD_
D7
R
IRRRD_
D6
R
IRRRD_
D5
R
IRRRD_
D4
R
IRRRD_
D3
R
IRRRD_
D2
R
IRRRD_D
1
R
IRRRD_D
0
R
This register indicates the number of received data items (infrared remote control signals) stored in the receive
FIFO register. When this register is “0x00,” it indicates that there is no data. When the value of this register
is “0xFF,” it indicates that the receive FIFO register is full of data.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.9.4 Transmit Data Count Register for Infrared Remote Control Signals (IRRSDNR)
Address: 0x00B3 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
IRRSD_D7
R
IRRSD_D6
R
IRRSD_D5
R
IRRSD_D4
R
IRRSD_D3
R
IRRSD_D2
R
IRRSD_D1
R
IRRSD_D0
R
This register indicates the number of data items not transmitted (infrared remote control signals) stored in the
transmit FIFO register. When the value of this register is “0x00,” it indicates that there is no data. When the
value of this register is “0xFF,” it indicates that the transmit FIFO buffer is full of data.
6.9.5 Receive FIFO Data Register for Infrared Remote Control Signals (IRRRFDR)
Address: 0x00B4 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
IRRRDR_D7
R
IRRRDR_D6
R
IRRRDR_D5
R
IRRRDR_D4
R
IRRRDR_D3
R
IRRRDR_D2
R
IRRRDR_D1
R
IRRRDR_D0
R
This register is an 8-bit FIFO register for storing received data. All the received data can be obtained from this
register until it is emptied. For details, refer to 6.9.8, “Infrared Remote Control Data Structure.”
6.9.6 Transmit FIFO Data Register for Infrared Remote Control Signals (IRRSFDR)
Address: 0x00B5 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
IRRSDR_D7
W
IRRSDR_D6
W
IRRSDR_D5
W
IRRSDR_D4
W
IRRSDR_D3
W
IRRSDR_D2
W
IRRSDR_D1
W
IRRSDR_D0
W
This register is an 8-bit FIFO register that stores transmission data. Transmission data can be stored until this
register is filled with data. For details, refer to 6.9.8, “Infrared Remote Control Data Structure.”
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.9.7 RTC/Touch Panel/Key Input/Power Supply Status Register (RTKISR)
This status register indicates the RTC, touch panel, or key input status. Below is a brief description of the
status bits for infrared remote control signals.
Address: 0x0090 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
0
R
0
R
0
R
IRRIF
R/W
POWERIF
R/W
KEYIF
R/W
TPIF
R/W
RTCIF
R/W
(1) IRRIF
IRRIF bit
Setting
0
A frame of data has not been transmitted or received. (Initial value)
1
A frame of data has been transmitted or received.
[Clear condition]
“0” is written with the IRRIF bit set to “1.”
6.9.8 Infrared Remote Control Data Structure
The following shows the relation between the infrared remote control data and repeat codes. In addition, it
Remote control
data
LEN
DATA1
DATA2
··········
DATAn
shows a structure of remote control data in the NEC format.
Example) NEC format remote control data
Repeat code
0x00
0x04
Custom 1
Custom 2
Data 1
Data 2
[Infrared Remote Control Operation Procedure]
[Initial setting]
(1) Two kinds of formats are set by selecting the FORMAT bit of the IRRCR register.
(2) The START bit of the IRRCR register is set to “1” to start infrared remote control and infrared signal
reception
(3) To enable an interrupt at the time of receiving a frame of the signal, the RDIE bit is set to “1.”
(4) To enable an interrupt at the time of transmitting a frame of the signal, the TDIE bit is set to “1.”
[For infrared signal reception]
(1) When a frame of data has been received (RDI=1), the IRRIF bit of the RTKISR register is set to
“1.”
(2) When an interrupt at completion of signal reception has been enabled (RDIE=1), an interrupt occurs when
a frame of data is stored in the IRRRFDE register.
(3) To obtain the received data, the receiving FIFO data register (IRRRFDR) is read. The IRRRFDR register
contains a data count (that indicates the number of items of one frame of data received) and the received
data itself. If this register is read, the data count and data itself are output in this order.
(4) The size of received data is set in the received data count register (IRRRDNR). When two frames have
been received, the total data count and the two frames of data are set in the received data count register
(IRRRDNR).
R0P7760TH001TRK User’s Manual
Power Supply Controller
[For infrared signal transmission]
(1) When transmission data is transmitted, it is written to the transmitting FIFO data register. The data count
for one frame of transmission data and the data itself are written to this data register. In addition, this
transmission data count is not counted as transmission data.
(2) The count for data not transmitted is set in the transmission data count register (IRRSDNR).
(3) Data can be written to the transmission data IRRSFDR until the count for data not transmitted (IRRSDNR)
reaches 255.
(4) When a frame of data has been transmitted (TDI=1), the IRRIF bit of the RTKISR register is set to “1.” An
interrupt for transmission completion occurs so long as it is enabled.
CAUTION
l
l
l
l
l
l
l
To change the type of format, the FORMAT value of the same register must be set before the
START bit of the IRRCR register is set to “1.”
When the START bit of the IRRCR register is “0,” transmission/reception is not
guaranteed.
When the specified size is larger than the IRRRDNR value during a read operation, “FF” is set for
excessive read data.
Only the custom code and data code are specified for transmission data, and the leader, stop bit,
frame space, and trailer are automatically added.
When the number of write data items is larger than that of the remaining transmission data (255–
byte transmission data count register IRRSDNR), a data length error occurs.
When the IRRRFDR register has become full during a read operation, the buffer full error bit is set
to “1,” and the data received later is discarded.
The IRRIF bit of the RTKISR register is cleared when “0” is written with the IRRIF bit set to “1.”
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.10 Serial EEPROM Control
This section describes the EEPROM control functions. Table 6.10 summarizes the serial EEPROM control
registers. For details of each register, refer to 6.10.1 to 6.10.3.
(1) Serial EEPROM (512 bytes) can be read and written.
Table 6.10 Serial EEPROM Control Registers
Register
Abbreviation
Address
R/W
Size
EEPROM control register
EEPROM data register
EEPCR
EEPDR
0x00C0
0x0100~0x02FF
R/W
R/W
1 byte
1 byte x 512
6.10.1 EEPROM Control Register (EEPCR)
Address: 0x00C0 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
0
R
0
R
0
R
0
R
0
R
0
R
0
R
START
R/W
(1) START
START bit
Setting
0
The serial EEPROM is disabled. (Initial value)
The1serial EEPROM is enabled.
6.10.2 EEPROM Data Register (EEPDR)
Address: 0x0100 to 0x02FF Initial value: Not defined
D7
D6
D5
D4
D3
D2
D1
D0
EEPDR_D7
R/W
EEPDR_D6
R/W
EEPDR_D5
R/W
EEPDR_D4
R/W
EEPDR_D3
R/W
EEPDR_D2
R/W
EEPDR_D1
R/W
EEPDR_D0
R/W
This register consists of 512 8-bit data in the above format.
EEPDR address
0x0100
0x0101
0x02FE
0x02FF
8 bit
8 bit
8 bit
8 bit
An EEPROM address corresponds to an EEPDR address. When a read/write operation is performed on the
EEPROM, the EEPDR address must be specified for the operation.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.10.3 Serial EEPROM Operation Procedure
[Initial Setting]
(1) The START bit of the EEPCR register is set to “1.”
[For a read/write operation to the serial EEPROM]
(1) An EEPDR address corresponding to an EEPROM address must be specified for a read/write
operation.
CAUTION
When the START bit of the EEPCR register is “0,” read/write data is not guaranteed.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.11 Electronic Volume Control
This section describes the electronic volume control functions. Table 6.11 summarizes the electronic volume
control registers. For details of each register, refer to 6.11.1 and 6.11.2.
(1) An electronic volume value can be set.
An electronic volume value can be set within a range from 0x00 (minimum sound volume) to 0xFF
(maximum sound volume).
(2) Two electronic volume values can be set.
An electronic volume value can be set for the right or left speaker.
Table 6.11 Electronic Volume Control Registers
Register
Abbreviation
Electronic volume data register for the right
EVRDR
speaker
Electronic volume data resister for the left speaker
EVLDR
6.11.1
Address
R/W
Size
0x00D0
R/W
1 byte
0x00D1
R/W
1 byte
Electronic Volume Data Register for the Right Speaker (EVRDR)
Address: 0x00D0 Initial value: 0x00
D7
D6
D5
EVRDR_D7
EVRDR_D
6
EVRDR_D
5
R/W
R/W
R/W
D4
D3
D2
D1
D0
EVRDR_D4
EVRDR_D3
EVRDR_D
2
EVRDR_D1
EVRDR_D
0
R/W
R/W
R/W
R/W
R/W
Values from 0x00 to 0xFF can be set.
6.11.2
Electronic Volume Data Register for the Left Speaker (EVLDR)
Address: 0x00D1 Initial value: 0x00
D7
D6
D5
D4
D3
D2
D1
D0
EVLRD_D7
EVLRD_D6
EVLDR_D5
EVLDR_D4
EVLDR_D3
EVLDR_D
2
EVLDR_D1
EVLDR_D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Values from 0x00 to 0xFF can be set.
R0P7760TH001TRK User’s Manual
Power Supply Controller
6.12 Power Supply Controller Initial Values
The register values for the power supply controller vary depending on the following conditions.
Under
condition A, all the power supply controller registers are initialized. The initial value of each register is given
in the description of each register in this manual.
For register values under conditions A to D, refer to the following table of RTC registers.
[Condition]
Condition A: The power is turned ON.
The hard reset switch (SW4) is pressed.
Condition B: The power is turned ON.
The RESTCR SORES bit has been set to “1.”
The RESTCR SWRES bit has been set to “1,” and the reset switch (SW2) has been pressed.
Condition C: The RESTCR SWES bit has been cleared to zero and the reset switch (SW2) has been
pressed.
Condition D: The SPOWCR1 SPOWER bit has been set to “0.”
Table 6.12 Values under RTC Register Conditions
Register
Abbreviatio
n
Condition A
Condition B
Condition C
Condition D
RTC control register
RTC status register
Second counter
Minute counter
Hour counter
Day-of-the-week counter
Day counter
Month counter
Year counter
Second alarm counter
Minute alarm counter
Hour alarm counter
Day-of-the-week alarm counter
Day alarm counter
Month alarm counter
RTC/Touch Panel/Key Input/Power
Supply status register
RTCCR
RTCSR
SECCNT
MINCNT
HRCNT
WKCNT
DAYCNT
MONCNT
YRCNT
SECAR
MINAR
HRAR
WKAR
DAYAR
MONAR
RTKISR
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Hold
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Hold
Hold
Hold
Hold
Hold
Hold
Initial value
Hold
Hold
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Initial value
Hold
Operation
Operation
Operation
Operation
Operation
Operation
Operation
Hold
Hold
Hold
Hold
Hold
Hold
Initial value
R0P7760TH001TRK User’s Manual
Power Supply Controller
Figure 6.13 Values under Touch Panel Register Conditions
Register
Abbreviation
Condition A
Condition B
Condition C
Condition D
Touch panel control register
Touch panel status register
Touch panel sampling control register
X position A/D register
Y position A/D register
X position dot register
Y position dot register
XA position dot register
YA position dot register
XB position dot register
YB position dot register
XC position dot register
YC position dot register
XA position A/D register
YA position A/D register
XB position A/D register
YB position A/D register
TPLCR
TPLSR
TPLSCR
XPAR
YPAR
XPDR
YPDR
XAPDR
YAPDR
XBPDR
YBPDR
XCPDR
YCPDR
XAPAR
YAPAR
XBPAR
YBPAR
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
XC position A/D register
YC position A/D register
DX dot register
DY dot register
XCPAR
YCPAR
DXDR
DYDR
Initial value
Initial value
Initial value
Initial value
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
X position dot calculation A/D value
X position dot calculation A/D value 1
XPARDOT
XPARDOT1
Initial value
Initial value
Hold
Hold
Hold
Hold
Hold
Hold
X position dot calculation A/D value 2
X position dot calculation A/D value 3
XPARDOT2
XPARDOT3
Initial value
Initial value
Hold
Hold
Hold
Hold
Hold
Hold
X position dot calculation A/D value 4
Y position dot calculation A/D value
XPARDOT4
YPARDOT
Initial value
Initial value
Hold
Hold
Hold
Hold
Hold
Hold
Y position dot calculation A/D value 1
Y position dot calculation A/D value 2
YPARDOT1
YPARDOT2
Initial value
Initial value
Hold
Hold
Hold
Hold
Hold
Hold
Y position dot calculation A/D value 3
Y position dot calculation A/D value 4
YPARDOT3
YPARDOT4
Initial value
Initial value
Hold
Hold
Hold
Hold
Hold
Hold
RTC/Touch Panel/Key
Supply status register
RTKISR
Initial value
Initial value
Hold
Initial value
Input/Power
Table 6.14 Values under Switch Input Register Conditions
Register
Abbreviation
Condition A
Condition B
Condition C
Condition D
Key control register
Key auto repeat time register
Key input status register
Key bit pattern register
RTC/Touch Panel/Key Input/Power
Supply status register
KEYCR
KATIMER
KEYSR
KBITPR
RTKISR
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Hold
Hold
Hold
Hold
Hold
Initial value
Initial value
Initial value
Initial value
Initial value
Table 6.15 Values under Power Supply Control Register Conditions
Register
Abbreviation
Condition A
Condition B
Condition C
Condition D
System power control register 1
System power snort register 2
RTC/Touch Panel/Key Input/Power
Supply status register
SPOWCR1
SPOWCR2
RTKISR
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Hold
Hold
Hold
0x00
Initial value
Initial value
R0P7760TH001TRK User’s Manual
Power Supply Controller
Table 6.16 Values under LED Register Conditions
Register
Abbreviation
Condition A
Condition B
Condition C
Condition D
LED register
LEDR
Initial value
Initial value
Hold
0x00
Table 6.17 Values under LCD Front Light Register Conditions
Register
Abbreviation
Condition A
Condition B
Condition C
Condition D
LCD front light register
LCDR
Initial value
Initial value
Hold
0x00
Table 6.18 Values under Reset Register Conditions
Register
Abbreviation
Condition A
Condition B
Condition C
Condition D
Reset control register
RESTCR
Initial value
Initial value
Hold
Initial value
Table 6.19 Values under Infrared Remote Control Register Conditions
Register
Abbreviation
Condition A
Condition B
Condition C
Condition D
Infrared remote control register
Infrared remote control status register
Receive data count register for infrared
remote control signals
Transmit data count register for infrared
remote control signals
Receiving FIFO data register for
infrared remote control signals
Transmitting FIFO data register for
infrared remote control signals
IRRCR
IRRSR
IRRRDNR
Initial value
Initial value
Initial value
Initial value
Initial value
Initial value
Hold
Hold
Hold
Initial value
Initial value
Initial value
IRRSDNR
Initial value
Initial value
Hold
Initial value
IRRRFDR
Initial value
Initial value
Hold
Initial value
IRRSFDR
Initial value
Initial value
Hold
Initial value
Table 6.20 Values under Serial EEPROM Control Register Conditions
Register
Abbreviation
Condition A
Condition B
Condition C
Condition D
EEPROM control register
EEPROM data register
EEPCR
EEPDR
Initial value
Initial value
Initial value
Initial value
Hold
Hold
Initial value
Initial value
Table 6.21 Values under Electronic Volume Control Register Conditions
Register
Abbreviation
Condition A
Condition B
Condition C
Condition D
Electronic volume data register for
the right speaker
Electronic volume data register from
the left speaker
EVRDR
Initial value
Initial value
Hold
Initial value
EVLDR
Initial value
Initial value
Hold
Initial value
R0P7760TH001TRK User’s Manual
External Interrupts
7. External Interrupts
7.1 SH7760 External Interrupts
Figure 7.1 shows a mechanism for the SH7760 interrupt signal.
Table 7.1 shows the levels for respective interrupt signals.
As shown in Figure 7.1, interrupt signals from devices within T-Engine are sent to the pins /IRQ4, PINT11,
PINT6 and PINT7 of theSH7760. The interrupt signals /IRQ0 to /IRQ3 are converted into the /IRL signals by
FPGA, then output to the /IRL [3:0] of the SH7760.
SH7760
FPGA
/IRL3
/IRL2
/IRL1
/IRL0
PCMCIA controller
MR-SHPC-01 V2T
/SIRQ3
/SIRQ2
/SIRQ1
/SIRQ0
Extension slot
local bus
IRQ3#
IRQ2#
IRQ1#
IRQ0#
Power supply controller
H8/3048F-ONE
/H8_IRQ(PB3)
IRQ -> IRL
conversion
UART
(ST16C2550)
INTA TXA ,RXA
TxD ,RxD
INTB TXB ,RXB
CN1
Host
Figure 7.1 Interrupt Signal Mechanism
Table 7.1 Interrupt Levels for Interrupt Signals
No.
Interrupt request source
Interrupt input pin
Interrupt signal level
Remarks
1
2
3
4
5
6
7
8
9
10
11
PCMCIAcontroller (SIRQ3)
PCMCIAcontroller (SIRQ2)
PCMCIAcontroller (SIRQ1)
PCMCIAcontroller (SIRQ0)
UART controller chA
UART controller chB
H8/3048F-ONE
Extension slot (IRQ3#)
Extension slot (IRQ2#)
Extension slot (IRQ1#)
Extension slot (IRQ0#)
/IRL [3:0]
/IRL [3:0]
/IRL [3:0]
/IRL [3:0]
/IRL [3:0]
/IRL [3:0]
/IRL [3:0]
/IRL [3:0]
/IRL [3:0]
/IRL [3:0]
/IRL [3:0]
/IRL [3:0] = 0001
/IRL [3:0] = 0101
/IRL [3:0] = 1000
/IRL [3:0] = 1010
/IRL [3:0] = 0110
/IRL [3:0] = 0011
/IRL [3:0] = 0010
/IRL [3:0] = 0000
/IRL [3:0] = 0100
/IRL [3:0] = 0111
/IRL [3:0] = 1001
Interrupt level 14
Interrupt level 10
Interrupt level 7
Interrupt level 5
Interrupt level 9
Interrupt level 12
Interrupt level 13
Interrupt level 15
Interrupt level 11
Interrupt level 8
Interrupt level 6
R0P7760TH001TRK User’s Manual
T-Engine Extension Slot
8. T-Engine Extension Slot
8.1 Extension Slot Specifications
Connector number: CN2
T-Engine connector model: 20-5603-14-0101-861 (Kyocera Elco)
Adaptable connector model: 10-5603-14-0101-861 (Kyocera Elco)
3. 00m m
Figure 8.1 shows the location of an extension slot.
Center of 3mm x 3mm
2.3
(Clearance 6)
3.00mm
75.00mm
120.00m m
CN1
Serial interface connector
5.50m m
0.58 Side pin
0.98 Side pin
Extension slot
37.50mm
139
140
1
Extension slot
(magnified)
Figure 8.1 Extension Slot Position
2
R0P7760TH001TRK User’s Manual
T-Engine Extension Slot
8.2 Extension Slot Signal Assignment
Table 8.1 shows the assignment of extension slot signals.
Table 8.1 Extension Slot Signals
Pin
Signal name
No.
I/O
Pin
Signal name I/O Pin No. Signal name
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
5V (*1)
5V
5V
5V
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
GND
GND
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
GND
GND
CKIO
GND
GND
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
GND
GND
A16
A17
A18
A19
A20
A21
A22
A23
I/O
I/O
I/O
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
A24
A25
EPROMCE#
CS2#
CS4#
CS5#
RDWR
BS#
GND
GND
RD#
WAIT#
WE0#
WE1#
WE2#
WE3#
GND
GND
IRQ0#
IRQ1#
IRQ2#
IRQ3#
NMI_IN
RST_IN#
RST_OUT#
DREQ#
DRAK#
DACK#
ROMSEL
BASE# (*2)
GND
GND
SCIF2_TXD
SCIF2_RXD
SCIF2_RTS#
I/O
Pin
No.
Signal name
I/O
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
OUT
IN
IN
OUT
IN
OUT
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
SCIF2_CTS#
GND
GND
TCK
TMS
TRST#
TDI
TDO
ASEBRKAK#
3.3VSB (*3)
3.3VSB
3.3VSB
3.3VSB
AUDATA0
AUDATA1
AUDATA2
AUDATA3
AUDSYNC#
AUDCK
3.3V (*4)
3.3V
3.3V
3.3V
3.3V
3.3V
VBAT_IN (*5)
VBAT_IN
VBAT_IN
VBAT_IN
GND
GND
GND
GND
IN
IN
IN
IN
IN
OUT
OUT
I/O
I/O
I/O
I/O
OUT
IN
-
: Indicates the address bus, data bus, control signals, and serial signals of the SH7760.
Supply voltage is 3.3V.
*1: 5.0V (typ.) is supplied when the SH7760 is turned on.
*2: If this pin is set to “Low,” output takes place from the SH7760 extension to the extension slot.
*3: 3.3V (typ.) is supplied when the battery is provided or the AC adapter is connected.
*4: 3.3V (typ.) is supplied when the SH7760 is turned on.
*5: Pin for power supply (4.2V to 3.6V). T-Engine can be powered via the extension slot.
R0P7760TH001TRK User’s Manual
Daughter Board Design Guide
9. Daughter Board Design Guide
This chapter describes the design of the daughter board to be connected to the extension slot of T-Engine.
The daughter board may contain user-specific devices and can be controlled by the address bus, data bus,
and control signals or serial signals (start-stop) of the SH7760 that connect to the extension slots of T-Engine.
9.1 Daughter Board Dimensions
The recommended daughter board size is the CPU board size (120mm x 75mm) of T-Engine.
9.2 Daughter Board Power Supply
Table 9.1 shows the voltage and current that can be supplied from T-Engine to a daughter board. When a
daughter board requires more current, a power supply must be mounted on the daughter board.
Table 9.1 Voltage and Current to the Daughter Board
Extension
name
3.3V
3.3VSB
5V
slot
signal
Output
voltage
3.3V
Permissible
current
250mA
5V
250mA
Remarks
3.3V: Supplied when the SH7760 is turned ON.
3.3VSB: Always supplied when the AC adapter
is connected.
Supplied when the SH7760 is turned ON.
CAUTION
When a peripheral device operating on the bus power via the USB has been connected to T-Engine or
the PCMCIA card is in use, the permissible current is the current obtained by subtracting the dissipation
current of the device and card from the permissible current.
R0P7760TH001TRK User’s Manual
Daughter Board Design Guide
9.3 Daughter Board Stack
A maximum of 3 daughter boards can be stacked. When multiple daughter boards are stacked, care should
be taken for electric capacity. Figure 9.2 shows an example of daughter board stacks.
T-Engine Board
Daughter board
Extension slot: 20-5603-14-0101-861
Extension slot: 10-5603-14-0101-861
Daughter board
Extension slot: 20-5603-14-0101-861
Extension slot: 10-5603-14-0101-861
Extension slot: 20-5603-14-0101-861
Figure 9.2 Daughter Board Stack
9.4 Daughter Board WAIT# Output
T-Engine is provided with a WAIT# input pin on the extension slot for WAIT input to the daughter board. When
a WAIT# is output from the daughter board, open collector output must take place to prevent a collision of
WAIT# output when multiple daughter boards are stacked.
T-Engine Board side
Daughter Board side
3.3V
SH7760
FPGA
/RDY
(Active Low)
IORDY
(Active High)
680 ohm
Extension slot
Extension slot
Extension slot device
Open collector output
Figure 9.3 Extension Slot IORDY Pin Structure
IORDY
(Active High)
R0P7760TH001TRK User’s Manual
Daughter Board Design Guide
9.5 Extension Slot AC Timing
As shown in Figure 9.4, the SH7760 bus signal is output to the extension slot via the bus buffer. For this
reason, the bus signal delays approx. 8nsec for the AC timing of the SH7760 bus.
When designing the
daughter board, consider this delay. Figure 9.5 shows the basic bus timing of the SH7760.
For details on SH7760 bus timing, refer to the pertinent SH7760 Hardware Manual.
SH7760
Bus signal
Extension slot
Bus buffer
Address bus
control signal
Data bus
Inside T-Engine Board
Figure 9.4 Extension Slot Bus Buffer Structure
CAUTION
The bus timing delay time must be used only for reference. This is not a guaranteed value.
TS1
T1
T2
TH1
CKIO
tAD
tAD
tCSD
tCSD
tRWD
t RWD
A25-A0
RD/
tRSD
D31-D0
(At Read)
tRDS
tWED1
tBSD
tRSD
tRSD
tRDH
tWED1
tWEDF
tBSD
tDACD
tDACD
DACKn
(SA: IO-Memory)
tDACD
tDACD
DACKn
(DA)
Note: IO: DACK DEVICE
SA: Single address DMA Transfer
DA: Dual address DMA Transfer
DACK in High Active
Figure9.5 Memory Byte control SRAM Bus cycle Basic Read cycle
(No wait, Address set up/Insert hold time, AnS=1, AnH=1)
R0P7760TH001TRK User’s Manual
Flash Memory Refresh
10. Flash Memory Refresh
When refreshing the contents of the flash memory on T-Engine or the internal flash memory of the power
supply controller (H8/3048F-ONE), connect the debug board to the extension slot of T-Engine and run the
program stored in the EPROM on the debug board.
10.1 Preparation for Flash Memory Refresh
Connect the debug board to the extension slot (CN2) of T-Engine. In addition, make the following settings for
the jumper switch.
For details, refer to 2.4.2 “Debug Board Connection” and 2.4.3 “Debug Board Jumper switch.”
Debug board jumper switch (J1): Pins 1 and 2 must be short-circuited (EPROM allocation to an address range
from h’00000000 to h’001FFFFF).
Connect the serial interface connector (CN1) of T-Engine and host system with an RS-232C interface cable
(accessory). Start communication software on the host system and make the following settings.
Baud rate: 115200bps
Data length: 8 bits
Parity bit: None
Stop bit: 1 bit
Flow control: Xon/Xoff
After making the above settings, turn on the power of T-Engine, and the title screen --- screen indicating the
execution status of the program stored in the EPROM --- will be displayed on the communication software as
shown below.
[Display Screen]
================================================
SH7760 Self Debugger
Ver x.xL (****/**/**)
----------------------------------------------------------------------------(C) Copyright 2002-2005. Hitachi.Ltd. All rights reserved.
=================================================
H [elp] for help messages...
Ready >
R0P7760TH001TRK User’s Manual
Flash Memory Refresh
10.2 T-Engine Flash Memory
10.2.1 Refresh Method
Figure 10.1 shows how the T-Engine flash memory is refreshed. As shown in Figure 10.1, the T-Engine flash
memory is refreshed in such a way that flash memory data is copied to SDRAM and the data transferred from
the host system is written to the flash memory.
H'00000000
Erasure
EPROM
EPROM
EPROM
H'001FFFFF
H'01000000
Flash memory
Copy
Flash
memory
Flash memory
SDRAM
SDRAM
Write
H'017FFFFF
H'0C000000
H'0C7FFFFF
SDRAM
H'0DFFFFFF
Transfer
from the
host system
Motorola S
format object file
Figure 10.1 Flash Memory Refresh
Below is a description of the T-Engine flash memory refresh method.
(1) As shown on the following screen, type “FL 0” and hit the Enter key after the title screen appears on the
communication software.
[Display Screen]
Ready >fl 0
R0P7760TH001TRK User’s Manual
Flash Memory Refresh
(2) As shown on the following screen, transfer the Motorola S format object file after the transfer request
message “Please Send A S-format Record” appears on the screen.
[Display Screen]
SH7760 Flash Memory Change Value!
Flash Memory data copy to RAM
Please Send A S-format Record
(3) Flash memory refresh normally terminates when the messages (“flash memory chip erase: complete” and
“flash write complete”) sequentially appear on the screen after the Motorola S format object file has been
transferred.
[Display Screen]
Ready >fl 0
SH7760 Flash Memory Change Value!
Flash Memory data copy to RAM
Please Send A S-format Record
Start Addrs = A0000000
End Addrs = A00FFFFF
Transfer complete
Flash chip erase: complete
Program :complete
Flash write complete
Ready >
R0P7760TH001TRK User’s Manual
Flash Memory Refresh
10.3 Power Supply Controller’s Internal Flash Memory
10.3.1 Refresh Method
Figure 10.2 shows how the flash memory of the power supply controller is refreshed. As shown in Figure 10.2,
data transferred from the host system is saved in the SDRAM when power supply controller’s flash memory is
refreshed.
The saved data is transferred to the power supply controller and written to the flash memory by the
power supply controller firmware. Though the flash memory of the power supply controller has been divided
into 8 blocks, the upper 4 blocks are occupied by the firmware for refreshing the flash memory and only the
remaining 4 blocks (BLK4 to BLK7) are rewritten.
H'00000000
H'001FFFFF
EPROM
Power supply controller(H8/3048F-ONE)
Internal flash memory
Transfer to power
supply controller
H'0C000000
Writing by
firmwawre
H'0C01FFFF
SDRAM
H'0DFFFFFF
Transfer
from host
system
Motorola S format
object file
Figure 10.2 Refreshing the Flash Memory of the Power Supply Controller
R0P7760TH001TRK User’s Manual
Flash Memory Refresh
Below is a description of the method for refreshing the flash memory of the power supply controller.
(1) As shown on the following screen, type “FL 1” and hit the Enter key after the title screen appears on the
communication software.
[Display Screen]
================================================
SH7760 Self Debugger
Ver x.xL (****/**/**)
----------------------------------------------------------------------------(C) Copyright 2002-2005. Hitachi.Ltd. All rights reserved.
=================================================
H [elp] for help messages...
Ready >
Ready>fl 1
(2) As shown on the following screen, transfer the Motorola S format object file after the transfer request
message “Please Send A S-format Record” appears on the screen.
Note: After data is transferred, its program ID is checked to determine whether the transferred data is
correct. When the program ID is not correct, the message “Wrong Data!!” appears and memory refresh
terminates.
[Display Screen]
================================================
SH7760 Self Debugger
Ver x.xL (****/**/**)
----------------------------------------------------------------------------(C) Copyright 2002-2005. Hitachi.Ltd. All rights reserved.
=================================================
H [elp] for help messages...
Ready >
Ready>fl 1
H8/3048Fone Flash Memory Change Value!
Clear data buffer (all 0xFF)
Please Send A S-format Record
R0P7760TH001TRK User’s Manual
Flash Memory Refresh
(3) Refreshing the flash memory of the power supply controller normally completes when the messages (“H8
flash erase: complete” and “flash write complete”) sequentially appear on the screen after the Motorola S
format object file has been transferred.
CAUTION
When the flash memory of the power supply controller is being refreshed, never power OFF T-Engine.
If ignored, refreshing may terminate in error or the flash memory may be damaged.
[Display Screen]
Ready>fl 1
H8/3048Fone Flash Memory Change Value!
Clear data buffer (all 0xFF)
Please Send A S-format Record
Start Addrs = 00001000
End Addrs = 00003D20
Transfer complete
H8 Flash erase: complete
Program :……………. complete
Flash write complete
Ready>
R0P7760TH001TRK User’s Manual
Flash Memory Refresh
10.3.2 Refresh Check
After the internal flash memory of the power supply controller is refreshed, the version of the refreshed
program or the data stored in the internal flash memory of the power supply controller can be checked by
entering the following command. However, note that the following command can be executed immediately
after the internal flash memory of the power supply controller has been refreshed. When T-Engine has been
turned off and on or the reset switch or NMI switch of T-Engine has been pressed, the following command
cannot be executed normally.
(1) Reading the version
Enter the command as shown on the following screen, and the version of the written program will be read
out. Version information is displayed in X.X.
[Display Screen]
Ready>h8_ver
------------------ROM Version
------------------Hitachi ULSI T-Engine PowerController VerX.X
(2) Reading flash memory data
When the command and the address to be read have been entered as shown on the following screen, 64byte data can be read out from the internal flash memory of the power supply controller.
[Display Screen]
Ready>h8d
10000
00010000 : 00 01 02 00 00 01 02 00 00 01 02 00 00 01 02 00
00010010 : 00 01 02 00 00 01 02 00 00 01 02 00 00 01 02 00
00010020 : 00 01 02 00 00 01 02 00 00 01 02 00 00 01 02 00
00010030 : 00 01 04 CC 00 01 05 2A 00 01 02 00 00 01 05 70
(3) Restarting the Power Supply Controller
To restart the power supply controller, enter the command as shown on the following screen. Once the
power supply controller is restarted, the SH7760 is restarted too.
[Display Screen]
Ready>restart
ReStart !!
R0P7760TH001TRK User’s Manual
Attached Documents
11. Attached Documents
11.1 T-Engine Board Parts List
11.1.1 CPU Board Parts list
CPU Board Parts List (1)
Parts name
Model name
Maker
Quantity
Parts No.
SH7760
H8/3048F-ONE
PC Card controller
HD6417760BP200D
HD64F3048BVF25
MR-SHPC-01V2T
RENESAS
RENESAS
Marubun
1
1
1
U7
U8
U12
UART (2Ch)
AUDIO CODEC
ispMACH 4A
ST16C2550CQ48
UDA1342TS
M4A3-256/192-7FAC
EXAR
PHILIPS
LATTICE
1
1
1
U18
U14
U11
ispMACH 4A
RTC
SWIFT
M4A3-32/32-7VC48
RV5C348B
TPS54316PWP
LATTICE
RICOH
T.I
1
1
1
U10
U17
U16
DC/DC Converter
DC/DC Converter
SIM Level Translator
LTC3440EMS
LTC1772CS6
LTC1555LEGN-1.8
LTC
LTC
LTC
1
1
1
U15
U1
U13
USB power switch
Digital Potentimeter
Power Switch
TPS2014D
MAX5413EUD
TPS2211IDB
T.I
MAXIM
T.I
1
1
1
U23
U26
U20
RS-232 Transceiver
Headphone amplifier
OP amplifier
SP3223ECY
LM4865MM
NJM2100V<TE1>
SIPEX
NS
JRC
1
2
2
U2
U27,U28
U24,U25
u voltage monitor
CBT-LV
LV Logic
MAX811REUS-T
SN74CBTLV3383DGV
SN74LV07APW
MAXIM
T.I
T.I
1
1
1
U22
U4
U21
LV1G Logic
LV1G Logic
256M SDRAM
HD74LV1G00ACM<E>
HD74LV1G08ACM<E>
HM5225165BTT-A6
MBM29DL640E90TN
RENESAS
RENESAS
ELPIDA
1
4
2
U6
U3,U5,U9,U19
M1,M2
S-29391AFJA
SML-310MT<T86>
Fujitsu
SII
ROHM
1
1
2
M3
M4
LED1,LED2
LED
OSC
OSC
GL100MN0MP
SG-8002JF-16.66700M-PCCB
SG8002JF-48.000000M-PCCB
SHARP
EPSON
EPSON
1
1
1
LED3
OSC1
OSC2
OSC
OSC
XTAL
SG8002JF-7.372800M-PCCB
SG-8002JF-22.579200M-PCCB
MC-146 32.768kHz
EPSON
EPSON
EPSON
1
1
1
OSC3
OSC4
X1
P-Channel MOS FET
P-Channel MOS FET
Transistor
2SK2980ZZ<TL>
SI3443DV-T1
2SD2150S(T100)
RENESAS
VISHY
ROHM
1
2
1
Q1
Q2,Q3
TR1
Digital transistor
EMI filter
DTC1423ZE<TL>
BLM18PG300SN1<D>
ROHM
Murata
Manufacturing
4
6
TR2-5
FL1-6
Coil
LQH55DN4R7M01L
1
L3
Coil
SLF6028<T>-100M1R3
Murata
Manufacturing
TDK
1
L1
Coil
SLF10145<T>-100M2R5
TDK
1
L2
64M-Flash Memory
Serial EEPROM
LED
R0P7760TH001TRK User’s Manual
Attached Documents
CPU Board Parts List (2)
Parts name
Model name
Maker
Quantity
Parts No.
CMS03
RB521S-30<TE61>
U1ZB6.8<TE12L>
Chip continuous resistance MNR15E0RP-J103
Chip resistance (1005)
MCR01MZS-J000
TOSHIBA
ROHM
TOSHIBA
ROHM
ROHM
3
1
1
SD1-3
SD4
ZD1
9
12
Chip resistance (1005)
MCR01MZS-J101
ROHM
6
NR1-9
R45 to R50, R59, R60,
R62, R69, R75, and
R84
R41 to R44, R110, and
R121
Chip resistance (1005)
MCR01MZS-J102
ROHM
20
Chip resistance (1005)
MCR01MZS-J103
ROHM
37
Chip resistance (1005)
MCR01MZS-J104
ROHM
12
R88, R89, R107, R115,
R116, R118, and R124
to R128
Chip resistance (1005)
MCR01MZS-J151
ROHM
2
R96 and R97
Chip resistance (1005)
MCR01MZS-J153
ROHM
4
Chip resistance (1005)
MCR01MZS-J164
ROHM
1
R100, R104, R113, and
R120
R119
Chip resistance (1005)
MCR01MZS-J202
ROHM
1
R81
Chip resistance (1005)
MCR01MZS-J222
ROHM
1
R108
Chip resistance (1005)
MCR01MZS-J224
ROHM
1
R99
Chip resistance (1005)
MCR01MZS-J330
ROHM
5
Chip resista nce (1005)
MCR01MZS-J471
ROHM
6
Chip resistance (1005)
Chip resistance (1005)
MCR01MZS-J473
MCR01MZS-J681
ROHM
ROHM
1
1
R25, R61, R92, R105,
and R106
R101, R102, R103,
R112, R117 and R122
R40
R123
Chip resistance (1608)
MCR03MZH-J100
ROHM
4
Chip resistance (1608)
MCR03MZH-J1R0
ROHM
3
R38, R83, R85, and
R93
R63, R68, and R70
Chip resistance (1608)
MCR03MZH-J221
ROHM
1
R71
Chip resistance (1608)
MCR03EZP-FX1004
ROHM
1
R73
Chip resistance (1608)
Chip resistance (1608)
MCR03EZP-FX2003
MCR03EZP-FX3002
ROHM
ROHM
1
1
R64
R65
Chip res istance (1608)
MCR03EZP-FX6203
ROHM
1
R72
Chip resistance (1608)
Chip resistance (1608)
MCR03EZP-FX6982
MCR03EZP-FX7872
ROHM
ROHM
1
1
R2
R1
Chip resistance (3216)
MCR18EZH-J101
ROHM
1
R3
Chip resistance (3216)
SR73M2B-TD 0.03ΩJ
KOA
1
R5
Schottky barrier diode
Schottky barrier diode
Zener diode
R17, R19 to R23, R26,
R28 to R33, R37, R52,
R54 to R56, R77, and
R78
R4, R6 to R14, R16,
R18, R24, R27, R34 to
R36, R39, R51, R53,
R57, R58, R67, R74,
R79, R80, R82, R86,
R87, R90, R91, R94,
R95, R98, R109, R111,
and R114
R0P7760TH001TRK User’s Manual
Attached Documents
CPU Board Parts List (3)
Parts name
Model name
Maker
Quantity Parts No.
Chip ceramic capacitor (1005) GRP1552C1H100JZ01<E>
Murata Manufacturing
1
C64
Chip ceramic capacitor (1005) GRP1552C1H101JD01<E>
Murata Manufacturing
C1, and C54 to C57
Chip ceramic capacitor (1005) GRP1552C1H470JZ01<E>
Murata Manufacturing
5
3
Chip ceramic capacitor (1005) GRP155B11H221KA01<E>
Murata Manufacturing
2
C2, C48
Chip ceramic capacitor (1005) GRP155F11H103ZA01<E>
Murata Manufacturing
10
Chip ceramic capacitor (1005) GRP155F11C104ZA01<E>
Murata Manufacturing
51
C8,C58,C60, C65,
C67, C69, C76, C77,C83,
C84,
C5, C6, C10, C14 to C21,
C24, C26, C28, C32 to
C34, C41, C42, C53, C59,
C61, C63, C66, C70 to
C72, C74, C75, C78 to
C82, C88 to C91, C94 to
C99, C101, C102, C104,
C108, C115, and C116
Chip ceramic capacitor (1005) GRP155F10J105ZD02<E>
Chip ceramic capacitor (1608) GRM188B11E104KA01<D>
Murata Manufacturing
Murata Manufacturing
1
6
Chip ceramic capacitor (1608) GRM188B11E473KA01<D>
Chip ceramic capacitor (1608) LMK107BJ105MA-T
Murata Manufacturing
TAIYO-YUDEN
1
6
Chip ceramic capacitor (3225) LMK325BJ106MN-T
TAIYO-YUDEN
4
Chip ceramic capacitor (4532) EMK432BJ226MM-T
Tantalum electrolytic capacitor TCFGA1A106M8R
(3216)
TAIYO-YUDEN
ROHM
1
7
C36
C7, C39, C68, C73, C86,
C87, and C100
Tantalum electrolytic capacitor TCFGB1A476M8R
(3528)
Tantalum electrolytic capacitor TCFGP1A225M8R
(2012)
POSCAP (D4)
4TPB470M
ROHM
5
ROHM
2
C29, C31, C44, C106, and
C113
C23 and C109
Sanyo Electronic
Components
1
C38
POSCAP(C)
6TPB100MC
Sanyo Electric
components
9
C3, C25, C30, C35, C40,
C43, C45, C46
And C62
Switch
Switch
Switch
SKRELBE010
SKQDAA
CHS-08B
ALPS
ALPS
Copal
3
1
1
SW1, SW2, and SW3
SW4
SW5
Connector
T-Engine connector
PC Card connector
RMC-EA15MY-OM15-MC1
24-5603-14-0101-861
31-5027-068-130-833
Honda Tsushin Kogyo 1
Kyosera Elco
1
Kyocera Elco
1
CN1
CN2
CN3
PC Card ejector
SIM Card connector
FPC connector
30-5027-000-907-000
04-5036-008-110-862
FH12-40S-0.5SH
Kyocera Elco
Kyocera Elco
Hirose Electric
For CN3
CN4
CN5 and CN16
FPC connector
USB connector
Connector
FH12-24S-0.5SH
24-5041-0041-10-834S
24-8005-002-100-867
Hirose Electric
Kyocera Elco
Kyocera Elco
φ 2.5 Jack
HSJ1602-011001
Power supply jack
FPC connector
1
1
2
1
C103, C107, and C114
C22
C4, C11 to C13, C49, and
C51
C37
C92, C93, C105, and
C110 to C112
C9, C27, C47, and C50
1
4
CN6
CN7
CN8, and CN11 to CN13
Hoshiden
2
CN9 and CN10
HEC3600-010020
Hoshiden
1
FH12-10S-0.5SH
Hirose Electric
2
CN14
CN15 and CN17
R0P7760TH001TRK User’s Manual
Attached Documents
11.1.2 LCD Board Parts List
LCD Board Parts List (1)
Parts name
Model name
Maker
Quantity Parts No.
LCD controller
Touch screen controller
DC-DC converter
S1L50282F23K100
ADS7843E
LT1615ES5
1
1
3
U2
U6
U3-5
Remote control receiving unit
Digital transistor
P-ch FET
GP1UC101
DTC143ZE<TL>
Si3443DV
NEC
T.I
LTC
SHARP
ROHM
VISHY
1
4
3
U1
TR1-4
Q1-3
Power inductor
Push-button switch
Push-button switch
LQH32CN100K11L
SKRHABE010
SKRAAAE010
Murata Manufacturing
ALPS
ALPS
3
1
2
L1-3
SW1
SW2-3
Diode
Schottky barrier diode
Variable resistance
Chip resistance (1608)
Chip resistance (1608)
1SS355<TE-17>
CRS03
G4BT104
ROHM
TOSHIBA
TOCOS
3
6
1
D1-3
SD1-6
VR1
MCR03EZH-J000
MCR03EZH-J103
ROHM
ROHM
2
9
R6 and R8
R1-5 and R14,
R16-18
Chip resistance (1608)
Chip resistance (1608)
Chip resistance (1608)
MCR03EZH-J124
MCR03EZH-F1004
MCR03EZH-F1373
ROHM
ROHM
ROHM
1
2
1
R7
R11 and R13
R10
Chip resistance (1608)
Chip resistance (1608)
Chip resistance (1608)
MCR03EZH-F1693
MCR03EZH-F80R6
ROHM
ROHM
ROHM
1
1
1
R9
R15
R12
Chip ceramic capacitor (1608) GRM1882C1H5R0CZ01<D>
Chip ceramic capacitor (1608) GRM188B11H102KA01<D>
Chip ceramic capacitor (1608) GRM188F11E104ZA01<D>
Murata Manufacturing
Murata Manufacturing
Murata Manufacturing
2
1
10
Chip ceramic capacitor (3216) GMK316BJ105ML
TAIYO-YUDEN
1
C7 and C10
C22
C1-4, C9,
C13, C15,
C18-19, and C21
C24
Chip ceramic capacitor (2125) LMK212F475ZG
TAIYO-YUDEN
7
C5-6,
C11,C20,C23,and
C25-26
Chip ceramic capacitor (3216) TMK316BJ105ML
Tantalum electric capacitor TCFGB1C226M8R
(B:3528)
TAIYO-YUDEN
ROHM
4
1
C12,C14, C16-17
C8
FPC connector
FPC connector
FPC connector
FH12-40S-0.5SH
FH12-24S-0.5SH
FH12-45S-0.5SH
HRS
HRS
HRS
1
1
1
CN1
CN2
CN3
FPC connector
FPC connector
04FLH-SM1-TB
SFW4R-1STE1
JST
FCI
1
1
CN4
CN5
MCR03EZH-F8872
R0P7760TH001TRK User’s Manual
Attached Documents
11.1.3 Debug Board Parts List
Debug Board Parts List
Parts name
Model name
Maker
Quantity
Parts No.
LVC logic
LVC logic
LVC logic
HD74LVC245AT
HD74LVC139T
HD74LVC374AT
RENESAS
RENESAS
RENESAS
4 U1, U2, U7, and U8
1 U3
1 U5
LV1G logic
8M-EPROM
Connector
HD74LV1G32ACM
MX27C8100PC-10
10-5603-14-0101-861
RENESAS
MXIC
Kyocera Elco
2 U4 and U6
1 M1
1 CN1
Connector
Short-circuit pin
Jumper pin
DX10M-36SE
FFC-2BMEP1B
DIC-252
Hirose Electric
Honda Tsushin Kogyo
Honda Tsushin Kogyo
1 CN2
1 J1
1 (For J1)
Dip switch
Test pin
LED
CHS-08B
HK-2-S
SML-310MT
Copal
Mac8
ROHM
2 SW1 and SW2
3 TP1-3
8 LED1-8
Chip capacitor (1608)
Chip resistance (1608)
GRM188F11E104ZA01<D>
MCR03EZH-J102
Murata Manufacturing
ROHM
5 C1-5
24 R1-24
11.1.4 I/O Board Parts List
I/O Board Parts List
Parts name
Model name
Maker
Quantity
Parts No.
Chip ceramic capacitor
GRM188F11E104ZA01<D>
(1608)
Tantalum capacitor (3216) TCFGA1A106M8R
Murata
Manufacturing
ROHM
5 C1-5
FPC connector
FPC connector
FPC connector
Hirose Electric
Hirose Electric
Hirose Electric
2 CN1 and CN3
1 CN2
1 CN4
FH12-40S-0.5SH
FH12-24S-0.5SH
FH12-10S-0.5SH
5 C6-10
R0P7760TH001TRK User’s Manual
Attached Documents
11.2 T-Engine FPGA Logic
11.2.1 CPU Board (U11) FPGA Logic
(1)ypa5010,vhd
-----------------------------------------------------------------------------------------SH7760 Solution Engine2(MS7760CP01P) FPGA
------------------------------------------------------------------------------------------- module name
: CPLD(YPA5010) Top module
-- entity
: YPA5010
-- file name
: YPA5010.vhd
------------------------------------------------------------------------------------------- rev : 0 2003.01.15
Initial release
------------------------------------------------------------------------------------------ (c) copyright Hitachi ULSI Systems Co.,Ltd. 2003
-----------------------------------------------------------------------------------------
---------------------------------------------------------------------------------Library
-------------------------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
----------------------------------------------------------------------------------------------------------------------------------------------------------------Entity
-------------------------------------------------------------------------------entity YPA5010 is
port(
-- from SH7760
ShDatas
: inout std_logic_vector(31 downto 0);
ShAddrs
: in std_logic_vector(25 downto 0);
ShCkio
: in std_logic;
ShCs_x
: in std_logic_vector(6 downto 0);
ShRdWr
: in std_logic;
ShBs_x
: in std_logic;
ShRd_x
: in std_logic;
ShWe_x
: in std_logic_vector(3 downto 0);
-- from Syetem
Rst_x
: in std_logic;
-- from PCIC
PcicCs_x
: out std_logic;
PcicRst_x : out std_logic;
PcicRdy_x: in std_logic;
PcSirq_x
: in std_logic_vector(3 downto 0);
-- from UART
UartCsA_x
UartCsB_x
UartIntA
UartIntB
: out std_logic;
: out std_logic;
: in std_logic;
: in std_logic;
-- from H8/3048
H8Irq_x
: in std_logic;
-- from Extend Connector
ExWait_x
ExIrq_x
: in std_logic;
: in std_logic_vector(3 downto 0);
-- UART ChA
-- UART ChB
R0P7760TH001TRK User’s Manual
Attached Documents
-- from Debug/Extend Board
RomSel
Base_x
: in std_logic;
: in std_logic;
-- from ID Switch
IdDatas
: in std_logic_vector(5 downto 0);
-- to pheliphe
FlCe_x
EpCe_x
: out std_logic;
: out std_logic;
-- to SH7760
ShRdy_x
Irl_x
: out std_logic;
: out std_logic_vector(3 downto 0);
-- to etc
ExAddrs
ExDatas
ExCkio
ExCs2_x
ExCs4_x
ExCs5_x
ExRdWr
ExBs_x
ExRd_x
ExWe_x
opt
: out std_logic_vector(25 downto 0);
: inout std_logic_vector(31 downto 0);
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic_vector(3 downto 0);
: out std_logic
);
end YPA5010;
--------------------------------------------------------------------------------
---------------------------------------------------------------------------------Architecture
-------------------------------------------------------------------------------Architecture RTL of YPA5010 is
component AddrDec_r0
port(
ShAdr
ShCs0_x
ShCs1_x
ShCs2_x
ShCs4_x
ShCs5_x
ShCs6_x
ShRdWr
RomSel
Base_x
: in std_logic_vector(25 downto 23);
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
ExWait_x
: in std_logic;
PcicRdy_x: in std_logic;
FlCe_x
EpCe_x
IntRegCs
PcicCs_x
UartCsA_x
UartCsB_x
IdRegCs
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
R0P7760TH001TRK User’s Manual
Attached Documents
BusEn
: out std_logic;
ShRdy_x
: out std_logic
);
end component;
component IrqCnt_r0
port(
PcSirq_x
UartIntA
UartIntB
ExIrq_x
H8Irq_x
: in std_logic_vector(3 downto 0);
: in std_logic;
: in std_logic;
: in std_logic_vector(3 downto 0);
: in std_logic;
-- MR-SHPC-01 interrupt
-- ST16C2550 ChA interrupt
-- ST16C2550 ChB interrupt
-- External Slot interrupt
-- H8/3048 interrupt
IrqEna
: in std_logic_vector(3 downto 0);
-- Interrupt enable
Irl_x
: out std_logic_vector(3 downto 0)
-- SH7760 IRL[3:0]
);
end component;
component IntReg_r0
port(
Addrs
IntRegCs
Rd_x
Wr_x
WrDatas
Rst
RdDatas
IrqEna
);
end component;
: in std_logic_vector(3 downto 1);
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic_vector(3 downto 0);
: in std_logic;
: out std_logic_vector(15 downto 0);
: out std_logic_vector(3 downto 0)
component IdReg_r0
port(
IdRegCs
Rd_x
IdDatas
RdDatas
);
end component;
: in std_logic;
: in std_logic;
: in std_logic_vector(5 downto 0);
: out std_logic_vector(15 downto 0)
component SLAddr_r0
port(
ShAdr
ShCkio
ShCs2_x
ShCs4_x
ShCs5_x
ShRdWr
ShBs_x
ShRd_x
ShWe_x
ExAddrs
ExCkio
ExCs2_x
ExCs4_x
: in std_logic_vector(25 downto 0);
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic_vector(3 downto 0);
: out std_logic_vector(25 downto 0);
: out std_logic;
: out std_logic;
: out std_logic;
R0P7760TH001TRK User’s Manual
Attached Documents
ExCs5_x
ExRdWr
ExBs_x
ExRd_x
ExWe_x
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic_vector(3 downto 0);
BusEn
Base_x
: in std_logic;
: in std_logic
);
end component;
component SLData_r0
port(
ShDin
ShDout
: in std_logic_vector(31 downto 0);
: out std_logic_vector(31 downto 0);
ExDatas
: inout std_logic_vector(31 downto 0);
BusEn
RdWr
: in std_logic;
: in std_logic
);
end component;
---------------------------------------------------------------------------------Signal
-------------------------------------------------------------------------------signal
IntRegCs
:std_logic;
signal
IdRegCs
:std_logic;
signal
Rst
:std_logic;
signal
BusEn
:std_logic;
signal
signal
signal
signal
IntRegDatas
IdRegDatas
ExRdDatas
IrqEna
:std_logic_vector(15 downto 0);
:std_logic_vector(15 downto 0);
:std_logic_vector(31 downto 0);
:std_logic_vector(3 downto 0);
R0P7760TH001TRK User’s Manual
Attached Documents
---------------------------------------------------------------------------------Function
---------------------------------------------------------------------------------Low hierarchy file port map
begin
Rst
<= not Rst_x;
ShDatas <= (ExRdDatas or ("0000000000000000" & (IntRegDatas or IdRegDatas)))
when ((IntRegCs = '1' or IdRegCs ='1' or BusEn = '1' ) and ShRd_x = '0')
else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
PcicRst_x <= '0' when (Rst_x = '0' or IrqEna(3) = '1')
else '1';
opt
<= not ShCs_x(3);
U_AddrDec : AddrDec_r0 port map (
ShAdr
=> ShAddrs(25 downto 23),
ShCs0_x
=> ShCs_x(0),
ShCs1_x
=> ShCs_x(1),
ShCs2_x
=> ShCs_x(2),
ShCs4_x
=> ShCs_x(4),
ShCs5_x
=> ShCs_x(5),
ShCs6_x
=> ShCs_x(6),
ShRdWr
=> ShRdWr,
RomSel
Base_x
=> RomSel,
=> Base_x,
ExWait_x
PcicRdy_x
=> ExWait_x,
=> PcicRdy_x,
FlCe_x
EpCe_x
IntRegCs
PcicCs_x
UartCsA_x
UartCsB_x
IdRegCs
=> FlCe_x,
=> EpCe_x,
=> IntRegCs,
=> PcicCs_x,
=> UartCsA_x,
=> UartCsB_x,
=> IdRegCs,
BusEn
=> BusEn,
ShRdy_x
=> ShRdy_x
);
U_IrqCnt : IrqCnt_r0 port map (
PcSirq_x
=> PcSirq_x,
UartIntA
=> UartIntA,
UartIntB
=> UartIntB,
ExIrq_x
=> ExIrq_x,
H8Irq_x
=> H8Irq_x,
);
IrqEna
=> IrqEna,
Irl_x
=> Irl_x
R0P7760TH001TRK User’s Manual
U_IntReg : IntReg_r0 port map (
Addrs
=> ShAddrs(3 downto 1),
IntRegCs
=> IntRegCs,
Rd_x
=> ShRd_x,
Wr_x
=> ShWe_x(0),
WrDatas
=> ShDatas(3 downto 0),
Rst
=> Rst,
RdDatas
=> IntRegDatas,
IrqEna
=> IrqEna
);
U_IdReg : IdReg_r0 port map (
IdRegCs
=> IdRegCs,
Rd_x
=> ShRd_x,
IdDatas
=> IdDatas,
RdDatas
=> IdRegDatas
);
U_SLAddr : SLAddr_r0 port map (
ShAdr
=> ShAddrs,
ShCkio
=> ShCkio,
ShCs2_x
=> ShCs_x(2),
ShCs4_x
=> ShCs_x(4),
ShCs5_x
=> ShCs_x(5),
ShRdWr
=> ShRdWr,
ShBs_x
=> ShBs_x,
ShRd_x
=> ShRd_x,
ShWe_x
=> ShWe_x,
ExAddrs
ExCkio
ExCs2_x
ExCs4_x
ExCs5_x
ExRdWr
ExBs_x
ExRd_x
ExWe_x
=> ExAddrs,
=> ExCkio,
=> ExCs2_x,
=> ExCs4_x,
=> ExCs5_x,
=> ExRdWr,
=> ExBs_x,
=> ExRd_x,
=> ExWe_x,
BusEn
Base_x
=> BusEn,
=> Base_x
);
U_SLData : SLData_r0 port map (
ShDin
=> ShDatas,
ShDout
=> ExRdDatas,
ExDatas
=> ExDatas,
BusEn
=> BusEn,
RdWr
=> ShRdWr
);
end RTL;
Attached Documents
R0P7760TH001TRK User’s Manual
Attached Documents
(2)AddrDec_r0.vhd
-----------------------------------------------------------------------------------------SH7760 Solution Engine2(MS7760CP01P) FPGA
------------------------------------------------------------------------------------------- module n ame
: Address Decoder for MS7760CP01P/0
-- entity
: AddrDec_r0
-- file name
: AddrDec_r0.vhd
------------------------------------------------------------------------------------------- rev : 0 2003.01.15
Initial release
----------------------------------------------------------------------------------------- (c) copyright Hitachi ULSI Systems Co.,Ltd. 2003
----------------------------------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity AddrDec_r0 is
port(
ShAdr
ShCs0_x
ShCs1_x
ShCs2_x
ShCs4_x
ShCs5_x
ShCs6_x
ShRdWr
: in std_logic_vector(25 downto 23);
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
RomSel
Base_x
: in std_logic;
: in std_logic;
ExWait_x
PcicRdy_x
FlCe_x
EpCe_x
IntRegCs
PcicCs_x
UartCsA_x
UartCsB_x
IdRegCs
: in std_logic;
: in std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
BusEn
: out std_logic;
ShRdy_x
: out std_logic
);
end AddrDec_r0;
Architecture RTL of AddrDec_r0 is
begin
-- decode
FlCe_x
<= '0' when ((ShCs0_x = '0' and Base_x = '1' and ShAdr(25) = '0' and ShAdr(24) = '0')
R0P7760TH001TRK User’s Manual
Attached Documents
or (ShCs0_x = '0' and Base_x = '0' and RomSel = '1' and ShAdr(25) = '0' and ShAdr(24) = '0')
or (ShCs0_x = '0' and Base_x = '0' and RomSel = '0' and ShAdr(25) = '0' and ShAdr(24) = '1'))
else '1';
EpCe_x
<= '0' when ((ShCs0_x = '0' and Base_x = '0' and RomSel = '1' and ShAdr(25) = '0' and ShAdr(24) = '1')
or (ShCs0_x = '0' and Base_x = '0' and RomSel = '0' and ShAdr(25) = '0' and ShAdr(24) = '0'))
else '1';
IntRegCs <= '1' when (ShCs1_x = '0')
else '0';
PcicCs_x <= '0' when (ShCs6_x = '0' and ShAdr(25) = '0')
else '1';
UartCsA_x <= '0' when (ShCs6_x = '0' and ShAdr = B"100")
else '1';
UartCsB_x <= '0' when (ShCs6_x = '0' and ShAdr = B"101")
else '1';
IdRegCs <= '1' when (ShCs6_x = '0' and ShAdr(25) = '1' and ShAdr(24) = '1')
else '0';
BusEn
<= '1' when ((ShCs0_x = '0' and Base_x = '0' and RomSel = '1' and ShAdr(25) = '0' and ShAdr(24) = '1')
or (ShCs0_x = '0' and Base_x = '0' and RomSel = '0' and ShAdr(25) = '0' and ShAdr(24) = '0')
or (ShCs2_x = '0' and Base_x = '0')
or (ShCs4_x = '0' and Base_x = '0')
or (ShCs5_x = '0' and Base_x = '0'))
else '0';
ShRdy_x <= '1' When ((ExWait_x = '0' and ShCs2_x = '0' and Base_x = '0')
or (ExWait_x = '0' and ShCs4_x = '0' and Base_x = '0')
or (ExWait_x = '0' and ShCs5_x = '0' and Base_x = '0')
or (PcicRdy_x = '1' and ShCs6_x = '0' and ShAdr(25) = '0'))
else '0';
end RTL;
R0P7760TH001TRK User’s Manual
Attached Documents
(3)IrqCnt_r0.vhd
-----------------------------------------------------------------------------------------SH7760 Solution Engine2(MS7760CP01P) FPGA
------------------------------------------------------------------------------------------- module name
: Interrupt Controler for MS7760CP01P/0
-- entity
: IrqCnt_r0
-- file name
: IrqCnt_r0.vhd
------------------------------------------------------------------------------------------- rev : 0 2003.01.28
Initial release
------------------------------------------------------------------------------------------ (c) copyright Hitachi ULSI Systems Co.,Ltd. 2003
----------------------------------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity IrqCnt_r0 is
port(
-- Interrupt input
PcSirq_x
UartIntA
UartIntB
ExIrq_x
H8Irq_x
-- Interrupt Enable input
IrqEna
-- Interrupt output
Irl_x
);
end IrqCnt_r0;
Architecture RTL of IrqCnt_r0 is
: in std_logic_vector(3 downto 0);
: in std_logic;
: in std_logic;
: in std_logic_vector(3 downto 0);
: in std_logic;
-- MR-SHPC-01 interrupt
-- ST16C2550 ChA interrupt
-- ST16C2550 ChB interrupt
-- External Slot interrupt
-- H8/3048 interrupt
: in std_logic_vector(3 downto 0);
-- Interrupt enable
: out std_logic_vector(3 downto 0)
R0P7760TH001TRK User’s Manual
signal
Irl
: std_logic_vector(3 downto 0);
begin
-- External slot interrupt
process(PcSirq_x, UartIntA, UartIntB, ExIrq_x, H8Irq_x, IrqEna)
begin
if
ExIrq_x(3) = '0'
then
elsif PcSirq_x(3) = '0'
then
elsif (H8Irq_x
= '0' and IrqEna(0) = '1')
then
elsif UartIntB
= '1'
then
elsif ExIrq_x(2) = '0'
then
elsif PcSirq_x(2) = '0'
then
elsif UartIntA
= '1'
then
elsif ExIrq_x(1) = '0'
then
elsif PcSirq_x(1) = '0'
then
elsif ExIrq_x(0) = '0'
then
els if PcSirq_x(0) = '0'
then
else
end if;
end process;
Irl_x
end RTL;
Attached Documents
<= not Irl;
Irl <= X"F";
Irl <= X"E";
Irl <= X"D";
Irl <= X"C";
Irl <= X"B";
Irl <= X"A";
Irl <= X"9";
Irl <= X"8";
Irl <= X"7";
Irl <= X"6";
Irl <= X"5";
Irl <= X"0";
-- Level 15
-- Level 14
-- Level 13
-- Level 12
-- Level 11
-- Level 10
-- Level 9
-- Level 8
-- Level 7
-- Level 6
-- Level 5
-- Level 0
R0P7760TH001TRK User’s Manual
Attached Documents
(4)IntReg_r0.vhd
-----------------------------------------------------------------------------------------SH7760 Solution Engine2(MS7760CP01P) FPGA
------------------------------------------------------------------------------------------- module name
: Internal register
-- entity
: IntReg_r0
-- file name
: IntReg_r0.vhd
------------------------------------------------------------------------------------------- rev : 0 2003.01.15
Initial release
------------------------------------------------------------------------------------------ (c) copyright Hitachi ULSI Systems Co.,Ltd. 2003
----------------------------------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity IntReg_r0 is
port(
Addrs
IntRegCs
Rd_x
Wr_x
WrDatas
Rst
RdDatas
IrqEna
: in std_logic_vector(3 downto 1);
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic_vector(3 downto 0);
: in std_logic;
: out std_logic_vector(15 downto 0);
: out std_logic_vector(3 downto 0)
);
end IntReg_r0;
Architecture RTL of IntReg_r0 is
constant
constant
constant
constant
constant
RegRD0
FpgaId0
FpgaId1
FpgaId2
FpgaId3
: std_logic_vector(15 downto 0) := X"0000";
: std_logic_vector(15 downto 0) := X"5950";
: std_logic_vector(15 downto 0) := X"4135";
: std_logic_vector(15 downto 0) := X"3031";
: std_logic_vector(15 downto 0) := X"3000";
signal
signal
IrqEnaReg
RegWr
:std_logic_vector(3 downto 0);
:std_logic;
begin
RegWr <= '1' when (Addrs = "000" and IntRegCs = '1' and Wr_x = '0')
else '0';
IrqEna <= IrqEnaReg;
process(Addrs, IntRegCs, Rd_x, IrqEnaReg)
begin
if (IntRegCs = '1' and Rd_x = '0') then
case Addrs is
-- 0x0000(Initial value)
-- 0x5950(Y P)
-- 0x4135(A 5)
-- 0x3031(0 1)
-- 0x3200(0 Null)
R0P7760TH001TRK User’s Manual
Attached Documents
when "000" => RdDatas <= (X"000" & IrqEnaReg); -- Interrupt control register
when "100" => RdDatas <= FpgaId0;
-- 0x5950(Y P)
when "101" => RdDatas <= FpgaId1;
-- 0x4135(A 5)
when "110" => RdDatas <= FpgaId2;
-- 0x3031(0 1)
when "111" => RdDatas <= FpgaId3;
-- 0x3000(0 Null)
when others => RdDatas <= RegRD0;
end case;
else RdDatas <= RegRD0;
end if;
end process;
-- Interrupt control register
process(RegWr, WrDatas, Rst)
begin
if(Rst ='1') then
IrqEnaReg <= "0000";
elsif (RegWr'event and RegWr = '0') then
IrqEnaReg <= WrDatas;
end if;
end process;
end RTL;
R0P7760TH001TRK User’s Manual
Attached Documents
(5)IdReg_r0.vhd
-----------------------------------------------------------------------------------------SH7760 Solution Engine2(MS7760CP01P) FPGA
------------------------------------------------------------------------------------------- module name
: ID register
-- entity
: IdReg_r0
-- file name
: IdReg_r0.vhd
------------------------------------------------------------------------------------------- rev : 0 2003.01.15
Initial release
------------------------------------------------------------------------------------------ (c) copyright Hitachi ULSI Systems Co.,Ltd. 2003
----------------------------------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity IdReg_r0 is
port(
IdRegCs
Rd_x
IdDatas
RdDatas
: in std_logic;
: in std_logic;
: in std_logic_vector(5 downto 0);
: out std_logic_vector(15 downto 0)
);
end IdReg_r0;
Architecture RTL of IdReg_r0 is
begin
process(IdRegCs, Rd_x, IdDatas)
begin
if (IdRegCs = '1' and Rd_x = '0') then RdDatas <= (X"00" & B"00" & IdDatas);
DIP-SW Read
(MDSW(5:0))
else
RdDatas <= X"0000";
end if;
end process;
end RTL;
--
MODE
setting
R0P7760TH001TRK User’s Manual
Attached Documents
(6)SLAddr_r0.vhd
-----------------------------------------------------------------------------------------SH7760 Solution Engine2(MS7760CP01P) FPGA
------------------------------------------------------------------------------------------- module name
: SH Local Address/Control Bus Interface in Extend Connector
-- entity
: SLAddr_r0
-- file name
: SLAddr_r0.vhd
------------------------------------------------------------------------------------------- rev : 0 2003.01.27
Initial release
------------------------------------------------------------------------------------------ (c) copyright Hitachi ULSI Systems Co.,Ltd. 2003
----------------------------------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity SLAddr_r0 is
port(
-- from SH side
ShAdr
ShCkio
ShCs2_x
ShCs4_x
ShCs5_x
ShRdWr
ShBs_x
ShRd_x
ShWe_x
-- from Extend Connector
ExAddrs
ExCkio
ExCs2_x
ExCs4_x
ExCs5_x
ExRdWr
ExBs_x
ExRd_x
ExWe_x
-- from Controler
BusEn
Base_x
);
end SLAddr_r0;
Architecture RTL of SLAddr_r0 is
begin
ExAddrs <= ShAdr
ExCkio
ExCs2_x
<= ShCkio
<= ShCs2_x
: in std_logic_vector(25 downto 0);
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic_vector(3 downto 0);
: out std_logic_vector(25 downto 0);
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic_vector(3 downto 0);
: in std_logic;
: in std_logic
when (BusEn = '1')
else "00000000000000000000000000";
when (Base_x = '0')
else '1';
when (Base_x = '0')
else '1';
R0P7760TH001TRK User’s Manual
end RTL;
Attached Documents
ExCs4_x
<= ShCs4_x
when (Base_x = '0')
else '1';
ExCs5_x
<= ShCs5_x
when (Base_x = '0')
else '1';
ExRdWr
<= ShRdWr
when (Base_x = '0')
else '1';
ExBs_x
<= ShBs_x
when (Base_x= '0')
else '1';
ExRd_x
<= ShRd_x
when (Base_x= '0')
else '1';
ExWe_x
<= ShWe_x
when (Base_x = '0')
else "1111";
R0P7760TH001TRK User’s Manual
Attached Documents
(7)SLData_r0.vhd
-----------------------------------------------------------------------------------------SH7760 Solution Engine2(MS7760CP01P) FPGA
------------------------------------------------------------------------------------------- module name
: SH Local Data Bus Interface in Extend Connector
-- entity
: SLData_r0
-- file name
: SLData_r0.vhd
------------------------------------------------------------------------------------------- rev : 0 2003.01.27
Initial release
------------------------------------------------------------------------------------------ (c) copyright Hitachi ULSI Systems Co.,Ltd. 2003
----------------------------------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity SLData_r0 is
port(
-- from SH side
ShDin
ShDout
-- from Extend Connector
ExDatas
-- from Controler
BusEn
RdWr
);
end SLData_r0;
: in std_logic_vector(31 downto 0);
: out std_logic_vector(31 downto 0);
: inout std_logic_vector(31 downto 0);
: in std_logic;
: in std_logic
Architecture RTL of SLData_r0 is
begin
ExDatas <= ShDin when (BusEn = '1' and RdWr = '0')
else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
ShDout <= ExDatas
end RTL;
when (BusEn = '1' and RdWr = '1')
else "00000000000000000000000000000000";
R0P7760TH001TRK User’s Manual
Attached Documents
(1)ypa5020,vhd
-----------------------------------------------------------------------------------------SH7760 Solution Engine2(MS7760CP01P) FPGA
------------------------------------------------------------------------------------------- module n ame
: CPLD(YPA5020) Top module
-- entity
: YPA5020
-- file name
: YPA5020.vhd
------------------------------------------------------------------------------------------- rev : 0 2003.01.28
Initial release
------------------------------------------------------------------------------------------ (c) copyright Hitachi ULSI Systems Co.,Ltd. 2003
-----------------------------------------------------------------------------------------
---------------------------------------------------------------------------------Library
-------------------------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------------------------------
---------------------------------------------------------------------------------Entity
-------------------------------------------------------------------------------entity YPA5020 is
port(
-- from SH7760
ShExtal
: in std_logic;
-- form ROM-ICE I/F
ExRstIn_x : in std_logic;
ExNmiIn
: in std_logic;
H8Rst_x
: in std_logic;
-- from H8/3048
ShRst_x
ShNmiIn
: in std_logic;
: in std_logic;
-- to SH7760
ShNmiOut: out std_logic;
-- to etc
Rst
Rst_x
MdSel
: out std_logic;
: out std_logic_vector(2 downto 0);
: out std_logic
);
end YPA5020;
--------------------------------------------------------------------------------
R0P7760TH001TRK User’s Manual
Attached Documents
---------------------------------------------------------------------------------Architecture
-------------------------------------------------------------------------------Architecture RTL of YPA5020 is
component RstCnt_r0
port(
ShExtal
: in std_logic;
ExRstIn_x : in std_logic;
ShRst_x
: in std_logic;
H8Rst_x
: in std_logic;
RstOut
MdSel
: out std_logic;
: out std_logic
);
end component;
---------------------------------------------------------------------------------Signal
-------------------------------------------------------------------------------signal
RstOut
:std_logic;
---------------------------------------------------------------------------------Function
---------------------------------------------------------------------------------Low hierarchy port map
begin
--Reset
Rst_x
Rst
<= "000" when (RstOut = '1')
else "111";
<= RstOut;
-- NMI
ShNmiOut <= '0' when (ShNmiIn = '0'
or ExNmiIn = '0')
else '1';
U_RstCnt : RstCnt_r0 port map (
ShExtal
=> ShExtal,
ExRstIn_x
=> ExRstIn_x,
ShRst_x
=> ShRst_x,
H8Rst_x
=> H8Rst_x,
RstOut
MdSel
);
end RTL;
=> RstOut,
=> MdSel
R0P7760TH001TRK User’s Manual
Attached Documents
(2) RstCnt_r0.vhd
-----------------------------------------------------------------------------------------SH7760 Solution Engine2(MS7760CP01P) FPGA
------------------------------------------------------------------------------------------- module name
: Reset control for MS7760CP01P/0
-- entity
: RstCnt_r0
-- file name
: RstCnt_r0.vhd
------------------------------------------------------------------------------------------- rev : 0 2003.01.15
Initial release
------------------------------------------------------------------------------------------ (c) copyright Hitachi ULSI Systems Co.,Ltd. 2003
----------------------------------------------------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity RstCnt_r0 is
port(
ShExtal
ExRstIn_x
ShRst_x
H8Rst_x
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
RstOut
MdSel
: out std_logic;
: out std_logic
);
end RstCnt_r0;
Architecture RTL of RstCnt_r0 is
signal
begin
MdSel_r :std_logic;
--Reset control
RstOut <= '1' When (ExRstIn_x = '0'
or ShRst_x
or H8Rst_x
else '0';
= '0'
= '0')
process(ShExtal, ExRstIn_x, ShRst_x, H8Rst_x)
begin
if(ExRstIn_x = '0' or ShRst_x ='0' or H8Rst_x ='0') then
MdSel_r <= '0';
elsif (ShExtal'event and ShExtal = '1') then
MdSel_r <= '1';
end if;
end process;
process(ShExtal)
begin
if (ShExtal'event and ShExtal = '1') then
MdSel <= MdSel_r;
end if;
end process;
end RTL;
R0P7760TH001TRK User’s Manual
11.3 T-Engine Board Circuit Diagrams
11.3.1 CPU Board Circuit Diagrams (MS7760CP01/1)
11.3.2 LCD Board Circuit Diagrams (MS7760LCD01/4)
11.3.3 Debug Board Circuit Diagrams (MS7760DBG01/3)
11.3.4 I/O Board Circuit Diagrams
11.4 T-Engine Board Dimensions
11.4.1 CPU Board (MS7760CP01/3) Dimensions
11.4.2 LCD Board (MS7760LCD01/4) Dimensions
11.4.3 Debug Board (MS7760DBG01/3) Dimensions
Attached Documents
1
2
3
4
5
6
7
8
CPU:SH7760(1)
D[31:0]
U7
A[25:0]
4/A6,4/E5,5/C2,5/A3,6/C2
U7
A
A25
A25
A24
R17
A24
A23
T18
A23
T17
A22
N4
A21
L4
A20
U15
A19
A18
U13
A18
A17
U9
A17
D22
A16
V15
V17
D21
A15
U17
D20
A14
Y19
D19
Y20
D18
V19
D17
U19
D16
D15
U2
D15
D14
V2
D14
D13
Y1
D13
D12
Y2
D11
D31
D31
D30
V20
D30
D29
W20
D29
U18
D28
W18
D27
Y18
D26
W17
D25
D24
W16
D24
D23
Y16
D23
D22
Y17
D21
D20
U7
MFID15/LCDD15/FLD7
STATUS1
D8
STATUS1
9/E2
MFID14/LCDD14/FLD6
M1
LCDD14
STATUS0
D6
STATUS0
9/E2
MFID13/LCDD13/FLD5
L1
LCDD13
K1
LCDD12
J1
LCDD11
H1
LCDD10
G1
LCDD9
MFID8/LCDD8/FLD0
F1
LCDD8
CS2
J4
MFID7/LCDD7/DRAK3/DACK3
N2
LCDD7
CS1
A16
MFID6/LCDD6/DREQ3
M2
LCDD6
V13
A15
MFID5/LCDD5/DRAK2/DACK2
L2
LCDD5
W13
A14
MFID4/LCDD4/DREQ2
K2
LCDD4
Y13
A13
J2
LCDD3
W12
A12
H2
LCDD2
Y12
A11
G2
LCDD1
W11
A10
F2
LCDD0
A9
Y11
A9
A8
W10
A8
A7
V9
A7
D12
A6
W9
U4
D11
A5
V4
D10
Y4
D9
Y5
D8
W5
D7
D6
W4
D6
D5
Y3
D5
D4
W3
D4
BREQ
E4
D3
U3
D3
BACK
F4
D2
W1
D2
D1
V1
D1
U1
D0
D26
D25
D19
D18
D17
D16
D10
D9
D8
D7
D0
A22
A21
A20
A19
A13
A12
A11
A10
A4
A3
A2
A1
A0
RESET
MRESET
NMI
CMT_CTR3
CMT_CTR2
A9
B9
CA
CMT_CTR3 11/C4,11/C2
MFID12/LCDD12/FLD4
MFID11/LCDD11/FLD3
MFID10/LCDD10/FLD2
MFID9/LCDD9/FLD1
MFID3/LCDD3/IRQ7
MFID2/LCDD2/IRQ6
MFID1/LCDD1
MFID0/LCDD0
CS6
WE3/DQM3/ICIOWR
Y14
WE3_DQM3 4/B2,5/C5
A6
MFI_MD/LCD_CL2
R2
CL2
7/C5
WE2/DQM2/ICIORD
W14
WE2_DQM2 4/B2,5/C5
Y9
A5
MFI_RS/LCD_M_DISP
T1
M_DISP
7/C5
WE1/DQM1
Y7
WE1_DQM1 4/C2,5/C2,5/C5,6/D2
W8
A4
FLM
7/C5
WE0/DQM0/REG
Y8
A3
VCPWC
7/C5
V6
A2
VEPWC
7/C5
T4
A1
R4
A0
MFI_RW/LCD_FLM
VCPWC/IRQ4
VEPWC/IRQ5
1 R39 2
R=10K
RST0
1/C7,3/D3,4/D2,5/C2
NMI
3/C3
D5
E2
FWE
K20
FWE
11/A2
FCDE
J19
FCDE
11/A2
FCE
J20
FCE
11/A2
FSC
H20
FSC
11/A2
FOE
H19
FOE
11/A2
SIM_CLK
7/D5
SIM_RST
7/E5
SIM_D
7/E5
SPI_RX
1/D5
SPI_CLK/SIM_CLK/MCCLK
B10
E1
E3
SPI_CS/SIM_RST/MCCMD
SPI_TX/SIM_D/MCDAT
A7
B7
A6
B6
I2C1_SCL
F17
I2C1_SCL
11/B2
I2C0_SCL
F19
I2C0_SCL
1/D5,9/B2
IRL0
I2C1_SDA
F18
I2C1_SDA
11/B2
I2C0_SDA
F20
I2C0_SDA
1/D5,9/B2
LCD_CLK
1/B5
SPI_RX
1/C5
I2C0_SCL
1/D5,9/B2
I2C0_SDA
1/D5,9/B2
SCIF1_RXD
SCIF1_RXD 11/B4,11/B2
SCIF1_RTS
B15
SCIF1_RTS 11/B2
SCIF1_CTS
B14
SCIF1_CTS 11/C4,11/B2
SCIF1_CLK
B11
SCIF0_RXD
SCIF0_CLK
B16
A15
4/E2,4/A3
RDY
4/C2
MD7
1/E4
SCIF1_CLK
11/C4,11/B2
SCIF0_TXD
11/B2
SCIF0_RXD 11/B4,11/B2
SCIF0_CLK
11/B4,11/B2
H17
MD6
3/B3
G19
MD5/FRB
G20
MD5
3/B3
MD4/CE2B
A17
MD4
3/B3
MD3/CE2A
B17
MD3
3/B3
MD2
C16
MD0
HD6417760BP200D
SH7760(2/8)
WE0_DQM0 4/C2,5/E2,5/C5,6/D2
C15
HDI_TCK
D12
HDI_TDI
10/E2,10/A7
10/E2,10/B7
TDO
C12
HDI_TDO
10/E2,10/B7
TMS
C10
HDI_TMS
10/E2,10/B7
TRST
D10
ASEBRK
10/E2,10/B7
ASEBRK/BRKACK
C8
HD6417760BP200D
SH7760(4/8)
U9
4
3.3V;5
GND;3
1
2
RST0
1/C4,3/D3,4/D2,5/C2
HDI_TRST
10/E2,10/B7
HD74LV1G08ACM
HD6417760BP200D
SH7760(3/8)
1 R51 2
1 R34 2 R=10K
1 R12 2 R=10K
1 R11 2 R=10K
R=10K
3.3V
D17
D16
W7
3.3V
H18
MD6/IOIS16
MD1
A16
IRL0
SCIF2_CTS 10/A7
B13
SCIF0_TXD
C1
TCK
TDI
3.3V
B1
T2
4/E2,4/A2
11/B2
4/B2,5/E2,5/C2,5/C5,6/D2
7/C5
4/E2,4/A3
SCIF1_TXD
5/C5
RD
CL1
N20
B12
RAS
Y6
R1
4/E2,4/B2
SCIF1_TXD
4/A2,5/C5
W15
MFI_E/LCD_CL1
IRL1
MD7
4/B2,6/D2
RDWR
W6
RAS
IRL2
MD8
5/D5
BS
T3
RD/CASS/FRAME
IRL3
A10
CKE
U6
7/C5
N19
SCIF2_CLK
4/B2,5/D5,6/F2
D1
1/D5
M20
SCIF2_CTS
CKIO
LCD_DON
IRL1
A13
Y10
LCD_CLK
M19
RDY
4/D2
CKIO
Y15
P2
IRL2
SCIF2_RTS 10/D5
CS0
L3
MFI_CS/LCD_DON
IRL3
A14
4/A2
CS0
F3
N3
MFI_INT/LCD_CLK
SPI_RX
10/C5
CS1
BS
CMT_CTR0 11/C4,11/C2
SCIF2_RXD 10/C5
4/B2
J3
CKE
CMT_CTR1 11/C4,11/C2
SCIF2_TXD
4/A2,5/C5
CS2
RD/WR
B8
A12
4/A2
CS3
DCK
A8
SCIF2_RXD
4/A2
CS4
CS3
CMT_CTR1
SCIF2_TXD
4/D2
CS5
CS4
P1
CMT_CTR2 11/C4,11/C2
A11
R3
CS6
CS5
CMT_CTR0/TCLK
SCIF2_RTS
D
7/A5
LCDD15
D27
C
LCDD[15:0]
N1
D28
B
4/E6,4/A2,5/D2,5/A2,6/A2
U7
R18
U20
1 R13 2
R=10K
GND
HD6417760BP200D
SH7760(1/8)
E
3.3V
1 R14 2
MD7
1/D4
01
R=10K
1 R15 2
R=0
Do not stuff
GND
F
Title: MS7760CP01P/1 Circuit Diagram
Date: 7-29-2003_14:52
Sheet
1
of
12
C=0.1UF
V=16V
1
D18
VDDQ12
C17
VDDQ11
3/C3
DRAK0
V18
CAN1_TX
T20
CAN1_TX
10/B7,11/C2
VDDQ9
V16
10/B7,11/C2
VDDQ8
V12
CAN1_RX
10/B7,11/C4,11/C2
VDDQ7
V11
R19
CAN0_RX
10/B7,11/C4,11/C2
VDDQ6
V10
CAN1_NERR
10/B7,11/C4,11/C2
VDDQ5
CAN0_NERR
10/C7,11/C4,11/C2
VDDQ4
VSS-PLL1
2
CAN0_TX
R20
CAN0_RX
2
T19
CAN1_RX
2
CAN0_TX
CAN1_NERR
CAN0_NERR
P19
VDDQ3
GND
GND
GND
1 R35 2
1 R36 2 R=10K
1 R10 2 R=10K
AN2
AN2
11/D3
VDDQ1
K3
AN1
L19
AN1
11/D3
VDDQ0
H3
AN0
L20
AN0
11/E3
ADTRG
2/C2
USB_DM
7/E2
VSS7
USB_DP
7/E2
VSS6
ADTRG
2/B5
2/B4
USB_DM
B19
ADTRG
2/C4
USB_DP
2/A5
USB_OVC
UCLK
C20
C18
D20
A20
7/E2
VSS3
UCLK
2/F2
VSS2
U7
VSS1
P4
VSS0
G4
VSSQ18
D9
1
K17
C=10UF
V=10V
C68
+ 1
2
C=0.01UF
V=50V
1
C67
2
C=10UF
V=10V
C7
+ 1
VSSQ17
VSSQ16
VSSQ15
VSSQ14
SH_AVSS
GND
11/D3
11/E3
C=0.1UF
V=16V
GND
2
GND OUT
F=48.0MHZ
1
C6
3
3.3V
1 R25 2
R=33
UCLK
1
C70
C=0.1UF
V=16V
2
1
C85
C=0.1UF
V=16V
2
1
C76
1
C79
C=0.1UF
V=16V
2
1
C78
C=0.1UF
V=16V
2
1
C71
C=0.1UF
V=16V
1
E17
M17
N17
VSSQ10
W19
VSSQ9
U16
VSSQ5
U12
U11
U10
U8
U5
VSSQ3
W2
VSSQ2
M4
VSSQ1
K4
VSSQ0
H4
HD6417760BP200D
SH7760(8/8)
OSC2
SG-8002JF-48.000000M-PCCB
1 OE/ST VCC 4
C=0.01UF
V=50V
D15
VSSQ11
VSSQ4
2
D13
J17
VSSQ6
2/A2,3/C2
D11
VSSQ12
VSSQ7
EXTAL
U14
VSSQ13
VSSQ8
F=16.6MHZ
C91
AVSS_ADC
2
2
HD6417760BP200D
SH7760(6/8)
VSSQ_USB
C19
P17
USB_OVC
SH_AVCC
C8
D
G17
VSS4
K18
1
AVCC_ADC
1 R92 2
R=33
GND
D14
7/E2
B20
C=0.01UF
V=50V
VDDQ_USB
3
GND
D7
USB_PENC
3.3V
GND OUT
GND
HD6417760BP200D
SH7760(7/8)
VSS5
3.3V
GND
U7
USB_PENC
OSC1
SG-8002JF-16.666700M-PCCB
1 OE/ST VCC 4
GND
M3
VDDQ2
AC97_RES
GND
V3
11/D3
DREQ1
GND
V5
AN3
K19
AC97_BIT_CLK1
1 R16 2 R=10K
R=10K
L17
GND
V8
L18
AN3
GND
3.3V
C
P20
3.3V
N18
VDDQ10
B18
B4
3.3V
M18
B2
C3
2
J18
C66
E18
3.3V
C=0.1UF
V=16V
C13
3.3V
2
VDDQ15
1
3/C3
3.3V
C65
DREQ0
3.3V
C=0.01UF
V=50V
E19
3.3V
2
DREQ0
3.3V
1
C11
GND
C77
VDDQ16
GND
C=0.01UF
V=50V
2/C2
VDDQ13
VCC
GND
2
C9
DREQ1
3/C3
2
P8
P7
P6
VDDQ17
E20
DACK0
VCC
GND
1
G3
3.3V
VDDQ14
VCC
P3
2/C2
D19
VCC
V7
VSS-CPG
HD6417760BP200D
SH7760(5/8)
E
V14
DREQ1
A18
8
P9
1
1
AC97_RES
DRAK0
C15
P5
C4
1608(0603)
1 R38 2
R=10
1608(0603)
1 R83 2
R=10
1
AC97_RES
DRAK1
C73
+ 1
P4
VDD0
A4
C=10UF
V=10V
1
VDD1
9/D3
B3
C87
+ 1
VDD2
P18
VSS-PLL3
VSS-PLL2
2
VDD3
2/C2
DACK0
C=10UF
V=10V
G18
VDD4
AC97_BIT_CLK0
DACK1
C86
+ 1
VDD-PLL1
VDD5
AC97_BIT_CLK1
A19
2
B
1608(0603)
1 R93 2
R=10
1608(0603)
1 R85 2
R=10
VDD-PLL2
R=0
9/A2
9/A2
C2
A3
C=10UF
V=10V
VDD-PLL3
D4
SSI_SCK
SSI_WS
AC97_BIT_CLK0
AC97_BIT_CLK1
VDD-CPG
B5
C14
C83
SSI0_WS/AC97_SYNC0
3.3V
D3
C7
VDD6
C=0.01UF
V=50V
VCC
1 R45 2 R=0
1 R50 2 R=0
1 R46 2 R=0
A5
VDD7
9/A2
1
D2
SSI1_WS/AC97_SYNC1
9/A2
SSI0_SDATA
2
A2
SSI1_SDATA
C69
SSI1_SCK/AC97_SD_IN1
SSI0_SCK/AC97_SD_IN0/BS2
XTAL
VCC
U7
1 R47 2
1 R48 2 R=0
1 R49 2 R=0
C=0.01UF
V=50V
C5
2
C6
SSI0_SDATA/AC97_SD_OUT0
1
A
SSI1_SDATA/AC97_SD_OUT1
7
C84
2/E2,3/C2
6
C=0.01UF
V=50V
EXTAL
5
2
A1
1
P1
U7
EXTAL
1
1
U7
P3
4
P2
3
1
2
1
1
CPU:SH7760(2)
02
GND
2/C4
2
C=0.1UF
V=16V
GND
F
Title: MS7760CP01P/1 Circuit Diagram
Date: 7-29-2003_14:52
Sheet
2
of
12
1
2
3
4
5
6
7
8
SH7760 MODE CONTROL & SIRIAL I/F
3.3V
(G4)
U4
1
R9
2
17
R=10K 21
3/E6,6/F2
1 R23 2
4
1 R24 2 R=1K 8
R=10K 14
1 R8 2
18
MD5SW
A1
C1
A2
C2
6
10
16
A3
C3
A4
C4
20
B0
D0
5
MD3
1/D4
5/D4
B1
D1
9
MD4
1/D4
5/D4
B2
D2
15
MD5
1/D4
B3
R=10K 22
(G4)
19
D3
B4
(G4)
2
MD6
5/D4
1/D4
23
D4
5/D4
U2
2
4
C1+
C2+
C1-
C2-
TXB
13
T1IN T1OUT
RTSB
12
T2IN T2OUT
15
RXB
10
CTSB
R1OUT R1IN
R2OUT R2IN
5
6
C=0.1UF
V=25V
11
FRB
C0
1608(0603)
C12
2
1
7
CE2B
11/B4,11/B2
A0
1608(0603)
C11
2
1
3
CE2A
C=0.1UF
V=25V
A
3.3V
(G4)
CN1
17 (G4)
8 (G4)
16 (G4)
9 (G4)
1
GND
2
TxD
3
RxD
4
GND
5
6
3.3V
3.3V
4/C8
C
2/E2,2/A2
3/C5,4/C8
8/F2,8/A4
1
IO4
2
IO6
IO3
3
IO7
IO2
ISP_TD
4
TDI
IO1
45
EXTAL
5
CLK0/I0
IO0
44
3/C2,4/C8
ISP_TCK
6
NC0
GND3
43
3/D3,4/C8
ISP_TMS
7
GND0
NC3
42
4/C8
ISP_TDI
3/D3
ISP_TDO
8
ISP_TCK
TCK
9
SH_RST
10
11
8/A4
SH_NMI
10/C5
A_DRAK0
10/C5
40
39
38
DREQ0
2/B4
DACK0
2/B4
DRAK0
2/B4
IO28
37
NMI
1/C4
13
IO12
IO27
36
MDSEL
3/B2
14
IO13
IO26
35
15
IO14
IO25
34
16
IO15
IO24
33
VCC0
TDO
GND2
NC1
NC2
GND1
32
RST
5/E2
ISP_TDO
3/C5
2
7
V-
IO17
TMS
28
ISP_TMS
3/C5,4/C8
22
IO18
IO23
27
RST2
10/C5
23
IO19
IO22
26
RST1
7/B7
24
IO20
IO21
25
RST0
1/C7,1/C4,4/D2,5/C2
3
1
1
C55
C=100PF
V=50V
2
C56
C=100PF
V=50V
2
1
C=100PF
V=50V
1
R6
2
R=10K 1
R7
2
13
12
4/A3
ID4
4/A3
ID5
6
11
8/D7,8/A3
H8_MD
7
10
MD5SW
8
9
03
Vcc=1.5V
GND
GND
1 R2 2
R=69.8K(FX)
1608(0603)
1
SD1
2
C1
GND
1
L3
L=4.7UH
2
CMS03
1
C9
C=10UF
V=10V
3225(1210)
2
1
C10
C=0.1UF
V=16V
14
4
GND
1 R1 2
R=78.7K(FX)
1608(0603)
SI3443DV 1 2 5 6
1
2
15
3
VCC
4
LTC1772CS6
GND
16
2
GND
5
C=100PF
V=50V
SENSE-
6
2
VFB
VIN
C3
+ 1
PGATE
GND
C=100UF
V=6.3V
ITH/RUN
SW5
1
5
3/B2,6/F2
1
1
3.3V
Q3 4
2
2
R4
R=10K
3
ID3
1
ID2
2
4/A3
3
2
C2
TDO
5 NR1
ID1
4
4/A3
6
ID0
7
4/A3
8
1
C=220PF
V=50V
GND
3.3V
9
U1
2
GND
RMC-EA15MY-OM15-MC1
R=10K
3216(1206)
1 R5 2
R=0.03
GND
TDI
15
3.3V
E
F
BScan
GND
GND
GND
Plug
13
29
21
GND
TMS
12
30
CLK1/I1
1
GND
11
GND
VBAT
TR2
GND
TCK
10
R=10K
IO16
3
GND
GND
9
14
GND
4/A3
DTC143ZE-TL
2
18
CTS
31
GND
VCC_ON
GND
SP3223ECY
M4A3-32_32-VC48
8/D7,8/E4
VCC
C54
V+
19
8
RTS
GND
41
IO29
20
A_NMI_IN
IO30
A_DACK0
46
3
3.3V
10
10/C5,10/D2
IO31
IO9
47
IO11
19
A_RST_IN
IO8
10/C5,10/E2
IO10
18
D
VCC1
A_DREQ0
12
17
10/C5,10/D2
48
IO5
H8_RES
(G4)
C=0.1UF
V=25V
GND 1608(0603)
U10
8/D7,8/A4,8/A7,12/A7
C13
ONLINE
2
C=0.1UF
V=25V
1
(G4)
SHUTDOWN
14
2
1608(0603)
C4
1
2
GND
20
11
C=100PF
V=50V
SN74CBTLV3383DGV
STATUS
1
MDSEL
EN
C5
1
1
C=0.1UF
V=16V
3/D3
BX 3.3V;24
GND;12
BE
C57
3.3V
13
GND
2
B
1
7
GND
Title: MS7760CP01/P1 Circuit Diagram
Date: 7-29-2003_14:52
Sheet
3
of
12
1
2
3
4
5
6
7
8
CPLD
IO4
IO5
IO6
IO52
FLASHCE
5/C2
IO53
IO54
ID3
L6
M5
K2
A_A0
IO101
IRL0
1/D4,4/E2
IO102
D6
VCC2
D9
D11
G12
D12
G14
D13
G15
D14
IO151
G11
D15
VCC7
G10
IO147
IO148
IO149
IO150
VCC3
VCC4
VCC5
VCC6
D11
E13
F4
GND
G7
RDWR
1/B7,5/C5
IO55
IO8
E6
IRL1
1/D4,4/E2
IO56
K1
IO104
R12
A_D16
IO152
F16
D16
VCC8
G13
IO9
A5
IRL3
1/C4,4/E2
IO57
L1
IO105
M11
A_D17
IO153
F11
D17
VCC9
H4
IO10
B5
PC_IRQ3
4/E2,6/E2
IO58
M1
ROMSEL
10/C5,10/E2
IO106
P11
A_D18
IO154
F12
D18
VCC10
H8
IO11
F6
CS2
1/A7
IO59
L3
BASE
10/E2,10/C5
IO107
M12
A_D19
IO155
F14
D19
VCC11
H9
RD
1/B7,5/E2,5/C2,5/C5,6/D2
IO60
P12
A_D20
E16
D20
T13
A_D21
F15
D21
T14
A_D22
D16
D22
R13
A_D23
D15
D23
A_D24
D24
IO15
C6
A4
C5
A3
PC_RDY
6/E2
IO61
PC_IRQ1
4/E2,6/E2
IO62
WE3_DQM3 1/B7,5/C5
IO63
IO16
B4
PC_CS
6/D2
IO17
D3
CKIO
1/B7,5/D5,6/F2
IO18
A2
IO19
B3
IO20
A1
IO21
B2
IO22
IO23
IO24
WE2_DQM2 1/B7,5/C5
C3
BS
C4
H5
G2
1/B7,6/D2
1/D4,4/E2
IRL2
L2
IO108
N1
P1
M2
A_WAIT
10/B5,10/E2
IO109
A_IRQ0
10/B5,10/D2
IO110
A_IRQ1
10/B5,10/D2
IO111
IO156
IO157
IO158
IO159
VCC12
VCC13
VCC14
VCC15
K7
IO64
A_IRQ2
10/C5,10/D2
IO112
IO160
VCC16
K10
IO65
P2
A_IRQ3
10/C5,10/D2
IO113
T15
A_D25
IO161
E11
D25
VCC17
K13
IO66
R1
A_WE3
10/B5
IO114
T16
A_D26
IO162
E14
D26
VCC18
M4
IO67
R2
IO115
R15
A_D27
IO163
C16
D27
VCC19
N6
IO68
M3
A_WE1
10/B5
IO116
R16
A_D28
IO164
C15
D28
VCC20
N9
IO69
T1
A_WE0
10/B5
IO117
P15
A_D29
IO165
B16
D29
VCC21
N11
P14
A_D30
B15
D30
P13
A_D31
A16
D31
K15
A_D0
B10
A15
K14
A_D1
F9
A14
A_D2
IO170
C11
A13
TDI
IO70
WE1_DQM1 1/B7,5/C2,5/C5,6/D2
IO71
RDY
1/D4
IO72
UART_CSB
5/D2
IO73
A_RD
R3
IO118
10/B5
A_BS
IO119
10/B5
R7
A_A16
T6
A_A17
IO74
M8
A_A18
IO122
K11
IO120
IO166
IO167
IO168
VCC22
GND
K4
E12
T2
GND
J9
R14
10/B5
GND
J8
N2
A_WE2
1
IO103
T12
3/E6
VCC1
D10
G16
C98
A_A1
ID5
3.3V
N13
N3
ISP_TCK
3/C5,3/C2
IO26
G3
C2
ISP_TDI
3/C5
IO27
H6
UART_INTB 5/E4
IO75
L8
A_A19
IO123
K12
A_D3
IO171
C10
A12
TDO
D14
ISP_TD
3/C2
IO28
G5
WE0_DQM0 1/B7,5/E2,5/C5,6/D2
IO76
R6
A_A20
IO124
L16
A_D4
IO172
A11
A11
TMS
P3
ISP_TMS
3/C5,3/D3
IO29
F1
IO77
L7
A_A21
IO125
L15
A_D5
IO173
B11
A10
IO30
F2
IO78
T5
A_A22
IO126
L11
A_D6
IO174
A12
A9
P6
A_A23
L14
A_D7
B12
A8
M7
A_A24
M16
A_D8
F10
A7
R5
A_A25
M15
A_D9
A13
A6
L12
A_D10
C12
A5
IO131
M14
A_D11
IO179
B13
A4
GND3
D10
A_D12
IO180
A14
A3
GND4
D12
IO181
A15
A2
GND5
D13
A1
IO25
IO31
IO32
IO33
IO34
E1
G6
F5
IO35
E2
IO36
E3
IO37
D1
IO38
D2
IO39
C1
IO40
K5
IO41
IO42
IO43
IO44
IO79
F3
UART_CSA
5/D2
IO80
H8_IRQ
8/A4
IO81
PC_IRQ2
4/E2,6/E2
IO82
CS0
PC_IRQ0
K6
1/B7
4/E2,6/E2
UART_INTA 5/E4
H1
PCIC_RST
6/F2,6/D5
H2
IO127
IO128
IO129
A_CKIO
10/A3
IO130
IO169
IO175
IO176
IO177
IO178
TCK
M4A3-256_192-7FAC
M4A3-256/192(5/6)
U11
GND0
GND1
GND2
D5
D7
D8
IO83
M6
IO84
P5
A_CS2
10/A5
IO132
N16
IO85
R4
A_CS4
10/A5
IO133
N15
A_D13
IO86
T3
IO134
P16
A_D14
IO182
B14
GND6
E4
IO87
P4
IO135
N14
A_D15
IO183
C13
A0
GND7
F13
IO88
T9
A_A8
IO136
H12
D0
IO184
C8
A23
GND8
G4
P9
A_A9
H11
D1
F8
A22
M9
A_A10
J16
D2
A9
A21
L9
A_A11
J15
D3
B9
A20
R8
A_A12
J14
D4
E8
A19
A_A13
IO141
J11
D5
IO189
C9
A18
GND13
H13
IO89
IO90
IO91
H3
T4
IO121
IO92
A_EPROMCE
A_CS5
10/A5
10/A5
A_RDWR
10/B5
IO137
IO138
IO139
IO140
IO185
IO186
IO187
IO188
GND9
GND10
GND11
GND12
G8
G9
H7
H10
IO45
J5
RST0
1/C7,1/C4,3/D3,5/C2
IO93
P8
IO46
J6
CS6
1/A7
IO94
P7
A_A14
IO142
J12
D6
IO190
E10
A17
GND14
J4
IO47
G1
IO95
T7
A_A15
IO143
K16
D7
IO191
A10
A16
GND15
J7
GBCLK0
A6
GBCLK1
T8
GBCLK2
T11
M4A3-256_192-7FAC
M4A3-256/192(1/6)
M4A3-256_192-7FAC
M4A3-256/192(2/6)
GND
M4A3-256_192-7FAC
M4A3-256/192(3/6)
GND
A_A[25:0]
3.3V
5 NR2
E
J13
M4A3-256_192-7FAC
M4A3-256/192(4/6)
GND18
GND
D[31:0]
1/A2,4/A6,5/C2,5/A3,6/C2
GND
A[25:0]
1/A4,4/A2,5/D2,5/A2,6/A2
GND19
GND20
GND21
K8
K9
L4
L13
IRL0
1/D4,4/A3
GND22
M13
2
IRL1
1/D4,4/A2
GND23
N4
3
IRL2
1/D4,4/A3
GND24
N5
4
IRL3
1/C4,4/B2
GND25
N7
6
PC_IRQ0
4/D2,6/E2
GND26
N8
PC_IRQ1
4/B2,6/E2
GND27
PC_IRQ2
4/C2,6/E2
GND28
PC_IRQ3
4/B2,6/E2
8
9
R=10K
J10
GND17
1
7
10
4/A5,10/A3
GND16
E9
GBCLK3
C=0.1UF
V=16V
A_A2
R11
IO100
D9
H15
1
P10
3/E6
H14
C90
A_A3
ID4
3.3V
C=0.1UF
V=16V
M10
IO99
3/E6
3.3V
2
IO51
3.3V
1
IO146
A_A4
ID2
L5
D4
C96
IO145
A_A5
R10
ID1
J1
1/B7
1/A7
A_A6
L10
J3
IO50
CS1
CS4
T10
IO98
IO49
3.3V
VCC0
IO7
IO14
D
C7
IO97
3/E6
3/E6
K3
IO13
C
B7
1/A7,5/C5
3/E6
ID0
D8
B6
IO12
B
CS3
F7
1/A7
IO144
IO48
1/A2,4/E5,5/C2,5/A3,6/C2
U11
IO96
H16
2
IO3
CS5
A7
D[31:0]
U11
C=0.1UF
V=16V
E7
10/A2
2
A8 A25
IO2
4/E3,10/A3
A_D[31:0]
A_A7
1
IO1
A_A[25:0]
R9
C97
A
IO0
U11
J2
C=0.1UF
V=16V
1/A4,4/E6,5/D2,5/A2,6/A2
U11
B8 A24
2
A[25:0]
U11 YPA501x
N10
04
N12
M4A3-256_192-7FAC
M4A3-256/192(6/6)
GND
F
Title: MS7760CP01P/1 Circuit Diagram
Date: 7-29-2003_14:52
Sheet
4
of
12
1
2
3
4
5
6
7
8
FLASH MEMORY&SDRAM
1/A2,4/A6,4/E5,5/C2,6/C2
D[31:0]
1/A4,4/E6,4/A2,5/D2,6/A2
A[25:0]
M3
A21
DQ15/A-1
45
D15
A16
21
BA1
DQ15
53
D31
A16
21
BA1
DQ15
53
D15
10
A20
DQ14
43
D14
A15
20
BA0
DQ14
51
D30
A15
20
BA0
DQ14
51
D14
A20
9
41
D13
A14
36
50
D29
A14
36
50
D13
A19
16
39
D12
A13
35
48
D28
A13
35
48
D12
A18
17
36
D11
A12
22
47
D27
A12
22
47
D11
A17
48
A16
DQ10
34
D10
A11
34
A9
DQ10
45
D26
A11
34
A9
DQ10
45
D10
A16
1
A15
DQ9
32
D9
A10
33
A8
DQ9
44
D25
A10
33
A8
DQ9
44
D9
A15
2
A14
DQ8
30
D8
A9
32
A7
DQ8
42
D24
A9
32
A7
DQ8
42
D8
A14
3
A13
DQ7
44
D7
A8
31
A6
DQ7
13
D23
A8
31
A6
DQ7
13
D7
A13
4
A12
DQ6
42
D6
A7
30
A5
DQ6
11
D22
A7
30
A5
DQ6
11
D6
A12
5
A11
DQ5
40
D5
A6
29
A4
DQ5
10
D21
A6
29
A4
DQ5
10
D5
A11
6
38
D4
A5
26
8
D20
A5
26
8
D4
A10
7
35
D3
A4
25
7
D19
A4
25
7
D3
33
D2
A3
24
5
D18
A3
24
5
D2
31
D1
A2
23
4
D17
A2
23
4
D1
29
D0
2
D16
2
D0
A19
DQ13
A18
DQ12
A17
DQ11
A10
DQ4
A9
DQ3
A8
DQ2
DQ12
A10
DQ11
DQ4
A3
A2
DQ3
A1
DQ2
A12
DQ13
A11
DQ12
A10
DQ11
DQ4
A3
A2
DQ3
A1
DQ2
8
18
A7
19
A6
A6
20
A5
19
CS
19
CS
A7
DQ1
DQ0
A0
DQ1
DQ0
A0
DQ1
DQ0
21
A4
18
RAS
18
RAS
A4
22
A3
17
CAS
17
CAS
A3
23
A2
16
WE
16
WE
A2
24
A1
25
A0
RY/BY#
15
38
BYTE
4/A2
FLASHCE
26
CE
1/B7,4/B2,5/E2,5/C5,6/D2
RD
28
OE
1/B7,4/C2,5/C5,6/D2 WE1_DQM1
11
WE
14
WP#/ACC
12
RESET
1 R79 2
R=10k
15
37
3.3V
1
47
39
A1
3.3V;37
GND;27,46
C72
1 R82 2
R=10k
RST0
DQ13
A11
A8
3.3V
1/C7,1/C4,3/D3,4/D2
A12
A9
A5
C
M2
13
A21
39
UDQM
15
LDQM
38
CLK
37
CKE
EDS2516APTA-75
3.3V;1,3,9,14,27,43,49
GND;6,12,28,41,46,52,54
C=0.1UF
V=16V
B
M1
A22
2
A
1/A7,4/A2
1/B7
MBM29DL640E90TN
GND
UDQM
LDQM
CLK
CKE
EDS2516APTA-75
3.3V;1,3,9,14,27,43,49
GND;6,12,28,41,46,52,54
CS3
RAS
1/B7,4/B2,5/E2,5/C2,6/D2
RD
1/B7,4/A2
RDWR
1/B7,4/B2 WE3_DQM3
1/B7,4/B2 WE2_DQM2
U18
D7
CDB
16
D6
2
D6
TXB
8
TXB
3/B5
1/B7,4/B2,6/F2
CKIO
D5
1
D5
RXB
4
RXB
3/B5
1/B7
CKE
D4
48
D4
RTSB
22
RTSB
3/B5
D3
47
D3
CTSB
23
CTSB
3/B5
D2
46
D2
DTRB
D1
45
D1
DSRB
D0
44
D0
RIB
A3
26
A2
CDA
40
A2
27
A1
TXA
7
A1
28
A0
RXA
UART_CSB
4/C2
UART_CSA
11
10
19
RD
15
1/B7,4/C2,5/C5,6/D2 WE0_DQM0
18
E
3/D3
RST
H8_CK
1 R81 2
R=2K
TXA
8/E4
RXA
8/E3
RTSA
8/C2
CSB
CTSA
38
CTSA
8/A4
CSA
DTRA
IOR
DSRA
IOW
RIA
3.3V
GND
GND
1
C60
C=0.01UF
V=50V
2
1
C61
C=0.1UF
V=16V
1
GND
GND
34
39
41
RXRDYB
RXRDYA
6
TXRDYB
43
TXRDYA
36
RESET
INTB
29
UART_INTB 4/C2
30
05
UART_INTA 4/D2
XTAL1
OP2B
14
3.3V
2
21
33
31
13
3.3V
C58
1
C59
20
5
3.3V
XTAL2
OP2A
ST16C2550CQ48
3.3V;42
GND;17
1
C75
2
9
32
1 R91 2
R=10K 1 R90 2
R=10K
GND
C=0.1UF
V=16V
3.3V
F
3.3V
35
RTSA
INTA
8/A4
1/B7,4/C2,5/E2,6/D2 WE0_DQM0
A[25:0]
4/C2
1/B7,4/B2,5/C2,5/C5,6/D2
3
C=0.01UF
V=50V
1/A4,4/E6,4/A2,5/A2,6/A2
D7
2
D
1/B7,4/C2,5/C2,6/D2 WE1_DQM1
2
D[31:0]
C=0.1UF
V=16V
1/A2,4/A6,4/E5,5/A3,6/C2
GND
Title: MS7760CP01P/1 Circuit Diagram
Date: 7-29-2003_14:52
Sheet
5
of
12
1
2
3
4
5
6
7
8
PC CARD I/F CONTROLER
SA23
CCA23
47
P_A23
97
SA22
CCA22
45
P_A22
A21
98
SA21
CCA21
42
P_A21
A20
99
40
P_A20
A19
100
SA19
CCA19
38
P_A19
A18
101
SA18
CCA18
35
P_A18
A17
102
CCA17
33
P_A17
A16
103
SA16
CCA16
44
P_A16
A15
104
SA15
CCA15
46
P_A15
A14
105
SA14
CCA14
36
P_A14
A13
106
34
P_A13
A12
107
48
P_A12
A11
108
28
P_A11
A10
110
SA10
CCA10
24
P_A10
A9
111
SA9
CCA9
30
P_A9
A8
112
SA8
CCA8
32
P_A8
A7
113
SA7
CCA7
50
P_A7
A6
114
SA6
CCA6
52
P_A6
SA5
CCA5
54
P_A5
SA4
CCA4
58
P_A4
60
P_A3
62
P_A2
65
P_A1
67
P_A0
A5
115
A4
116
A3
117
A2
118
A1
119
A0
120
CCA20
SA20
SA17
SA13
CCA13
SA12
CCA12
SA11
CCA11
SA3
CCA3
SA2
CCA2
SA1
CCA1
SA0
CCA0
U20
4
P_D[15:0]
122
SD15
CD15
23
P_D15
123
CD14
20
P_D14
6/F4
VCC3
2
SD14
VCCD1
124
CD13
17
P_D13
6/F4
VCC5
1
SD13
VCCD0
14
VPPD1
CD12
P_D12
VPP1
SD12
15
6/F4
12
P_D11
6/F4
VPP0
75
P_D10
P_D8
SD7
CD7
19
P_D7
SD6
CD6
16
P_D6
P_D5
133
D5
134
SD5
CD5
13
D4
135
SD4
CD4
11
P_D4
D3
136
SD3
CD3
9
P_D3
D2
137
74
P_D2
D1
138
71
P_D1
D0
139
69
P_D0
SD2
CD2
SD1
CD1
SD0
CD0
3.3V
1/B7,4/B2
BS
XBS
XCCE2
P_CE2
7/A3
4/B2
PC_CS
7
XCS
XCCE1
21
P_CE1
7/A2
1/B7,4/B2,5/E2,5/C2,5/C5
RD
3
XSRD
XCIORD
29
P_IORD
7/B3
1/B7,4/C2,5/C2,5/C5 WE1_DQM1
5
XSWE1
XCIOWR
31
P_IOWR
7/B3
1/B7,4/C2,5/E2,5/C5 WE0_DQM0
4
XSWE0
XCOE
26
P_OE
7/B2
XSWAIT
XCWE_PGM
P_WE
7/B2
84
PC_RDY
CBVD2_SPKR
141
P_BVD2
7/C3
P_BVD1
7/C3
P_CD2
7/C3
PC_IRQ2
4/E2,4/B2
PC_IRQ1
143
SIRQ1
XCCD1
10
P_CD1
7/A3
4/E2,4/D2
PC_IRQ0
144
SIRQ0
CRDY_BSY_IREQ
41
P_RDY
7/B2
XCREG
64
P_REG
7/C3
XCCWAIT
59
P_WAIT
7/C3
CWP_XIOIS16
76
P_IOIS16
7/C2
P_RESET
7/C3
P_INPACK
7/C3
P_VS2
7/C3
P_VS1
7/B3
SLED_OUT
XVS2
RA23
XVS1
89
RA22
93
ENDIAN
85
TEST
CKIO
4/D2,6/D5
PCIC_RST
91
2
GND
27
XCVCC3
80
VCC3
6/C5
XCVCC5
81
VCC5
6/C5
CVPP1
78
VPP1
6/C5
CVPP0
79
VPP0
6/C5
CARD_PW_GOOD
CARD_VCC1
1/B7,4/B2,5/D5
53
CKIO
CARD_VCC2
XRESET
CARD_VCC3
GND
GND
CARD_VPP
7/B3,7/B2
CARD_PW
6/F2
GND
8
7
1
2
U19
4
HD74LV1G08ACM
3.3V;5
GND;3
5V
GND
06
3.3V
22
3.3V
CARD_VCC 6/B7,7/B3,7/B2
43
63
MR-SHPC-01V2T
3.3V;14,55,90,127
GND;1,18,37,56,73,92,109,121,131,140
1
8
CARD_PW
RA24
61
C95
MD5SW
XCINPACK
57
C=0.1UF
V=16V
88
RA25
77
2
1 R57 2
R=10K
87
GND
6/D7
SSPKR_OUT
CRESET
86
3/E6,3/B2
XCCD2
68
PC_IRQ3
83
CBVD1_STSCHG
SIRQ2
66
4/E2,4/B2
82
SIRQ3
39
4/E2,4/C2
142
SHDN
GND
PCIC_RST
2
D6
VPPD0
TPS2211IDB
4/D2,6/F2
1
P_D9
70
C88
72
CD8
GND
C=0.1UF
V=16V
CD9
SD8
2
SD9
1
132
10
OC
16
C89
130
D7
15
C=0.1UF
V=16V
129
D8
CD10
1
D9
SD10
C94
128
CD11
AVPP
CARD_VCC 6/F4,7/B3,7/B2
C=0.1UF
V=16V
D10
SD11
2
126
11
3.3V_2
D13
125
12
AVCC1
3.3V_1
D14
D11
13
AVCC2
5V_2
D15
D12
AVCC3
7/A2
25
E
5V_1
3
6
4/B2
12V
5
6
1
D
9
3.3V
D[31:0]
C
F
5V
1
96
A22
C93
A23
7/A2
C=1UF
V=10V
1608(0603)
P_A24
2
P_A25
49
1
51
CCA24
C92
CCA25
SA24
C=1UF
V=10V
1608(0603)
SA25
95
C28
1/A2,4/A6,4/E5,5/C2,5/A3
94
A24
C=0.1UF
V=16V
B
P_A[25:0]
U12
A25
2
A[25:0]
2
1/A4,4/E6,4/A2,5/D2,5/A2
A
Title: MS7760CP01P/1 Circuit Diagram
GND
GND
GND
Date: 7-29-2003_14:52
Sheet
6
of
12
1
2
3
4
5
6
7
8
PC CARD I/F,USB I/F&LCD I/F,SIM CARD I/F
6/C4
P_D[15:0]
6/A4
P_A[25:0]
A
6/D4
P_D3
2
P_D4
3
P_D5
4
P_D6
5
P_D7
6
P_CE1
P_A10
6/D4
6/E4
B
D5
D6
D7
CE1#
P_A11
10
P_A9
11
P_A8
12
P_A13
13
P_A14
14
P_RDY
6/F4,6/B7,7/B3 CARD_VCC
17
6/C7,7/B3
C
6/E4
P_A16
19
P_A15
20
P_A12
21
P_A7
22
P_A6
23
P_A5
24
P_A4
25
P_A3
26
P_A2
27
P_A1
28
P_A0
29
P_D0
30
P_D1
31
P_D2
32
38
P_D13
39
P_D14
40
P_D15
41
42
OE#
6/E4
P_VS1
43
A11
6/D4
P_IORD
44
A9
6/D4
P_IOWR
45
WE#
READY,IREQ#
P_A17
46
P_A18
47
P_A19
48
P_A20
49
P_A21
50
51
6/F4,6/B7,7/B2 CARD_VCC
Vcc
6/C7,7/B2
Vpp1
52
CARD_VPP
A16
A15
A12
A7
6/E4
P_VS2
A5
6/E4
P_RESET
A4
6/E4
P_WAIT
A6
P_A22
53
P_A23
54
P_A24
55
P_A25
56
57
58
59
A3
6/E4
P_INPACK
60
A2
6/E4
P_REG
61
A1
6/E4
P_BVD2
62
A0
6/E4
P_BVD1
63
P_D8
D0
D1
D2
6/E4
WP,IOIS16#
34
P_D12
P_CE2
A14
33
P_IOIS16
37
6/D4
A13
18
CARD_VPP
P_D11
A10
A8
15
16
6/E4
36
P_CD1
D4
9
P_WE
6/E4
D3
8
P_OE
35
GND
7
VBAT
CN3
CN3
1
64
P_D9
65
P_D10
66
67
P_CD2
68
GND
CD1#
D11
GND
1
1
VBAT
GND
2
2
VBAT
GND
3
3
D12
1/A6
VBAT
5
LCDD[15:0]
D14
LCDD0
D15
NC
6
LCDD1
8/F2,8/C5
VBAT
4
D13
LCD0
7
LCD1
CE2#
LCDD2
8
VS1#
LCDD3
9
LCD3
RFU,IORD#
KEY_IN0
8/F2,8/C5
KEY_IN1
8/F2,8/C5
KEY_IN2
8/F2,8/C5
KEY_IN3
4
5
6
8
KEY_OUT0
8/C5
KEY_OUT1
9
KEY_OUT1
KEY_OUT2
10
KEY_OUT2
11
GND
8/C5
LCD4
LCDD5
11
LCD5
A17
LCDD6
12
12
LCD6
LCDD7
13
13
14
A20
15
A21
LCDD8
Vcc
GND
16
LCDD9
Vpp2
GND
LCD8
17
LCD9
LCDD10
18
LCD10
LCDD11
19
LCD11
A23
LCDD12
20
LCD12
A24
LCDD13
21
A25
LCDD14
22
VS2#
LCDD15
23
A22
26
CL1
CL2
27
CL2
1/B5
LCD_DON
28
DON
1/B5
M_DISP
29
M_DISP
1/B5
FLM
30
FLM
1/C5
VEPWC
D10
1/C5
VCPWC
GND
9/F2
IR_IN
H8_RXD1
H8_SCK1
17
PAD_CLK
3/D3
RST1
18
RESET#
8/E2,8/D2
LCD_FLON
19
8/E2,8/D2
LCD_PWRDY
PAD_DOUT
LCD_FLON#
20 LCD_PWRDY#
21
GND
3.3V
22
GND
3.3VSB
3.3VSB
NC
34
3.3V
PAD_DIN
8/E7,8/C7,8/E4,8/A7
8/E7,8/B7,8/E4,8/A7,9/C2
VCPWC
33
GND
PAD_IRQ#
VEPWC
32
CD2#
PAD_CS#
GND
CL1
31
GND
FH12-24S-0.5SH
1/B5
D9
KEY_IN4
16
GND
1/B5
D8
15
24
GND
BVD1,STSCHG#
H8_TXD1
23
25
BVD2,SPKR#
8/E7,8/C7,8/E4,8/A7,9/C2
14
LCD15
24
REG#
PAD_CS
PAD_IRQ
LCD14
WAIT#
RFU,INPACK#
8/E7,8/A4
8/E2,8/C2
LCD13
RESET
KEY_IN3
KEY_IN4
KEY_OUT0
LCD2
LCD7
KEY_IN2
8/C5
10
A19
KEY_IN1
8/F2,8/C5
LCDD4
A18
KEY_IN0
7
RFU,IOWR#
31-5027-068-130-833
31-5027-068-130-833
CN6
CN5
GND
GND
35
GND
36
IR_IN
37
3.3V
38
3.3V
39
3.3V
40
3.3V
FH-12-40S-0.5SH
3.3V
D
GND
GND
R=2(F)
3
DD+
VBUS
GND
SHIELD
R=2(F)
1 R104 2
R=15K
1
C107
2
2
C114
C=47PF
V=50V
USB_DP
2
1 R113 2
R=15K
1 R106 2
1608(0603)
1
2/C4
USB_DM
C=47PF
V=50V
2/C4
GND
GND
DVCC
VIN
5
13
6
12
7
8
8/E4
SIM_M2
M2
C1+
11
8/E4
SIM_M1
7
M1
C1-
10
8/E4
SIM_M0
8
M0
GND
9
1
1 R56 2
1 R55 2 R=1K
1 R54 2 R=1K
4
R=1K
CN7
1 R105 2
1608(0603)
VCC
14
6
GND
USB_OVC
I/O
DDRV
4
LTC1555LEGN-1.8
GND
C3:CLK
C4
C5:GND
C6:Vpp
C7:I/O
C8
04-5036-008-110-862
GND
GND
CN13
1
2
GND
5
C23
+ 1
GND
DATA
C2:RST
15
C=2.2UF
V=10V
1
5
GND
RST
C1:Vcc
2
3
2
SIM_D
4
E
2/C4
3
RIN
1
16
1
1/C5
2
CLK
C22
SIM_RST
CIN
C=1UF
V=6.3V
1/C5
1
2
SIM_CLK
1
TPS2014D
1/C5
C24
5
C101
OC
3.3V
U13
C=0.1UF
V=16V
EN
6
2
OUT1
C=150UF
V=10V
OUT2
IN2
CN4
3.3V
C=0.1UF
V=16V
1
IN1
7
2
1
4
2
TR3
8
C=0.1UF
V=16V
USB_PENC
3
3
OUT3
GND
2
C100
2
+ 1
1 R114 2
R=10K
U23
1
C117
2/C4
DTC143ZE-TL
2
1 R98 2
R=10K
5V
GND
C4
07
C8
24-8005-002-100-867
Do not stuff
24-5041-0041-10-834S
GND
Do not stuff
GND
GND
F
Title: MS7760CP01P/1 Circuit Diagram
Date: 7-29-2003_14:52
Sheet
7
of
12
1
Vcc
3/C2,8/D7,8/A4,12/A7
H8_RES
2
~RES
8/E7,8/E3
H8_FWE
3
FWE
8/D7,8/A3
4
H8_MD0
8/D7,8/A3
H8_MD1
8/D7,8/A3
H8_MD2
7/B7,8/E7,8/C7,8/E4,9/C2
H8_TXD1
5
6
7
7/B7,8/E7,8/C7,8/E4
H8_RXD1
8
7/B7,8/E7,8/B7,8/E4,9/C2
H8_SCK1
9
10
3
3.3VSB
51
2
CS
DO
6
4
SK
DI
5
AVCC
A13/P25
50
H8_SW2
8/E7
VREF
A12/P24
49
H8_SW1
8/E7
KEY_OUT2
7/B7
7/B7,8/E7,8/E4,8/A7,9/C2
H8_TXD1
KEY_OUT1
7/B7
7/B7,8/E7,8/E4,8/A7
H8_RXD1
KEY_OUT0
7/A7
8/F2,8/A4
RTC_CE
GND
A7/P17
43
VOUT2
P76/AN6/DA0
A6/P16
42
VOUT1
H8/3048F-ONE
85
P77/AN7/DA1
A5/P15
41
86
AVSS
A4/P14
40
P80/RFSH/IRQ0
A3/P13
87
88
89
90
U8
P81/CS3/IRQ1
A2/P12
HD64F3048BVF25
P82/CS2/IRQ2
A1/P11
A0/P10
P83/CS1/IRQ3
P84/CS0
39
38
37
36
SCLK
4
SI
3
SO
6
INTR
KEY_IN4
7/A7,8/F2
KEY_IN3
7/A7,8/F2
KEY_IN2
7/A7,8/F2
KEY_IN1
7/A7,8/F2
KEY_IN0
7/A7,8/F2
VCC0
35
LED7
8/E2,8/C2
RTC_INTR
1
C64
2
C=10PF
V=50V
9
GND
8
OSCIN
OSCOUT
VSS5
D15/P37
93
PA0/TP0/TEND0/TCLKA
D14/P36
33
LED6
94
PA1/TP1/TEND1/TCLKB
D13/P35
32
LED5
8/A3,8/A7
H8_MD2
1 NR4
8/E2,12/D7
NMI_SW
95
PA2/TP2/TIOCA0/TCLKC
D12/P34
31
LED4
8/A3,8/A7
H8_MD1
2
7/B7,8/E2 LCD_PWRDY
96
PA3/TP3/TIOCB0/TCLKD
D11/P33
30
LED3
8/A3,8/A7
H8_MD0
3
PA4/TP4/TIOCA1/A23/CS6
D10/P32
LED2
3/E6,8/A3
H8_MD
LED1
8/A3
H8_NMI
LED0
3/C2,8/A4,8/A7,12/A7
H8_RES
8/A4
H8_STBY
D8/P30
28
27
26
3.3VSB
RTC_CE
8/B7,8/A4
SROM_CS
1
1
SIM_M2
SIM_M0
7/E5
SIM_M1
VCC5_ON
8/F2,12/E2
4
6
7
8
9
R=10K 1 NR5
8/A4,9/C2
VOL_CS
3/E2,8/E4
VCC_ON
8/E4,12/D2
VCC33A_ON
2
VCC33B_ON
3
10
5
GND
7/B7,8/B7,8/E4,8/A7,9/C2
H8_SCK1
7/B7,8/C7,8/E4,8/A7,9/C2
H8_TXD1
7/B7,8/C7,8/E4,8/A7
H8_RXD1
7/B7,8/A4
PAD_CS
8/C5
VOUT2
8/C5
VOUT1
8/B5
H8_SW2
8/B5
H8_SW1
8/E3,8/A7
H8_FWE
6
7
8
9
10
R=10K
1 R27 2
R=10K 1 R18 2
R=10K
1 R26 2
R=1K 1 R17 2
R=1K 1 R40 2
R=47K
08
7/E5
GND
7/E5
8/D7VCC33B_ON
VCC_ON
3/E2,8/D7
8/D7,12/D2VCC33A_ON
H8_SCK1
IR_IRQ
RXA
7/B7,8/E7,8/B7,8/A7,9/C2
SH_RST
8/C7,8/A4
H8_RXD1
KEY_IN0
3/C2,8/A4
9/F3
7/A7,8/C5
R=1K 1 R20 2
R=1K 1 R30 2
R=1K 1 R22 2
R=1K 1 R37 2
GND
7/B7,8/E7,8/C7,8/A7
KEY_IN1
TXA
KEY_IN2
7/A7,8/C5
5/D4
7/A7,8/C5
H8_TXD1
KEY_IN4
KEY_IN3
R=10K
1 R33 2
R=1K 1 R28 2
R=1K 1 R19 2
7/B7,8/E7,8/C7,8/A7,9/C2
7/A7,8/C5
7/A7,8/C5
10
5/D4
VCC5_ON
9
H8_FWE
8/E4,12/E2
8
8/E7,8/A7
PAD_IRQ
12/A5 SOFT_RES
RTC_INTR
7/B7,8/C2
IR_COUT
8/C7,8/C2
7
9/E2
8/C2,12/B7 POWER_SW
6
C14
4
RESET_SW
C=0.1UF
V=16V
NMI_SW
8/D2,12/C7
2
8/D2,12/D7
GND
C16
3
2
2
IR_DOUT
ADP_IN
LCD_FLON
LCD_PWRDY
7/B7,8/D2
9/E2
8/D2,12/B3
7/B7,8/D2
C=0.1UF
V=16V
3.3VSB
5
GND
5
4
3.3VSB
1 NR3
3.3VSB
8/E4
D6/P46
D5/P45
29
25
24
D4/P44
23
D3/P43
VSS1
22
21
D2/P42
20
D0/P40
D1/P41
19
18
IRQ5/SCK1/P95
17
RXD1/P93
IRQ4/SCK0/P94
16
15
TXD1/P91
RXD0/P92
14
13
VSS0
TXD0/P90
12
11
FWE
D7/P47
10
ADTRG/DREQ1/TP15/PB7
TIOCXB4/TP13/PB5
CS7/DREQ0/TP14/PB6
8
7
TIOCB4/TP11/PB3
TIOCXA4/TP12/PB4
6
5
1
TIOCA4/TP10/PB2
PA7/TP7/TIOCB2/A20
9
PA6/TP6/TIOCA2/A21/CS4
VCC/VCL
IR_DIN
99
100
4
ADP_IN
D9/P31
TIOCB3/TP9/PB1
8/E2,12/B3
PA5/TP5/TIOCB1/A22/CS5
3
SIGN
98
TIOCA3/TP8/PB0
12/E7
97
2
LCD_FLON
5
VSS
RV5C348B
RESET_SW
92
10
VDD
8/E2,12/C7
9/F3
F
2
8/E7
34
7/B7,8/E2
E
8/E7
1
32KOUT
2
P75/AN5
84
CE
SD4
83
3.3VSB
U17
7
1
44
RB521S-30_TE61
VSS2
C62
+ 1
A8/P20
P74/AN4
C=100UF
V=6.3V
45
P73/AN3
2
46
1
47
82
91
D
A9/P21
2
C63
RTSA
A10/P22
P72/AN2
48
C=0.1UF
V=16V
RTC_INTR
5/D4
A11/P23
P71/AN1
C80
C=0.1UF
V=16V
4
8/C7,8/E2
8/E2,12/B7 POWER_SW
81
P70/AN0
1
X1
PAD_IRQ
7
3
H8_SCK1
1
1
C21
C=0.1UF
V=16V
2
1
C82
C=0.1UF
V=16V
2
1
C81
C=0.1UF
V=16V
2
GND
7/B7,8/E2
GND
VCC
1 R84 2
R=0
8
SROM_CS
77
80
GND
PR
8/F2,8/A4
76
79
GND
NC
S-29391AFJA
78
C
Vss
7/B7,8/E7,8/E4,8/A7,9/C2
F=32.768KHZ
AMP
SCK1
3.3VSB
3.3VSB
VOLT
RxD1
M4
1
A14/P26
A15/P27
52
53
A16/P50
55
54
A17/P51
A18/P52
56
A19/P53
57
VSS3
P60/WAIT
58
59
P61/BREQ
60
61
CK
P62/BACK
63
64
65
66
67
68
69
62
STBY
RES
NMI
VSS4
EXTAL
XTAL
VCC1
P63/AS
70
P64/RD
P65/HWR
71
72
P66/LWR
74
73
MD0
75
MD2
GND
12/E7
TxD1
3.3VSB
B
12/D7
MD2
GND
2
C=0.1UF
V=16V
MD1
C74
MD1
FH12-10S-0.5SH
F=7.3728MHZ
1
MD0
2
GND OUT
8
CN15
3.3VSB
OSC3
SG-8002JF-7.372800M-PCCB
1 OE/ST VCC 4
2
7
3.3VSB
5/D4
8/F2,8/C7
7/B7,8/E7
8/D7,9/C2
6
CTSA
RTC_CE
PAD_CS
8/F2,8/B7
5
VOL_CS
3/C2,8/F2
SROM_CS
3/C2
4/C2
SH_RST
SH_NMI
H8_IRQ
H8_CK
H8_NMI
8/D7
H8_MD 3/E6,8/D7
H8_MD0 8/D7,8/A7
H8_MD1 8/D7,8/A7
H8_MD2 8/D7,8/A7
A
5/E2
4
8/D7
3
H8_STBY
2
H8_RES 3/C2,8/D7,8/A7,12/A7
1
H8/3048F-ONE
R=1K 1 R29 2
R=1K 1 R52 2
R=1K
GND
Title: MS7760CP01P/1 Circuit Diagram
Date: 7-29-2003_14:52
Sheet
8
of
12
1
2
3
4
5
6
7
8
CODEC
CN11
1
5V
AVCC5
2
FL6
LA
4
GND OUT
3
HD74LV07AT
3.3VSB;14
GND;7
R=470
R=470
HD74LV07AT
U25
1
AC97_BIT_CLK0 2/A5
1 R120 2
R=15K
1
C116
2
7
C=0.1UF
V=16V
STATUS0
LED1
5V
2
E
IR_COUT
TR1
U3
4
2
HD74LV1G08ACM
3.3VSB;5
GND;3
1 R32 2
R=1K
IR_DOUT
8/E3
1 R31 2
R=1K
8/E3
1
GND
GND
1 R21 2
R=1K
1
1
GL100MN0MP
2
R3
R=100
P=1/4W
3216(1206)
C108
1
AGND
FL5
1
2
BLM18PG300SN1-D
E
3
GND
CN10
1
1
C104
2
2
3
C=0.1UF
V=16V
AGND
4
5
VDDA
U24
1
+
NJM2100V
VDDA;8
AGND;4
AGND
R-IN
R-OUT
MIC_IN
HP-SENSE
CN8
1
VDDA
AGND
GND
HSJ1602-011010
MIC_IN
1 R117 2
R=470
C=47PF
V=50V
AGND
2
C
1 B
2SD2150_T100_S
LED3
1 R100 2
R=15K
C=0.1UF
V=16V
1 R78 2
R=1K
C30
+ 1
1 R77 2
R=1K
2
1 R107 2
R=100K
VDDA
C25
+ 1
2
- 6
NJM2100V
VDDA;8
AGND;4
1 R99 2
R=220K
C103
1
2
VDDA
FL3
1
2
BLM18PG300SN1-D
FL4
1
2
BLM18PG300SN1-D
+
5
2
MIC_IN
GND
24-8005-002-100-867
AGND Do not stuff
U24
VDDA
3
7
2
2
1
VDDD
2
1
STATUS1
C=1UF
V=10V
1608(0603)
C110
2
1
U25
2
3.3V
LED2
TR4
AGND
1 R118 2
R=100K
2
3.3V
DTC143ZE-TL
2
2SK2980
R=160K
GND
1/A7
+ 3
- 2
NJM2100V
VDDA;8
AGND;4
1 R119 2
C=0.1UF
V=16V
1/A7
3
AGND
C=47UF
V=10V
1 R61 2
R=47
Q1
1
1 R103 2
C=100UF
V=6.3V
C26
1
C44
1 +
2
1 R69 2
R=0
3.3V
F=22.579200MHZ
D
3.3VSB;14
GND;7
6
1
TR5
AGND
AGND
1
3
AVCC5
1
2
1 R101 2
C=100UF
V=6.3V
2
5
3
DTC143ZE-TL
2
AVCC5
C102
HD74LV07AT
3
AGND
R=470
U21
HP_OUT
AGND
C=0.1UF
V=16V
3.3VSB;14
GND;7
1 R124 2
R=100K
AVCC5
1 R102 2
2
U21
OSC4
SG-8002JF-22.579200M-PCCB
1 OE/ST VCC 4
AGND
2
HSJ1602-011010
AVCC5
AGND
2
VOL_CS
BYPASS
LM4865MM
AVCC5;1
AGND;6
L
5
1 R115 2
R=100K
AGND
U21
1
HP-SENSE
AVCC5
4
AGND
AGND
R
4
AVCC5
3
WB
AVCC5;11
AGND;1 LB
3
1 R116 2
R=100K
8/D7,8/A4
7
C=47UF
V=10V
C=0.1UF
V=16V
H8_SCK1
VOL
MAX5413ECD
H8_TXD1
7/B7,8/E7,8/B7,8/E4,8/A7
4
8
VO2
2
1 R127 2
R=100K
14
2
7/B7,8/E7,8/C7,8/E4,8/A7
HP
GND
C113
1 +
2
1 R108 2
R=2.2K
AGND
L-
1 R128 2
R=100K
12
HB
27
3
13
UDA1342TS
C
C=1UF
V=10V
1608(0603)
C105
2
1
CS
1
5
VO1
1
C40
+ 1
C=100UF
V=6.3V
WA
L+
CN9
AGND
VIN-
C115
VSSA_DAC
HA
SCLK
2
C109
+ 1
VSSD
2
1
C41
11
1 R68 2
R=1
1608(0603)
25
C=0.1UF
V=16V
VDDA_DAC
2
1
C33
VDDD
C=0.1UF
V=16V
2
2
C=100UF
V=6.3V
C35
+ 1
10
DIN
CN12
1
C=2.2UF
V=10V
7
1 R63 2
R=1
1608(0603)
1 R109 2
R=10K
C43
+ 1
9
Do not stuff
AGND
U28
2
U26
8
AVCC5
BYPASS
AGND
AVCC5
5
VOL
LM4865MM
AVCC5;1
AGND;6
2
VADCN
C=47UF
V=10V
8
1 R122 2
R=470
1
VINR2
1 R71 2
R=220
1608(0603)
VO2
24-8005-002-100-867
1 R121 2
R=100
C=47UF
V=10V
HP
C106
1 +
2
5
1 R126 2
R=100K
VDDD
C34
VINL2
2
VINR1
6
8
C31
1 +
2
7
VINL1
4
AGND
1
SYSCLK
VADCP
2
1 R70 2
R=1
1608(0603)
VO1
C=1UF
V=10V
12
7
VIN-
1608(0603)
C112
2
1
TEST1
4
C=1UF
V=10V
STATIC
VSSA_ADC
AGND
3
VDDA
3
QMUTE
2
1608(0603)
C111
2
1
23
VDDA_ADC
IPSEL
1 R110 2
R=100
1 R111 2
R=10K
9
C=100UF
V=6.3V
L3DATA
2
15
C45
+ 1
L3CLOCK
28
C=100UF
V=6.3V
L3MODE
14
22
1
13
1 R58 2 R=0
21
R=10K 20
B
STATUS
2
1 R60 2
1 R59 2 R=0
VDDD
DATAI
C46
+ 1
I2C0_SDA
C=47UF
V=10V
R24-8005-002-100-867
Do not stuff
U27
C29
1 +
2
24
C=100UF
V=6.3V
1/D5,1/D5
R=0
26
C42
I2C0_SCL
VOUTR
WS
VREF
1 R62 2
1/D5,1/D5
VOUTL
BCK
2
19
DATAO
C=0.1UF
V=16V
17
2
SSI1_SDATA
16
1
2/A5
18
C32
SSI_WS
C=0.1UF
V=16V
SSI_SCK
2/A5
2
SSI0_SDATA
2/A5
C=0.1UF
V=16V
2/A5
R+
1 R112 2
R=470
U14
1 R125 2
R=100K
A
1
2
BLM18PG300SN1-D
+
5
- 6
NJM2100V
VDDA;8
AGND;4
09
AGND
GND
U21
7/D5
IR_IN
9
1
4
2
F
IR_DIN
2
3.3VSB;14
GND;7
U21
8/D2
11
HD74LV1G08ACM
3.3VSB;5
GND;3
1
8
HD74LV07AT
U5
10
HD74LV07AT
U6
3.3VSB;14
GND;7
U21
4
HD74LV1G00ACM
3.3VSB;5
GND;3
IR_IRQ
13
8/E4
12
HD74LV07AT
GND
3.3VSB;14
GND;7
Title: MS7760CP01P/1 Circuit Diagram
Date: 7-29-2003_14:52
Sheet
9
of
12
1
2
3
4
5
6
7
8
BASE BOARD INTERFACE CONNECTOR
A
CN2
1
2
5V
3
4
36
A_D30
37
A_D31
38
39
5V
5
A_D1
6
D1
A_D2
7
A_D3
40
D0
D30
D31
4/C3 A_EPROMCE
GND
4/D3
A_A24
71
A_A25
72
73
74
A_CS2
75
A24
CN2
1/D2
106
SCIF2_CTS
107
A25
108
~EPROMCE
109
~CS2
110
~SCIF-CTS
N.C
ASEMD0
GND
GND
4/D3
A_CS4
CKIO
4/D3
A_CS5
76
~CS5
1/C7,10/E2
HDI_TCK
111
TCK
D2
42
GND
4/D3
A_RDWR
77
RDWR
1/C7,10/E2
HDI_TMS
112
TMS
8
D3
43
GND
A_BS
78
~BS
1/C7,10/E2
HDI_TRST
113
~TRST
A_D4
9
D4
44
GND
79
GND
1/C7,10/E2
HDI_TDI
114
TDI
A_D5
10
D5
A_A0
45
A0
80
GND
1/C7,10/E2
HDI_TDO
115
A_D6
11
A_A1
46
A_D7
12
A_A2
47
A_D8
13
A_A3
48
A_D9
14
A_A4
49
A_D10
15
D10
A_A5
50
A5
4/B3
A_D11
16
D11
A_A6
51
A6
4/B3
A_D12
17
D12
A_A7
52
A7
A_D13
18
D13
A_A8
53
A8
A_D14
19
D14
A_A9
54
A9
4/B3,10/D2
A_IRQ0
A_D15
20
A_A10
55
A10
4/B3,10/D2
A_IRQ1
A_A11
56
A_A12
57
A_A13
58
59
A14
3/D2,10/D2
60
A15
3/D3
GND
3/C3,10/E2
D7
D8
D9
D15
GND
GND
A_D16
23
A_D17
24
D17
A_A14
A_D18
25
D18
A_A15
A_D19
26
D19
61
A_D20
27
D20
62
A_D21
28
A_D22
29
A_D23
30
A_D24
31
A_D25
32
A_D26
33
A_D27
34
A_D28
35
D16
A1
4/C3
4/B3
A_RD
A2
4/B3,10/E2
A_WAIT
A3
4/B3
A_WE0
A4
4/B3
A_WE1
83
84
87
GND
88
89
4/B3,10/D2
A_IRQ2
4/B3,10/D2
A_IRQ3
A13
3/D2,10/D2
A_NMI_IN
92
93
A_RST_IN
94
RST2
95
A_DREQ0
96
A_DRAK0
97
D21
A16
3/C3
A_DACK0
D22
A_A17
64
A17
4/B3,10/E2
ROMSEL
99
A_A18
65
A18
4/B3,10/E2
BASE
A_A19
66
A_A20
67
A_A21
68
D27
A_A22
69
A22
1/D2
D28
A_A23
70
A23
1/D2
D26
24-5603-14-0101-861
GND
101
102
A20
1/D2
103
SCIF2_TXD
119
TDO
~ASEBRK
3.3VSB
3.3VSB
3.3VSB
3.3VSB
CAN0_TX
121
AUDATA0
2/B4,11/C2
CAN1_TX
122
AUDATA1
GND
2/B4,11/C4,11/C2
CAN0_RX
123
AUDATA2
~IRQ0
2/B4,11/C4,11/C2
CAN1_RX
124
AUDATA3
~IRQ1
~IRQ2
2/B4,11/C4,11/C2
2/C4,11/C4,11/C2
125
CAN1_NERR
126
CAN0_NERR
127
~IRQ3
128
NMI-in
~AUDSYNC
AUDCK
3.3V
3.3V
~RES-in
129
3.3V
~RES-out
130
3.3V
~DREQ0
131
3.3V
~DRAK0
132
3.3V
~DACK0
133
VBAT_IN
ROMSEL
134
VBAT_IN
3.3V
VBAT
135
~BASE
GND
GND
SCIF-TxD
SCIF2_RXD
SCIF-RxD
SCIF2_RTS
105
~SCIF-RTS
2
SD3
136
1
137
CMS03
24-5603-14-0101-861
GND
GND
120
104
24-5603-14-0101-861
GND
D
100
A19
A21
3.3VSB
~WE1
2/B4,11/C2
98
D25
118
~WE0
~WE2
91
ASEBRK
~WAIT
~WE3
90
116
117
86
63
D24
1/C7,10/E2
A_WE3
A_A16
D23
~RD
A_WE2
A12
3/C3
82
85
A11
GND
81
~CS4
1
D6
A_CKIO
C53
4/C3
C=0.1UF
V=16V
22
E
D29
41
21
C
5V
A_D29
2
B
5V
A_D0
CN2
CN2
5V
C39
+ 1
A_D[31:0]
C=10UF
V=10V
A_A[25:0]
4/A5
2
4/E3,4/A5
138
VBAT_IN
VBAT_IN
GND
GND
139
GND
140
GND
24-5603-14-0101-861
GND
GND
GND
3.3V
4/B3,10/B5
A_IRQ0
1 NR6
4/B3,10/B5
A_IRQ1
2
4/B3,10/C5
A_IRQ2
3
4/B3,10/C5
A_IRQ3
4
3/D2,10/C5
A_NMI_IN
6
3/D2,10/C5
A_RST_IN
3/C3,10/C5
A_DREQ0
4/B3,10/C5
ROMSEL
5
7
8
9
10
R=10K
1 NR7
4/B3,10/C5
BASE
1/C7,10/A7
HDI_TCK
2
1/C7,10/B7
HDI_TMS
3
1/C7,10/B7
HDI_TRST
4
1/C7,10/B7
HDI_TDI
6
1/C7,10/B7
HDI_TDO
7
1/C7,10/B7
ASEBRK
5
10
8
9
10
R=10K
4/B3,10/B5
A_WAIT
1 R123 2
R=680
F
Title: MS7760CP01P/1Circuit Diagram
Date: 7-29-2003_14:52
Sheet
10
of
12
1
2
3
4
5
6
7
8
I/O PORT INTERFACE
A
CN16
1
1/C5
FWE
1/C5
FCE
1/C5
FCDE
2
3
4
5
1/C5
FSC
1/C5
FOE
6
3/A2,11/B4
FRB
7
8
1/D5
I2C1_SDA
9
1/D5
I2C1_SCL
10
11
12
1/E2 SCIF0_TXD
B
1/E2,11/B4
SCIF0_RXD
1/E2,11/B4
SCIF0_CLK
13
14
1/D2
SCIF1_TXD
15
1/D2,11/B4
SCIF1_RXD
16
1/D2
SCIF1_RTS
17
1/D2,11/C4
SCIF1_CTS
18
1/D2,11/C4
SCIF1_CLK
19
20
1/C2,11/C4
CMT_CTR3
1/C2,11/C4
CMT_CTR2
1/C2,11/C4
CMT_CTR1
1/D2,11/C4
21
22
23
24
CMT_CTR0
25
2/B4,10/B7
C
CAN1_TX
26
2/B4,10/B7
CAN0_TX
27
2/B4,10/B7,11/C4
CAN1_RX
28
2/B4,10/B7,11/C4
CAN0_RX
29
2/B4,10/B7,11/C4
2/C4,10/C7,11/C4
30
CAN1_NERR
31
CAN0_NERR
32
33
34
35
36
37
38
39
40
CN17
1
GND
2
FWE
3
FCE
4
FCDE
3.3V
5
FSC
6
FOE
7
FRB
5V
8
GND
9
I2C1_SDA
10
I2C1_SCL
GND
GND
GND
GND
N.C
3.3V
3.3V
N.C
5V
5V
FH12-10S-0.5SH
GND
SCIF0_TXD
GND
SCIF0_RXD
SCIF0_CLK
3.3V
SCIF1_TXD
1 NR8
3/A2,11/B2
FRB
SCIF1_CTS
1/E2,11/B2
SCIF0_RXD
3
SCIF1_CLK
1/E2,11/B2
SCIF0_CLK
4
GND
1/D2,11/B2
SCIF1_RXD
SCIF1_RXD
5
2
SCIF1_RTS
6
7
CMT_CTR3
1/D2,11/B2
SCIF1_CTS
CMT_CTR2
1/D2,11/B2
SCIF1_CLK
GND
1/C2,11/C2
CMT_CTR3
1 NR9
CAN1_TX
1/C2,11/C2
CMT_CTR2
2
1/C2,11/C2
CMT_CTR1
3
1/D2,11/C2
8
9
CMT_CTR1
10
R=10K
CMT_CTR0
CAN0_TX
CMT_CTR0
4
CAN0_RX
2/B4,10/B7,11/C2
CAN1_RX
6
CAN1_NERR
2/B4,10/B7,11/C2
CAN0_RX
CAN0_NERR
2/B4,10/B7,11/C2
CAN1_NERR
GND
2/C4,10/C7,11/C2
CAN0_NERR
CAN1_RX
5
7
8
9
10
R=10K
Avss_ADC
Avss_ADC
AN0
AN1
AN2
AN3
Avcc_ADC
Avcc_ADC
FH-12-40S-0.5SH
D
GND
3.3V
FL2
1
2
BLM18PG300SN1-D
1 R44 2
1 R43 2 R=100
1 R42 2 R=100
2/C4
AN2
2/C4
AN1
2/C4
AN0
2/C4
SH_AVSS
2/D4
1
C=0.1UF
V=16V
1
C19
2
2/D4
AN3
C=0.1UF
V=16V
2
2
FL1
1
2
BLM18PG300SN1-D
C20
1
C18
E
C=0.1UF
V=16V
1
C17
2
C=0.1UF
V=16V
1 R41 2 R=100
R=100
SH_AVCC
11
GND
F
Title: MS7760CP01P/1 Circuit Diagram
Date: 7-29-2003_14:52
Sheet
11
of
12
1
2
3
4
5
6
POWER
7
8
3.3VSB
1 R95 2
R=10K
8/E3
A
1 R96 2
R=150
SOFT_RES
VBAT
3.3VSB
CN14
ADP_IN
U22
SW4
1
1
2
3
ZD1
DC-
2
1
HEC3600-010020
U1ZB6R8
DC+
2
3
1
GND
MR VCC
GND RES
4
2
MAX811REUS-T
VRES=2.63V
C99
1
2
GND
ADP_IN
1 R97 2
R=150
H8_RES
3/C2,8/D7,8/A4,8/A7
C=0.1UF
V=16V
8/E2,8/D2
GND
VBAT
FSEL
VIN2
VIN1
15
VIN0
SS/ENA
PH4
PH3
C=0.1UF
V=25V
GND
C
PWRGD
3
NC
2
PH1
7
PH0
6
BOOT
5
VSENSE PGND2
PGND1
1
AGND
PGND0
POWER_SW 8/E2,8/C2
3.3V
1 R86 2
R=10K
3.3VSB
1
1608(0603)
C37
1
2
2
SW2
L=10UH
C=47000PF
V=25V
13
L2
1
12
3
Q2 4
RESET_SW 8/E2,8/D2
3.3V
1 R94 2
R=10K
3.3V
SI3443DV 1 2 5 6
GND
SW3
3225(1210)
C27
2
1
GND
2
GND
11
TPS54316PWP
VOUT=3.3V
8/D7,8/E4
2
GND
GND
9
PH2
VBIAS
4
10
8
1
C=10UF
V=10V
VCC33A_ON
1
2
NMI_SW
8/E2,8/D2
VBAT
GND
1 R88 2
R=100K
17
SW1
3225(1210)
C50
1
2
14
C=10UF
V=10V
18
C=33000PF
V=25V
RT
C38
+ 1
19
1 R80 2
R=10K
16
C=470UF
V=6.3V
Do not stuff
1608(0603)
C52
1
2
1608(0603)
C51
1
2
U16
20
3.3V
1 R75 2
R=0
2
Do not stuff
1 R76 2
R=71.5K(FX)
1608(0603)
VBAT
1 R67 2
R=10K
B
GND
D
2
U15 L=10UH
8
R=1M(FX)
2
Do not stuff
1
VOUT
SD/SS
FB
MD/SYNC
VC
RT
LTC3440EMS
AMP
8/C1
SIGN
8/D2
4
5V
GND
6
(typ:5.002V)
9
10
1
1 R65 2
R=30K(FX)
1608(0603)
1
C47
C=0.1UF
V=25V
2
1608(0603)
C49
2
1
E
1 R74 2
R=10K
1 R66 2
R=10K
VCC5_ON
C=10UF
V=10V
3225(1210)
8/F2,8/E4
VIN
SW2
GND
5
C48
2
C=220PF
V=50V
R=10K
1608(0603)
1 R73 2
SW1
1
CMS03
7
C=22UF
V=16V
4532(1812)
2
2
SD2
C36
1
1 R72 2
R=620K(FX)
1608(0603)
VBAT
1 R64 2
R=200K(FX)
1608(0603)
3
1 R87 2
1 R53 2 R=10K
L1
8/B1
1 R89 2
R=100K
1
VOLT
12
GND
GND
F
Title: MS7760CP01P/1 Circuit Diagram
Date: 7-29-2003_14:52
Sheet
12
of
12
1
2
3
4
5
6
7
8
CPU BOARD I/F,PAD I/F & KEY I/F
3.3VSB
4/A7
+3.3V
3
GND
+3.3V
4
GND
RESET
7
~RESET
7
IN3
PENIRQ 11
VCC1 10
N.C
1/A8 PAD_DCLK
8
PAD_CLK
8
IN4
VREF 9
VCPWC
1/A8 PAD_DOUT
9
1/A8
PAD_CS
12
~PAD_CS
GND
3.3VSB
DON
DON
13
3/C5
CL2
14
CL2
14
GND
CL1
15
CL1
1/C5 KEY_OUT2
15
KEY_OUT2
16
GND
1/C5 KEY_OUT1
16
KEY_OUT1
17
GND
1/C5 KEY_OUT0
17
KEY_OUT0
LCD15
18
LCD15
1/D5
KEY_IN4
18
KEY_IN4
LCD14
19
LCD14
1/D5
KEY_IN3
19
KEY_IN3
LCD13
20
LCD13
1/D5
KEY_IN2
20
KEY_IN2
LCD12
21
LCD12
1/D5
KEY_IN1
21
KEY_IN1
1/B3 KEY_OUT2
LCD11
22
LCD11
1/D5
KEY_IN0
22
KEY_IN0
1/B3 KEY_OUT1
LCD10
23
LCD10
23
GND
1/B3 KEY_OUT0
LCD9
24
LCD9
24
GND
LCD8
25
LCD8
26
GND
GND
28
LCD7
LCD6
29
LCD6
LCD5
30
LCD5
LCD4
31
LCD4
LCD3
32
LCD3
LCD2
33
LCD2
LCD1
34
LCD1
LCD0
35
LCD0
36
N.C
37
VBAT
38
VBAT
39
VBAT
C=4.7UF
V=10V
1
2
C26
C23
2
2
GND
D1
FH12-24S-05SH
GND
1
27
LCD7
1
3/C5
13
3.3VSB
GND
GND
SW1
SW3
1
3
3.3VSB
2
1/A8
GND
~PAD_IRQ
D3
M_DISP
PAD_DIN
1
12
1/B3
2
4
1SS355_TE-17
11
2
PAD_IRQ
PAD_IRQ
D2
10
1/B8
PAD_DOUT 1/B3
1
PAD_DIN
FLM
1/B3
1/B3
ADS7843E
PAD_DOUT
VEPWC
D
YGND
11
40
YD
4/A7
PAD_DIN
BUSY 13
DOUT 12
6
10
VBAT
X-
5
F-LED ON
FLM
C
4
PWR RDY
VEPWC
LCD[15:0]
XR
PAD_DCLK 1/B3
PAD_CS
14
6
LCD_PWRDY
4/B4 LCD_FLON
2/B2
3/D2
4/A7
DIN
5
VCPWC
M_DISP
Y+
1
9
3
C19
8
YU
2
GND
4/A7
1
7
X+
C21
GND
2
C=0.1UF
V=25V
IR_IN
6
VCC0
XL
DCLK 16
CS 15
2
5
1
4
TP9
+3.3VSB
TP4
+3.3VSB
2
1
3
3.3VSB
U6
1
C=4.7UF
V=10V
TP5
TP6
TP1
1
1
TP7
TP2
1
1
TP3
+3.3V
2/A2
3/C5
B
1
1
TP8
IR_IN
1
1/E6
+3.3V
2
3.3VSB
CN2
1
1SS355_TE-17
CN1
1
C=0.1UF
V=25V
3.3V
1SS355_TE-17
A
SW2
1
4
2
5
3
6
1
2
3
4
SKRHABE010
1/C3
1/C3
1/C3
1/B3
1/B3
KEY_IN0
KEY_IN1
KEY_IN2
KEY_IN3
KEY_IN4
VBAT
FH12-40S-05SH
GND
3.3VSB
GND
U1
1
GP1UC101
BPF=38KHZ
2
IR_IN
1/A2
3
4
E
GND
01
F
MS7727LCD01/4
PAGE=1
Last Update:
7-10-2002_19:56
1
2
3
4
5
6
7
8
LCD PANEL POWER
3.3V
1 R16 2
R=10K
A
VCC
1
DTC143ZE-TL
2
SI3443DV 1 2 5 6
3
1
2
TR3
C=4.7UF
V=10V
VCPWC
Q3 4
C25
1/B2
3
GND
GND
VBAT
5
VIN
4
SHDN
2
GND
SW 1
FB
5.25V 5.4mA
1
CRS03
3
C8
+ 1
2
C=22UF
V=16V
2
U3 L=10UH
SD1
2
L1
C=5PF
V=50V
1
1
1
C=4.7UF
V=10V
TR1
VDD
SI3443DV 1 2 5 6
C5
VEPWC
3
Q1 4
2
1/B2
DTC143ZE-TL
2
3
1 R11 2
R=1M(FX)
C7
2
1
1 R14 2
R=10K
B
LT1615ES5
GND
GND
GND
1 R10 2
1 R9 2
R=137K(FX) R=169K(FX)
GND
C
GND
2
1
2
(g4)
2
GND
FB
3
1
C14
GND VGON
15V 0.1mA
1
C12
1
(g4)
C=1UF
V=25V
CRS03
C=5PF
V=50V
SW 1
SD3
1 R13 2
R=1M(FX)
C10
2
1
SHDN
C=1UF
V=25V
2
CRS03
VIN
4
2
1
5
C16
SD2
1
2
2
U4 L=10UH
C=4.7UF
V=10V
1
C11
2
L2
C=1UF
V=25V
2
GND
1
2
2
1
D
VGOFF
-15V 0.2mA
CRS03
SD5
C=1UF
V=25V
SD4
CRS03
1
C17
GND
E
GND
GND
1 R12 2
R=88.7K(FX)
LT1615ES5
GND
02
GND
F
MS7727LCD01/4
PAGE=2
1
2
3
4
5
6
7
8
LCD CONTROLLER
DB0
41
VDD4
DB1
42
BO0
DB2
43
BO1
DB3
44
BO2
45
BO3
DB4
46
BO4
DB5
47
GND6
DG0
49
48
BO5
DG1
50
GO0
DG2
51
GO1
DG3
52
GO2
DG4
53
GO3
VDD5
GO4
DG5
DR0
54
DR1
56
55
GO5
DR2
57
RO0
DR3
61
VDD6
GND5
DR4
62
RO4
DR5
63
RO5
HCK 39
GND4 38
HSP 37
64
GND8
4/B2
VCK
65
VCK
INH
4/A2
VOE
66
VOE
4/A2
VSP
67
VSP
68
GND9
69
HOEPW
70
DSE
71
PCI
72
PANS1
73
PANS0
74
VDD7
75
INVSE
76
HDRES
77
PCSE
78
TESTEN
79
CKS
80
GND10
4/C2
4/C2
STB
4/C2
INV
4/D2
HOE 33
PC 32
HOE
3/E2
POL
4/C2
DON
1/B2
OEN
3/E2
M_DISP
CL2
1/B2
1/B2
GND1
LCD11
20
1
C2
C=0.1UF
V=25V
2
1
C=0.1UF
V=25V
C1
2
1
C=0.1UF
V=25V
C4
2
1
C3
C=0.1UF
V=25V
VCC
2
RI2
19
LCD12
RI3
18
LCD13
RI4
17
LCD14
RI5
16
LCD15
GI0
15
LCD5
VDD1
14
GI1
13
LCD6
GI2
12
LCD7
GI3
11
LCD8
GI5
GI4
10
LCD9
9
LCD10
GND0
BI0
8
7
BI1
6
LCD0
BI2
5
LCD1
BI3
4
VDD0
HSP
DLP 35
INV 34
RI1 22
VDD2 21
1
LCD[15:0]
4/C2
GND2 24
RI0 23
LCD4
1/B2
HCK
AP
DE 27
GND3 26
DCK 25
LCD2
INVSE
BI4
3/E2
BI5
PANS0
3
3/E2
36
OEN 29
TESTEN2 28
LCD3
PANS1
40
VDD3 31
POC 30
U2
S1L50282F23K100
2
3/E2
C
D
RO1
GND7
B
58
DR[5:0]
RO2
DG[5:0]
4/B2
RO3
DB[5:0]
4/B2
60
4/C2
59
A
VCC
E
3/B5
HOE
3/C2
PANS1
3/C5
OEN
3/C2
PANS0
3/C2
INVSE
R=10K 1 R4 2
R=10K 1 R5 2
R=10K
1 R1 2
R=10K 1 R3 2
R=10K 1 R2 2
GND
03
F
MS7727LCD01/4
PAGE=3
1
2
3
4
5
6
7
8
LCD PANEL I/F & FRONT LIGHT POWER
A
XR
1
XR
2
VSP
1/A6
YD
2
YD
3
VGON
1/A6
XL
3
XL
4
VOE
1/A6
YU
4
5
VGOFF
6
VCK
7
VDD
8
GND
DR5
9
D05
DR4
10
D04
DR3
11
D03
DR2
12
D02
DR1
13
D01
DR0
14
D00
DG5
15
D15
DG4
16
D14
DG3
17
D13
DG2
18
D12
DG1
19
D11
DG0
20
D10
DB5
21
D25
DB4
22
D24
DB3
23
D23
DB2
24
D22
DB1
25
D21
DB0
26
D20
27
GND
DB[5:0]
VCC
C
3/B5
HSP
28
HSP
3/B5
HCK
29
HCK
30
VCC
3/B5
AP
31
AP
3/B5
STB
32
STB
3/B5
POL
33
POL
3/B5
INV
34
INV
35
N.C
2
36
VCOM
C=4.7UF
V=10V
37
GAM
38
V4
39
V3
40
V2
41
V1
42
V0
43
N.C
44
COM
VDD
D
1
1 R7 2
R=120K
1 R8 2
R=0
1 VR1 3
G4BT104
R=100K
2
1 R6 2
R=0
C6
GND
45
TR4
1
U5 L=10UH
5
VIN
4
SHDN
2
GND
GND GND
V1
3
GND
4
1
CRS03
SW 1
FB 3
LT1615ES5
GND
GND
2
1
1
2
2
SD6
GND
2
C=1UF
V=35V
TR2
1
L3
C24
1/B3 LCD_FLON
3
3
SI3443DV 1 2 5 6
1
V2
04FLH-SM1-TB
2
DTC143ZE-TL
DTC143ZE-TL
2
CN4
GND
1 R15 2
R=80.6(FX)
3/A3
DG[5:0]
Q2 4
1
3/A2
3
C22
B
VBAT
2
DR[5:0]
C=1000PF
V=50V
VCK
YU
SFW4R-1STE1
1
VOE
C=4.7UF
V=10V
VSP
C20
3/A2
1/A6
2
3/B2
GND
1 R18 2
R=10K
3/B2
1
1 R17 2
R=10K
3/B2
CN5
CN3
VDD VGOFF VGON
GND
GND
GND
FH12-45S-05SH
GND
GND
GND
GND
1
C13
C=0.1UF
V=25V
VDD
2
1
C15
C=0.1UF
V=25V
VGOFF
2
1
C18
C=0.1UF
V=25V
VGON
2
1
C9
2
E
C=0.1UF
V=25V
VCC
GND
04
F
MS7727LCD01/4
PAGE=4
1
2
3
4
5
6
7
8
CPU BOARD INTERFACE CONNECTOR
A
2/A2
A_A[25:0]
2/D2
A_D[31:0]
CN1
CN1
1
5V
2
5V
5V
3
5V
4
B
5
D0
A_D1
6
D1
A_D2
7
A_D3
8
A_D4
9
A_D5
10
A_D6
11
A_D7
12
A_D8
13
14
A_D10
15
A_D11
A_D12
A_D13
A_D14
19
A_D15
20
37
A_D31
38
39
A_CKIO
D30
D31
2/D2
A_A24
71
A_A25
72
73
A_EPROMCE
74
GND
A_CS2
GND
A_CS4
75
~CS4
CKIO
A_CS5
76
~CS5
TMS
~BS
2/C7
TRST
113
~TRST
D4
44
GND
79
GND
2/C7
TDI
114
TDI
D7
D8
A_A0
45
A_A1
46
A_A2
47
A_A3
48
A1
A3
A_A6
51
A6
A_A7
52
A7
D13
A_A8
53
A8
A_A9
54
A_A10
55
A_A11
56
A_A12
57
58
A13
D15
GND
GND
2/C3,2/C4
A2
D12
D14
80
A0
D11
81
A_RD
82
A_WAIT
2/E4
83
A_WE0
D16
1/E2
24
D17
A_A14
59
A14
1/E2
25
D18
A_A15
60
A15
A_D19
26
D19
61
A_DREQ0
96
A_D20
27
D20
62
GND
A_DRAK0
97
A_D21
28
D21
A_A16
63
A16
A_DACK0
98
A_D22
29
A_A17
64
A_NMI_IN
A_RST_IN
94
2/C7 A_RST_OUT
95
A_A20
67
D26
A_A21
68
A21
1/E3
D27
A_A22
69
A22
1/E3
D28
A_A23
70
A23
1/E3
D25
99
ROMSEL
100
A18
101
A19
102
A20
TXD
103
RXD
104
RTS
105
10-5603-14-0101-861
10-5603-14-0101-861
GND
GND
AUDATA1
123
AUDATA2
AUDATA3
A_D18
66
AUDATA0
122
AUDATA2
2/B7
93
A_A19
121
AUDATA1
~IRQ0
A_D17
D24
AUDATA0
2/A7
A_A13
D23
3.3VSB
2/B7
92
~IRQ1
2/B7
AUDSYNC
~IRQ2
2/A7
AUDCK
124
125
126
127
~IRQ3
AUDATA3
~AUDSYNC
AUDCK
3.3V
NMI-in
128
3.3V
~RES-in
129
3.3V
~RES-out
130
3.3V
~DREQ0
131
3.3V
~DRAK0
132
3.3V
~DACK0
133
VBAT
ROMSEL
3.3V
134
VBAT
135
~BASE
136
GND
137
GND
VBAT
VBAT
VBAT
GND
TxD
138
GND
RxD
139
GND
~RTS
140
GND
10-5603-14-0101-861
10-5603-14-0101-861
GND
3.3VSB
3.3VSB
120
2/B7
A_IRQ3
3.3VSB
~WE2
GND
91
~ASEBRKAK
~WE1
GND
90
TDO
119
~WE3
A12
65
3.3VSB
88
A_IRQ2
A_A18
118
~WE0
87
A_IRQ1
1/D2
117
86
A11
A17
ASEBRKAK
A_WE3
89
116
~WAIT
85
23
D22
2/C7
115
TDO
A_WE2
A10
GND
~RD
2/C7
A_WE1
A_IRQ0
A9
GND
84
A_D16
35
TMS
2/C7
78
18
A_D28
TCK
R/W
A_BS
17
34
GND
111
A_RDWR
16
A_D27
GND
110
TCK
GND
A5
33
2/B7
GND
A4
A_D26
~CS2
N.C
43
50
32
109
~CTS
ASEMD0
D3
A_A5
A_D25
108
D2
D10
31
107
112
D9
A_D24
106
CTS
~EPROMCE
41
49
30
1/E3
A25
40
A_A4
A_D23
A24
77
D6
22
CN1
CN1
D29
42
D5
21
C
36
A_D30
5V
A_D0
A_D9
A_D29
GND
D
1/C5
J1
1
ROMSEL
2
GND
1/C5
E
1/C5
TP1
1
NMI
A_NMI_IN
TP2
1
RESET
A_RST_IN
1/C5
TXD
1
1/D5
RXD
1
1/D5
RTS
1/A7
CTS
TP3
1
GND
GND
1
1
TH1
TH2
TH3
01
TH4
F
Title: MS7760DBG01-1/1 Circuit Diagram
Date: 7-29-2003_14:55
$1I260
Sheet
1
of
2
1
2
3
4
5
6
7
8
EPROM & E10A INTERFACE
Q11
E_D11
A14
Q10
19
E_D10
A13
Q9
17
E_D9
15
E_D8
29
E_D7
27
E_D6
25
E_D5
A_A15
35
A_A14
36
A_A13
37
A_A12
38
A_A11
39
A_A10
40
A12
Q8
A11
Q7
A10
Q6
A9
Q5
E_D4
Q3
20
E_D3
Q2
18
E_D2
A5
Q1
16
E_D1
A4
Q0
14
E_D0
41
A8
A_A8
3
A7
A_A7
4
A6
A_A6
5
A_A5
6
A_A4
7
A_A3
8
A_A2
9
A_A1
10
3.3V
GND
C
1/B5,2/C4
1/A5
3
1
A_RD
2
1
A_EPROMCE
B
Y1
G
4
B5
14
5
12
E_D10
7
A6
B6
13
6
11
A7
B7
A8
B8
E_D9
8
E_D8
9
2
Y2
Y3
7
12
7
10
11
8
9
1
AUDCK
2
1/B7
1/B7
1/B7
AUDATA0
AUDATA1
AUDATA2
3.3V;20
DIR GND;10
1/C7
3.3V
A1
B1
A2
B2
A3
B3
18
SW2
1
1/B7
17
2
15
16
3
14
A4
B4
15
4
13
E_D3
6
A5
B5
14
5
12
E_D2
7
A6
B6
13
6
11
E_D1
8
A7
B7
12
7
10
E_D0
9
A8
B8
11
8
9
1
1/B7
1/B7
1/B7
1/B7
TRST
TDI
TDO
1/B7
G
A_D13
4
A_D12
5
E_D15
17
E_D14
A1
B1
A2
B2
A3
B3
16
E_D13
A4
B4
15
E_D12
GND
1/C5 A_RST_OUT
6
A5
B5
14
E_D11
A_D10
7
A6
B6
13
E_D10
A_D9
8
A7
B7
12
E_D9
A_D8
9
A8
B8
11
E_D8
1
GND
3.3V
C2
A_D11
19
G
3.3V;20
DIR GND;10
HD74LVC245AT
GND
18
3
A2
B2
17
E_D6
A_D5
4
A3
B3
16
E_D5
A_D4
5
A4
B4
15
E_D4
A_D3
6
A5
B5
14
E_D3
8
A_D0
9
19
1
A6
B6
A7
B7
A8
B8
13
E_D2
12
E_D1
11
E_D0
1/B5
G
1D
1Q
2
4
2D
2Q
5
E_D5
7
3D
3Q
6
E_D4
8
4D
4Q
9
R=1K
5D
5Q
12
R3
6D
6Q
13
E_D2
14
E_D1
17
E_D0
18
TCK
GND
TMS
GND
21
~TRST
22
GND
23
TDI
24
GND
25
TDO
26
GND
~ASEBRK
GND
Vcc
GND
31
nRESET
32
GND
33
GND
34
GND
35
N.C
GND
DX10M-36SE
Hitachi UDI port
A_WE0
2
11
4
1
7Q
8D
8Q
R2
1
2
1
2
1
2
1
2
1
LED2
2
LED3
2
2
R=1K
1
R4
LED4
2
R=1K
19
R5
LED5
2
R=1K
CLK
1
OC
R6
2
1
2
1
LED6
2
R=1K
HD74LVC374AT
GND
3.3V
7D
1
15
16
2
LED1
R=1K
1
1
HD74LV1G32ACM
3.3V;5
GND;3
3.3V;20
GND;10
1
R7
LED7
2
R=1K
1
R8
2
1
LED8
02
2
R=1K
C3
7
A_D1
1
E_D7
1
B1
A_D6
A_D2
GND
C=0.1UF
V=25V
A1
2
E
2
3
E_D6
E_D3
1
R1
E_D7
U4
U2
A_D7
N.C
3.3V
U5
1
3
18
C=0.1UF
V=25V
A_D14
GND
16
36
2
D
2
N.C
15
30
GND
AUDSYNC
GND
29
HD74LVC245AT
GND
14
28
3.3V;20
DIR GND;10
AUDATA3
13
27
ASEBRKAK
GND
12
20
U1
A_D15
AUDATA2
19
TMS
3.3V;16
GND;8
A_D[31:0]
GND
18
HD74LVC139T
1/A2
AUDATA1
7
17
TCK
U6
19
GND
6
11
AUDSYNC
16
5
4
AUDATA0
5
10
G
GND
4
9
AUDATA3
AUDCK
3
8
1/B7
E_D4
HD74LV1G32ACM
3.3V;5
GND;3
5
6
13
A5
E_D7
5V;22
GND;12,31
U3
A_A22
14
4
6
4
Y0
3
E_D11
3
A
16
B4
E_D5
1/B5,2/C3
2
B3
U8
M27C160F1
A_A23
A3
A4
E_D6
OE
17
15
1
GND
A_RD
B2
3.3V
5V
13
A2
5
A0
CE
15
B1
4
A1
11
2
A1
1/C7
HD74LVC245AT
A2
BYTE/VPP
CN2
16
E_D12
GND
A3
32
3.3V
SW1
1
E_D13
19
C5
Q4
23
A_A9
5V
1
34
3
R=1K 2 R16 1
R=1K
A15
21
A_A16
E_D14
18
R=1K 2 R24 1
R=1K
E_D12
A16
2
R=1K 2 R21 1
R=1K 2 R22 1
R=1K 2 R23 1
24
33
E_D15
2 R17 1
R=1K 2 R18 1
R=1K 2 R19 1
R=1K 2 R20 1
Q12
A_A17
1
E_D13
A17
C4
26
Q14
2
C=0.1UF
V=25V
Q13
A18
A_A18
2
E_D14
1
U7
C=0.1UF
V=25V
28
A_A19
Q15/A-1
1
E_D15
A19
C1
30
42
2
B
E_D[15:0]
M1
A_A20
C=0.1UF
V=25V
A_A[25:0]
2
1/A3
R=1K 2 R13 1
R=1K 2 R14 1
R=1K 2 R15 1
A
2 R9 1
R=1K 2 R10 1
R=1K 2 R11 1
R=1K 2 R12 1
3.3V
3.3V;20
DIR GND;10
HD74LVC245AT
GND
U3
14
13
A
Y0
B
Y1
Y2
F
15
G
Y3
12
11
10
9
HD74LVC139T
GND
3.3V;16
GND;8
Title: MS7760DBG01-1/1 Circuit Diagram
Date: 7-29-2003_14:55
Sheet
2
of
2
1
2
3
4
5
6
7
8
CPU BOARD INTERFACE
5V
CAN1_NERR
2/B5
CAN0_RX
2/B5
CAN1_RX
2/B5
CAN0_TX
2/B5
11
12
13
14
15
CAN1_TX
16
CMT_CTR0
17
2/C5
CMT_CTR1
18
2/C5
CMT_CTR2
19
2/C5
CMT_CTR3
2/C5
20
21
C
2/C5
SCIF1_CLK
2/C5
SCIF1_CTS
22
23
2/C5
SCIF1_RTS
24
2/C5
SCIF1_RXD
25
2/C5
SCIF1_TXD
26
2/D5
SCIF0_TXD
27
2/D5
SCIF0_RXD
28
2/D5
SCIF0_CLK
29
30
2/D5
I2C1_SCL
2/D5
I2C1_SDA
31
32
33
2/A3
FRB
34
2/B3
FOE
35
2/B3
FSC
36
2/B3
FCDE
37
2/B3
FCE
38
2/B3
FWE
39
40
Avss_ADC
1
C1
C=0.1UF
V=16V
7
3.3V
Avss_ADC
8
GND
9
GND
CAN0_NERR
CAN1_NERR
CAN0_RX
CAN1_RX
10
CAN0_TX
GND
CMT_CTR0
N.C
GND
4
3.3V
5
6
LCD_FLON#
7
GND
RESET
7
RESET#
PAD_CLK
PAD_DOUT
2/A3,2/C2
GND
VEPWC
10
VEPWC
H8_TXD1
10
M_DISP
LCD_DON
2/C2
CL2
8
11
12
13
14
CL1
GND
2/A3,2/A2 LCDD[15:0]
SCIF1_CLK
SCIF1_CTS
SCIF1_RTS
SCIF1_RXD
SCIF0_TXD
GND
I2C1_SCL
I2C1_SDA
GND
FRB
M_DISP
PAD_IRQ
12
PAD_CS
13
DON
14
CL2
15
CL1
16
GND
17
GND
KEY_OUT2
KEY_OUT1
17
KEY_OUT0
KEY_IN4
KEY_IN3
KEY_IN4
LCD14
KEY_IN3
19
LCDD13
20
LCD13
KEY_IN2
LCDD12
21
LCDD11
22
LCDD10
23
LCDD9
24
LCD9
LCDD8
25
LCD8
26
GND
LCD12
KEY_IN1
LCD11
KEY_IN0
LCDD6
29
LCD6
LCDD5
30
LCDD4
31
LCDD3
32
LCDD2
33
LCDD1
34
LCD1
LCDD0
35
LCD0
36
NC
37
VBAT
38
VBAT
VBAT
FSC
FCDE
GND
39
40
20
21
22
23
LCD10
LCD7
GND
KEY_OUT0
LCD15
GND
GND
16
19
28
PAD_CS#
KEY_OUT1
LCDD14
27
PAD_IRQ#
KEY_OUT2
18
LCDD7
PAD_DIN
15
18
SCIF0_CLK
SCIF0_RXD
FLM
11
LCDD15
SCIF1_TXD
LCD_PWRDY#
LCD_FLON
9
2/C2
GND
LCD_PWRDY
H8_RXD1
2/C2
GND
GND
H8_SCK1
FLM
3.3VSB
IR_IN
VCPWC
2/C2
3.3VSB
6
NC
GND
GND
3
3.3V
9
CMT_CTR3
FWE
3.3V
VCPWC
CMT_CTR2
FCE
2
GND
GND
CMT_CTR1
FOE
CN4
1
3.3V
8
FH12-10S-0.5SH
GND
IR_IN
3.3V
2/C2
CAN1_TX
FH12-40S-0.5SH
D
6
AN0
5
1
2/B5
10
CAN0_NERR
AN1
4
3.3V
C3
2/B5
5
3
N.C
C=0.1UF
V=16V
9
4
5V
2
7
3
2
C8
+ 1
AVSS_ADC
3.3V
CN3
1
5V
C=10UF
V=10V
2/B5
2
6
1
AN0
C2
AN1
2/A5
C=0.1UF
V=16V
2/A5
2
5
AN2
C6
+ 1
4
AN3
C=10UF
V=10V
AN2
Avcc_ADC
2
2/A5
3
C7
+ 1
AN3
2
C=10UF
V=10V
AVCC_ADC
2/A5
1
Avcc_ADC
2
2/A5
2
8
B
3.3V
CN2
CN1
1
2
A
24
KEY_IN2
KEY_IN1
KEY_IN0
GND
GND
FH12-24S-0.5SH
GND
LCD5
LCD4
LCD3
LCD2
VBAT
VBAT
FH12-40S-0.5SH
GND
GND
E
01
F
Title: MS7760DBG01-2/1 Circuit Diagram
Date: 7-29-2003_14:58
Sheet
1
of
2
1
2
3
4
5
6
7
8
I/O PORT INTERFACE
A
5V
CN15
5
LCDD3
6
LCDD4
7
LCDD5
8
LCDD6
9
LCDD7
10
11
12
B
LCDD8
13
LCDD9
14
LCDD10
15
LCDD11
16
LCDD12
17
LCDD13
18
LCDD14
19
LCDD15
20
21
22
C
1/B5
CL2
23
1/B5
FLM
24
1/B5
CL1
25
M_DISP
26
1/B5
LCD_DON
27
1/B7,2/A3
RESET
1/B5
28
29
30
31
32
33
34
35
3.3V
36
37
1
C4
C=0.1UF
V=16V
2
C9
+ 1
2
D
C=10UF
V=10V
38
39
40
3
RESET
4
MFI_D1
MFI_D2
1/C2
FRB
5
MFI_D3
1/D2
FSC
6
MFI_D4
1/D2
FOE
7
MFI_D5
MFI_D6
MFI_D7
GND
GND
MFI_D8
MFI_D9
MFI_D10
MFI_D11
1/D2
LCDD8
8
LCDD9
9
LCDD10
10
LCDD11
11
LCDD12
12
LCDD13
13
LCDD14
14
LCDD15
15
FCDE
16
MFI_D12
1/D2
FWE
17
MFI_D13
1/D2
FCE
18
19
MFI_D14
20
MFI_D15
21
GND
22
GND
MFI_MD
23
3.3V
24
MFI_RW/RD
25
MFI_E/WR
MFI_RS
MFI_CS
MFI_INT
MFI_RSTOUT
26
1
LCDD2
1/B7,2/C2
C5
4
MFI_D0
2
C=0.1UF
V=16V
LCDD1
1/B5,2/A2 LCDD[15:0]
2
3
GND
C10
+ 1
LCDD0
1
C=10UF
V=10V
2
1/B5,2/A3 LCDD[15:0]
CN16
MFI
GND
2
1
N.C
GND
GND
GND
GND
CN5
OPT
GND
1/A2
AVCC_ADC
GND
1/A2
AN3
RESET#
1/A2
AN2
1
2
3
4
SE
1/A2
AN1
RDY/BUSY#
1/A2
AN0
5
SC
1/B2
AVSS_ADC
6
1
2
AN3
3
AN2
4
AN1
IO2
CN6
1/B2
CAN0_TX
IO3
1/B2
CAN0_RX
IO4
1/B2
CAN0_NERR
2
3
5V
5V
3.3V
CN13
Do not stuff
1
5V
Do not stuff
Avss_ADC
1
IO0
IO1
5V
FFC-4BMEP1B
AN0
FFC-6AMEP1B
OE#
2
HCAN0
3
CAN0_TX
4
CAN0_RX
3.3V
3.3V
3.3V
3.3V
FFC-4BMEP1B
CAN0_NERR
Do not stuff
FFC-3AMEP1B
IO5
Do not stuff
CN14
IO6
CN7
IO7
CDE#
1/B2
CAN1_TX
1
WE#
1/B2
CAN1_RX
2
CE#
1/B2
CAN1_NERR
3
N.C
1
HCAN1
2
CAN1_TX
3
CAN1_RX
4
CAN1_NERR
GND
GND
GND
GND
FFC-3AMEP1B
FFC-4BMEP1B
Do not stuff
Do not stuff
N.C
GND
CN8
N.C
1
N.C
1/B2
CMT_CTR0
Reserved
1/B2
CMT_CTR1
2
Reserved
1/B2
CMT_CTR2
3
VCC
1/B2
CMT_CTR3
4
CMT
CMT_CTR0
CMT_CTR1
CMT_CTR2
CMT_CTR3
FFC-4AMEP1B
VCC
Do not stuff
FFC-26BMEP1B
Do not stuff
CN9
GND
1/C2
SCIF1_TXD
1/C2
SCIF1_RXD
1/C2
SCIF1_RTS
1/C2
SCIF1_CTS
1/C2
SCIF1_CLK
1
2
3
4
5
SCIF1
SCIF1_TXD
SCIF1_RXD
SCIF1_RTS
SCIF1_CTS
SCIF1_CLK
FFC-5AMEP1B
GND
Do not stuff
N.C
CN10
N.C
VCC
1/C2
SCIF0_TXD
VCC
1/C2
SCIF0_RXD
VCC
1/C2
SCIF0_CLK
1
2
3
SCIF0
SCIF0_TXD
SCIF0_RXD
SCIF0_CLK
FFC-3AMEP1B
VCC
Do not stuff
FFC-40BMEP1B
Do not stuff
CN11
GND
GND
CN12
ADC
Avcc_ADC
1/C2
I2C1_SCL
1
1/C2
I2C1_SDA
2
I2C
I2C1_SCL
I2C1_SDA
FFC-2AMEP1B
Do not stuff
E
02
F
Title: MS7760DBG01-2/1 Circuit Diagram
Date: 7-29-2003_14:58
Sheet
2
of
2
SH7760 T-Engine User’s Manual
R0P7760TH001TRK
Publication Date
Published by
Edit by
Aug. 2004
Rev.1.00
Renesas Solutions Corp.
Microcomputer Tool Marketing Department
Renesas Solutions Corp.
Microcomputer Tool Marketing Department
© 2004. Renesas Technology Corp. and Renesas Solutions Corp., All rights reserved. Printed in Japan.
R0P7760TH001TRK
User’s Manual