Download fulltext - DiVA Portal

CHAPTER 4
49
Programmer’s Reference Manual [11] could be useful1 . In software, people
can just follow the instructions on the OpenRISC official toolchain webpage
[12] to get the OpenRISC compiler and debugging toolset. When trying to
build the toolchain manually, an application note [13] from Jeremy Bennett
is recommended as a reference.
So far, we had introduced the OpenRISC processor from many aspects.
In the following sections, the OR1200 architecture will be firstly described
and then several topics related to the OR1200, including the registers, the
exceptions, the Tick Timer (TT) and the Programmable Interrupt Controller
(PIC). After that, a section is reserved for the details of porting the uC/OSII Real-Time Operating System (RTOS) to the OR1200.
4.2
OR1200 Features and Architecture
To give an overview of the CPU performance, some of the OR1200 features
[10] are listed below:
• 32-bit RISC processor
• Harvard architecture
• 5-stage pipeline
• Cache and MMU supported
• WISHBONE bus interface
• 300 Dhrystone 2.1 MIPS at 300MHz using 0.18u process
• Target medium and high performance networking and embedded
applications
• Competitors include ARM10, ARC and Tensilica RISC processors
The OR1200 has a clear architecture, showed in Figure 4.1. It has a CPU/DSP
core at the center and includes data/instruction caches, data/instruction
Memory Management Units (MMUs), a timer, an interrupt controller, a
debug unit and a power management unit.
1
These 2 documents were updated in late 2010. We didn’t have them when doing the
thesis.