Download Graphical programs with FIFO structure for controller/FPGA

US007945895B2
(12)
United States Patent
(10) Patent N0.:
US 7,945,895 B2
(45) Date of Patent:
*May 17, 2011
Breyer
(54) GRAPHICAL PROGRAMS WITH FIFO
(75)
*
,
,
0s
eta .
400% Andrade
4/2006 Peterson et a1.
7/2006 Kodosky
Inventor:
6,763,515 B1
7/2006 Vazquez
John R. Breyer, Austin, TX (US)
Notice:
FOREIGN PATENT DOCUMENTS
Subject to any disclaimer, the term of this
patent is extended or adjusted under 35
U'S'C' 15403) by 1385 days‘
This patent is subject to a terminal dis-
EP
1 004 085 B1
8/2003
OTHER PUBLICATIONS
International search report and Written opinion for application No.
PCTMSZOOe/OMOIZmeiledJuI1~ 6, 2007
Clalmer'
(Continued)
Appl' N05 11/421,691
.
715/771
............ ..
(Continued)
Austin, TX (U S)
(21)
0
7,024,660 B2
7,028,222 B2
6,219,628 B1
(73) Assignee: National Instruments Corporation,
(*)
gogoskkz et 3%
STRUCTURE FOR CONTROLLER/FPGA
COMMUNICATIONS
Primary Examiner * John Chavis
_
(74) Attorney, Agent, or Firm * Meyertons Hood Kivlin
(22) Flled'
Jun‘ 1’ 2006
KoWert & GoetZel, P.C.; Jeffrey C. Hood; Mark S. Williams
Us 2007/0089063
PI‘IOI‘
A1Publication
APR 19,Data
2007
_
System and method for communicating between graphical
_
programs executing on respective devices, e.g., a program
Related U-s- APPlleatmn Data
mable hardware element (PHE) and a controller. The system
(63) Continuation-in-part of application No. 11/252,001,
Includes a ?rst node repreSemmga?rSt 1n’ ?rst Du? (FIFO)
?led on Oct 17 2005 HOW Pat NO 7 606 950
'
(51)
’
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’
structure, and a second node prov1d1ng a controller rnterface
'
to the FIFO structure. A ?rst portion of the FIFO is imple
Int Cl
mented on the PHE, and a second portion of the FIFO is
G08]? /45
(52)
’
(2006 01)
implemented in memory of the controller. The ?rst and sec
'
US. Cl. ...... .... ...... ... .................................... .. 717/113
ond nodes are operable to be included respectively in ?rst and
Second graphical programs’ Where the ?rst graphical program
Fleld 0f ~(jla'ssl?catlon Search . . . . . . . . . . . . .
is deployable to the
See aPPheanOn ?le for Complete Search hlstol'y-
gram is deployable to the controller, and Where the graphical
_
(56)
programs communicate via the FIFO in cooperatively per
References Clted
forming a speci?ed task. The FIFO may implement a Direct
Memory Access (DMA) FIFO, Where at least part of a DMA
U.S. PATENT DOCUMENTS
4/1990 Kodosky et a1.
4,914,568 A
5,481,741 A
Where the Second graphical pro
controller is implemented on or coupled to the PHE.
43 Claims, 13 Drawing Sheets
1/1996 McKaskle et al.
include first node representing a FIFO in a first
graphical program, where a portion of the
FIFO is deployable to a programmable
hardware element and a second portion of the
FIFO ls deployable to a computer system
coupled to the programmable hardware
element
include a second node providing a controller
interface to the FIFO in 5 second graphical
program
504
(optional)
in response to the inclusion of the first node,
automatically generate data transfer logic
implementing at least a portion of FIFO
functionality for the FIFO tor deployment to
the programmable hardware element
i
deploy the first graphical program and
(optionally) the generated data transfer lOglO
to the programmable hardware element, and
the second graphical plog rem to the computer
system
5%
concurrently execute the first graphical
program on the programmable hardware
element and the second graphical program on
the computer system, where the first and
second graphlcal programs communicate via
the FlFO to cooperatively perform a specified
task
.5111
US 7,945,895 B2
Page 2
U.S. PATENT DOCUMENTS
7,085,670 B2 *
7,530,052 B2 *
8/2006 Odom et al' """""""" " 702/127
5/2009 Morrow et al.
. 717/113
7,565,609 B2 *
7/2009 Vrancic et a1‘ “““““““ “ 715/734
2001/0020291 A1
2003/0034998 A1
9/2001 Kudukoli et 31‘
2/2003 Kodosky et al.
OTHER PUBLICATIONS
Steven S. Lumetta and David E. Culler; “Managing Concurrent
A
f Sh dM
A t. M
,,' IEEE P
d.
f
00655 or I are
emory
c We.
essages ,-
rocee lngs 0
the International Parallel Processing Symposium; Apr. 1998; pp.
272-278.
2003/0040881 A1 * 2/2003 Steger et al. ................ .. 702/123
2003/ 0192032 A1 * 10/2003 Andrade et al.
. 717/124
2004/0015924 A1*
1/2004 Shah et al. .... ..
. 717/154
Michel Dubois and Christoph Scheurich; “Memory Access Depen
dencies in Shared-Memory Multiprocessors”; IEEE Transactions on
Software Engineering; Jun. 1990; pp. 660-673; vol. 16, No. 6.
2005/0257194 A1
11/2005 MOIIOW
Narain H. Gehani; “Capsules: A Shared Memroy Access Mechanism
2005/0257195 A1 *
11/2005 MOIIOW et a1~ ~~~~~~~~~~~~~ ~~ 717/109
2006/0015862 A1
2006/0041859 A1
2006/0053211 A1
1/2006 Odom
2/2006 Vmncic
3/2006 Komerup
2007/0044072 A1 *
2/2007
2007/0088865 A1*
4/2007
for Concurrent C/C++”; IEEE Transactions on Parallel and Distrib
uted Systems; Jul. 1993; pp. 795-811; Vol.4, No. 7.
“LabVIEW Real-Time Module User Manual”, Apr. 2004 Edition; 72
pages; National Instruments Corporation.
Hayles ........................ .. 717/113
* cited by examiner
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include first node representing a FIFO in a first
graphical program, where a portion of the
FIFO is deployable to a programmable
hardware element and a second portion of the
FIFO is deployable to a computer system
coupled to the programmable hardware
element
Q
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include a second node providing a controller
interface to the FIFO in a second graphical
program
5%
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(optional)
in response to the inclusion of the first node,
automatically generate data transfer logic
implementing at least a portion of FlFO
functionality for the FIFO for deployment to
the programmable hardware element
506
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deploy the first graphical program and
(optionally) the generated data transfer logic
to the programmable hardware element, and
the second graphical program to the computer
system
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concurrently execute the first graphical
program on the programmable hardware
element and the second graphical program on
the computer system, where the first and
second graphical programs communicate via
the FIFO to cooperatively perform a specified
task
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FIFO node
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loop structure
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FIFO manager node
loop structure
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US 7,945,895 B2
1
2
GRAPHICAL PROGRAMS WITH FIFO
STRUCTURE FOR CONTROLLER/FPGA
COMMUNICATIONS
4,914,568; 5,291,587; 5,301,301; and 5,301,336; among oth
ers, to Kodosky et al disclose a graphical programming envi
ronment Which enables a user to easily and intuitively create
a graphical program. Graphical programming environments
such as that disclosed in Kodosky et al can be considered a
higher and more intuitive Way in Which to interact With a
CONTINUATION AND PRIORITY DATA
This application is a Continuation-In-Part of, and claims
computer. A graphically based programming environment
bene?t of priority to, US. patent application Ser. No. 11/252,
001, titled “Graphical Programs With Direct Memory Access
FIFO For Controller/FPGA Communications”, ?led Oct. 17,
can be represented at a level above text-based high level
programming languages such as C, Basic, Java, etc.
FIELD OF THE INVENTION
A user may assemble a graphical program by selecting
various icons or nodes Which represent desired functionality,
and then connecting the nodes together to create the program.
The nodes or icons may be connected by lines representing
data How betWeen the nodes, control How, or execution ?oW.
Thus the block diagram may include a plurality of intercon
The present invention relates to the ?eld of graphical pro
gramming, and more particularly to a system and method for
plays a procedure or method for accomplishing a certain
result, such as manipulating one or more input variables and/
2005, now US. Pat. No. 7,606,950 Whose inventor is John R.
Breyer, and Which is incorporated by reference in its entirety
as though fully and completely set forth herein.
nected icons such that the diagram created graphically dis
enabling a graphical program executing on a controller to
communicate With a graphical program executing on a pro
or producing one or more output variables. In response to the
20
grammable hardWare element, e.g., a ?eld programmable
gate array (FPGA).
25
execution procedure that corresponds to the displayed proce
dure. The graphical program may be compiled or interpreted
by a computer.
30
A graphical program may have a graphical user interface.
For example, in creating a graphical program, a user may
create a front panel or user interface panel. The front panel
may include various graphical user interface elements or front
panel objects, such as user interface controls and/or indica
35
tors, that represent or display the respective input and output
that Will be used by the graphical program, and may include
other icons Which represent devices being controlled.
Thus, graphical programming has become a poWerful tool
available to programmers. Graphical programming environ
DESCRIPTION OF THE RELATED ART
Traditionally, high level text-based programming lan
guages have been used by programmers in Writing application
programs. Many different high level text-based programming
languages exist, including BASIC, C, C++, Java, FORTRAN,
Pascal, COBOL, ADA, APL, etc. Programs Written in these
high level text-based languages are translated to the machine
language level by translators known as compilers or interpret
ers. The high level text-based programming languages in this
level, as Well as the assembly language level, are referred to
herein as text-based programming environments.
Increasingly, computers are required to be used and pro
grammed by those Who are not highly trained in computer
programming techniques. When traditional text-based pro
gramming environments are used, the user’s programming
skills and ability to interact With the computer system often
become a limiting factor in the achievement of optimal utili
Zation of the computer system.
ments such as the National Instruments LabVIEW product
have become very popular. Tools such as LabVIEW have
40
used for test and measurement, data acquisition, process con
45
ming model, programmable hardWare elements have increas
conceptually model a process often does not closely corre
ingly been included in devices, such as simulation, measure
50
used to program a computer system to model such a process.
In other Words, the requirement that a user program in a
text-based programming environment places a level of
abstraction betWeen the user’ s conceptualiZation of the solu
tion and the implementation of a method that accomplishes
data acquisition (SCADA) applications, modeling, simula
tion, image processing/machine vision applications, and
motion control, among others.
In parallel With the development of the graphical program
further complicated by the fact that a sequence of mathemati
cal formulas, steps or other procedures customarily used to
spond to the traditional text-based programming techniques
greatly increased the productivity of programmers, and
increasing numbers of programmers are using graphical pro
gramming environments to develop their softWare applica
tions. In particular, graphical programming tools are being
trol, man machine interface (MMI), supervisory control and
There are numerous subtle complexities Which a user must
master before he can e?iciently program a computer system
in a text-based environment. The task of programming a
computer system to model or implement a process often is
user constructing a diagram or graphical program using the
block diagram editor, data structures and/ or program instruc
tions may be automatically constructed Which characterize an
ment, and control devices, Where the programmable
hardWare element is con?gurable to perform a function, such
as simulation or modeling of a device, a measurement and/or
control function, modeling or simulation function, or any
other type of function. Typically, a softWare program, e.g., a
55
text based program or a graphical program, such as may be
this solution in a computer program. Thus, a user often must
developed in National Instruments Corporation’s LabVIEW
substantially master different skills in order to both concep
graphical development environment, is developed either
tualiZe a problem or process and then to program a computer
to implement a solution to the problem or process. Since a
manually or pro grammatically, and converted into a hardWare
con?guration program, e.g., a netlist or bit ?le, Which is then
user often is not fully pro?cient in techniques for program
60
ming a computer system in a text-based environment to
implement his solution, the ef?ciency With Which the com
puter system can be utiliZed often is reduced.
To overcome the above shortcomings, various graphical
programming environments noW exist Which alloW a user to 65
deployed onto the programmable hardWare element, thereby
con?guring the programmable hardWare element to perform
the function. For example, the programmable hardWare ele
ment may be a ?eld programmable gate array (FPGA). Simi
larly, the program may be an FPGA VI, operable to be
deployed to the FPGA.
construct a graphical program or graphical diagram, also
In many applications, a task, such as a measurement task,
referred to as a block diagram. US. Pat. Nos. 4,901,221;
may be performed conjunctively by programs executing
US 7,945,895 B2
3
4
respectively on a computer system and a programmable hard
Ware element coupled to the computer system, and thus may
ured to include) a DMA controller, described in more detail
alloWs LabVIEW users to run graphical programs on FPGA
hardWare. The FPGAs that LabVIEW can run on are comput
beloW. As described further beloW, in other embodiments
various data transfer logic may be implemented on the FIFO
to facilitate use of the FIFO by the ?rst and second graphical
programs. Alternatively, or in addition, a portion or all of the
FIFO interface may be implemented in softWare.
In some embodiments, other techniques of data transfer
ing nodes that are distinct from other computing nodes in the
may be used to interface to the FIFO. For example, in some
system, such as WindoWs or LabVIEW RT (LabVIEW “Real
7831R FPGA board, Which is a PXI board that includes an
embodiments, the recon?gurable device may not include data
transfer logic, e.g., DMA logic, coupled to or included in the
programmable hardWare element, and such logic may not be
FPGA that is targetable by LabVIEW FPGA. The PXI-7831R
used to transfer the data. There are tWo other common meth
itself is typically installed in a PXI chassis With a controller
(i.e., an embedded computer) that runs either WindoWs or
LabVIEW RT. Therefore, there are tWo computing nodes in
grammed I/O and interrupt-driven I/O. Programmed U0 is
require communication betWeen the programs during perfor
mance of the task. For example, LabVIEW FPGA is an add
on module for the LabVIEW development environment that
Time”) nodes. One speci?c example of this is the NI PXI
ods of doing device I/O other than DMA, knoWn as pro
the system, the FPGA (that runs LabVIEW FPGA), and the
controller (that runs LabVIEW or LabVIEW RT). These tWo
nodes are distinct, and yet may need to Work together and
communicate With each other.
In prior art systems, such communication has generally
been performed via either interrupts or register accesses. For
example, interrupts may be used to alloW an FPGA node to
send an event to the controller node, Which may then respond
to the event and perform an action. Interrupts have the draW
back of not being able to send data With the interrupt. Register
20
completely under the control of the host processor (CPU) and
the program that is running on it. The processor (CPU) may
move data to and from the device by performing reads and
Writes to the device, e.g., via messages and/or registers. The
processor may retrieve status information from the device
(such as Whether the data are ready) by also performing reads
to the device, Where reads and Writes to the device may occur
one after the other. Note that is a relatively sloW method of
moving data. For example, in Waiting for a block of data on
the device, the device may have to be continuously polled to
25
check the status until the data are ready, and then move the
access are often used to send data to and from the FPGA
data point by point by reading the device to put the data in ho st
device. HoWever, register accesses have the draWback of
being sloW, especially in the case of very large amounts of
data. For example, if 1,000,000 samples are to be transferred
betWeen the FPGA and the controller, 1,000,000 individual
memory.
Interrupt-driven U0 is similar to programmed I/O in that
the processor or CPU still moves data to and from the device
30
by having the device send interrupts to the processor. This can
35
SUMMARY OF THE INVENTION
One embodiment of the present invention comprises a sys
tem and method for communicating betWeen programs
executing respectively on a controller and a programmable
by reading and Writing to the device. HoWever, in this
approach status information may be received from the device
register accesses must typically be performed.
Thus, improved systems and methods are desired for com
municating betWeen programs executing respectively on a
computer system and a programmable hardWare element.
be much more ef?cient than programmed I/ O. Using the same
example as for programmed I/O, in Waiting for a block of data
on the device, to check the status the device does not have to
be continuously polled until the data are ready, rather, a pro
cess Would simply register to receive an interrupt from the
device and put the process thread to sleep until the interrupt
Was received, With no polling required. Data is still moved
40
point by point by the processor by reading the device to put
hardWare element (or alternatively, on respective program
mable hardWare elements).
the data into host memory.
A ?rst node representing a ?rst in, ?rst out data structure
(FIFO) may be included in a ?rst graphical program in
response to user input. In other Words, the ?rst node may
element may not be con?gured to control the data transfers.
For example, in some embodiments, the data transfers may be
performed via the controller’s processor, e.g., the processor
of the computer system, or that of a different controller. In
other Words, instead of using DMA to transfer data to and
from the FIFO, the controller’s processor executes softWare
instructions to perform the data transfers, referred to as pro
Thus, in some embodiments, the programmable hardWare
45
comprise a graphical representation of the FIFO. The ?rst
graphical program may comprise a ?rst plurality of intercon
nected nodes that visually indicate functionality of the ?rst
graphical program. The ?rst graphical program is intended
for deployment and execution on a programmable hardWare
50
?gurable device may be coupled via a bus to a computer
system (controller). Note that the bus may be any type of
transmission medium desired, including for example a trans
mission cable, a local area netWork (LAN), a Wide area net
the FIFO, e.g., may be con?gurable to specify one or more of:
55
Ware element to controller memory, and the data type of the
FIFO structure, among others. The FIFO structure node may
60
mable hardWare element, e.g., an FPGA, of the recon?g
urable device.
the recon?gurable device may also include (e.g., be con?g
also be operable to provide status information for the FIFO
structure, such as Whether the FIFO (or the portion imple
mented on the programmable hardWare element) is full, and
so forth.
In one embodiment, the FIFO may be implemented as a
DMA FIFO, although it should be noted that this is but one of
numerous Ways to implement the FIFO. In this embodiment,
depth of the FIFO structure (described in more detail beloW),
direction of the FIFO structure, i.e., controller memory to
programmable hardWare element, or programmable hard
Work (WAN), e.g., the Internet, etc., including Wired or Wire
less transmission means, as desired. For example, in preferred
embodiments, at least a ?rst portion of the FIFO is operable to
be implemented on a programmable hardWare element. For
example, at least a ?rst portion of the FIFO data storage
elements may be operable to be implemented on a program
grammed I/O.
Note that in some embodiments, the ?rst node, e.g., the
FIFO node, may be con?gurable to specify some attributes of
element, e.g., such as on recon?gurable device. The recon
65
A second node may be included in a second graphical
program in response to second user input, Where the second
node is operable to provide a controller interface to the FIFO
structure. Like the ?rst graphical program, the second graphi
cal program may comprise a second plurality of intercon
US 7,945,895 B2
5
6
nected nodes that visually indicate functionality of the second
graphical program. The second graphical program is intended
ality, the second node may represent the speci?ed function
ality of the FIFO structure in the second graphical program.
For example, if FIFO read functionality Were selected, the
for deployment and execution on a controller, such as the
computer system (or another computer system) or another
controller. The second graphical program (i.e., block dia
second node may then function as a FIFO read node in the
second graphical program. In one embodiment, the appear
ance of the second node may be automatically modi?ed to
re?ect or indicate the speci?ed functionality, e.g., the node’s
gram) may include a loop structure or other graphical pro
gram construct(s) as desired, and the second node, Which may
icon, color, shape, or label, may be modi?ed in accordance
With the selected option.
be referred to as a FIFO manager node, may be contained
therein.
In some embodiments, a second portion of the FIFO struc
ture is operable to be implemented in memory of the control
In some embodiments, to provide the one or more select
able options for specifying the desired function of the FIFO
structure, program code, e.g., comprised in the development
ler, e.g., the computer system. For example, a second portion
ofthe FIFO, e.g., a second portion ofthe FIFO’s data storage
elements, may be operable to be implemented in the memory
of the controller (or computer system or another computer
system). Thus, the FIFO structure may be comprised on both
the programmable hardWare element and the controller, and
thus may comprise a distributed FIFO.
In some embodiments, the second node, e. g., the FIFO
manager node may be con?gurable to specify a desired func
tion of the FIFO structure. For example, the second node may
environment and/ or the second node, and/or associated With
the second node, may be operable to determine the FIFO
structure’s con?guration, and only provide or present options
that are in accordance With the FIFO structure’s con?gura
tion. In other Words, the options provided by or for the second
node may be based on the FIFO structure’s con?guration. For
20
be operable to receive input specifying FIFO read operations,
FIFO Write operations, FIFO start operations, FIFO stop
operations, and FIFO con?gure operations, among other
FIFO methods or functionality. For example in one embodi
ment, to specify a desired function of the FIFO structure, one
or more selectable options for specifying the desired function
of the FIFO structure may be provided, and input, e.g. user
ration information included in, or associated With, the FIFO
structure node, i.e., the ?rst node, described above. Based on
25
input, may be received selecting one of the one or more
selectable options to specify the desired function of the FIFO
structure, after Which, the second node may be executable to
invoke or perform the desired function of the FIFO structure.
In various embodiments, the selectable options may be
provided by program code, e. g., program instructions, stored
in the memory of the computer system, e.g., comprised in the
development environment in Which the graphical program is
being Written and/or by the second node or program code
associated With the second node. For example, in preferred
30
or receiving input), the node may include both edit time and
runtime program code, Where the edit time code implements
functionality that may operate at edit time, and Where the
runtime code operates at runtime, the edit time code of the
node may execute to provide the options. In preferred
embodiments, such edit time code of the second node may
operate in conjunction With other program code, e.g., pro
gram code comprised in the development environment, e. g.,
the graphical program editor, to manage the presentation and
selection of the options.
this con?guration information, only those options that are
consonant With the con?guration information, i.e., With the
con?gured capabilities of the FIFO structure, may be pre
sented.
In some embodiments, determining the FIFO structure’s
con?guration may include accessing edit time source code of
the ?rst node, and/or a compiled bit ?le generated from the
source code of the ?rst node. For example, in one embodi
ment, the editor (of the development environment) may
access the ?rst graphical program source code, e.g., via a
project that includes the source code for both the ?rst and
35
second graphical programs. As another example, the editor
(or node or associated code) may access the compiled bit ?le
generated from the source code of the ?rst node, and thus this
access may be performed after compilation.
40
selectable options may specify a ?rst function that requires
embodiments, e. g., Where the second node functions as a user
interface node (i.e., is capable of displaying information and/
example, in one embodiment, the development environment
(e.g., editor), the second node, and/or program code associ
ated With the second node, may access and analyZe con?gu
In some embodiments, at least one of the one or more
one or more corollary functions. For example, in one embodi
ment, FIFO read functionality may alWays require prior per
formance of a FIFO start function, for example, or a validate
state function; thus, a selected option specifying FIFO read
operations may automatically specify inclusion of the FIFO
start or validate functionality in the graphical program, along
With the FIFO read functionality, this being but one simple
example. In preferred embodiments, this automatic inclusion
of corollary functionality based upon selected FIFO function
FIFO structure may be displayed by the node, e.g., “FIFO
options is transparent to the user. For example, in some
embodiments, the graphical program may not contain any
visible graphical program elements speci?cally indicating or
Read”, “Number of Elements”, “Timeout”, “Data”, and “Ele
representing the corollary functionality. Thus, if the second
50
In some embodiments, various attributes or ?elds of the
ments Remaining”, although other ?elds or attributes may be
used as desired. Note that provision of the selectable options
may be invoked in any of a variety of Ways. For example, in
one embodiment, the user may click (e.g., left-click, right
click, double click, etc., of a mouse or other pointing device)
on the node to invoke display of the options, eg in a drop
doWn display of the node. The user may then select one of the
options to specify the desired functionality of the FIFO struc
ture, e.g., by clicking on the desired option. Of course, any
node is con?gured to invoke the ?rst function, the second
55
Alternatively, in other embodiments, in response to the selec
tion of the option, the one or more additional graphical pro
60
Once the selection has been made, i.e., once the node/FIFO
structure has been con?gured to provide the desired function
gram elements, e.g., nodes, indicating or representing the
corollary functionality associated With the selected option
may automatically be included and displayed in the graphical
program.
other means for providing, displaying, and/or selecting the
selectable options are also contemplated, the above being but
an exemplary manner of doing so.
node may be executable to automatically invoke the one or
more corollary functions in addition to the ?rst function.
It should be noted that the ?rst graphical program, includ
65
ing the ?rst node, is preferably deployable to the program
mable hardWare element, While the second graphical pro
gram, including the second node, is preferably deployable to
the controller, or computer system, Where the ?rst and the
US 7,945,895 B2
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8
second graphical program are executable to communicate via
be comprised on the programmable hardWare element at all,
the FIFO structure to cooperatively perform a speci?ed task.
In various embodiments, the FIFO structure may be imple
mented in any of a variety of Ways. For example, in some
embodiments, the FIFO structure may require data transfer
i.e., may simply be coupled to the programmable hardWare
element.
Thus, in some embodiments, the system may include the
computer system, Where the computer system includes a pro
cessor and memory, the programmable hardWare element,
logic for transferring data betWeenpor‘tions of the FIFO struc
ture. In different embodiments, the data transfer logic may be
implemented in softWare, and/ or hardWare, and may be com
prised in one or both of the controller and the recon?gurable
device.
For example, as noted above, in one embodiment, the FIFO
coupled to the computer system, and data transfer logic, in the
form of a DMA controller comprised on and/ or coupled to the
programmable hardWare element. In one embodiment, the
DMA controller may include ?rst DMA logic, coupled to or
comprised on the programmable hardWare element, Where
the ?rst DMA logic implements DMA functionality, and sec
ond DMA logic, comprised on the programmable hardWare
structure may be implemented as a Direct Memory Access
(DMA) FIFO, Where DMA is used to transfer data betWeen
the tWo portions of the FIFO. As is Well knoWn in the art of
element, Where the second DMA logic implements FIFO
functionality for the ?rst DMA logic. Once the ?rst and
memory access and management, a DMA controller is gen
erally used to facilitate direct access to memory in place of a
processor. Thus, in embodiments of the present system Where
the FIFO structure is implemented as a DMA FIFO, the
recon?gurable device may require a DMA controller, i.e.,
DMA logic, e. g., either coupled to and/ or implemented on the
20
programmable hardWare element. For example, in one
embodiment, the DMA controller may be included on the
same circuit board as the programmable hardWare element,
and may be communicatively coupled thereto to facilitate
direct memory access by the DMA FIFO, e.g., by the pro
25
grammable hardWare element, of the portion of the DMA
FIFO comprised in the memory of the controller (or computer
system). HoWever, in some embodiments, the DMA control
ler may not inherently support or provide FIFO functionality,
and so custom logic may need to be generated, as described
beloW.
Thus, in embodiments Where data transfer logic, e.g., a
memory controller, is required to transfer data betWeen por
tions of the FIFO, at least a portion of this data transfer logic
may be automatically generated in response to including the
?rst node in the ?rst graphical program, and may be generated
in accordance With con?guration information for the FIFO.
For example, in embodiments Where the FIFO is a DMA
FIFO, at least a portion of the DMA controller, i.e., additional
DMA logic, may be automatically generated in response to
including the ?rst node in the ?rst graphical program, and
may be generated in accordance With con?guration informa
tion for the DMA FIFO. The at least a portion of DMA logic
may be deployable to the programmable hardWare element to
implement FIFO functionality for the DMA controller, e.g.,
to implement the DMA FIFO functionality.
the execution of the ?rst graphical program to cooperatively
perform the speci?ed task. Note that in embodiments Where
the FIFO structure is implemented as a DMA FIFO, the FIFO
30
(possibly in conjunction With the DMA controller) preferably
facilitates direct memory access of the controller memory,
35
speci?cally, FIFO storage elements comprised in the memory
of the controller, by the ?rst graphical program, during execu
tion. As noted above, in other embodiments, the controller
transfers the data betWeen the controller and the recon?g
urable device, and so no special data transfer logic, e.g., such
as a DMA controller, is needed.
40
BRIEF DESCRIPTION OF THE DRAWINGS
A better understanding of the present invention can be
obtained When the folloWing detailed description of the pre
ferred embodiment is considered in conjunction With the
45
folloWing draWings, in Which:
FIG. 1A illustrates a computer system that may be suitable
for implementing an embodiment of the present invention;
FIG. 1B illustrates a netWork system comprising the com
50
computer system). Note that deploying the second graphical
program to the computer system may simply mean compiling
the program for execution by the processor, placing the pro
gram in a particular directory, or otherWise making sure that
the second graphical program is properly executable by the
computer system, since in preferred embodiments, the second
graphical program is developed on the computer system, and
thus may already be present.
programmable hardWare element, and the second graphical
program may be executed on the controller concurrently With
The ?rst graphical program, and optionally the at least a
portion of data transfer logic, e.g., of DMA logic, may be
deployed to the programmable hardWare element. The second
graphical program may be deployed to the controller (or
second graphical programs (and possibly some or all of the
DMA controller logic) have been deployed, the DMA con
troller may be operable to receive instructions from the ?rst
node and the second node and directly transfer data betWeen
the programmable hardWare element and the memory of the
computer system in accordance With the received instruc
tions.
Finally, the ?rst graphical program may be executed on the
55
puter system of FIG. 1A and a device suitable for implement
ing some embodiments of the present invention;
FIG. 2A illustrates an instrumentation control system
according to one embodiment of the invention;
FIG. 2B illustrates an industrial automation system accord
ing to one embodiment of the invention;
FIG. 3A is a high-level block diagram of an exemplary
system that may execute or utiliZe graphical programs;
FIG. 3B illustrates an exemplary system that may perform
control and/or simulation functions utiliZing graphical pro
In some embodiments Where the FIFO structure is a DMA
FIFO, the ?rst DMA controller portion may be coupled to the
programmable hardWare element, but may not actually be
implemented on the programmable hardWare element. In
other embodiments, the ?rst DMA controller portion may be
deployed to and comprised on the programmable hardWare
60
element. Node that in various other DMA FIFO embodi
ments, the DMA controller may be comprised entirely on the
programmable hardWare element, or, alternatively, may not
65
grams;
FIG. 4 is an exemplary block diagram of the computer
systems of FIGS. 1A, 1B, 2A and 2B and 3B;
FIG. 5 is a ?owchart diagram illustrating one embodiment
of a method for enabling a graphical program executing on a
controller to communicate With a graphical program execut
ing on a programmable hardWare element, according to one
embodiment;
US 7,945,895 B2
9
10
FIGS. 6A and 6B illustrate exemplary graphical programs
or random access memory such as DRAM, DDR RAM,
implementing a FIFO structure, respectively executable on a
SRAM, EDO RAM, Rambus RAM, etc.; or a non-volatile
programmable hardware element and a controller, according
memory such as a magnetic media, e.g., a hard drive, or
to one embodiment;
optical storage. The memory medium may comprise other
FIGS. 7A and 7B illustrate systems implementing various
embodiments of the present invention;
FIGS. 8A and 8B illustrate simpli?ed block diagrams of a
FIFO structure, according to one embodiment; and
types of memory as well, or combinations thereof. In addi
tion, the memory medium may be located in a ?rst computer
in which the programs are executed, or may be located in a
second different computer which connects to the ?rst com
puter over a network, such as the Internet. In the latter
FIG. 9 illustrates an embodiment of a FIFO implemented
on two recon?gurable devices including respective program
mable hardware elements, according to one embodiment.
While the invention is susceptible to various modi?cations
and alternative forms, speci?c embodiments thereof are
shown by way of example in the drawings and are herein
described in detail. It should be understood, however, that the
drawings and detailed description thereto are not intended to
limit the invention to the particular form disclosed, but on the
contrary, the intention is to cover all modi?cations, equiva
lents and alternatives falling within the spirit and scope of the
present invention as de?ned by the appended claims.
instance, the second computer may provide program instruc
tions to the ?rst computer for execution. The term “memory
medium” may include two or more memory mediums which
may reside in different locations, e. g., in different computers
that are connected over a network.
Carrier Mediumia memory medium as described above,
as well as signals such as electrical, electromagnetic, or digi
tal signals, conveyed via a communication medium such as a
bus, network and/or a wireless link.
20
Programmable Hardware Elementiincludes various
types of programmable hardware, recon?gurable hardware,
programmable logic, or ?eld-programmable devices (FPDs),
DETAILED DESCRIPTION OF THE PREFERRED
EMBODIMENTS
The following references are hereby incorporated by ref
such as one or more FPGAs (Field Programmable Gate
Arrays), or one or more PLDs (Programmable Logic
Devices), such as one or more Simple PLDs (SPLDs) or one
or more Complex PLDs (CPLDs), or other types of program
erence in their entirety as though fully and completely set
forth herein:
mable hardware. A programmable hardware element may
also be referred to as “recon?gurable logic”.
Incorporation by Reference
US. Pat. No. 4,914,568 titled “Graphical System for Mod
eling a Process and Associated Method,” issued on Apr. 3,
25
Mediumiincludes one or more of a memory medium,
30
1 990.
encompasses various types of mediums that can either store
US. Pat. No. 5,481,741 titled “Method and Apparatus for
Providing Attribute Nodes in a Graphical Data Flow Environ
ment,” issued on Jan. 2, 1996.
US. Pat. No. 5,481,741 titled “Method and Apparatus for
Providing Attribute Nodes in a Graphical Data Flow Environ
ment”.
US. Pat. No. 6,173,438 titled “Embedded Graphical Pro
program instructions/data structures or can be con?gured
35
gramming System” ?led Aug. 18, 1997.
US. Pat. No. 6,219,628 titled “System and Method for
40
Con?guring an Instrument to Perform Measurement Func
tions UtiliZing Conversion of Graphical Programs into Hard
ware Implementations,” ?led Aug. 18, 1997.
US. Patent Application Publication No. 20010020291
(Ser. No. 09/745,023) titled “System and Method for Pro
carrier medium, and/or programmable hardware element;
with a hardware con?guration program. For example, a
medium that is “con?gured to perform a function or imple
ment a software object” may be 1) a memory medium or
carrier medium that stores program instructions, such that the
program instructions are executable by a processor to perform
the function or implement the software object; 2) a medium
carrying signals that are involved with performing the func
tion or implementing the software object; and/or 3) a pro
grammable hardware element con?gured with a hardware
con?guration program to perform the function or implement
the software object.
45
Programithe term “program” is intended to have the full
grammatically Generating a Graphical Program in Response
breadth of its ordinary meaning. The term “program”
to Program Information,” ?led Dec. 20, 2000.
US. patent application Ser. No. 08/912,427 titled “System
and Method for Converting Graphical Programs Into Hard
ware Implementations” ?led on Aug. 18, 1997, whose inven
tors were Jeffrey L. Kodosky, Hugo Andrade, Brian Keith
Odom, and Cary Paul Butler.
US. patent application Ser. No. 10/177,553 titled “Target
Device-Speci?c Syntax and Semantic Analysis For a Graphi
includes 1) a software program which may be stored in a
memory and is executable by a processor or 2) a hardware
cal Program” ?led on Jun. 21, 2002, whose inventors were
Newton G. Petersen and Darshan K. Shah.
US. patent application Ser. No. 11/252,001, titled
“Graphical Programs With Direct Memory Access FIFO For
Controller/FPGA Communications”, ?led Oct. 17, 2005,
whose inventor is John R. Breyer.
50
Software Programithe term “software program” is
intended to have the full breadth of its ordinary meaning, and
includes any type of program instructions, code, script and/or
55
60
ming languages, such as C, C++, Pascal, Fortran, Cobol, Java,
assembly language, etc.; graphical programs (programs writ
ten in graphical programming languages); assembly language
language; scripts; and other types of executable software. A
The following is a glossary of terms used in the present
application:
software program may comprise two or more software pro
grams that interoperate in some manner.
Memory MediumiAny of various types of memory
?oppy disks 104, or tape device; a computer system memory
data, or combinations thereof, that may be stored in a memory
medium and executed by a processor. Exemplary software
programs include programs written in text-based program
programs; programs that have been compiled to machine
Terms
devices or storage devices. The term “memory medium” is
intended to include an installation medium, e.g., a CD-ROM,
con?guration program useable for con?guring a program
mable hardware element.
65
Hardware Con?guration Programia program, e.g., a
netlist or bit ?le, that can be used to program or con?gure a
programmable hardware element.