Download Preliminary User`s Manual

440EPx – PPC440EPx Embedded Processor
Revision 1.12 – April 25, 2007
Preliminary User’s Manual
Figure 24-16. DMA to PLB3 Status Register (DMA2P30_SR)
0:3
CS[0:3]
Channel 0–3 Terminal Count Status
0 Terminal count has not occurred
1 Terminal count has been reached
Set when the transfer count reaches 0.
4:7
TS[0:3]
Channel 0–3 End of Transfer Status
0 End of transfer has not been requested
1 End of transfer has been requested
Only valid for channels with
DMA2P30_CRn[ETD]=0.
8:11
RI[0:3]
Channel 0–3 Error Status
0 No error
1 Error occurred
See “Errors” on page 637 for more information.
12:15
IR[0:3]
Internal DMA Request
0 No internal DMA request pending
1 Internal DMA request is pending
16:19
ER[0:3]
External DMA Request
0 No external DMA request pending
1 External DMA request is pending
20:23
CB[0:3]
Channel Busy
0 Channel is idle
1 Channel currently active
24:27
SG[0:3]
Scatter/Gather Status
0 No scatter/gather operation in progress
1 Scatter/gather operation in progress
28:31
Reserved
24.2.6.4 DMA to PLB 3 Channel Control Registers (DMA2P30_CR0–DMA2P30_CR3)
DMA2P30_CR0–DMA2P30_CR3 are used to configure and enable their respective DMA channels. Before a DMA
channel can transfer data, the channel control, source address, destination address, and transfer count registers
must be programmed. If a DMA channel is programmed for scatter/gather transfers (DMA_SGC[SSGn]=1) the
DMA channel control register is automatically loaded from memory. For additional details, see Scatter/Gather
Transfers on page 622.
Figure 24-17. DMA to PLB3 Channel Control Registers (DMA2P30_CR0–DMA2P30_CR3)
0
CE
Channel Enable
0 Channel is disabled
1 Channel is enabled
This field is automatically cleared when the
transfer completes or an error occurs.
1
CIE
Channel Interrupt Enable
0 Disable interrupts from this channel
1 Enable interrupts from this channel
When enabled, interrupts are generated for terminal count, end of transfer, and errors conditions. See DMA Interrupts on page 638.
2
TD
In peripheral mode:
0 Transfers are from memory-to-peripheral
1 Transfers are from peripheral-to-memory
In device-paced memory-to-memory mode:
TD is not used (don’t care) for software-initiated
memory-to-memory transfers.
0 Peripheral is at the destination address
1 Peripheral is at the source address
3
632
PL
Peripheral Location
0 External peripheral (EBC) bus
1 OPB (UART0)
AMCC Proprietary