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VS1000 Programmer’s Guide
PKP
VSMPG
4. PERIPHERAL DOCUMENTATION
ECC counter register
NFLSH ECC CNT bits
Bits Description
7:0 Calculated ecc words (data is processed in 16-bit
format)
Name
ecc-cnt
Ecc-cnt register counts the 16-bit words that are read or written to dreg. This information
is required when lpl, lph and cp are calculated. The register is updated only when the
ecc is enabled (ecc-ena = ’1’). In write operation the register is updated one clock cycle
after the write took place (as the data is being moved to the data buffer) and in the read
operation it is updated in the same clock cycle.
4.6.4
VS1000 ROM code usage
The ROM code in VS1000 has the following usage for the Nand Flash controller:
At boot-up the Nand Flash chip select is checked: if it’s pulled high, Nand flash scan is
attempted. For proper recognition of the Nand Flash, a number of access methods are
used to attempt to read the first 512 bytes of the Nand Flash chip and look for an 8-byte
NandType record from the beginning of the block. The NandType record should confirm
the proper access method number for the Flash in question and specify the device size
and erasable block size of the Flash chip (see datasheet).
The remaining 504 bytes of the first block can contain a VSDSP boot record, which can
be used to load data to X RAM or I RAM and optionally execute code to extend or
replace firmware functionality on chip.
If the ROM does not have a proper access method for the Nand Flash, but reading at
least the first block is successful with one of the ROM methods, the boot record can be
used to load an access method to RAM so the bootup can be continued.
For VS1000B the first block also indicates how many extra sectors belong to the boot
record, so that upto 16-block executables can be loaded. However, this can only be used
with one of the supported FLASH access methods.
Nand Flash access methodology
VS1000 writes to the nand flash in blocks of 512 (data) + 16 (spare) bytes. single-level
cell (SLC) large page flashes (block size 2112) are mostly ok with this, but multi-level cell
(MLC) have problems with this so those are not supported by the ROM code. VS1000
ROM contains own wear levelling algorithm and logical-to-physical block mapper that
greatly extends the life of the nand flash chips.
Rev. 0.15 Preliminary
2008-06-30
Page 72(87)