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BASE+3 CH1 counter latch source/counter latch on reset Bit D7 D6 D5 D4 D3 D2 D1 D0 Value NA NA NA NA LC S2 S1 S0 BASE+4 CH2 counter latch source/counter latch on reset Bit D7 D6 D5 D4 D3 D2 D1 D0 Value NA NA NA NA LC S2 S1 S0 BASE+5 CH3 counter latch source/counter latch on reset Bit D7 D6 D5 D4 D3 D2 D1 D0 Value NA NA NA NA LC S2 S1 S0 S2, S1, S0 The source of the signal to latch the counter data 000 S/W read latch data 001 Index-in latch data 010 DI0 latch data 011 DI1 latch data 100 Timer latch data LC Reset/do not reset counter value after it is latched 0 Do not reset counter after it is latched 1 Reset counter after it is latched BASE+6 Counter overflow lock control Bit D7 D6 D5 D4 D3 D2 D1 D0 Value NA NA NA NA NA OL3 OL2 OL1 OL3 ~ OL1 Counter overflow lock control (OL3 = CH3, OL2 = CH2, OL1 = CH1) 36 0 Counter value locked when counter overflows 1 Counter continues counting (wraps over) when counter overflows PCL-833 User's Manual
