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Download USER`S MANUAL
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BASIC TIMER and TIMER 0 S3C830A/P830A RESET or STOP Bit 1 Bits 3, 2 Basic Timer Control Register (Write '1010xxxxB' to Disable) Data Bus fXX/4096 Clear fXX/1024 fXX DIV fXX/128 MUX 8-Bit Up Counter (BTCNT, Read-Only) OVF fXX/16 R Start the CPU (note) Bit 0 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). Figure 10-2. Basic Timer Block Diagram 10-4 RESET
