Download Evaluation Module User Manual

56858
Evaluation Module User Manual
56F850
16-bit Digital Signal Controllers
DSP56858EVMUM
Rev. 3
07/2005
freescale.com
TABLE OF CONTENTS
Preface vii
Chapter 1
Introduction
1.1
1.2
1.3
56858EVM Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
56858EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
56858EVM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Chapter 2
Technical Summary
2.1
56858. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Program and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.1
SRAM Bank 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.2
SRAM Bank 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3
SPI Serial EEPROM/Data FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.4
RS-232 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.5
Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.6
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.7
Debug LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.8
Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.8.1
JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.8.2
Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.9
External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.10 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.11 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.12 Stereo Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.12.1
Analog Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.12.2
Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.13 Daughter Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.13.1
Memory Daughter Card Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.13.2
Peripheral Daughter Card Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.14 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.15 Host Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.16 Test Points. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Table of Contents, Rev. 3
Freescale Semiconductor
i
Appendix A
56858EVM Schematics
Appendix B
56858EVM Bill of Material
DSP56858EVM User Manual, Rev. 3
ii
Freescale Semiconductor
LIST OF FIGURES
1-1
Block Diagram of the 56858EVM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-2
56858EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-3
Connecting the 56858EVM Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2-1
Schematic Diagram of the External CS0 Memory Interface . . . . . . . . . . . . . . . . . . . 2-3
2-2
Schematic Diagram of the External CS1/CS2 Memory Interface . . . . . . . . . . . . . . . 2-4
2-3
SPI EEPROM Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-4
Schematic Diagram of the RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-5
Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2-6
Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2-7
Block Diagram of the Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2-8
Schematic Diagram of the User Interrupt Interface. . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-9
Schematic Diagram of the RESET Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2-10
Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2-11
CODEC Analog Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2-12
CS4218 Stereo Audio Codec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2-13
Diagram of the USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
List of Figures, Rev. 3
Freescale Semiconductor
iii
DSP56858EVM User Manual, Rev. 3
iv
Freescale Semiconductor
LIST OF TABLES
1-1
56858EVM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2-1
SPI Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-2
RS-232 Serial Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-3
Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-4
LED Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-5
JTAG Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2-6
Parallel JTAG Interface Disable Jumper Selection . . . . . . . . . . . . . . . . . . . . . . 2-10
2-7
Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2-8
Codec Sample Rate Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2-9
ESSI Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2-10
GPIO Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2-11
Memory Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2-12
Peripheral Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . 2-21
2-13
Host Interface Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
List of Tables, Rev. 3
Freescale Semiconductor
v
DSP56858EVM User Manual, Rev. 3
vi
Freescale Semiconductor
Preface
This reference manual describes in detail the hardware on the 56858 Evaluation Module.
Audience
This document is intended for application developers who are creating software for
devices using the Freescale 56858 part.
Organization
This manual is organized into two chapters and two appendixes.
•
Chapter 1, Introduction - provides an overview of the EVM and its features.
•
Chapter 2, Technical Summary - describes in detail the 56858 hardware.
•
Appendix A, 56858EVM Schematics - contains the schematics of the
56858EVM.
•
Appendix B, 56858EVM Bill of Material - provides a list of the materials used on the
56858EVM board.
Suggested Reading
More documentation on the 56858 and the 56858EVM kit may be found at URL:
www.freescale.com
Preface, Rev. 3
Freescale Semiconductor
vii
Notation Conventions
This manual uses the following notational conventions:
Term or Value
Symbol
Examples
Active High Signals
(Logic One)
No special symbol
attached to the signal
name
A0
CLKO
Active Low Signals
(Logic Zero)
Noted with an
overbar in text and in
most figures
WE
OE
Hexadecimal Values
Begin with a “$” symbol
$0FF0
$80
Decimal Values
No special symbol
attached to the
number
Binary Values
Begin with the letter
“b” attached to the
number
b1010
b0011
Numbers
Considered positive
unless specifically
noted as a negative
value
5
-10
Blue Text
Linkable on-line
Bold
Reference sources,
paths, emphasis
Exceptions
In schematic drawings,
Active Low Signals may be
noted by a backslash: /WE
10
34
Voltage is often shown as
positive: +3.3V
...refer to Chapter 7,
License
...see:
www.freescale.com
DSP56858EVM User Manual, Rev. 3
viii
Freescale Semiconductor
Definitions, Acronyms, and Abbreviations
Definitions, acronyms and abbreviations for terms used in this document are defined below for
reference.
Codec
COder/DECoder; a part used to convert analog signals to digital (coder) and digital
signals to analog (decoder)
DIP
Dual Inline Package
EEPROM
Electrically Erasable Programmable Read-Only Memory
EOnCE
Enhanced On-Chip Emulation; a debug bus and port created by Freescale to enable
a designer to create a low-cost hardware interface for a professional quality debug
environment
ESSI
Enhanced Synchronous Serial Interface; a communications port on Freescale’s
family of controllers
EVM
Evaluation Module; a hardware platform which allows a customer to evaluate the
silicon and develop his application.
GPIO
General Purpose Input and Output port on Freescale’s family of controllers; does
not share pin functionality with any other peripheral on the chip and can only be
set as an input, output or level-sensitive interrupt input
HI
Host Interface; a communications port on Freescale’s family of controllers
IC
Integrated Circuit
JTAG
Joint Test Action Group; a bus protocol/interface used for test and debug
LED
Light Emitting Diode
LQFP
Low Profile Quad Flat Pack package
MPIO
Multi Purpose Input and Output port on Freescale’s family of controllers; shares
package pins with other peripherals on the chip and can function as a GPIO
PCB
Printed Circuit Board
PLL
Phase Locked Loop
RAM
Random Access Memory
ROM
Read Only Memory
SCI
Serial Communications Interface; a communications port on Freescale’s family of
controllers
Preface, Rev. 3
Freescale Semiconductor
ix
SPI
Serial Peripheral Interface; a communications port on Freescale’s family of
controllers
SRAM
Static Random Access Memory
SSI
Synchronous Serial Interface; a communications port on Freescale’s family of
controllers
THD
Total Harmonic Distortion
USB
Universal Serial Bus
WS
Wait State
References
The following sources were referenced to produce this manual:
[1] DSP56800E Reference Manual, DSP56800ERM, Freescale Semiconductor
[2] DSP5685x 16-Bit Digital Signal Processor User’s Manual, DSP5685xUM, Freescale Semiconductor
[3] DSP56858 16-Bit Digital Signal Processor Technical Data, DSP56858, Freescale
Semiconductor
DSP56858EVM User Manual, Rev. 3
x
Freescale Semiconductor
Chapter 1
Introduction
The 56858EVM is used to demonstrate the abilities of the 56858 and to provide a hardware tool
allowing the development of applications that use the 56858.
The 56858EVM is an evaluation module board that includes a 56858 part, 16-bit stereo codec,
USB 1.1/2.0 interface, external memory and a daughter card expansion interface. The daughter
card expansion connectors are for signal monitoring and user feature expandability.
The 56858EVM is designed for the following purposes:
•
Allowing new users to become familiar with the features of the 56800E architecture. The
tools and examples provided with the 56858EVM facilitate evaluation of the feature set
and the benefits of the family.
•
Serving as a platform for real-time software development. The tool suite enables the user
to develop and simulate routines, download the software to on-chip or on-board RAM, run
it, and debug it using a debugger via the JTAG/Enhanced OnCE (EOnCE) port. The
breakpoint features of the EOnCE port enable the user to easily specify complex break
conditions and to execute user-developed software at full speed until the break conditions
are satisfied. The ability to examine and modify all user-accessible registers, memory and
peripherals through the EOnCE port greatly facilitates the task of the developer.
•
Serving as a platform for hardware development. The hardware platform enables the user
to connect external hardware peripherals. The on-board peripherals can be disabled,
providing the user with the ability to reassign any and all of the controller's peripherals.
The EOnCE port's unobtrusive design means that all memory on the board and on the chip
is available to the user.
Introduction, Rev. 3
Freescale Semiconductor
1-1
1.1 56858EVM Architecture
The 56858EVM facilitates the evaluation of various features present in the 56858 part. The
56858EVM can be used to develop real-time software and hardware products based on the
56858. The 56858EVM provides the features necessary for a user to write and debug software,
demonstrate the functionality of that software and interface with the customer's
application-specific device(s). The 56858EVM is flexible enough to allow a user to fully exploit
the 56858's features to optimize the performance of his product, as shown in Figure 1-1.
56858
RESET
LOGIC
RESET
MODE
LOGIC
MODE
CS0
(Program Memory)
128Kx16-bit SRAM
SPI
SPI Data
FLASH 1M-bit
IRQ
IRQ Interface
SCI0
RS-232
Interface
DSub
9-Pin
Address,
Data &
Control
CS1/CS2
(Data Memory)
128Kx16-bit SRAM
ESSI1
SCI1
Peripheral
Daughter
Card
Connector
ESSI0
Stereo 16-bit
Codec
Stereo Line Out
Amp
Headphone Jack
Memory
Daughter Card
Connector
USB
Con
USB Interface
(CS3)
JTAG
Connector
DSub
25-Pin
JTAG/EOnCE
GPIO
Debug LEDs
HI
Host Interface
Connector
Parallel
JTAG Interface
4.00MHz
Crystal
Stereo Line In
XTAL/EXTAL
+1.8V,
+3.3V
& GND
Power Supply
+1.8V, +3.3V & +5.0V
Figure 1-1. Block Diagram of the 56858EVM
DSP56858EVM User Manual, Rev. 3
1-2
Freescale Semiconductor 56858EVM Configuration Jumpers
1.2 56858EVM Configuration Jumpers
Ten jumper groups, (JG1-JG11), shown in Figure 1-2, are used to configure various features on
the 56858EVM board. Table 1-1 describes the default jumper group settings.
2
8
1
7
2 4
JG8
JG10
5
2
1
P3
J5
JG9
P1
S1
JG5
JG11
JG5
JG2
TB1
P2
S/N
6
JG1
1 3
JG7
JG8
JTAG
RESET
DSP56858EVM
RE10519B REV
J3
JG11
1
3
JG10
J2
2
4
1
3
JG9
JG1
U2
S2
JG6
IRQA
U1
JG4
U3
S3
JG2
JG7
J4
JG4
J1
JG3
HEADPHONE
IRQB
P6
1
2
9
10
S4
Y1
JG3
JG6
S4
P4
LEDS
3
P5
U6
U7
LINE
IN
1
LINE
OUT
Figure 1-2. 56858EVM Jumper Reference
Table 1-1. 56858EVM Default Jumper Options
Jumper
Group
Comment
Jumpers
Connections
JG1
Enable on-board Word selectable SRAM via CS0 (U2)
1–2
JG2
Enable on-board Byte selectable SRAM via CS1/CS2 (U3)
JG3
Use on-board EXTAL crystal input for oscillator
2–3
JG4
Use on-board XTAL crystal input for oscillator
1–2
JG5
Enable on-board Parallel JTAG Host/Target Interface
NC
JG6
Enable ESSI0 Port for CODEC data
JG7
Enable GPIO for CODEC control
JG8
Enable SCI0 Port to RS-232 transceiver
JG9
Enable RS-232 output
JG10
Enable SPI Port to Serial EEPROM/Data FLASH
JG11
Enable USB interface via CS3
1-2, 3-4
1-2, 3-4, 5-6, 7-8,
9-10
1-2, 3-4, 5-6
1–2, 3-4
NC
1–2, 3–4, 5–6 & 7–8
1-2
Introduction, Rev. 3
Freescale Semiconductor
1-3
1.3 56858EVM Connections
An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external
+12.0V DC/AC power supply or external +5.0V DC lab power supply to the 56858EVM board.
Parallel Extension
Cable
56858EVM
PC-compatible
Computer
P1
Connect cable
to Parallel/Printer port
P2
External
with 2.1mm, +12.0V
receptacle
Power
connector
TB1
+5.0V
Lab
Supply
Figure 1-3. Connecting the 56858EVM Cables
Perform the following steps to connect the 56858EVM cables:
1. Connect the parallel extension cable to the Parallel port of the host computer.
2. Connect the other end of the parallel extension cable to P1, shown in Figure 1-3, on the
56858EVM board. This provides the connection which allows the host computer to
control the board.
3. Make sure that the external +12.0V DC 1.2A switching power supply or the external
+5.0V DC 1A lab power supply is not plugged into a +120V AC power source.
4. Connect the 2.1mm output power plug from the external switching power supply into P2,
shown in Figure 1-3, on the 56858EVM board. Optionally, attach an external +5.0V DC
lab power supply via the 2-pin terminal block, TB1.
5. Apply power to the external power supply. The green Power-On LED, LED7, will
illuminate when power is correctly applied.
DSP56858EVM User Manual, Rev. 3
1-4
Freescale Semiconductor Chapter 2
Technical Summary
The 56858EVM is designed as a versatile controller development card for developing real-time
software and hardware products to support a new generation of applications in digital and
wireless messaging, digital answering machines, feature phones, modems, and digital cameras.
The power of the 16-bit 56858 controller, combined with the on-board 128K u16-bit external
program/data static RAM (SRAM), 128K u16-bit external data/program SRAM, RS-232
interface, Stereo 16-bit codec interface, USB 2.0 interface, Daughter Card Expansion interface
and parallel JTAG interface, makes the 56858EVM ideal for developing and implementing many
audio and voice algorithms, as well as for learning the architecture and instruction set of the
56858 processor.
The main features of the 56858EVM, with board and schematic reference designators include:
•
56858 16-bit +1.8V/+3.3V Digital Signal Processor operating at 120MHz [U1]
•
External fast static RAM (FSRAM) memory, configured as:
— 128Ku16-bit of memory [U2] with one wait state at 120MHz via CS0
— 128Ku16-bit of memory [U3] with one wait state at 120MHz via CS1/CS2
•
1M-bit Serial EEPROM/Data FLASH [U4]
•
4.00MHz crystal oscillator for controller frequency generation [Y1]
•
Optional external oscillator frequency input connectors [JG3 and JG4]
•
Joint Test Action Group (JTAG) port interface connector for an external debug Host
Target Interface [J3]
•
On-board Parallel JTAG Host Target Interface, with a connector for a PC printer port
cable [P1]
•
RS-232 interface for easy connection to a host processor [U5 and P3]
•
16-bit stereo codec interface [U6, JG6, JG7, P4 and P5]
•
Stereo headphone interface [U8 and P6]
•
Codec sample rate selector [S5]
Technical Summary, Rev. 3
Freescale Semiconductor
2-1
•
USB interface [U15and J5]
•
Peripheral Daughter Card Expansion Connector, to allow the user to connect his own SCI,
ISSI, SPI or GPIO-compatible peripheral to the controller [J2]
•
Memory Daughter Card Expansion Connector, to allow the user to connect his own
memory or memory device to the controller [J1]
•
Host Interface Connector, for high-speed bus data transfer [J4]
•
On-board power regulation from an external +12V DC-supplied power input [P2]
•
On-board power regulation from an optional +5V DC-supplied power input [TB1]
•
Light Emitting Diode (LED) power indicator [LED7]
•
Six on-board real-time user debugging LEDs [LED1-6]
•
Boot MODE selector [S4]
•
Manual RESET push-button [S1]
•
Manual interrupt push-button for IRQA [S2]
•
Manual interrupt push-button for IRQB [S3]
2.1 56858
The 56858EVM uses a Freescale DSP56858FV120 part, designated as U1 on the board and in the
schematics. This part will operate at a maximum speed of 120MHz. A full description of the
56858, including functionality and user information, is provided in these documents:
•
DSP56858 Technical Data, (DSP56858): Provides features list and specifications,
including signal descriptions, DC power requirements, AC timing requirements and
available packaging
•
DSP5685x User’s Manual, (DSP5685xUM): Provides an overview description of the
controller and detailed information about the on-chip components, including the memory
and I/O maps, peripheral functionality, and control/status register descriptions for each
subsystem
•
DSP56800E Reference Manual, (DSP56800ERM): Provides a detailed description of the
core processor, including internal status and control registers and a detailed description of
the family instruction set
Refer to these documents for detailed information about chip functionality and operation. They
can be found on this URL:
www.freescale.com
DSP56858EVM User Manual, Rev. 3
2-2
Freescale Semiconductor Program and Data Memory
2.2 Program and Data Memory
The 56858EVM contains two 128Kx16-bit Fast Static RAM banks. SRAM bank 0 is controlled
by CS0 and SRAM bank 1 is controlled by CS1 and CS2.
2.2.1 SRAM Bank 0
SRAM bank 0, which is controlled by CS0, uses a 128Ku16-bit Fast Static RAM (GSI GS72116,
labelled U2) for external memory expansion; see the FSRAM schematic diagram in Figure 2-1.
CS0 can be configured to use this memory bank as 16-bit program memory, data memory, or
both. Additionally, CS0 can be configured to assign this memory’s size and starting address to
any modulo address space.
This memory bank will operate with one wait state access while the 56858 is running at 120MHz
and can be disabled by removing the jumper at JG1.
GS72116
56858
A0-A16
A0-A16
D0-D15
DQ0-DQ15
RD
OE
WR
WE
CS0
+3.3V
1
2
Jumper Pin 1-2:
Enable SRAM
JG1
Jumper Removed:
Disable SRAM
CE
Figure 2-1. Schematic Diagram of the External CS0 Memory Interface
Technical Summary, Rev. 3
Freescale Semiconductor
2-3
2.2.2 SRAM Bank 1
SRAM bank 1, which is controlled by CS1 and CS2, uses a 128Ku16-bit Fast Static RAM (GSI
GS72116, labeled U3) for external memory expansion; see the FSRAM schematic diagram in
Figure 2-2. Using CS1 and CS2, this memory bank can be configured as byte (8-bit) or word
(16-bit) accessable program memory, data memory, or both. Additionally, CS1 and CS2 can be
configured to assign this memory’s size and starting address to any modulo address space.
This memory bank will operate with one wait state access while the 56858 is running at 120MHz
and can be disabled by removing the jumpers at JG2.
GS72116
56858
A0-A16
A0-A16
D0-D15
DQ0-DQ15
OE
RD
WR
JG2
CS1
1 2
CS2
3 4
WE
LB
HB
CE
Jumper Pin 1-2:
Enable SRAM Low Byte
Jumper Pin 3-4:
Enable SRAM High Byte
Figure 2-2. Schematic Diagram of the External CS1/CS2 Memory Interface
DSP56858EVM User Manual, Rev. 3
2-4
Freescale Semiconductor SPI Serial EEPROM/Data FLASH Memory
2.3 SPI Serial EEPROM/Data FLASH Memory
A 1M-bit +3.3V SPI serial EEPROM/Data FLASH Memory, Atmel AT45DB011B-SC, is
provided on the 56858EVM, reference Figure 2-3. This memory connects directly to the SPI
Port through a header on the 56858. It can be used to load program code and data into the 56858’s
internal or external memory spaces. Jumper block JG10 is provided to allow the user to
disconnect the on-board SPI EEPROM/Data FLASH from the SPI port and allow him to connect
his own SPI port peripheral. The header details are shown in Table 2-1.
Data FLASH Enable
Serial EEPROM /
Data FLASH
(SPI Port Connector)
56858
MOSI/SRFS
SDI
MISO/SRCK
SDO
SCLK/STCK
SCK
SS/STFS/PC3
CS
JG10
Figure 2-3. SPI EEPROM Memory Block Diagram
.
Table 2-1. SPI Port Connector Description
JG10
Pin #
Signal
Pin #
Signal
1
SS/PF3
2
CS
3
MISO/PF0
4
SDO
5
MOSI/PF1
6
SDI
7
SCK/PF2
8
SCK
Technical Summary, Rev. 3
Freescale Semiconductor
2-5
2.4 RS-232 Serial Communications
The 56858EVM provides an RS-232 interface by the use of an RS-232 level converter, (Maxim
MAX3245EEAI, designated as U5). Refer to the RS-232 schematic diagram in Figure 2-4. The
RS-232 level converter transitions the SCI UART’s +3.3V signal levels to RS-232-compatible
signal levels and connects to the host’s serial port via connector P3. Flow control is not provided,
but could be implemented using uncommitted GPIO signals. The pinout of connector P3 is listed
in Table 2-2. The RS-232 level converter/transceiver can be disabled by placing a jumper at JG9.
RS-232
Level Converter
Interface
56858
TXD0
T1in
RXD0
R1out
P3
T1out
R1in
+3.3V
x
FORCEOFF
Jumper Removed:
Enable RS-232
Jumper Pin 1-2:
Disable RS-232
1
6
2
7
3
8
4
9
5
JG9
1
2
Figure 2-4. Schematic Diagram of the RS-232 Interface
Table 2-2. RS-232 Serial Connector Description
P3
Pin #
Signal
Pin #
Signal
1
Jumper to 6 & 4
6
Jumper to 1 & 4
2
TXD0
7
Jumper to 8
3
RXD0
8
Jumper to 7
4
Jumper to 1 & 6
9
N/C
5
GND
DSP56858EVM User Manual, Rev. 3
2-6
Freescale Semiconductor Clock Source
2.5 Clock Source
The 56858EVM uses a 4.00MHz crystal, Y1, connected to its external crystal inputs, EXTAL
and XTAL. To achieve its 120MHz maximum operating frequency, the 56858 uses its internal
PLL to multiply the input frequency by 30. An external oscillator source can be connected to the
controller by using the oscillator bypass connectors, JG3 and JG4; see Figure 2-5. If the input
frequency is above 4MHz, then the EXTAL input should be jumpered to ground by adding a
jumper between JG4 pins 1 and 2. The input frequency would then be injected on JG3’s pin 2. If
the controller needs to be synchronized to the codec’s sample frequency, then the controller’s
input frequency should be jumpered using the 12.2280MHz codec frequency. If the input
frequency is below 4MHz, then the input frequency can be injected on JG4’s pin 2.
EXTERNAL
OSCILLATOR
HEADERS
56858
JG4
3
+1.65V
2
EXTAL
1
4.00MHz
JG3
1
2
12.2880MHz
3
XTAL
Figure 2-5. Schematic Diagram of the Clock Interface
Technical Summary, Rev. 3
Freescale Semiconductor
2-7
2.6 Operating Mode
The 56858EVM provides a boot-up MODE selection switch, S4. This switch is used to select the
operating mode of the controller as it exits RESET. Refer to the DSP56858 User’s Manual for a
complete description of the chip’s operating modes. Table 2-3 shows the two operation modes
available on the 56858.
Table 2-3. Operating Mode Selection
Operating Mode
S4 (ON)
Comment
0
1–2, 3-4 & 5-6
1
3-4 & 5-6
Bootstrap from SPI
2
1-2 & 5-6
Normal Expanded mode
3
5-6
4
1-2 & 3-4
5
3-4
Bootstrap from External byte-wide memory
Development Expanded mode
Host Interface Port Single Strobe mode
Host Interface Port Dual Strobe mode
2.7 Debug LEDs
Six on-board Light-Emitting Diodes, (LEDs), are provided to allow real-time debugging for user
programs. These LEDs will allow the programmer to monitor program execution without having
to stop the program during debugging; refer to Figure 2-6. Table 2-4describes the control of
each LED.
Table 2-4. LED Control
Controlled by
User LED
Port
Signal
LED1
Port D
PD0
LED2
Port D
PD1
LED3
Port D
PD2
LED4
Port D
PD3
LED5
Port D
PD4
LED6
Port D
PD5
DSP56858EVM User Manual, Rev. 3
2-8
Freescale Semiconductor Debug Support
Setting PD0, PD1, PD2, PD3, PD4 or PD5 to a Logic One value will turn on the associated LED.
56858
INVERTING BUFFER
+3.3V
RED LED
PD0
YELLOW LED
PD1
GREEN LED
PD2
RED LED
PD3
YELLOW LED
PD4
GREEN LED
PD5
Figure 2-6. Schematic Diagram of the Debug LED Interface
2.8 Debug Support
The 56858EVM provides an on-board Parallel JTAG Host Target Interface and a JTAG interface
connector for external Target Interface support. Two interface connectors are provided to support
each of these debugging approaches. These two connectors are designated the JTAG connector
and the Host Parallel Interface Connector.
Technical Summary, Rev. 3
Freescale Semiconductor
2-9
2.8.1 JTAG Connector
The JTAG connector on the 56858EVM allows the connection of an external Host Target
Interface for downloading programs and working with the 56858’s registers. This connector is
used to communicate with an external Host Target Interface which passes information and data
back and forth with a host processor running a debugger program. Table 2-5 shows the pin-out
for this connector.
Table 2-5. JTAG Connector Description
J3
Pin #
Signal
Pin #
Signal
1
TDI
2
GND
3
TDO
4
GND
5
TCK
6
GND
7
NC
8
KEY
9
RESET
10
TMS
11
+3.3V
12
NC
13
DE
14
TRST
When this connector is used with an external Host Target Interface, the parallel JTAG interface
should be disabled by placing a jumper in jumper block JG5. Reference Table 2-6 for this
jumper’s selection options.
Table 2-6. Parallel JTAG Interface Disable Jumper Selection
JG5
Comment
No jumpers
On-board Parallel JTAG Interface Enabled
1–2
Disable on-board Parallel JTAG Interface
DSP56858EVM User Manual, Rev. 3
2-10
Freescale Semiconductor Debug Support
2.8.2 Parallel JTAG Interface Connector
The Parallel JTAG Interface Connector, P1, allows the 56858 to communicate with a Parallel
Printer Port on a Windows PC; reference Figure 2-7. Using this connector, the user can
download programs and work with the 56858’s registers. Table 2-7 shows the pin-out for this
connector. When using the parallel JTAG interface, the jumper at JG5 should be removed, as
shown in Table 2-6.
Parallel JTAG Interface
DB-25 Connector
IN OUT
OUT IN
TDI
TDO
56858
P_TRST
IN
OUT
TDI
TDO
TRST
TMS
IN
OUT
TMS
TCK
IN
OUT
TCK
P_RESET
IN
OUT
RESET
IN
OUT
DE
P_DE
+3.3V
Jumper Removed:
Enable JTAG I/F
EN
JG5
1
2
Jumper Pin 1-2:
Disable JTAG I/F
Figure 2-7. Block Diagram of the Parallel JTAG Interface
Technical Summary, Rev. 3
Freescale Semiconductor
2-11
Table 2-7. Parallel JTAG Interface Connector Description
P1
Pin #
Signal
Pin #
Signal
1
NC
14
NC
2
PORT_RESET
15
PORT_IDENT
3
PORT_TMS
16
NC
4
PORT_TCK
17
NC
5
PORT_TDI
18
GND
6
PORT_TRST
19
GND
7
PORT_DE
20
GND
8
PORT_IDENT
21
GND
9
PORT_VCC
22
GND
10
NC
23
GND
11
PORT_TDO
24
GND
12
NC
25
GND
13
PORT_CONNECT
DSP56858EVM User Manual, Rev. 3
2-12
Freescale Semiconductor External Interrupts
2.9 External Interrupts
Two on-board push-button switches are provided for external interrupt generation, as shown in
Figure 2-8. S1 allows the user to generate a hardware interrupt for signal line IRQA. S2 allows
the user to generate a hardware interrupt for signal line IRQB. These two switches allow the user
to generate interrupts for his user-specific programs.
+3.3V
56858
10K
S2
IRQA
0.1µF
+3.3V
10K
S3
IRQB
0.1µF
Figure 2-8. Schematic Diagram of the User Interrupt Interface
Technical Summary, Rev. 3
Freescale Semiconductor
2-13
2.10 Reset
Logic is provided on the 56858 to generate an internal Power-On RESET. The 56858EVM
provides reset logic to support the RESET signals from the JTAG connector, the Parallel JTAG
Interface and the user RESET push-button; refer to Figure 2-9.
JTAG_RESET
RESET
RESET
PUSHBUTTON
MANUAL RESET
TRST
JTAG_TAP_RESET
Figure 2-9. Schematic Diagram of the RESET Interface
DSP56858EVM User Manual, Rev. 3
2-14
Freescale Semiconductor Power Supply
2.11 Power Supply
The main power input, +12.0V DC/AC, to the 56858EVM is through a 2.1mm coax power jack.
An optional +5.0V DC power supply input is available through a 2-pin terminal block, TB1. A
+12.0V DC 1.2A power supply is provided with the 56858EVM; however, less than 500mA is
required by the EVM. The remaining current is available for user daughter card applications
when connected to the daughter card interface. The power regulation on the 56858EVM provides
+5.0V DC voltage regulation for the codec’s analog circuits and to the additonal voltage
regulation logic on the EVM. The additonal voltage regulation logic provides +1.8V DC voltage
regulation for the controller’s core and +3.3V DC voltage regulation for the controller’s I/O,
memory, parallel JTAG interface and supporting logic; refer to Figure 2-10. Power applied to the
56858EVM is indicated with a Power-On LED, referenced as LED7.
P2
+12.0V DC
+5.0V
Regulator
Power
Condition
+5.0V DC
Analog
+3.3V
Regulator
+3.3V DC
CODEC
TB1
+5.0V DC
56858
GND
56858EVM
PARTS
+1.8V
Regulator
+1.8V DC
56858
CORE
Figure 2-10. Schematic Diagram of the Power Supply
Technical Summary, Rev. 3
Freescale Semiconductor
2-15
2.12 Stereo Codec
A 16-bit audio-quality stereo codec, Crystal Semiconductor CS4218, is connected to the 56858’s
ESSI port to support audio, voice and signal analysis applications. The codec is clocked with a
12.288MHz oscillator. This allows the codec to operate between a sample frequency of 8KHz
and 48KHz. The sample rate can be manually set by setting the appropriate switch positions on
DIP switch S5. The sample rate selections possible using this three-position dip switch are
detailed in Table 2-8. The codec supports +3.3V digital levels, eliminating the need for voltage
level translation circuitry. Additionally, a set of zero ohm resistors are provided on the EVM to
allow a user to disconnect the on-board codec from the ESSI port and allow him to connect his
own codec to the ESSI port; see Figure 2-12. The on-board codec has analog signal conditioning
logic, allowing direct connection to its line-level input and line-level output signals through two
1/8” stereo jacks; reference Figure 2-11.
Table 2-8. Codec Sample Rate Selector
SW 5
Position 3
(MF6)
SW 5
Position 2
(MF7)
SW 5
Position 3
(MF8)
Sample Rate
ON
ON
ON
48.00KHz
ON
ON
OFF
32.00KHz
ON
OFF
ON
24.00KHz
ON
OFF
OFF
19.20KHz
OFF
ON
ON
16.00KHz
OFF
ON
OFF
12.00KHz
OFF
OFF
ON
9.60KHz
OFF
OFF
OFF
8.00KHz
DSP56858EVM User Manual, Rev. 3
2-16
Freescale Semiconductor Stereo Codec
2.12.1 Analog Input/Output
The 56858EVM uses jacks for line-level stereo input, line-level stereo output and stereo
headphone output. A National Semiconductor LM4880 provides the drive required for the use of
headphones. This device offers a THD, which is superior by a factor of two to the CS4218’s
on-chip headphone drive circuitry. The basic Analog codec connections are shown in
Figure 2-11.
CS4218
P4
Line-Level
Input
P5
RIN1
LOUTL
LIN1
LOUTR
Line-Level
Output
A
A
LM4880
P6
Headphone
Output
A
Figure 2-11. CODEC Analog Connections
2.12.2 Digital Interface
The serial interface of the codec transfers digital audio data and control data into and out of the
device. The ESSI port consists of independent transmitter and receiver sections and is used for
serial communication with the codec.
On the controller side, the Serial Transmit Data pin, STD0, is an output when data is being
transmitted to the codec. The Serial Receive Data pin, SRD0, is an input when data is being
received from the codec. These two pins are connected to the codec’s Serial Data Input, SDIN,
and Serial Data Output, SDOUT, pins.
The controller’s Transmit Serial Clock pin, SCK0, provides the serial bit rate clock for the ESSI
interface. It is connected to the CODEC’s Serial Port Clock pin, SCLK. Data is transmitted on the
rising edge of SCLK and is received on the falling edge of SCLK.
The controller’s GPIO PORT C Bit 4 pin, PC4, is programmed to control the codec’s Active Low
Reset signal, RESET.
The Serial Transmit Frame Sync pin, SC02, is programmed to control the codec’s Frame Sync
signal, FSYNC. This signal is sampled by SCLK, with a rising edge indicating a new frame is
Technical Summary, Rev. 3
Freescale Semiconductor
2-17
about to start. The FSYNC frequency is always the system’s sample rate. It may be an input to
the codec, or it may be an output from the codec in data mode.
The basic codec digital connections are shown in Figure 2-12, Table 2-9 and Table 2-10.
The codec’s MODE is set by the three MODE selection resistors, R42-R44. In the factory default
setting of MODE 4, the codec is set to be the master of the ESSI bus with its data word set at 32
bits per frame; i.e., 16 bits Left channel and 16 bits Right channel. The sample rate is selected on
the Sample Rate Selector switch S5; see Table 2-8 for selection options. Codec control
information is sent over a separate serial port using: PC3 as the Control Chip Select signal, CCS;
PE2 as the Control Data Input signal, CDIN; and PE3 as the Control Clock signal, CCLK.
CODEC Enable Logic
56858
CS4218
JG6
STD0
1
2
SDIN
SRD0
3
4
SDOUT
SCK0
5
6
SCLK
SC02
7
8
FSYNC
PC4
9
10
RESET
PC3
1
2
CCS
PE2
3
4
CDIN
PE3
5
6
CCLK
JG7
Figure 2-12. CS4218 Stereo Audio Codec
Table 2-9. ESSI Port Connector Description
JG6
Pin #
Controller Signal
Pin #
Codec Signal
1
STD0
2
SDIN
3
SRD0
4
SDOUT
5
SCK0
6
SCLK
7
SC02
8
FSYNC
9
PC4
10
RESET
DSP56858EVM User Manual, Rev. 3
2-18
Freescale Semiconductor Daughter Card Connectors
Table 2-10. GPIO Port Connector Description
JG7
Pin #
Controller Signal
Pin #
Codec Signal
1
PC3
2
CCS
3
PE2
4
CDIN
5
PE3
6
CCLK
2.13 Daughter Card Connectors
The EVM board contains two daughter card expansion connectors. One connector, J1, contains
the controller’s external memory bus signals. The other connector, J2, contains the controller’s
peripheral port signals.
2.13.1 Memory Daughter Card Expansion Connector
The controller’s external memory bus signals are connected to the Memory Daughter Card
Expansion connector, J1. Table 2-11 shows the port signal-to-pin assignments.
Table 2-11. Memory Daughter Card Connector Description
J1
Pin #
Signal
Pin #
Signal
1
A10
2
A11
3
A9
4
CS1
5
A8
6
A15
7
A7
8
A14
9
A20
10
A19
11
WR
12
A13
13
D0
14
A12
15
D1
16
D8
17
D2
18
D9
Technical Summary, Rev. 3
Freescale Semiconductor
2-19
Table 2-11. Memory Daughter Card Connector Description (Continued)
J1
Pin #
Signal
Pin #
Signal
19
GND
20
GND
21
D3
22
D10
23
D4
24
D11
25
D5
26
D12
27
D6
28
D13
29
A18
30
A17
31
D7
32
D14
33
CS0
34
D15
35
A0
36
RD
37
A1
38
A6
39
A16
40
GND
41
A2
42
A5
43
A3
44
A4
45
CS3
46
CS2
47
+3.3V
48
+3.3V
49
GND
50
GND
51
+5.0V
DSP56858EVM User Manual, Rev. 3
2-20
Freescale Semiconductor Daughter Card Connectors
2.13.2 Peripheral Daughter Card Expansion Connector
The controller’s peripheral port signals are connected to the Peripheral Daughter Card Expansion
connector, J2. Table 2-12 shows the port signal-to-pin assignments.
Table 2-12. Peripheral Daughter Card Connector Description
J2
Pin #
Signal
Pin #
Signal
1
CS0/PA0
2
CS1/PA1
3
CLKO
4
CS2/PA2
5
TIO0/PG0
6
TIO1/PG1
7
CS3/PA3
8
RSTOUT
9
TIO2/PG2
10
TIO3/PG3
11
NC
12
NC
13
GND
14
GND
15
SRD0/PC1
16
SRD1/PD1
17
SC01/PC4
18
SC11/PD4
19
SCK/PF2
20
SCK1/PD2
21
GND
22
GND
23
MOSI/PF1
24
SC10/PD3
25
MISO/PF0
26
SC12/PD5
27
GND
28
GND
29
SS/PF3
30
STD1/PD0
31
SC00/PC3
32
MODA/PH0
33
SC02/PC5
34
MODB/PH1
35
RESET
36
MODC/PH2
37
GND
38
GND
39
STD0/PC0
40
RXD1/PE2
41
SCK0/PC2
42
TXD1/PE3
Technical Summary, Rev. 3
Freescale Semiconductor
2-21
Table 2-12. Peripheral Daughter Card Connector Description (Continued)
J2
Pin #
Signal
Pin #
Signal
43
IRQB
44
RXD0/PE0
45
IRQA
46
TXD0/PE1
47
+3.3V
48
+3.3V
49
GND
50
GND
51
+5.0V
2.14 USB
A USB version 2.0 interface controller, NetChip NET2270, is connected to the 56858’s external
address/data bus via CS3. The NET2270 is clocked with a 30.00MHz crystal. This allows the
NET2270 interface controller to support the USB Full Speed (12 Mb/sec USB version 1.1) along
with the USB High Speed (480 Mb/sec USB version 2.0) bus transfer rates. The NET2270
provides a USB Tranceiver, Serial Interface Engine, USB Protocol Controller, Endpoint FIFOs,
Local Bus Interface and Configuration Registers. Refer to the USB diagram in Figure 2-13. The
USB Interface’s use of CS3 can be disabled by removing the jumper at JG11.
USB Interface
56858
LD0-LD15
D0-D15
J5
LA0-LA4
DM
2
RD
IOR
DP
3
WR
IRQA
IOW
IRQ
A0-A4
CS3
JG11
1
2
USB
B-TYPE
CS
Jumper Pin 1-2:
Enable USB
Jumper Removed:
Disable USB
Figure 2-13. Diagram of the USB Interface
DSP56858EVM User Manual, Rev. 3
2-22
Freescale Semiconductor Test Points
2.15 Host Interface Connector
The 56858EVM board contains a Host Interface connector. The HI connector, J4, provides the
signals present on the 56858’s HI port. Table 2-13 shows the HI connectors signal-to-pin
assignments.
Table 2-13. Host Interface Connector Description
J4
Pin #
Signal
Pin #
Signal
1
HD0
2
HD1
3
HD2
4
HD3
5
HD4
6
HD5
7
HD6
8
HD7
9
HA0
10
HA1
11
HA2
12
HRW
13
HDS
14
HCS
15
HREQ
16
HACK
17
+3.3V
18
GND
19
+3.3V
20
GND
2.16 Test Points
The 56858EVM board has a total of seven test points. Three digital GND test points are located
in corners of the board. The +5.0VA and AGND test points are located in the analog corner of the
board. The +1.8V and +3.3V test points are located in the power supply section of the board.
Technical Summary, Rev. 3
Freescale Semiconductor
2-23
DSP56858EVM User Manual, Rev. 3
2-24
Freescale Semiconductor Appendix A
56858EVM Schematics
56858EVM Schematics, Rev. 3
Freescale Semiconductor
Appendix A-1
DSP56858EVM User Manual, Rev. 3
Appendix A-2
Freescale Semiconductor 1
2
3
4
A
A
+3.3V
+3.3V
+1.8V
TDI
TDO
TCK
/TRST
TMS
/DE
MODA
MODB
M O DC
/CS0
/CS1
/CS2
/CS3
/RD
/WR
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
24
5
20
45
61
68
80
105
113
129
139
14
52
87
125
58
57
60
56
59
55
17
18
19
83
84
85
86
8
9
81
94
95
96
97
98
120
121
122
123
124
137
138
142
143
144
10
11
12
13
29
30
31
32
48
49
50
51
63
64
65
66
75
76
77
78
79
U1
VDDA
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDDC1
VDDC2
VDDC3
VDDC4
TDI
TDO
TCK
TRST
TMS
DE
MISO/PF0
IRQA
IRQB
XTAL
EXTAL
CLKOUT
TIO0/PG0
26
7
21
47
62
70
82
106
115
130
141
16
54
89
127
39
38
93
116
117
118
119
33
34
35
40
41
42
43
44
90
91
92
114
112
111
110
99
100
101
102
103
104
131
132
133
134
135
136
108
107
74
73
1
2
3
4
22
23
27
28
37
/RESET
/RSTOUT
HRW
/HDS
/HCS
/HREQ
/HACK
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HA0
HA1
HA2
TIO0
TIO1
TIO2
TIO3
STD1
SRD1
S C K1
S C 10
S C 11
S C 12
STD0
SRD0
S C K0
S C 00
S C 01
S C 02
TXD1
RXD1
TXD0
RXD0
MISO
MOSI
SCK
/SS
/IRQA
/IRQB
XTAL
EXTAL
C L KO
C
C
SC12
SC11
SC10
SCK1
SRD1
STD1
PD5
PD4
PD3
PD2
PD1
PD0
B
Size
Title
13
11
9
5
3
1
2
4
6
8
10
12
GREEN LED
L E D6
YELLOW LED
L E D5
RED LED
L E D4
GREEN LED
L E D3
YELLOW LED
L E D2
RED LED
L E D1
270
R80
270
R79
270
R78
270
R77
270
R76
270
R75
+3.3V
DSP56858EVM.DSN
D
Date: Thursday, January 10, 2002
Document
Number
E
E
of
11
1.2
Rev.
FAX: (480) 413-2510
Sheet 1
(480) 413-5090
2100 East Elliot Road
Tempe, Arizona 85284
DSP Standard Products Division
Designer: DSPD Design
DSP56858 Processor and DEBUG LEDS
M C 74AC04AD
U11F
M C 74AC04AD
U 1 1E
M C 74AC04AD
U11D
M C 74AC04AD
U11C
M C 74AC04AD
U 1 1B
M C 74AC04AD
U 1 1A
D
Figure A-1. 56858 Processor and Debug LEDs
B
VSSA
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSSC1
VSSC2
VSSC3
VSSC4
RESET
RSTOUT
HRW/HRD/PB11
HDS/HWR/PB12
HCS/PB13
HREQ/HTRQ/PB14
HACK/HRRQ/PB15
HOST
HD0/PB0
HD1/PB1
HD2/PB2
HD3/PB3
HD4/PB4
HD5/PB5
HD6/PB6
HD7/PB7
HA0/PB8
HA1/PB9
HA2/PB10
TIO3/PG3
TIMER TIO1/PG1
TIO2/PG2
ESSI1
STD1/PD0
SRD1/PD1
SCK1/PD2
SC10/PD3
SC11/PD4
SC12/PD5
SC01/PC4
SC02/PC5
ESSI0 SSCCK0 00 // PP CC 23
STD0/PC0
SRD0/PC1
SCI1 RT XX DD 11 // PP EE 23
SCI0 RT XX DD 00 // PP EE 01
SS/PF3
SPI MSOCSKI // PP FF 21
D S P 56858FV80
MODA/PH0
MODB/PH1
MODC/PH2
CS0/PA0
CS1/PA1
CS2/PA2
CS3/PA3
RD
WR
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B
1
2
3
4
56858EVM Schematics, Rev. 3
Freescale Semiconductor
Appendix A-3
1
2
3
4
R92
10K
Vcc/2
R91
10K
+3.3V
A
Y1
4.00MHz
A
+3.3V
3
2
3
2
DS1818
1
RST
DS1818
GND
Vcc
U20
1
1
3
2
2
/POR
A
Size
Title
/POR
XTAL
EXTAL
R71
10K
R72
10K
R73
10K
S4
DSP56858EVM.DSN
C
Date: Thursday, January 10, 2002
Document
Number
2
4
6
D
D
MODC
MODB
MODA
/IRQB
/IRQA
470K
R74
470K
R70
470K
R69
E
+3.3V
E
of
11
1.2
Rev.
FAX: (480) 413-2510
Sheet 2
(480) 413-5090
2100 East Elliot Road
Tempe, Arizona 85284
DSP Standard Products Division
MODA
MODB
MODC
C24
0.1uF
R67
10K
+3.3V
C23
0.1uF
R66
10K
+3.3V
Designer: D S P D D e s i g n
Boot MODE
Select
1
3
5
S3
IRQB PUSHBUTTON
S2
IRQA PUSHBUTTON
RESET, CLOCK, BOOT MODE & IRQS
C
Figure A-2. Reset, Clock, Boot Mode & IRQs
B
C25
0.1uF
R68
10K
DNP
+3.3V
3
1
JG4
OSC BYPASS
RESET PUSHBUTTON
S1
12.288MHZ
R8
10M
Vcc/2
JG3
B
1
2
3
4
DSP56858EVM User Manual, Rev. 3
Appendix A-4
Freescale Semiconductor 1
2
3
4
/CS0
A
1
2
JG1
A
C
R62
1K
/RD
/WR
U2
VSS
VSS
VDD
VDD
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
GS72116ATP-7
OE
WE
CE
LB
UB
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
12
34
11
33
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
B
NC
SRAM DISABLE
A
Size
+3.3V
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
/ECS2
/ECS1
10K
R65
10K
R64
+3.3V
/CS1
/CS2
2
4
JG2
1
3
5
4
3
2
1
44
43
42
27
26
25
24
21
20
19
18
22
U3
VSS
VSS
VDD
VDD
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
GS72116ATP-7
OE
WE
CE
LB
UB
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
12
34
11
33
7
8
9
10
13
14
15
16
29
30
31
32
35
36
37
38
NC
NC
DSP56858EVM.DSN
C
Date: Sunday, October 06, 2002
Document
Number
Sheet 3
E
of
11
1.2
Rev.
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
(480) 413-5090
Designer: DSPD Design
D
NC
NC
3-4
3-4
+3.3V
DSP Standard Products Division
SRAM DISABLE
1-2
1-2
SRAM WORD ENABLE
SRAM LOWER BYTE ENABLE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
JG2
SRAM UPPER BYTE ENABLE
OPTION
CS1/CS2 ENABLE JUMPER
R61
1K
41
17
6
/ E C S 1 39
/ E C S 2 40
/RD
/WR
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
P R O G RAM [WORD] (CS0) and DATA [BYTE] (CS1/CS2) SRAM MEMORY
1-2
SRAM ENABLE
Title
JG1
OPTION
CS0 ENABLE JUMPER
R63
1K
41
17
6
39
40
5
4
3
2
1
44
43
42
27
26
25
24
21
20
19
18
22
E
128Kx16-bit Data Memory (CS1/CS2)
D
Figure A-3. Program [Word] (CS0) & Data [Byte] (CS1/CS2) SRAM Memory
/ECS0
R60
10K
+3.3V
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
128Kx16-bit Program Memory (CS0)
B
1
2
3
4
56858EVM Schematics, Rev. 3
Freescale Semiconductor
Appendix A-5
1
2
3
4
A
A
+3.3V
HD0
HD2
HD4
HD6
HA0
HA2
/HDS
/HREQ
/HACK
/HREQ
/HCS
/HDS
HRW
J4
2
4
6
8
10
12
14
16
18
20
10K
10K
10K
10K
10K
+3.3V
B
HD1
HD3
HD5
HD7
HA1
HRW
/HCS
/HACK
A
Size
Title
3
5
7
MISO
MOSI
SCK
JG10
8
6
4
2
8
1
2
EE_SO
EE_SI
EE_SCK
DSP56858EVM.DSN
C
Date: Thursday, January 10, 2002
Document
Number
U4
GND
WP
R56
R54
10K
10K
7
5
3
6
+3.3V
/WP
/RST
+3.3V
E
E
of
11
1.2
Rev.
FAX: (480) 413-2510
Sheet 4
(480) 413-5090
2100 East Elliot Road
Tempe, Arizona 85284
DSP Standard Products Division
/WP
Designer: D S P D D e s i g n
D
VCC
RESET
AT45DB011B-SC
SCK
SI
SO
CS
/RST
4
/EE_CS
D
HOST Port and SPI Serial 1M EEPROM MEMORY
EEPROM Enable
1
/SS
C
Figure A-4. HOST Port and SPI Serial 1M-bit Serial EEPROM Memory
R59
R58
R57
R55
R53
HOST PORT
1
3
5
7
9
11
13
15
17
19
B
1
2
3
4
DSP56858EVM User Manual, Rev. 3
Appendix A-6
Freescale Semiconductor 1
2
3
4
1 - 2
RS-232 DISABLE
A
N/C
TXD0
RXD0
RS-232 ENABLE
RS-232 ENABLE
A
1
2
JG9
JG8
1
3
A
Size
Title
/EN
1
1
1
1
1
T2IN
T3IN
22
23
20
19
18
17
16
15
14
13
12
2
24
1
28
GND
V+
V-
VCC
INVALID
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T2OUT
T3OUT
21
4
5
6
7
8
9
10
11
1
T8
R2IN
R3IN
R4IN
R5IN
T1
T2
27
1
1
C21
1.0 uF
3
25
C20
1.0 uF
26
+3.3V
DSP56853EVM.DSN
C
Date: Thursday, January 10, 2002
Document
Number
SCI PORT, RS-232 AND CONNECTOR
MAX3245EEAI
FORCEOFF
FORCEON
R2OUTB
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
T1IN
T2IN
T3IN
C2-
C1C2+
C1+
U5
C
P3
DCD
DSR
TXD
CTS
RXD
RTS
DTR
RI
GND
D
R5IN
R4IN
R3IN
R2IN
T3IN
T2IN
/EN
E
R52
R51
R50
R49
R48
R46
R45
1K
1K
1K
1K
1K
1K
1K
+3.3V
E
of
11
1.2
Rev.
FAX: (480) 413-2510
Sheet 5
(480) 413-5090
2100 East Elliot Road
Tempe, Arizona 85284
DSP Standard Products Division
SCI
RS-232
CONNECTOR
1
6
2
7
3
8
4
9
5
Designer: D S P D D e s i g n
D
Figure A-5. SCI Port, RS-232 and Connector
B
R47
1K
T4
T5
T6
T7
T3
C22
1.0 uF
C19
1.0 uF
TX
RX
+3.3V
2
4
B
1
2
3
4
56858EVM Schematics, Rev. 3
1
2
3
4
Line-Input
Stereo Jack
1/8"
P4
3
11
10
2
1
A
+3.3V
TIP_IN
RING_IN
A
SC00
R X D1
TXD1
S T D0
SRD0
SCK0
SC02
SC01
1K
R32
JG7
1
3
5
GND
EN OUT
3
2
4
6
2
4
6
8
10
/CCS
CDIN
CCLK
M O D E3
DNP
M O D E2
M O D E1
NOTE: DNP - Do Not Populate
CODEC Mode Select
0 Ohm
R44
0 Ohm
R43
0 Ohm
R42
1K
R33
12.288MHZ
C4
470pF
C2
470pF
CODEC_SDIN
C O D E C _ S D O UT
C O D E C _ S C LK
CODEC_FSYNC
/ C O D E C _ R E SET
SERIAL MODE 4 SELECTED
MASTER, 32BITS PER FRAME
PC3
PE2
PE3
PC4
JG6
1
3
5
7
9
U7
VCC
1 2 . 2 8 8 M HZ OSC
2
1
4
R23
5.62K
1%
R20
5.62K
1%
+ 3 .3V
5.62K
1%
R25
5.62K
1%
R19
C6
0.33uF
C1
0.33uF
B
B
14
C11
0.47uF
S5
1
1
1
0
1
43
42
16
15
8.00
9.60
12.00
16.00
19.20
C13
0.1uF
C
LOUT
ROUT
+3.3V
MODE3
MODE2
MODE1
MF6
MF7
MF8
MF5
/CCS
CCLK
CDIN
MF1
L O UT
ROUT
+
1uF
25V
C16
1uF
25V
C14
C12
4 7 uF
10VDC
C7
0.0022uF
R40
C18
1uF
25V
20.0K
1%
R41
20.0K
1%
B
Size
Title
5
3
2
6
GND
VDD
OUT_A
OUT_B
LM4880M
SHUTDN
BYPASS
IN_A
IN_B
U8
2 0 .0K 1%
R39
2 0 .0K 1%
R37
R27
3 9 .2K
1%
D
4
8
1
7
+5.0VA
R28
39.2K
1%
TIP_OUT
RING_OUT
3
11
10
2
1
DSP56858EVM.DSN
D
Date: Thursday, January 10, 2002
Document
Number
SSI 16-BIT STEREO CODEC
SHUTDN
BYPASS
C8
0.0022uF
C5
1uF
25V
C3
1uF
25V
Figure A-6. SSI 16-Bit Stereo Codec
1
1
0
1
0
1
1
0
1
0
1
0
0
32.00
1
0
24.00
48.00
0
0
0
MF8
GND
VDD
REFGND
REFBY
35
26
23
28
25
24
32
30
29
33
34
10
9
FS (KHZ)
5
3
1
WF6
WF7
WF8
MF5
MF4
MF3
MF2
MF1
LOUT
ROUT
SWODE3
SWODE2
SWODE1
C S 4218-KQ
GNDA
VDDA
Sample Select
6
4
2
MF7
MF6
MF7
MF8
17
18
CLKIN
RESET
PDN
SSYNC
SCLK
SDOUT
SDIN
REFBUF
LIN2
RIN2
LIN1
RIN1
0
MF6
+5.0VA
41
40
7
39
38
37
36
22
C10
0.47uF
1 2 .288MHZ
/ C O D E C _ R E SET
/PDN
CODEC_FSYNC
C O D E C _ S C LK
C O D E C _ S D O UT
CODEC_SDIN
20
C9
0.47uF
21
19
U6
C
+
+
Freescale Semiconductor
Appendix A-7
TIP_PHN
RING_PHN
1/8"
Headphone Out
Stereo Jack
P6
10K
10K
R35
10K
R34
10K
R31
10K
R30
10K
R29
10K
R26
10K
R24
10K
R22
MF1
10K
R38
10K
SHUTDN R36
MF5
/CCS
MF8
MF7
MF6
MODE3
MODE2
MODE1
/PDN
R21
+3.3V
E
of
11
1.2
Rev.
FAX: (480) 413-2510
Sheet 6
(480) 413-5090
2100 East Elliot Road
Tempe, Arizona 85284
DSP Standard Products Division
3
11
10
2
1
Designer: DSPD Design
C17
4 7 uF
10VDC
C15
4 7 uF
10VDC
1/8"
Line Out
Stereo Jack
P5
E
1
2
3
4
DSP56858EVM User Manual, Rev. 3
1
2
3
4
A
A
P_RESET
5.1K
R14
DB25M
13
12
11
10
9
8
7
6
5
4
3
2
1
B
E
2N2222A
C
B
Q1
2N2222A
/ J _ R E SET
R13
5.1K
+3.3V
P O R T _ C O N NECT
P O RT_TDO
P O R T _ VCC
P O R T _DE
/ P O RT_TRST
P O R T _ TDI
P O RT_TCK
PORT_TMS
P O RT_RESET
/J_TRST
/POR
/ J _ R E SET
10
9
2
1
7 4 AC00
U10C
7 4 AC00
U10A
51 Oh m
R9
51 Oh m
R7
270
R5
270
R4
270
R3
270
R2
270
R1
C
8
3
JG5
+ 3 .3V
13
12
5
4
7 4 AC00
U10D
7 4 AC00
U 1 0B
B
Size
Title
11
6
R10
5.1K
1
/TRST
/RESET
T11
20
1
19
3
5
7
11
8
6
4
2
GND
2A4
2A3
2A2
2Y1
1Y4
1Y3
1Y2
1Y1
TCK
TDO
TDI
/DE
10
17
15
13
9
12
14
16
18
+ 3 .3V
MC74LCX244D W
VCC
1G
2G
2Y4
2Y3
2Y2
2A1
1A4
1A3
1A2
1A1
U9
D
13
11
9
7
5
3
1
J3
14
12
10
8
6
4
2
KEY
/J_TRST
TMS
/J_TRST
P _ DE
/DE
TDO
DSP56858EVM.DSN
D
Date: Thursday, January 10, 2002
Document
Number
47K
R12
5.1K
R6
5.1K
R16
47K
R11
+3.3V
(480) 413-5090
Designer: DSPD Design
E
Sheet 7
of
11
1.2
Rev.
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
DSP Standard Products Division
JTAG Connector
/ J _ R E SET
+3.3V
TDO
P_DE
/J_TRST
TDI
TCK
TMS
P_RESET
E
PARALLEL JTAG HOST TARGET INTERFACE AND JTAG CONNECTOR
On-Board
Host Target Interface
Disable
Parallel JTAG Interface
C
Figure A-7. Parallel JTAG Host Target Interface and JTAG Connector
R15
47K
25
24
23
22
21
20
19
18
17
16
15
14
P1
P O R T _ I DENT
B
2
1
Appendix A-8
Freescale Semiconductor 1
2
3
4
56858EVM Schematics, Rev. 3
Freescale Semiconductor
Appendix A-9
1
2
3
4
A
GND
A
D3
D4
D5
D6
A18
D7
/CS0
A0
A1
A16
A2
A3
/CS3
A10
A9
A8
A7
A20
/WR
D0
D1
D2
GND
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
GND
GND
GND
GND
GND
GND
/DS
+3.3V
STD0
SCK0
/IRQB
/IRQA
/SS
SC00
SC02
/RESET
MOSI
MISO
SRD0
SC01
SCK
/CS0
CLKO
TIO0
/CS3
TIO2
GND
GND
GND
GND
GND
DSP56858EVM.DSN
C
Date: Thursday, January 10, 2002
Document
Number
D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
J2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
GND
GND
GND
GND
GND
+3.3V
PE2
PE3
PE0
PE1
PD0
PH0
PH1
PH2
PD3
PD5
PD1
PD4
PD2
PG3
PA1
PA2
PG1
Sheet 8
E
of
11
1.2
Rev.
FAX: (480) 413-2510
2100 East Elliot Road
Tempe, Arizona 85284
(480) 413-5090
Designer: D S P D D e s i g n
D
RXD1
TXD1
RXD0
TXD0
STD1
MODA
MODB
MODC
SC10
SC12
SRD1
SC11
SCK1
/CS1
/CS2
TIO1
/RSTOUT
TIO3
E
DSP Standard Products Division
Daughter Peripheral Port Connector
+5.0V
+3.3V
PC0
PC2
PF3
PC3
PC5
PF1
PF0
PC1
PC4
PF2
PG0
PA3
PG2
PA0
D A U G H T E R CARD EXPANSION CONNECTORS
A5
A4
/CS2
D10
D11
D12
D13
A17
D14
D15
/RD
A6
A11
/CS1
A15
A14
A19
A13
A12
D8
D9
C
Figure A-8. Daughter Card Expansion Connectors
B
A
Size
Title
Daughter Address/Data Connector
+5.0V
+3.3V
GND
/PS
GND
GND
GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
J1
B
1
2
3
4
DSP56858EVM User Manual, Rev. 3
1
2
3
4
GND
+3.3V
+3.3V
A
A
L7
FERRITE BEAD
L9
FERRITE BEAD
L8
FERRITE BEAD
+3.3VD
/CS3
R90
C70
0.01uF
C64
0.01uF
9.09K 1%
R89
10K
2
+
+
RREF
/ECS3
+3.3VD
+3.3VA
+3.3VD
+3.3VD
/ R E S ET
/RD
/WR
ANALOG GND
C69
4 7 uF
10VDC
+3.3VA
DIGITAL GND
C63
4 7 uF
10VDC
USB SELECT
1
J G 11
A0
A1
A2
A3
A4
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
8
7
6
5
4
14
15
16
18
20
21
22
23
25
26
27
28
30
31
33
34
B
RREF
57
17
32
10
42
62
51
3
36
13
49
37
43
44
45
/ECS3 46
B
U15
+3.3VA
+3.3VD
NET2270
C71
0.01uF
C65
0.01uF
54
60
63
19
24
29
9
41
61
50
52
38
39
40
1
2
64
47
C72
0.1uF
C66
0.01uF
/IRQA
R84
1
T9
35.7 1%
R85
35.7 1%
Y2
30.00MHz
1.5K
R86
C L O C K _OUT
C L K O UT
35
12
VBUS
48
CLKIN
RPU
53
11
RSDP
RSDM
55
58
56
59
AGND
VSS1
VSS2
VSS3
VSSIO1
VSSIO2
VSSIO3
VSSC1
VSSC2
PVSS
AVSS1
AVSS2
DACK
EOT
ALE
TEST1
TEST2
TEST3
IRQ
LCLKO
XOUT
XIN
VBUS
RPU
RSDP
DM
DP
RSDM
C
C67
0.1uF
T10
C61
C68
0.1uF
1 2 pF
C62
1 2 pF
B
Size
Title
R87
1M
D
D
S-L
1
2
3
4
S-R
J5
E
E
of
11
1.2
Rev.
FAX: (480) 413-2510
Sheet 9
(480) 413-5090
2100 East Elliot Road
Tempe, Arizona 85284
DSP Standard Products Division
Designer: DSPD Design
USB B-TYPE
DSP56858EVM.DSN
C60
0.01uF
USBCGND
USBVCC
DM
DP
USBLGND
USBCGND
Date: Thursday, January 10, 2002
Document
Number
USB 2.0 Controller Interface
42 OHM
42 OHM
R88
47K
L6
FERRITE BEAD
L5
FERRITE BEAD
Figure A-9. USB 2.0 Controller Interface
VDD
VDDIO1
VDDIO2
VDDC1
VDDC2
PVDD
AVDD
SMC
DMARD
DMAWR
RREF
DREQ
RESET
IOR
IOW
CS
LA0
LA1
LA2
LA3
LA4
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15
C
1
Appendix A-10
Freescale Semiconductor 1
2
3
4
56858EVM Schematics, Rev. 3
Freescale Semiconductor
Appendix A-11
1
2
3
4
3
L3
D4
A
+5.0V
+ 1
FERRITE BEAD
L4
FERRITE BEAD
1
2
TB1
LED7
R83
270
+3.3V
+
-
2 -
1
POWER GOOD LED
+5.0V
+5VDC
INPUT
2
P2
EXTERNAL POWER INPUT
7-12VDC/AC
A
3
4
+5.0VA
1
3
2
3
MC33269
1
4
B
5.0V, 3.3V
& Adj
REGULATOR
C58
0.1uF
+ C53
470uF
16VDC
B
VOUT
VOUT
2
A
C54
0.1uF
+
3
3
C
VOUT
VOUT
MC33269DT-ADJ
GND
VIN
U14
FM4001
D3
DSP56F858EVM.DSN
1
VOUT
VOUT
MC33269DT-3.3
GND
VIN
Date: Thursday, January 10, 2002
Document
Number
P O W ER SUPPLIES
C59
47uF
10VDC
C56
0.1uF
1
Figure A-10. Power Supplies
Size
Title
4
U13
FM4001
FM4001
+5.0V
D2
D1
MC33269DT-5
GND
VIN
U12
C
R81
243
1%
D
L1
+
+
VCC
C57
47uF
10VDC
C55
47uF
10VDC
E
E
of
11
1.2
Rev.
FAX: (480) 413-2510
Sheet 1 0
(480) 413-5090
2100 East Elliot Road
Tempe, Arizona 85284
DSP Standard Products Division
Rlow = 107 1% for 1.8V
Rlow = 243 1% for 2.5V
Rlow = 127 1% for 1.9V
+1.8V
+3.3V
Vout = 1.25( 1 + (Rlow/Rhigh))
FERRITE BEAD
L2
FERRITE BEAD
Designer: D S P D D e s i g n
Rlow
R82
107
1%
Rhigh
4
2
4
2
D
1
2
3
4
DSP56858EVM User Manual, Rev. 3
1
2
3
4
C26
0.01uF
+3.3V
C38
0.01uF
+3.3V
+3.3V
A
C49
0.01uF
+3.3V
CS4218
+3.3V
GS72116
+3.3V
C50
0.1uF
C39
0.1uF
C27
0.1uF
+3.3V
C29
0.1uF
+3.3V
OSC
+3.3V
C51
0.01uF
C40
0.01uF
C41
0.1uF
+3.3V
B
C52
0.1uF
+5.0VA
+3.3V
C31
0.1uF
A
+5.0VA
TP2
+3.3V
+3.3V
C44
0.1uF
74AC00
C34
0.01uF
C
C35
0.1uF
C45
0.01uF
D
+3.3V
1
1
1
DNP
D
TP4
C48
0.1uF
E
of
11
1.2
Rev.
FAX: (480) 413-2510
Sheet 1 1
(480) 413-5090
2100 East Elliot Road
Tempe, Arizona 85284
DSP Standard Products Division
+1.8V
TEST POINT
TP5
+1.8V
C47
0.1uF
+3.3V
Host Port
E
+3.3V
+3.3V
74LCX244
C37
0.1uF
+3.3V
TEST POINT
C46
0.1uF
MAX3245
Designer: D S P D D e s i g n
TP7
TP6
TP1
C36
0.01uF
+1.8V
Near VDDA
+1.8V
GROUND
TEST POINT
+3.3V
DS1818
+1.8V
D S P 5 6 8 58EVM.DSN
TP3
ANALOG GROUND
TEST POINT
C43
0.1uF
C33
0.1uF
+1.8V
Date: Thursday, January 10, 2002
Document
Number
BYPASS CAPS
+5.0VA
TEST POINT
C42
0.01uF
C32
0.01uF
+1.8V
74AC04
+1.8V
Figure A-11. Power Supplies
Size
Title
+3.3V
AT45DB011
C30
0.01uF
LM4880
+3.3V
GS72116
C28
0.01uF
+3.3V
DSP56858
1
C
1
B
1
A
1
Appendix A-12
Freescale Semiconductor 1
2
3
4
Appendix B
56858EVM Bill of Material
Qty
Description
Ref. Designators
Vendor Part #s
Integrated Circuits
1
56858
U1
2
GS72116
1
AT45DB011
U4
Atmel, AT45DB011B-SC
1
MAX3245
U5
Maxim, MAX3245EEAI
1
CS4218
U6
Crystal Semiconductor, CS4218-KQ
1
12.288MHz OSC
U7
Epson, SG-531P-12.288MC
1
LM4880
U8
National Semiconductor, LM4880M
1
74LCX244
U9
ON Semiconductor, MC74LCX244ADW
1
74AC00
U10
Fairchild, 74AC00SC
1
74AC04
U11
ON Semiconductor, MC74AC04AD
1
+5.0V Voltage Regulator
U12
ON Semiconductor, MC33269DT-5
1
+3.3V Voltage Regulator
U13
ON Semiconductor, MC33269DT-3.3
1
+1.8V Voltage Regulator
U14
ON Semiconductor, MC33269DT-ADJ
1
NET2270
U15
NetChip, NET2270
1
DS1818
U20
Dallas Semiconductor, DS1818
U2, U3
Freescale, DSP56858FV120
GSI, GS72116ATP-7
Resistors
12
270 :
R1 - R5, R75 - R80, R83
SMEC, RC73L2A270OHMJT
5
5.1K :
R6, R10, R13, R14, R16
SMEC, RC73L2A5.1KOHMJT
2
51 :
R7, R9
SMEC, RC73L2A51OHMJT
56858EVM Bill of Material, Rev. 3
Freescale Semiconductor
Appendix B-1
Qty
Description
Ref. Designators
Vendor Part #s
Resistors (Continued)
1
10M :
R8
SMEC, RC73L2A10MOHMJT
4
47K :
R11, R12, R15, R88
SMEC, RC73L2A47KOHMJT
4
5.62K :
R19, R20, R23, R25
SMEC, RC73L2A5.62KOHMFT
29
10K :
2
39.2K :
13
1K :
4
20.0K :
2
:
R42, R43
SMEC, RC73JP2A
0
:
R44
SMEC, RC73JP2A
0
10K :
R68
SMEC, RC73L2A10KOHMJT
3
470K :
R69, R70, R74
SMEC, RC73L2A470KOHMJT
1
:
R81
SMEC, RC73L2A243OHMFT
1
107 :
R82
SMEC, RC73L2A107OHMFT
2
35.7 :
R84, R85
SMEC, RC73L2A35.7OHMFT
1
1.5K :
R86
SMEC, RC73L2A1.5KOHMJT
1
1M :
R87
SMEC, RC73L2A1MOHMJT
1
9.09K :
R89
SMEC, RC73L2A9.09KOHMFT
R21, R22, R24, R26, R29-R31,
R34-R36, R38, R53-R60,
R64-R67, R71-R73, R90-R92
R27, R28
R32, R33, R45-R52, R61-R63
R37, R39-R41
SMEC, RC73L2A10KOHMJT
SMEC, RC73L2A39.2KOHMFT
SMEC, RC73L2A1KOHMJT
SMEC, RC73L2A20.0KOHMFT
Inductors
4
1.0mH FERRITE BEAD
L1 - L4
Panasonic, EXC-ELSA35V
5
FERRITE BEAD
L5 - L9
TOKO, FLSM2520-1R0J
LEDs
2
Red LED
LED1, LED4
Hewlett-Packard, HSMS-C650
2
Yellow LED
LED2, LED5
Hewlett-Packard, HSMY-C650
3
Green LED
LED3, LED6, LED7
Hewlett-Packard, HSMG-C650
DSP56858EVM User Manual, Rev. 3
Appendix B-2
Freescale Semiconductor
Qty
Description
Ref. Designators
Vendor Part #s
Diodes
1
S2B-FM401
D1
Vishay, DL4001DICT
1
+50V 1A BRIDGE RECT
D2
DIODES, DF02S
Capacitors
2
0.33PF
C1, C6
SMEC, MCCE334K3NR-T1
2
470pF
C2, C4
SMEC, MCCE471J2NO-T1
9
1.0PF, +25V DC
C3, C5, C14, C16, C18-C22
SMEC, MCCE105K3NR-T1
2
0.0022PF
C7, C8
SMEC, MCCE222K2NR-T1
3
0.47PF
C9-C11
SMEC, MCCE474K3NR-T1
8
47PF, +16V DC
C12, C15, C17, C55, C57, C59,
C63, C69
ELMA, RV2-16V470M-R
25
0.1PF
C13, C23-C25, C27, C29, C31,
C33, C35, C37, C39, C41, C43,
C44, C46-C48, C50, C52, C54,
C56, C58, C67, C68, C72
SMEC, MCCE104K2NR-T1
18
0.01PF
C26, C28, C30, C32, C34, C36,
C38, C40, C42, C45, C49, C51,
C60, C64-C66, C70, C71
SMEC, MCCE103K2NR-T1
1
470PF, +16V DC
C53
ELMA, RV-16V471MH10R
2
15pF
C61, C62
SMEC, MCCE150J2NO-T1
Jumpers
4
1 u 2, 2mm Header
JG1, JG5, JG9, JG11
SAMTEC, TMM-102-02-S-S
2
2 x 2, 2mm Header
JG2, JG8
SAMTEC, TMM-102-02-S-D
2
3 u 1, 2mm Header
JG3, JG4
SAMTEC, TMM-103-02-S-S
1
5 x 2, 2mm Header
JG6
SAMTEC, TMM-105-02-S-D
1
3 x 2, 2mm Header
JG7
SAMTEC, TMM-103-02-S-D
1
4 u 2, 2mm Header
JG10
SAMTEC, TMM-104-02-S-D
56858EVM Bill of Material, Rev. 3
Freescale Semiconductor
Appendix B-3
Qty
Description
Ref. Designators
Vendor Part #s
Test Points
4
Black Test Point
TP1, TP3, TP6, TP7
Keystone, 5001
1
Red Test Point
TP2
Keystone, 5000
1
White Test Point
TP4
Keystone, 5002
1
Yellow Test Point
TP5
Keystone, 5004
Crystals
1
4.00MHz Crystal
Y1
CTS, ATS04ASM-T
1
30.00MHz Crystal
Y2
Epson, MA-306 30.000M-C2
Connectors
1
DB25M Connector
P1
AMPHENOL, 617-C025P-AJ121
1
2.1mm coax
Power Connector
P2
Switchcraft, RAPC-722
1
DE9S Connector
P3
AMPHENOL, 617-C009S-AJ120
3
1/8” Stereo Jack
P4 - P6
2
51-Pin HD Connector
1
7 x 2 Bergstick
J3
SAMTEC, TSW-107-07-S-D
1
10 x 2 RT Bergstick
J4
SAMTEC, TSW-110-07-S-D-RT
1
Type B USB
J5
Mill-Max, 897-30-004-90-000000
1
2-Pin Terminal Block
J1, J2
TB1
Switchcraft, 35RAPC4BHN2
BERG, 91930-21151
On-Shore Technology, ED500/2DS
Switches
3
SPST Pushbutton
S1 - S3
Panasonic, EVQ-PAD05R
2
3-Position DIP SW
S4, S5
CTS, 209-3LPST
Transistors
1
2N2222A
Q1
ZETEX, FMMT2222ACT
Miscellaneous
20
2mm Shunt
SH1 - SH20
4
Rubber Feet
RF1 - RF4
Samtec, 2SN-BK-G
3M, SJ5018BLKC
DSP56858EVM User Manual, Rev. 3
Appendix B-4
Freescale Semiconductor
INDEX
C
F
Clock Source 2-7
Codec Preface-ix
Connectors
Host Interface 2-23
FSRAM 2-3, 2-4
D
Daughter Card Connectors 2-19
Daughter Card Expansion interface 2-1
Debugging 2-8
DIP Preface-ix
DSP56858EVM
+12.0V DC power supply 2-15
1 M-bit Serial EEPROM/Data FLASH 2-1
128Kx16-bit of memory 2-1
16-bit +1.8V/+3.3V Digital Signal Processor 2-1
16-bit stereo codec interface 2-1
4.00MHz crystal oscillator 2-1
Codec sample rate selector 2-1
connecting to the PC 1-4
Development Card 2-1
external oscillator frequency input 2-1
FSRAM 2-1
GPIO compatible peripheral 2-2
Host Interface Connector 2-2
interconnection diagram 1-4
ISSI compatible peripheral 2-2
JTAG port interface 2-1
Memory Daughter Caard Expansion Connector 2-2
On-board power regulation 2-2
Parallel JTAG Host Target Interface 2-1
power connection cable connection 1-4
real-time debugging 2-8
RS-232 interface 2-1
SCI compatible peripheral 2-2
SPI compatible peripheral 2-2
test points 2-23
USB interface 2-2
E
G
GPIO Preface-ix
H
HI Preface-ix
Host Parallel Interface Connector 2-9
Host Target Interface 2-9
I
IC Preface-ix
J
JTAG Preface-ix, 1-1, 2-1
connector 2-10
Jumper Group
JG1 1-3
JG10 1-3
JG11 1-3
JG2 1-3
JG3 1-3
JG4 1-3
JG5 1-3
JG6 1-3
JG7 1-3
JG8 1-3
JG9 1-3
Jumper Options 1-3
L
LED Preface-ix
LQFP Preface-ix
M
MPIO Preface-ix
EEPROM Preface-ix
EOnCE Preface-ix
ESSI Preface-ix
EVM Preface-ix
O
Operating Mode 2-8
Index, Rev. 3
Freescale Semiconductor
Index-1
P
PCB Preface-ix
PLL Preface-ix
power supply, external 1-4
R
RAM Preface-ix
ROM Preface-ix
RS-232
interface 2-1, 2-6
level converter 2-6
schematic diagram 2-6
RS-232 Serial Communications 2-6
S
SCI Preface-ix
SPI Preface-x
SRAM Preface-x
external data 2-1
external program 2-1
SSI Preface-x
stereo 16-bit codec interface 2-1
Stereo headphone interface 2-1
T
THD Preface-x
U
USB Preface-x, 2-22
schematic diagram 2-22
W
WS Preface-x
DSP56858EVM User Manual, Rev. 3
Index-2
Freescale Semiconductor
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Freescale Semiconductor products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other
application in which the failure of the Freescale Semiconductor product could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor,
Inc. All other product or service names are the property of their respective owners.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005. All rights reserved.
DSP56858EVMUM
Rev. 3
07/2005