Download V850E2/ML4 CPU Board R0K0F4022C000BR User`s Manual

User’s Manual
32
R0K0F4022C000BR
V850E2/ML4 CPU Board User's Manual
Renesas Microcomputer
V850E2/ML4 Microcontroller
Rev. 1.00
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corporation without notice. Please review the latest information published by
Renesas Electronics Corporation through various means, including the Renesas Electronics
Corporation website (http://www.renesas.com).
www.renesas.com
Rev. 1.00
May 2012
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you
or third parties arising from the use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of
third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No
license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of
Renesas Electronics or others.
4.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration,
modification, copy or otherwise misappropriation of Renesas Electronics product.
5.
Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The
recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below.
“Standard”:
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to
human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property
damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas
Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any
application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred
by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas
Electronics.
6.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas
Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation
of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by
you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility
of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive.
Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws
and regulations.
9.
Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose
manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use
Renesas Electronics products or technology described in this document for any purpose relating to military applications or use
by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas
Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this
document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of
unauthorized use of Renesas Electronics products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas
Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document
or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(2012.4)
WEEE Directive
Renesas development tools and products are directly covered by the European Union's Waste
Electrical and Electronic Equipment, (WEEE), Directive 2002/96/EC.
As a result, this equipment, including all accessories, must not be disposed of as household
waste but through your locally recognized recycling or disposal schemes.
As part of our commitment to environmental responsibility Renesas also offers to take back the
equipment and has implemented a Tools Product Recycling Program for customers in Europe.
This allows you to return equipment to Renesas for disposal through our approved Producer
Compliance Scheme.
To register for the program, click here "http://www.renesas.com/weee".
This page is intentionally left blank
About This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the functions and operating specifications of this
CPU board. A basic knowledge of electrical circuits, logical circuits, and microcomputers (MCUs) is necessary in order
to use this manual.
This manual is composed of an overview of the CPU board; its functional and operating specifications.
Carefully read all notes described in the body of text in the manual.
The Revision History summarizes the modifications and additions to the previous versions. Refer to the text of the manual
for details.
The following documents apply to the V850E2/ML4 CPU Board R0K0F4022C000BR.
Document Type
User’s Manual
Description
Document Title
Document No.
Describes functions (devices, memory V850E2/ML4 CPU Board This publication
maps, electrical characteristics), and
R0K0F4022C000BR
operating specifications (connectors,
User’s Manual
and switches)
Installation Manual
Describes how to set up hardware
SH726B CPU Board
and software
R0K5726B0C000BR
R20UT0603JJ
Installation Manual
The following documents apply to the V850E2/ML4 . Make sure to refer to the latest versions of these documents. The
newest versions of the documents listed may be obtained from the Renesas Electronics website.
Document Type
User’s manual: Hardware
Description
Document Title
Hardware specifications (pin assignments,
V850E2/ML4
memory maps, peripheral function
User’s manual:
specifications, electrical characteristics,
Hardware
Document No.
R01UH0262EJ
timing charts) and operation description
Note: Refer to application notes for details
on using peripheral functions
User’s manual:
Description of CPU instruction set
Architecture
V850E2M
R01US0001EJ
User’s manual:
Architecture
Application note
Applications, sample programs
Available from the Renesas Electronics
Renesas technical update
Product specifications, updates on
website.
documents, etc.
2. Frequently Used Abbreviations and Acronyms
ACIA
Asynchronous Communication Interface Adapter
bps
Bits per second
CRC
Cyclic Redundancy Check
DMA
Direct Memory Access
DMAC
Direct Memory Access Controller
GSM
Global System for Mobile Communications
Hi-Z
High Impedance
IEBus
Inter Equipment bus
I/O
Input/Output
IrDA
Infrared Data Association
LSB
Least Significant Bit
MSB
Most Significant Bit
NC
Non-Connection
PLL
Phase Locked Loop
PWM
Pulse Width Modulation
SFR
Special Function Registers
SIM
Subscriber Identity Module
UART
Universal Asynchronous Receiver/Transmitter
VCO
Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners.
Table of Contents
About This Manual................................................................................................................................................4
1.
2.
3.
Overview.................................................................................................................................................... 1-1
1.1
Overview .......................................................................................................................................... 1-1
1.2
R0K0F4022C000BR Configuration .................................................................................................. 1-2
1.3
R0K0F4022C000BR External Specification..................................................................................... 1-3
1.4
Block Diagram for R0K0F4022C000BR........................................................................................... 1-4
1.5
Memory Map .................................................................................................................................... 1-5
1.6
Absolute Maximum Ratings ............................................................................................................. 1-6
1.7
Operating Conditions........................................................................................................................ 1-6
Function Specification ............................................................................................................................... 2-1
2.1
Functions Overview.......................................................................................................................... 2-1
2.2
CPU.................................................................................................................................................. 2-2
2.3
External Memory .............................................................................................................................. 2-3
2.3.1
SDRAM .................................................................................................................................... 2-3
2.3.2
EEPROM.................................................................................................................................. 2-4
2.4
I/O Ports ........................................................................................................................................... 2-5
2.5
Serial Port Interfae ......................................................................................................................... 2-10
2.6
CAN Interface................................................................................................................................. 2-11
2.7
LCD Interface ................................................................................................................................. 2-12
2.8
USB Interface ................................................................................................................................. 2-13
2.9
Ethernet Interface........................................................................................................................... 2-14
2.10
Emulator Interface .......................................................................................................................... 2-15
2.11
Switches ......................................................................................................................................... 2-16
2.12
LEDs, Potentiometer ...................................................................................................................... 2-17
2.13
Power module ................................................................................................................................ 2-18
2.14
Clock Module.................................................................................................................................. 2-19
2.15
Reset Module ................................................................................................................................. 2-20
Operational Specification........................................................................................................................... 3-1
3.1
Connector Overview......................................................................................................................... 3-1
3.1.1
Application Headers (JA1 to JA3, JA5 and JA6) ..................................................................... 3-2
3.1.2
USB Connectors (J1and J3) .................................................................................................... 3-9
3.1.3
Ethernet Connector (J2)......................................................................................................... 3-10
3.1.4
CAN Connector (J14)............................................................................................................. 3-11
3.1.5
Serial Port Connnetor (J5)) .................................................................................................... 3-12
3.1.6
LCD Connector (J6) ............................................................................................................... 3-13
3.1.7
External Power Supply Connectors (J7 and J2 to J14) ......................................................... 3-14
3.1.8
DC Power Jack (J9) ............................................................................................................... 3-16
3.1.9
E1 Connector (J10) ................................................................................................................ 3-17
3.1.10
GND Connector (J15) ............................................................................................................ 3-18
3.2
Operating Components .................................................................................................................. 3-19
3.2.1
Jumpers (JP1, JP2, JP4, JP5, JP7 to JP13) ......................................................................... 3-19
3.2.2
Swiches.................................................................................................................................. 3-23
3.2.3
Potentiometer ....................................................................................................................... 3-25
3.2.4
LEDs ...................................................................................................................................... 3-25
3.3
Dimensions..................................................................................................................................... 3-26
V850E2/ML4 CPU Board R0K0F4022C000BR
1. Overview
1. Overview
1.1
Overview
The V850E2/ML4 CPU Board R0K0F4022C000BR (hereinafter called the “R0K0F4022C000BR”) is the evaluation
board designed to evaluate features and performance of the V850E2/ML4 of Renesas Electronics 32-bit single chip
microcontroller and to conduct development and evaluation for its application software. The features of the
R0K0F4022C000BR are described below.
1.1.1
Features of the R0K0F4022C000BR
• Usually includes a 16MB SDRAM (16-bit bus connect) and an 8KB EEPROM as external memories.
• Usually includes a serial port connector (RS-232C), a USB connector, an ETHERNET connector, and a CAN
connector as peripheral interfaces of the V850E2/ML4.
• The USB connector normally equips a Series A-receptacle to evaluate the USB host controller, and a Series Mini-B
receptacle to evaluate the USB function controller.
• The data bus, the address bus and the pins of peripheral functions of the V850E2/ML4 are connected to the expansion
connector to enable timing evaluation with the peripheral devices using measurement hardware, and development of
expansion boards for the development purpose.
• Enables to evaluate the debugging with Renesas Electronics On-chip Debugging Emulator E1 (14-pin connector).
R20UT0778EJ0100 Rev.1.00
May 20, 2012
Page 1 of 7
V850E2/ML4 CPU Board R0K0F4022C000BR
1.2
1. Overview
System Configuration
Figure 1.1 shows the system configuration with the R0K0F4022C000BR.
Figure 1.1 System Configuration
R20UT0778EJ0100 Rev.1.00
May 20, 2012
Page 2 of 7
V850E2/ML4 CPU Board R0K0F4022C000BR
1.3
1. Overview
External Specifications
Table 1.1 lists the external specifications of the R0K0F4022C000BR.
Table 1.1 External Specifications
No.
1
Item
CPU
Description
•
V850E2/ML4
• Input (XIN) clock: 10MHz
• CPU clock: Up to 200MHz
• Memory controller bus (E bus) clock: Up to 66.667MHz
(SDRAM interface: Up to 50MHz)
• Peripheral bus (P bus) clock: Up to 66.667MHz
• On-chip memories
-Flash memory: 1MB
-On-chip RAM: 64KB
-H bus shared memory: 64KB
2
3
External memories
Connectors/
Through holes
4
5
6
7
Switches
LED, Potentiometer
Clock
Dimensions/
Lamination
R20UT0778EJ0100 Rev.1.00
May 20, 2012
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
-Flash cache: 16KB
• Source voltage:
-Internal: 1.2V
-I/O: 3.3V (5V external supply when using the AD converter with 5.0V)
• Package: 216 pin QFP (0.4mm pitch)
SDRAM: 16MB (CS4 space)
EEPROM: 8KB (12C bus interface)
Serial port connector (D-sub 9-pin, RS232C)
CAN connector (3-pin)
LCD connector (14-pin)
USB host connector (Series A receptacle)
USB function connector (Series Mini-B receptacle)
ETHERNET connector 100Base-T(8-pin, RJ-45)
E1 connector (14-pin)
Through holes for the expansion connector (Application header):
JA1/JA2 (26 pins for each),
JA3 (50 pins), JA5/JA6 (24pins for each)
Reset switch: 1
External interrupt switches: 3 (NMI, INTP1, INTP2)
Operation mode setting DIP switch: 1 (4/package)
Users DIP switch: 1 (4/package)
Ethernet PHY setting DIP switch: 1
Power LED: 1
User LEDs: 4 (connected with the I/O port pins of the V850E2/ML4)
Ethernet PHY LEDs: 3
10kΩPotentiometer:1
Resonator for CPU: 10MHz
Oscillator for USB: 48MHz
Resonator for Ethernet PHY: 25MHz
Dimensions: 125mm × 170 mm
Mounting form: 4 layered double-sided, (thickness:1.6mm)
Number of boards: 1
Page 3 of 7
V850E2/ML4 CPU Board R0K0F4022C000BR
1.4
1. Overview
R0K0F4022C000BR Block Diagram
Figure 1.2 shows the R0K0F4022C000BRsystem block diagram.
USB host
connector
USB function
connector
Ethernet connector
Resonator
USBF
USBH
CAN
connector
5V⇔3.3V
25MHz
PHY
OCD
V850E2/ML4
IICB
UARTJ0
FCN0
PORT
LCD
connector
Serial port
connector
E1 connector
200MHz
Resonator
EEPROM
8KB
SDRAM
16MB
CPU:10MHz
16 bits
8/16 bits
Oscillator
USB:48MHz
5V
DC-DC
3.3V
1.2V
3.3V
5V
A/D
converter
Power source
selection
8/16 bits
CS4
(CS4 space
for SDRAM)
Memory controller bus (E bus): Up to 66.67MHz
(SDRAM interface: Up to 50MHz for CPU
specification)
AVDD
3.3V or 5V
(5V: external supply)
Application header
Figure 1.2 System Block Diagram
R20UT0778EJ0100 Rev.1.00
May 20, 2012
Page 4 of 7
V850E2/ML4 CPU Board R0K0F4022C000BR
1.5
1. Overview
Memory Mapping
Figure 1.3 shows the memory mapping on the V850E2/ML4 and the R0K0F4022C000BR.
Figure 1.3 Memory Mapping
R20UT0778EJ0100 Rev.1.00
May 20, 2012
Page 5 of 7
V850E2/ML4 CPU Board R0K0F4022C000BR
1.6
1. Overview
Absolute Maximum Rating
Table 1.2 shows the absolute maximum rating on the R0K0F4022C000BR.
Table 1.2 Absolute Maximum Rating
Symbol
Item
Value
Remarks
VCC
5V system power supply voltage
-0.5V to 6.0V
Reference voltage: VSS
3VCC
3.3V system power supply voltage
-0.5V to 4.1V
Reference voltage: VSS (only direct supply)
1.2VCC
1.25V system power supply voltage
-0.5V to 1.6V
Reference voltage: VSS (only direct supply)
Topr
Operating ambient temperature
0C to 50C
Do not expose to condensation or corrosive
gases
Tstg
Storage ambient temperature
-20C to 60C
Do not expose to condensation or corrosive
gases
Note: The ambient temperature is the air temperature immediate to the board.
1.7
Operating Conditions
Table 1.3 lists the operating conditions on the R0K0F4022C000BR.
Table 1.3
Symbol
Operating Conditions
Item
Value
VCC
5V system power supply voltage
4.75V to 5.25V
-
Maximum consumption voltage on
the board
Up to 1.5A
Topr
Operating ambient temperature
0C to 50C
Remarks
Reference voltage: VSS
Do not expose to condensation or corrosive
gases
Note: The ambient temperature is the air temperature immediate to the board.
R20UT0778EJ0100 Rev.1.00
May 20, 2012
Page 6 of 7
V850E2/ML4 CPU Board R0K0F4022C000BR
2. Function Specification
2. Function Specification
2.1
Functions Overview
Table 2.1 lists the R0K0F4022C000BR function modules.
Table 2.1 R0K0F4022C000BR Function modules
Section
2.2
Function
CPU
Description
V850E2/ML4
•
Input (XIN) clock: 10MHz
•
CPU clock: Up to 200MHz
•
Memory contoroller bus (E bus) clock: Up to 66.667MHz
(SDRAM Interface: Up to 50MHz)
•
Perepheral bus (P bus) clock: Up to 66.667MHz
•
Internal memory:
‐Flash memory: 1MB
‐Internal RAM: 64KB
‐H bus shared memory: 64KB
‐Flash cache: 16KB
2.3
2.4
2.5
2.6
External Memory
I/O Ports
Serial Port Interface
CAN Interface
•
SDRAM: 16MB (CS4 space)
•
EEPROM: 8KB (I2C bus interface)
Connects the V850E2/ML4bus and I/O port to the application header
Connects the V850E2/ML4 UARTJ0 signal to the serial port connector
Connects the V850E2/ML4 CAN signal to the CAN connector via the CAN
transceiver
2.9
LCD Interface
USB Interface
Ethernet Interface
2.10
Emulator Interface
2.11
Switches
2.7
2.8
Character LCD interface
Connects the V850E2/ML4 USB signal to the USB connector
Connects the V850E2/ML4 Ethernet MAC signal to the Ethernet connector via
the PHY
Connects the V850E2/ML4 OCD signal to the E1 connector (14-pin)
Enables debug evaluation with the E1 emulator
2.12
2.13
2.14
LEDs and Potentiometer
Power Module
Clock Module
•
User DIP swich: 1 (4/package)
•
Operation mode setting DIP switch: 1 (4/package)
•
External interrupt swiches: 3 (NMI, INTP1, and INTP2)
•
Reset swich: 1
•
Ethernet PHY Setting DIP switch: 1 (8/package)
•
User LEDs: 4
•
USB host bus LED: 1
•
Ethernet PHY LEDs: 3
•
Power LED: 1
•
10kΩ Potentiometer: 1
Controls the R0K0F4022C000BR system power supply
•
Resonator for CPU: 10MHz
•
Oscillator for USB: 48MHz
•
Resonator for Ethernet PHY: 25MHz）
2.15
Reset Module
Executes reset control of the device which mounted in theR0K0F4022C000BR
―
Operating specifications
Refer to Chapter 3 for details on connectors, jumpers, switches, LEDs, and
potentiometer.
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 1 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2.2
2. Function Specification
CPU
The R0K0F4022C000BR includes the V850E2/ML4, the 32-bit RISK microcontroller, which operates with a maximum CPU
clock of 200MHz and a maximum peripheral clock of 66.667MHz. The V850E2/ML4 is the microcontroller which has 1 MB of
flash memory, 64 KB of RAM, and 64 KB of H bus shared memory to support various applications such as data processing and
equipment control
Figure 2.1 shows the block diagram on the V850E2/ML4. The unused pins on the R0K0F4022C000BR are not listed.
SDRAM
JA3
JA5
LED
JA6
SDRAM
JA3
(JA2, JA3)
JA2
JA3
SDRAM
JA5
JA6
JA5
LCD
JA6
JA1
JA6
JA2
JA6
JA1
Ethernet
JA1
JA2
JA1
18
17
16
15
14
13
12
11
10
9
8
7
216
215
214
213
212
211
210
209
208
207
206
205
198
197
196
195
194
193
192
191
190
189
188
187
184
183
182
181
180
177
176
175
174
173
172
171
75
76
77
78
79
80
81
82
83
84
91
92
93
94
95
96
97
98
JA5
Potentiometer
(VR1)
JA1
User DIP
switch
JA5
139
138
134
129
128
127
126
125
124
P3_0/A0
P3_1/A1
P3_2/A2
P3_3/A3
P3_4/A4
P3_5/A5
P3_6/A6
P3_7/A7
P3_8/A8
P3_9/A9
P3_10/A10
P3_11/A11/CSI0F_CS7
P3_12/A12/CSI0F_CS6
P3_13/A13/CSI0F_CS5
P3_14/A14/CSI0F_CS4
P3_15/A15/CSI0F_CS3
V850E2/ML4
P4_0/A16/INTP7/TA1_I8/TA1_O8/CSI0F_CS2
P4_1/A17/INTP8/TA1_I9/TA1_O9/CSI0F_CS1
P4_2/A18/INTP9/TA1_I10/TA1_O10/CSI0F_CS0
P4_3/A19/INTP10/TA1_I11/CSI0F_RYI/TA1_O11/CSI0F_RYO
P4_4/A20/INTP11/TA1_I12/CSI0F_SSI/TA1_O12
P4_5/A21/INTP12/TA1_I13/SI0F/TA1_O13
P4_6/A22/INTP13/TA1_I14/SO0F/TA1_O14
P4_7/A23/INTP14/TA1_I15/SCK0F/TA1_O15
P4_8/BUSCLK
P4_9/LLBE/LLWR
P4_10/LUBE/LUWR
P4_11/WR/RW
P4_12/RD
P4_13/CS1
P4_14/CS2/DMAAK5/CSI1F_CS7
P4_15/CS3/DMATC5/CSI1F_CS6
P0_0/D0
P0_1/D1
P0_2/D2
P0_3/D3
P0_4/D4
P0_5/D5
P0_6/D6
P0_7/D7
P0_8/D8
P0_9/D9
P0_10/D10
P0_11/D11
P0_12/D12
P0_13/D13
P0_14/D14
P0_15/D15
P1_0/D16/TA0_I0/TE0_TI0/INTP5/TA0_O0
P1_1/D17/TA0_I1/OCI/INTP6/TA0_O1
P1_2/D18/TA0_I2/TE0_TI1/INTP7/TA0_O2
P1_3/D19/TA0_I3//INTP8/TA0_O3/PPON
P1_4/D20/TA0_I4/TE0_AI/INTP9/TA0_O4
P1_5/D21/TA0_I5/INTP10/TA0_O5
P1_6/D22/TA0_I6/TE0_BI/INTP11/TA0_O6
P1_7/D23/TA0_I7/INTP12/TA0_O7
P1_8/D24/TA0_I8/TE0_ZI/INTP13/TA0_O8
P1_9/D25/TA0_I9/INTP14/TA0_O9
P1_10/D26/TA0_I10/INTP15/TA0_O10
P1_11/D27/TA0_I11/INTP16/TA0_O11
P1_12/D28/TA0_I12/INTP17/TA0_O12
P1_13/D29/TA0_I13/INTP18/TA0_O13
P1_14/D30/TA0_I14/INTP19/TA0_O14
P1_15/D31/TA0_I15/INTP20/TA0_O15
P5_0/ESO0/TA1_I0/SO0/A24/TA1_O0
P5_1/ESO2/TA1_I1/SCK0/A25/TA1_O1
P5_2/ESO3/TA1_I2/SI0/CS4/TA1_O2/ADCNV0
P5_3/INTP15/TA1_I3/TE1_TI0/CSI0_SSI/SDCKE/TA1_O3/ADCNV1
P5_4/INTP16/TA1_I4/TE1_TI1/CSI0_RYI/SDRAS/TA1_O4/CSI0_RYO/ADCNV2
P5_5/INTP17/TA1_I5/TE1_AI/RXD1/SDCAS/TA1_O5
P5_6/INTP18/TA1_I6/TE1_BI/SDWE/TA1_O6/TXD1
P5_7/INTP19/TA1_I7/TE1_ZI/RXD1F/LLDQM/TA1_O7
P5_8/INTP20/TA1_I8/LUDQM/TA1_O8/TXD1F
P5_9/INTP21/TA1_I9/CSI1_SSI/ULDQM/TA1_O9/DMAAK2
P5_10/INTP22/TA1_I10/CSI1_RYI/UUDQM/TA1_O10/DMATC2/CSI1_RYO
P5_11/INTP23/TA1_I11/SCK1/REFRQ/TA1_O11/DMAAK4
P5_12/INTP24/TA1_I12/SO1/BUSRQ/TA1_O12/DMATC4
P5_13/INTP25/TA1_I13/HLDAK/TA1_O13
P5_14/INTP26/TA1_I14/HLDRQ/SI1/TA1_O14
P5_15/INTP27/TA1_I15/TA1_O15
P6_0/INTP0/ETH_CRS/TA0_I0/TE0_TI0/TA0_O0
P6_1/INTP1/ETH_COL/TA0_I1/TA0_O1
P6_2/INTP2/ETH_TXD3/TA0_I2/TE0_TI1/TA0_O2
P6_3/INTP3/ETH_TXD2/TA0_I3/TA0_O3
P6_4/INTP4/ETH_TXD1/TA0_I4/TE0_AI/DMATC0/TA0_O4
P6_5/ETH_TXD0/TA0_I5/DMATC1/TA0_O5
P6_6/ETH_TXEN/TA0_I6/TE0_BI/DMAAK0/TA0_O6
P6_7/ETH_TXCLK/TA0_I7/DMAAK1/TA0_O7
P6_8/ETH_TXER/TJ_I0/TA0_I8/TE0_ZI/TJ_O0/TA0_O8
P6_9/ETH_RXER/TJ_I1/TA0_I9/TJ_O1/TA0_O9
P6_10/ETH_RXCLK/INTP21/TA0_I10/TA0_O10
P6_11/ETH_RXDV/INTP22/TA0_I11/TA0_O11
P6_12/ETH_RXD0/INTP23/TA0_I12/TA0_O12
P6_13/ETH_RXD1/INTP24/TA0_I13/TA0_O13
P6_14/ETH_RXD2/INTP25/TA0_I14/TA0_O14
P6_15/ETH_RXD3/TA0_I15/TA0_O15
P7_0/TJ_I2/INTP26/TJ_O2
P7_1/TJ_I3/INTP27/TJ_O3
ANI00
ANI01
ANI05
P8_0/ANI06
P8_1/ANI07
P8_2/ANI08
P8_3/ANI09
P8_4/ANI10
P8_5/ANI11
UDPH
UDMH
UDPF
UDMF
MDO0
MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7
MCKO
MSEO0
MSEO1
EVTI
EVTO
DCK/TCK/FLSCK
DDI/TDI/FLSI/FLRXD
DDO/TDO/FLSO
DMS/TMS
DRST/TRST
TRDY
RESET
P2_0/NMI
P2_1/INTP0/ADTRG00/CSI1F_RYI/BCYST/TXD0/CSI1F_RYO
P2_2/WAIT/ADTRG10/RXD0/CSI1F_SSI
P2_3/INTP1/ADTRG20/ULBE/ULWR/CSI1F_CS0
P2_4/ESO0/TA1_I0/UUBE/TA1_O0/UUWR/CSI1F_CS1
P2_5/ESO2/TA1_I1/TA1_O1/CSI1F_CS2
P2_6/ESO3/TA1_I2/SO1F/DMAAK3/TA1_O2/ADCNV0
P2_7/INTP2/TA1_I3/TE1_TI0/SCK1F/DMATC3/TA1_O3/ADCNV1
P2_8/INTP3/TA1_I4/TE1_TI1/SI1F/TA1_O4/ADCNV2
P2_9/INTP4/TA1_I5/TE1_AI/OCI/TA1_O5/CSI1F_CS3
P2_10/INTP5/TA1_I6/TE1_BI/PPON/TA1_O6/CSI1F_CS4
P2_11/INTP6/TA1_I7/TE1_ZI/UCLK/TA1_O7/CSI1F_CS5
P2_12/TJ_I0/SCL0/RXD0F/TJ_O0
P2_13/TJ_I1/ADTRG01/SDA0/TJ_O1/TXD0F
P2_14/TJ_I2/ADTRG11/SCL1/CAN0RXD/TJ_O2
P2_15/TJ_I3/ADTRG21/SDA1/TJ_O3/CAN0TXD
MODE3
MODE2
FLMD1
FLMD0
25
26
27
28
29
30
31
32
33
34
35
38
39
40
41
42
55
56
57
58
59
60
61
62
63
64
65
66
71
72
73
74
52
51
48
47
108
107
106
105
104
103
102
101
109
113
110
114
115
121
118
117
120
119
116
148
149
170
167
166
165
164
163
162
161
160
159
158
157
156
155
154
4
3
23
22
SDRAM
JA3
JA2
JA6
(JA2)
JA2
LED
JA6
JA2
USB
UDI (E1 and OCD)
or
ROM writer (PG-FP5)
(OCD and PG-FP5 with
optional connector)
RESET
JA2
NMI
JA3
USB
INTP1
JA5
JA2
INTP2
USB
JA5
JA1
Serial port
CAN,
EEPROM
JA1, JA5
Operation mode
setting DIP switch
Figure 2.1 V850E2/ML4 Block Diagram
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 2 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2.3
2.3.1
2. Function Specification
External Memory
SDRAM
The R0K0F4022C000BR includes 16-MB SDRAM (2-Mword x 16-bitｘ4-bank), which is controlled by the V850E2/ML4
_______
memory controller CS4 . The pins used for SDRAM control are also connected to the application headers (JA3, JA5 and JA6)
as pins related to bus, pins related to the SCI and pins related to timer respectively. These pins cannot be used to avoid overlaps.
_______
Uninstall the CS4 jumper (JP11) when using the application headers.
Figure 2.2 shows the circuit configuration for the connection between the V850E2/ML4 and the SDRAM.
Note: The items of rising and falling of the bus clock do not satisfy with the requirement specification for the SDRAM on the
R0K0F4022C000BR. Only the R0K0F4022C000BR which have no operational problem are delivered. We do not guarantee
operation of the R0K0F4022C000BR when users apply it to their system. Users should carefully execute evaluation on their
system and determine its applicability.
3VCC
22kΩ x 6
V850E2/ML4
22kΩ
16MB SDRAM
(2-Mword×16-bit×4-bank)
14
P4_7/A23, P4_6/A22,
P3_12/A12 ～ P3_1/A1
A23,A22
BA1, BA0
A12～A1
A11～A0
CKE
P5_3/SDCKE
P4_8/BUSCLK
CLK
JP11
P5_2/CS4
CS
P5_4/SDRAS
RAS
P5_5/SDCAS
CAS
P5_6/SDWE
WE
DQMH
P5_8/LUDQM
P5_7/LLDQM
DQML
DQ15～DQ0
22kΩ
P0_15/D15 ～ P0_0/D0
16
VSS
22kΩ×2
VSS
VSS
Application header (JA3)
43,41,13～2
46
44
0Ω
28
50
49
0Ω×3
26
47
48
36～29,24～17
0Ω×3
B3, B2, A11～A0
CKE
CLK
CS4n
RASn
CASn
RDWRn
WRHn/DQMH
WRLn/DQML
DQ15～DQ0
Application header (JA2)
9
20
22
-
Application header (JA5)
9
17
Composition: 2M word ×16-bit ×4-bank
Capacity: 16MB (8M word/16 bit)
row address: A0 to A11
column address: A0 to A8
18
0Ω×2
: Optional
M2_TRCCLK
M2_TRDCLK
Application header (JA6)
7
8
Zero-ohm resistors for damping and signal allocation are not indicated.
IRQ4
A22
9
A23
11
SCIbRX
SCIbTX
SCIcTX
SCIcCK
Figure 2.2 Circuit Configuration of SDRAM
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 3 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2.3.2
2. Function Specification
EEPROM
The R0K0F4022C000BR includes the 8-KB EEPROM (8-Kword x 8-bit), which is controlled by the I2C bus (IICB) interface
mounted in the V850E2/ML4. The IICB signal is multiplexed with the CAN signal, therefore the EEPROM is not available
when the CAN connector is in use. Install the jumper (JP8 and JP10) in appropriate pin to use.
Figure 2.3 shows the circuit configuration of the V850E2/ML4 and the EEPROM.
3VCC
V850E2/ML4
22kΩ×4
EEPROM
(8-Kword×8-bit)
4.7kΩ×2
P2_14/SCL1/CAN0RXD
JP8
P2_15/SDA1/CAN0TXD
JP10
SCL
SDA
A2
A1
A0
WP
22kΩ×4
VSS
0Ω×4
P6_12/INTP23
Application header (JA1)
26
P6_11/INTP22
25
P7_0/INTP26
SCL
SDA
CAN connector (J4)
0Ω×2
-
0Ω×3
Application header (JA5)
6
: Optional
5
CAN1RX
CAN1TX
Figure 2.3 Circuit Configuration of EEPROM
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 4 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2.4
2. Function Specification
I/O Ports
On the R0K0F4022C000BR, the V850E2/ML4 I/O ports are connected to the application headers. Table 2.1 to Table 2.6 list
the I/O port functions. The unused pins on the R0K0F4022C000BR are not listed. Some of the I/O ports are connected to
devices, I/O connectors, switches and LEDs on the board. Refer to Chapter 3 Operational Specification for details.
Table 2.2 I/O Port Functions (1/5)
V850E2/ML4
Pin No.
Application headers
Pin name
JA1
JA2
JA3
JA5
On-board function
JA6
M
E
U
C_S
LC
S,L,V
3
MODE2
SW2
4
MODE3
SW2
7
P3_11/A11/CSI0F_CS7
12
SD
8
P3_10/A10
11
SD
9
P3_9/A9
10
SD
10
P3_8/A8
9
SD
11
P3_7/A7
8
SD
12
P3_6/A6
7
SD
13
P3_5/A5
6
SD
14
P3_4/A4
5
SD
15
P3_3/A3
4
SD
16
P3_2/A2
3
SD
17
P3_1/A1
2
SD
18
P3_0/A0
22
FLMD0
23
FLMD1
25
P0_0/D0
17
SD
26
P0_1/D1
18
SD
27
P0_2/D2
19
SD
28
P0_3/D3
20
SD
29
P0_4/D4
21
SD
30
P0_5/D5
22
SD
31
P0_6/D6
23
SD
32
P0_7/D7
24
SD
33
P0_8/D8
29
SD
34
P0_9/D9
30
SD
35
P0_10/D10
31
SD
38
P0_11/D11
32
SD
39
P0_12/D12
33
SD
40
P0_13/D13
34
SD
41
P0_14/D14
35
SD
42
P0_15/D15
36
SD
(13)
1
SW2
SW2
【Notes】 M: On-board memory (SD=SDRAM), E: Ethernet, U: USB, C_S: CAN_Serial, LC:LCD, S,L,V: Switches, LED, Potentiometer
( ): Not connected by default.
R20UT0778EJ0100 Rev.1.00
May 31, 2012
Connectable at a zero-ohm resistor.
page 5 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2. Function Specification
Table 2.3 I/O Port Functions (2/5)
V850E2/ML4
Pin No.
Application headers
Pin name
JA1
JA2
JA3
JA5
Ob-board functions
JA6
M
E
U
47
UDMF
F
48
UDPF
F
51
UDMH
H
52
UDPH
H
55
P1_0/D16/TA0_I0/TE0_TI0/INTP5/TA0_O0
C_S
LC
S,L,V
21
_______
56
P1_1/D17/TA0_I1/OCI /INTP6/TA0_O1
57
P1_2/D18/TA0_I2/TE0_TI1/INTP7/TA0_O2
(15), 19
22
58
P1_3/D19/TA0_I3/INTP8/TA0_O3/PPON
(9)
59
P1_4/D20/TA0_I4/TE0_AI/INTP9/TA0_O4
25
60
P1_5/D21/TA0_I5/INTP10/TA0_O5
61
P1_6/D22/TA0_I6/TE0_BI/INTP11/TA0_O6
62
P1_7/D23/TA0_I7/INTP12/TA0_O7
63
P1_8/D24/TA0_I8/TE0_ZI/INTP13/TA0_O8
64
P1_9/D25/TA0_I9/INTP14/TA0_O9
11
65
P1_10/D26/TA0_I10/INTP15/TA0_O10
13
66
P1_11/D27/TA0_I11/INTP16/TA0_O11
14
71
P1_12/D28/TA0_I12/INTP17/TA0_O12
15, (17)
72
P1_13/D29/TA0_I13/INTP18/TA0_O13
16
73
P1_14/D30/TA0_I14/INTP19/TA0_O14
74
P1_15/D31/TA0_I15/INTP20/TA0_O15
75
P6_0/INTP0/ETH_CRS/TA0_I0/TE0_TI0/TA0_O0
15
E
76
P6_1/INTP1/ETH_COL/TA0_I1/TA0_O1
16
E
77
P6_2/INTP2/ETH_TXD3/TA0_I2/TE0_TI1/TA0_O2
17
E
78
P6_3/INTP3/ETH_TXD2/TA0_I3/TA0_O3
18
E
14
LED0
15
26
LED1
16
1
(23)
(8)
13
(12)
(14)
(15), 17
18
_______________
(11)
3
SW7
79
P6_4/INTP4/ETH_TXD1/TA0_I4/TE0_AI/DMATC0 /TA0_O4
80
P6_5/ETH_TXD0/TA0_I5/DMATC1 /TA0_O5
81
P6_6/ETH_TXEN/TA0_I6/TE0_BI/DMAAK0 /TA0_O6
82
P6_7/ETH_TXCLK/TA0_I7/DMAAK1 /TA0_O7
83
P6_8/ETH_TXER/TJ_I0/TA0_I8/TE0_ZI/TJ_O0/TA0_O8
19
E
84
P6_9/ETH_RXER/TJ_I1/TA0_I9/TJ_O1/TA0_O9
20
E
SW7
91
P6_10/ETH_RXCLK/INTP21/TA0_I10/TA0_O10
E
SW7
92
P6_11/ETH_RXDV/INTP22/TA0_I11/TA0_O11
(25)
E
93
P6_12/ETH_RXD0/INTP23/TA0_I12/TA0_O12
(26)
E
_______________
20
_______________
2
_______________
E
E
E
E
SW7
SW7
【Notes】 M: On-board memory (SD=SDRAM), E: Ethernet, U: USB, C_S: CAN_Serial, LC:LCD, S,L,V: Switches, LED, Potentiometer
( ): Not connected by default.
Connectable at a zero-ohm resistor.
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 6 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2. Function Specification
Table 2.4 I/O Port Functions (3/5)
V850E2/ML4
Pin No.
Application headers
Pin name
JA1
94
P6_13/ETH_RXD1/INTP24/TA0_I13/TA0_O13
95
P6_14/ETH_RXD2/INTP25/TA0_I14/TA0_O14
96
P6_15/ETH_RXD3/TA0_I15/TA0_O15
97
P7_0/TJ_I2/INTP26/TJ_O2
98
P7_1/TJ_I3/INTP27/TJ_O3
JA2
JA3
JA5
On-board functions
JA6
M
21
E
U
C_S
LC
S,L,V
E
7
22
(6)
E
SW7
E
SW7
E
E
124
P8_5/ANI11
2
125
P8_4/ANI10
1
126
P8_3/ANI09
12
SW1
127
P8_2/ANI08
11
SW1
128
P8_1/ANI07
10
SW1
129
P8_0/ANI06
9
SW1
134
ANI05
138
ANI01
139
ANI00
144
X1
145
X2
148
VR1
4
3
(2)
____________
RESET
1
149
P2_0/NMI
3
154
P2_15/TJ_I3/ADTRG21/SDA1/TJ_O3/CAN0TXD
25
5
EE
CAN
155
P2_14/TJ_I2/ADTRG11/SCL1/CAN0RXD/TJ_O2
26
6
EE
CAN
156
P2_13/TJ_I1/ADTRG01/SDA0/TJ_O1/TXD0F
(6)
157
P2_12/TJ_I0/SCL0/RXD0F/TJ_O0
(8)
158
P2_11/INTP6/TA1_I7/TE1_ZI0/UCLK/TA1_O7/CSI1F_CS5
159
P2_10/INTP5/TA1_I6/TE1_BI/PPON/TA1_O6/CSI1F_CS4
P2_9/INTP4/TA1_I5/TE1_AI/OCI /TA1_O5/CSI1F_CS3
161
P2_8/INTP3/TA1_I4/TE1_TI1/SI1F/TA1_O4
162
P2_7/INTP2/TA1_I3/TE1_TI0/SCK1F/DMATC3 /TA1_O3
163
P2_6/ESO3/TA1_I2/SO1F/DMAAK3 /TA1_O2
164
P2_5/ESO2/TA1_I1/TA1_O1/CSI1F_CS2
P2_4/ESO0/TA1_I0/UUBE /TA1_O0/UUWR /CSI1F_CS1
P2_3/INTP1/ADTRG20/ULBE /ULWR /CSI1F_CS0
167
__________ ___________
_________
P2_2/WAIT /ADTRG10/RXD0/CSI1F_SSI
H
14
H
8
10, 23
13
SW5
6
___________
166
UR
(16)
_______________
165
UR
23
_______________
__________
SW3
HF
_______
160
(17)
8
(14)
12
(18)
11
F
9
F
45
SW4
(12)
【Notes】 M: On-board memory (SD=SDRAM), E: Ethernet, U: USB, C_S: CAN_Serial, LC:LCD, S,L,V: Switches, LED, Potentiometer
( ): Not connected by default.
Connectable at a zero-ohm resistor.
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 7 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2. Function Specification
Table 2.5 I/O Port Functions (4/5)
V850E2/ML4
Pin No.
170
Application headers
Pin name
JA1
P2_1/INTP0/ADTRG00/CSI1F_RYI/BCYST /TXD0/
171
P5_15/INTP27/TA1_I15/TA1_O15
172
P5_14/INTP26/TA1_I14/HLDRQ /SI1/TA1_O14
M
E
U
C_S
24
(14)
23
____________
(39)
P5_13/INTP25/TA1_I13/HLDAK /TA1_O13
_______________
P5_12/INTP24/TA1_I12/SO1/CPUBUSRQ/TA1_O12/DMATC4
P5_11/INTP23/TA1_I11/SCK1/REFRQ /TA1_O11/DMAAK4
_____________
_______________
P5_10/INTP22/TA1_I10/CSI1_RYI/UUDQM/TA1_O10/
_______________
DMATC2 /CSI1_RYO
_______________
177
P5_9/INTP21/TA1_I9/CSI1_SSI/ULDQM/TA1_O9/DMAAK2
180
P5_8/INTP20/TA1_I8/LUDQM/TA1_O8/TXD1F
181
P5_7/INTP19/TA1_I7/TE1_ZI/RXD1F/LLDQM/TA1_O7
___________
182
P5_6/INTP18/TA1_I6/TE1_BI/SDWE /TA1_O6/TXD1
183
P5_5/INTP17/TA1_I5/TE1_AI/RXD1/SDCAS/TA1_O5
E
(38)
(14)
LC
S,L,V
LC
7
LC
22
LC
21
8
LC
20
10
LC
19
LC
(13)
(9)
(47)
(22)
(48)
9
(20)
(26)
18
SD
49
17
SD
50
10
SD
____________
(8)
SD
(7)
SD
____________
P5_4/INTP16/TA1_I4/TE1_TI1/CSI0_RYI/SDRAS/
TA1_O4/CSI0_RYO
187
JA6
(9), (13)
(3)
_____________
175
184
JA5
12
174
176
JA3
____________
CSI1F_RYO
173
JA2
On-board functions
P5_3/INTP15/TA1_I3/TE1_TI0/CSI0_SSI/SDCKE/TA1_O3
_______
46
SD
SD
188
P5_2/ESO3/TA1_I2/SI0/CS4 /TA1_O2
(28)
189
P5_1/ESO2/TA1_I1/SCK0/A25/TA1_O1
(43)
190
P5_0/ESO0/TA1_I0/SO0/A24/TA1_O0
_______ _______________
191
P4_15/CS3 /DMATC5 /CSI1F_CS06
192
P4_14/CS2 /DMAAK5 /CSI1F_CS7
193
P4_13/CS1
_______ _______________
24
(42)
(10)
(27)
(26) 28, (45)
_______
27
_____
194
P4_12/RD
195
P4_11/WR/RW
25
______ ______
26
__________ ___________
196
P4_10/LUBE /LUWR
197
P4_9/LLBE /LLWR
47
48
198
P4_8/BUSCLK
44
205
P4_7/A23/INTP14/TA1_I15/SCK0F/TA1_O15
(13)
(41)
11
SD
206
P4_6/A22/INTP13/TA1_I14/SO0F/TA1_O14
(11)
43
9
SD
207
P4_5/A21/INTP12/TA1_I13/SI0F/TA1_O13
42
12
208
P4_4/A20/INTP11/TA1_I12/CSI0F_SSI/TA1_O12
41
LED3
209
P4_3/A19/INTP10/TA1_I11/CSI0F_RYI/TA1_O11/CSI0F_RYO
40
LED2
E
_________ __________
SD
【Notes】 M: On-board memory (SD=SDRAM), E: Ethernet, U: USB, C_S: CAN_Serial, LC:LCD, S,L,V: Switches, LED, Potentiometer
( ): Not connected by default.
Connectable at a zero-ohm resistor.
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 8 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2. Function Specification
Table 2.6 I/O Port Functions (5/5)
V850E2/ML4
Pin No.
Pin name
Application headers
JA1
JA2
JA3
210
P4_2/A18/INTP9/TA1_I10/TA1_O10/CSI0F_CS0
39
211
P4_1/A17/INTP8/TA1_I9/TA1_O9/CSI0F_CS1
38
212
P4_0/A16/INTP7/TA1_I8/TA1_O8/CSI0F_CS2
37
213
P3_15/A15/CSI0F_CS3
16
214
P3_14/A14/CSI0F_CS4
15
215
P3_13/A13/CSI0F_CS5
14
216
P3_12/A12/CSI0F_CS6
13
JA5
On-board functions
JA6
M
E
U
C_S
LC
S,L,V
15
SD
【Notes】 M: On-board memory (SD=SDRAM), E: Ethernet, U: USB, C_S: CAN_Serial, LC:LCD, S,L,V: Switches, LED, Potentiometer
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 9 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2.5
2. Function Specification
Serial Port Interface
On the R0K0F4022C000BR, the V850E2/ML4 UARTJ0 is connected to the serial port connector (J5) via the RS-232C
transceiver. Also, pins 5 and 6 of the application header (JA6) can be connected to the serial port connector (J5) via the
RS-232C transceiver by installing JP2 and JP5 in appropriate pin. Short-circuit is used for pins 1and 2 of both JP2 and JP5 to
connect to the serial port connector (J5). When using the V850E2/ML4 UARTJ0 as the serial port, it cannot be used as the
application header.
Figure 2.4 shows the R0K0F4022C000BR serial port block diagram.
3VCC
V850E2/ML4
Serial port connector (J5)
22kΩ
22kΩ
P2_13/TXD0F
RS-232C
transceiver
JP5
P2_12/RXD0F
1
2
3
4
2
4
0Ω
0Ω
0Ω
0Ω
JP2
1
3
0Ω
0Ω
0Ω
0Ω
0Ω
VSS
Application header (JA6)
5 RS232TX
6 RS232RX
P2_6/SO1F
P2_8/SI1F
0Ω×4
Male plug with the crossover cable (optional)
Female socket with the straight cable
(optional)
Male plug with the
crossover cable
Application header (JA2)
6 SCIaTX
8 SCIaRX
GND
TXD
RXD
5
4
3
2
1
Female socket with the
straight cable
1
9
8
TXD
7
RXD
2
3
4
6
GND
5
6
7
8
9
: Optional
Figure 2.4 Serial Port Block Diagram
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 10 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2.6
2. Function Specification
CAN Interface
The R0K0F4022C000BR includes a 3-pin CAN connector (J4). The V850E2/ML4 CAN0TXD is connected to J4 connector via
the jumper, a zero-ohm resistor and the CAN transceiver, and the CAN0RXD is connected to J4 connector via the jumper, a
zero-ohm resistor and the level shifter and the CAN transceiver. The CAN0TXD and the CAN0RXD are also connected to the
application header (JA5). When using the application header (JA5), remove zero-ohm resistors on the CAN connector side. The
CAN signals both at the CAN connector and the application header cannot be used.
The V850E2/ML4 SDA1/CAN0TXD and the SCL1/CAN0RXD pins are also connected to the EEPROM and the application
header (JA1), and remove or install the jumper to specify the pin function. The CAN connector and the EEPROM cannot be
used at the same time. (When storing the Ethernet MAC address to the EEPROM, both the CAN connector and the Ethernet
MAC address cannot be accessed at the same time).
Figure 2.5 shows the CAN interface block diagram.
3VCC
3VCC
3VCC
5VCC
CAN
trarnsceiver
V850E2/ML4
P2_14/SCL1/CAN0RXD
22kΩ
JP8
22kΩ
VCCA
0Ω
A
B
GND
VSS
3VCC
RXD
JP10
0Ω
3
TXD
VSS
22kΩ
Application header (JA5)
5
P6_11/INTP22
2
CANL
6
P6_12/INTP23
1
120Ω
VSS
0Ω×2
P7_0/INTP26
CAN connector
(J4)
CANH
DIR
3VCC
22kΩ
P2_15/SDA1/CAN0TXD
22kΩ
VCCB
CAN1RX
CAN1TX
EEPROM
0Ω×4
Application header (JA1)
26
25
: Optional
IIC_SCL
IIC_SDA
Figure 2.5 CAN Interface Block Diagram
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 11 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2.7
2. Function Specification
LCD Interface
The R0K0F4022C000BR includes a 14-pin character LCD connector (J6). The V850E2/ML4 P5_10 to P5_15 control the
character LCD. The signals are connected to the application headers (JA5 and JA6) as timer and SCI signals. The functions of
these application headers are not available when using the LCD connector. Remove the LCD connector to use the application
headers.
Figure 2.6 shows the character LCD interface block diagram.
V850E2/ML4
P5_12/SO1/TA1_O12
P5_13/HLDAK/TA1_O13
P5_14/HLDRQ/SI1/TA1_O14
P5_15/INTP27/TA1_O15
LCD connector
(J6)
LCDD15
14
13
LCDD14
LCDD13
12
11
LCDD12
10
9
5VCC
P5_10/INTP22/TA1_O10
P5_11/SCK1/REFRQ/TA1_O11
8
7
LCDE
6
5
LCDRS
4
3
2
1
RW (Fized to write)
1kΩ
100kΩ
VSS
VSS
0Ω×2
Application header (JA1)
14
0Ω
0Ω×2
Application header (JA2)
3
38
39
19
20
21
22
23
24
0Ω×2
: Optional
DAC1
7
8
10
NMI
Application header (JA3)
A17
A18
Application header (JA5)
M2-Up
M2-Un
M2-Vp
M2-Vn
M2-Wp
M2-Wn
Application header (JA6)
SCIbRX
SCIbTX
SCIbCK
Figure 2.6 Character LCD Interface Block Diagram
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 12 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2.8
2. Function Specification
USB Interface
The R0K0F4022C000BR includes the USB host connector (series A-receptacle, J1) and USB function connector (series Mini-B
_______
receptacle, J3). The V850E2/ML4 USB host bus is connected to the series A-receptacle, and the OCI and PPON are connected
_______
to the USB host bus switch. The OCI signal is connected to the application header (JA5) as port and timer signals, which can be
selected instead of using the USB host bus switch. The PPON signal is connected to the application header (JA1) as IRQ signal,
which can be selected instead of using the USB host bus switch. The V850E2/ML4 USB function bus is connected to the series
Mini-B receptacle, and P2_4 and INTP1 are used to control the USB function. The P2_4 and the INTP1 are also connected to
the application headers (JA1, JA2, and JA5), which can be selected instead of using the series Mini-B receptacle.
Figure 2.7 shows the USB interface block diagram.
V850E2/ML4
Oscillator
(48MHz)
P2_11/UCLK
27Ω
UDPH
UDMH
USB host
connector (J1)
5VCC
D+
27Ω
3VCC
22kΩ
P2_9/OCI
JP7
P2_10/PPON
FLG
JP9
EN
22kΩ
VSS
VSS
GND
0Ω
0Ω
15kΩ
0Ω
USBhost bus
switch
VSS
OUT2
15kΩ
FG2
VSS
VBus
1.5kΩ
OUT1
D-
GND FRAME
VSS
IN
FG1
VSS
LED4
VSS VSS VSS
JA2-16：P2_9/TA1_I5
JA5-14：P2_9/TA1_I5
JA1-23：P2_10/INTP5/TA1_I6/TA1_O6
0Ω
0Ω
0Ω
0Ω
JP4
P2_4
P2_3/INTP1
UDPF
UDMF
: Optional
JA2-18：P2_4/TA1_I0/TA1_O0
JA5-11：P2_4/TA1_I0/TA1_O0
JA1-8：P2_3/INTP1/ADTRG20
JA2-9：P2_3/INTP1/ADTRG20
EVDD
27Ω
JP1
1kΩ
1.5kΩ
USB function
connector (J3)
VBus
D+
27Ω
22kΩ
1.8kΩ
DGND
VSS
VSS VSS
FG3
FG2
FG1
FRAME
VSS
Figure 2.7 USB Interface Block Diagram
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 13 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2.9
2. Function Specification
Ethernet Interface
The R0K0F4022C000BR includes the Ethernet connector (J2) via PHY. The V850E2/ML4 Ethernet-related signals are
connected to the application headers (JA1, JA2 and JA6) as port signals. When using the Ethernet-related signals as port signal
of JA1, remove the zero-ohm resistor (R261) and the 22-ohm resistors between JA1-15, 16, and 20 to 22 and the PHY (R61,
R258, R259, R68 and R70 respectively), and install a 22-ohm resistor at R276. When pull-ups and pull-downs are required for
the signals of JA1-17 to 19, use the resistor with up to 10k ohms.
The MAC address can be stored in the EEPROM of the R0K0F4022C000BR. When storing the MAC address in the EEPROM,
the CAN cannot be use.
Figure 2.8 shows the Ethernet interface block diagram.
V850E2/ML4
3VCC
3VCC
Ethernet PHY (U17)
1.5kΩ
P7_1(ETH_MDIO)
MDIO
P7_0(ETH_MDC)
MDC
22Ω R70
P6_15/ETH_RXD3
22Ω
P6_14/INTP25/ETH_RXD2
22Ω R68
P6_13/ETH_RXD1
22Ω
P6_12/INTP23/ETH_RXD0
22Ω
P6_8/ETH_TXER
P0RXD1
3AVDD
10Ω×2
P0RXCLK/GPIO3
P0RXERR
Ethernet connector (J2)
P0TXERR/GPIO9
22Ω
P6_7/ETH_TXCLK
P0RXD2/GPIO8
P5_9/INTP21
49.9Ω×4
22Ω R259
P6_9/ETH_RXER
22Ω
P0RXDV
22Ω
P6_10/ETH_RXCLK
LED8
GPIO14
P0RXD3/GPIO7
330Ω×3
LED7
INT/GPIO4
P0RXD0
22Ω
P6_11/INTP22/ETH_RXDV
P0LINKLED/GPIO0
LED6
TXP
TD+
TXN
TD-
P0TXCLK
TCT
P6_6/DMAAK0/ETH_TXEN
P0TXEN
P6_5/TA0_O5/ETH_TXD0
P0TXD0
RCT
P6_4/DMATC0/ETH_TXD1
P0TXD1
N.C.
FG
P6_3/ETH_TXD2
P0TXD2/GPIO11
GND
FG
P6_2/ETH_TXD3
P0TXD3/GPIO10
22Ω R61
P6_0/ETH_CRS
R261
3VCC
SW7-1
SW7-2
SW7-3
SW7-4
SW7-5
SW7-6
SW7-7
SW7-8
R276
4.7kΩ
×8
XCLK0
Ethernet PHY setting
DIP switch (SW7)
: Optional
XCLK1
RESET
22Ω
VSS
* Refer to the supplemental circuit
diagram for the power and GND
pins.
22kΩ×3
VSS
VSS
0Ω
VSS
AVSS
P0CRS/GPIO6
VSS
0Ω
AVSS
P0COLSD/GPIO19
12.4kΩ 1%
VSS
RD-
AVSS
RESETB
X3
25MHz
RD+
RXN
EXTRES
ATP
TEST
REGOFFD
22Ω R58
P6_1/ETH_COL
RXP
2 DACK
3 TEND
Application header (JA6)
6
Application header (JA5)
7
20 IRQ0
TMR1
Application header (JA2)
22
21
20
19
18
17
16
15
Application header (JA1)
IO_7
IO_6
IO_5
IO_4
IO_3
IO_2
IO_1
IO_0
Figure 2.8 Ethernet Interface Block Diagram
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 14 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2.10
2. Function Specification
Emulator Interface
The R0K0F4022C000BR includes 14-pin E1 connector (J10) to connect to the emulator, and enables to connect to the E1
emulator.
Figure 2.9 shows the E1 connector block diagram.
1
GND1
3
DCK/TCK/FLSCK
TCK
5
DMS/TMS
DDI/TDI/FLSI/FLRXD
TMS
7
22Ω×3
TDI
MSEO0
9 TDO
11 MSEO0
MSEO1
MSEO1
DDO/TDO/FLSO/FLTXD
13
15 NC1
17 MCKO
22Ω
MCKO
19
22Ω×8
MDO0
3VCC
3VCC
OCD connector (J11)
22kΩ
22kΩ
22kΩ
3VCC
10kΩ
V850E2/ML4
10kΩ
22kΩ
3VCC
MDO2
27 MDO3
29
MDO4
31
MDO5
33
MDO6
35
MDO7
37
GND3
MDO3
MDO4
MDO5
MDO6
MDO7
VCCIO
TRST
RESET
FLMD0
TRDY
EVTO
EVTI
NC2
NC3
21 MDO0
23
MDO1
25 MDO2
MDO1
GND2
NC4
MDO8
MDO9
MDO10
MDO11
MDO12
MDO13
MDO14
MDO15
GND4
22kΩ
2
22kΩ
4
6
8
10
12
14
22Ω
16
18
20
22
24
26
28
30
32
34
36
38
VSS
DRST/TRST
RESET
TRDY
JP13
22Ω
FLMOD0
FLMOD1
JP12
EVTO
EVTI
22kΩ
E1 connector (J10)
3VCC
1
2
3
Operation mode setting
DIP switch (SW2)
4
5
6
FLMOD0
7
FLMOD1
VSS
9
22kΩ
22kΩ
8
10
11
12
VSS
13
14
: Optional
TCK
GND1
TRST
VSS
Reset module
(SW6)
FLMOD0
TDO
NC1
TDI
VDD
TMS/FLMOD1
PG-FP5 connector (J8)
RESET
FLMOD0
FLMOD1
RESET2
TRDY
GND2
RESET1
GND3
VSS
Figure 2.9 E1 Connector Block Diagram
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 15 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2.11
2. Function Specification
Switches
______________
The R0K0F4022C000BR includes push switches for reset, external interrupts (NMI, INTP1 and INTP2) and ADTRG input,
and DIP switches for users, operation mode setting and Ethernet PHY. The user DIP switch is connected to P8_0 to P8_3. The
operation mode setting DIP switch executes settings for the V850E2/ML4 FLMD0, FLMD1, MODE2 and MODE3 signals.
Refer to Figure 2.11 for these DIP switches, and Figure 2.8 for the Ethernet PHY DIP switch.
Figure 2.10 shows the push switch block diagram related to the external interrupt input.
3VCC
3VCC
10kΩ
4.7kΩ
220Ω
0Ω
INTP2 external
interrupt switch (SW5)
Open
Drain
3VCC
VSS
3VCC
4.7kΩ
10kΩ
0Ω
220Ω
INTP1 external
interrupt switch (SW4)
V850E2/ML4
Open
Drain
3VCC
VSS
10kΩ
4.7kΩ
JP1
0Ω
220Ω
NMI external interrupt
switch (SW3)
162
3VCC
166
149
P2_7/INTP2/TA1_I3/SCK1F
P2_3/INTP1/ADTRG20
P2_0/NMI
Open
Drain
VSS
0Ω
0Ω×4
Application header (JA1)
8
ADTRG20
Application header (JA2)
3
9
10
23
NMI
INTP1
SCIaCK
INTP2
Application header (JA5)
13
0Ω
TA1_I3
Application header (JA6)
17
-
USB function connector (J3)
: Optional
VBus
Figure 2.10 Push Switch Block Diagram
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 16 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2.12
2. Function Specification
LEDs and Potentiometer
The R0K0F4022C000BR includes four user LEDs (LED0 to LED3), a USB host bus LED (LED4), three Ethernet PHY LEDs
(LED6 to LED8), and a power LED (LED9). The user LEDs are controlled by the V850E2/ML4 P1_4, P1_5, P4_3 and P4_4.
The R0K0F4022C000BR also includes a potentiometer, which is connected to the ANI05 of the A/D converter.
Figure 2.11 shows LED (user LED) and potentiometer block diagram.
3VCC
LED3
(red)
LED2
(red)
V850E2/ML4
LED0
(green)
LED1
(orange)
P1_4/TA0_I4/TE0_AI/INTP9
P1_5/D21/TA0_I5
P4_3/A19
P4_4/A20
JA2-25
JA6-15
SW2-1
SW2-2
SW2-4
3VCC
SW2-3
JA3-40
Operation mode
setting DIP switch
(SW2)
0Ω
JA3-41
PG-FP5
(connector NOT
installed)
E1 connector (J10)
OCD (connector NOT
installed)
FLMD0
FLMD1 FLMD0
MODE3
MODE2
FLMD1
FLMD0
User DIP switch
(SW1)
9
JA1
SW1-1
SW1-2
SW1-4
3VCC
SW1-3
22kΩ×4
VSS
AVDD
10kΩ
Potentiometer
(VR1)
10kΩ
AVSS
P8_0/ANI06
10
P8_1/ANI07
11
P8_2/ANI08
12
JA5
ANI05
P8_3/ANI09
1
P8_4/ANI10
2
P8_5/ANI11
22kΩ×4
VSS
Figure 2.11 LED and Potentiometer Block Diagram
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 17 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2.13
2. Function Specification
Power Module
On the R0K0F4022C000BR, a 5V power supply is input to the board to generate 3.3V and 1.2 V using the regulator.
A 3.3V is input to the AVDD, although a 5V can be provided from the external power supply by removing the zero-ohm
resistor.
Figure 2.12 show the R0K0F4022C000BR power supply circuit block diagram.
IVDD
0Ω
5V→1.2V
5VCC
DC power
jack (J9)
IVDD
1kΩ
VSS
LED9
L7
IVDD
External J14
power
supply
DC5V
Input
PLLVDD
EVDD
VSS
0Ω
5V→3.3V
EVDD
L3
VSS
5VCC
External
power
supply
V850E2/ML4
OSCVDD
L4
J7
UVDD
VSS
DVDD
L5
3AVDD
AVDD
External
power
supply
L6
AVDD
J13
L8
VSS
0Ω
AVSS
AVSS
Note: PLLVSS、OSCVSS
pins are connected to VSS.
AVDD
External memory
(SDRAM、EEPROM)
EVDD
External J12
power
supply
Other devices and
connectors
VSS
■Coloring of Power Supply Lines
: test pin
5V system power supply line
: Optional (through-hole)
3.3V system power supply line
1.2V system power supply line
AVDD Power supply line (EVDD or external supply)
CAN/Level shifter
USB host interface
Character LCD
Figure 2.12 Power Supply Circuit Block Diagram
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 18 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2.14
2. Function Specification
Clock Module
The R0K0F4022C000BR connects the 10MHz resonator to the V850E2/ML4 X1 and X2 pins, and the 48MHz oscillator to the
UCLK pin.
A clock input can be provided to the EXTAL pin via the application header (JA2). In this case, remove the zero-ohm resistor of
X1 (R35) and install a zero-ohm (R2, not installed by default). A pull-up resistor (R29) can be installed if needed.
Figure 2.13 shows the R0K0F4022C000BR clock module block diagram.
V850E2/ML4
Application header (JA3)
P4_8/BUSCLK
3VCC
22Ω
44
SDCLK
Optional
Application header (JA2)
CON_EXTAL
R29
2
X1
P2_11/UCLK
X2
R34
0Ω
R35
0Ω
22Ω
SDRAM
CLK
0Ω
X1
10MHz
Oscillator
(48MHz)
VSS
VSS
Figure 2.13 Clock Module Block Diagram
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 19 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
2.15
2. Function Specification
Reset Module
____________
The R0K0F4022C000BR reset module generates RESET signal using the power-on reset and reset switch (SW).
Figure 2.14 shows the R0K0F4022C000BR reset module block diagram.
3VCC
E1 connector (J10)
22kΩ
RESET2
RESET1
PG-FP5
(connector NOT installed)
RESET
V850E2/ML4
OCD
(connector NOT installed)
3VCC
22kΩ
RESET
RESET
3VCC
System reset IC
OUT
VCC
0Ω
15kΩ
0.1uF
IN
10kΩ
GND
Cd
Ethernet PHY
JP13
4.7kΩ
Open drain output
RESETB
100Ω
0.1uF
Reset switch
(SW6)
Application header (JA2)
1
VSS
RESET
■Reset IC output delay time: td = 0.34×Cd(pF) = 34ms
(Min: 16ms, Max: 70ms)
■Reset IC output detect voltage:
Ra + Rb
Vs = 1.25　× = 3.125 V
Ra=15kΩ, Rb=10kΩ ->
Rb
Figure 2.14 Reset Module Block Diagram
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 20 of 20
V850E2/ML4 CPU Board R0K0F4022C000BR
3.
Operational Specification
3.1
Connector Overview
3. Operational Specification
Figure 3.1 shows the connector assignments for the R0K0F4022C000BR.
CAN connector
Serial port connector
LCD connector
J4
J5: RS-232C
Serial port
Character LCD
CAN
E1
connector
J6
UARTJ0
JA5
JA6
Application headers
J10
J10
E1
U1
V850E2/ML4
Ethernet
connector
ON
8
1
JA1
JA1
JA2
JA2
SW7
J2：RJ-45
U19
SDRAM
SW4
INTP1
SW1
JA3
JA3
SW5
INTP2
SW3
NMI
ON
1
SW2
USBF
ON
1
J3
4
USB function
connector
4
USBH
J1
SW6
RESET
J9
DC
USB host
connector
Figure 3.1 R0K0F4022C000BR Connector Assignments
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 1of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3.1.1
3. Operational Specification
Application Headers (JA1 to JA3, JA5 and JA6)
The R0K0F4022C000BR includes through-holes for mounting application headers (JA1 to JA3, JA5 and JA6) to
which the V850E2/ML4 I/O pins are connected. The standard MIL connectors can be implemented to the through-holes
to connect an expansion board.
Figure 3.2 shows the pin assignments, and Table 3.1 to Table 3.6 lists the pin descriptions for the application
headers (JA1 to JA3, JA5 and JA6).
JA5
JA6
JA1
JA2
JA3
Figure 3.2 Application Header Pin Assignments (JA1 to JA3, JA5 and JA6)
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 2of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3. Operational Specification
Table 3.1 Application Header (JA1) Pin Descriptions
Pin No.
Signal Name
Signal connected to JA1 by default
Other connection
1
5VCC
5VCC
2
GND
GND
3
3VCC
3VCC
4
GND
GND
5
AVDD
AVDD
6
AVSS
AVSS
7
AVDD
AVDD
8
P2_3 (JP1-3)
SW4 (INTP1), JA2-9
9
P2_3/INTP1/ADTRG20∗1,
P1_14/TA0_O14∗2
P8_0/ANI06
P8_0
SW1-1
10
P8_1/ANI07
P8_1
SW1-2
11
P8_2/ANI08
P8_2
SW1-3
12
P8_3/ANI09
P8_3
SW1-4
NC
-
∗2
13
P3_0/A0 ,
P5_9/INTP21∗2
14
NC
-
15
P5_14/HLDRQ/SI1/TA1_O14∗2,
P5_10/INTP22/TA1_O10∗2
P6_0
P6_0
Ethernet PHY (P0CRS)
16
P6_1
P6_1
Ethernet PHY (P0COLSD)
17
P6_2
P6_2
Ethernet PHY (P0TXD3)
18
P6_3
P6_3
Ethernet PHY (P0TXD2)
19
P6_8
P6_8
Etherne tPHY (P0TXERR)
20
P6_9
P6_9
Ethernet PHY (P0RXERR)
21
P6_13
P6_13
Ethernet PHY (P0RXD1)
22
P6_15
P6_15
Ethernet PHY (P0RXD3)
23
P2_10/INTP5/TA1_I6/TA1_O6
P2_10
USBH
24
NC
NC
-
25
P2_15/SDA1/CAN0TXD∗1,
P6_11/INTP22∗2
P2_14/SCL1/CAN0RXD∗1,
P6_12/INTP23∗2
P2_15 (JP10-1)
EEPROM (SDA)
P2_14 (JP8-1)
EEPROM (SCL)
26
_____________
Notes: 1. These pins are connected to through-holes via zero-ohm resistors (installed by default) and jumpers.
2.These pins are connected to through-holes via zero-ohm resistors (NOT installed by default).
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 3of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3. Operational Specification
Table 3.2 Application Header (JA2) Pin Descriptions
Pin No.
1
2
Signal Name
Signal connected to JA2 by default
____________
____________
RESET
X1∗3
∗1
Other connection
RESET
Ethernet PHY, E1
NC
-
P2_0
SW3 (NMI)
4
P2_0/NMI ,
P5_15/INTP27/TA１_O15∗3
GND
GND
-
5
NC
NC
-
6
P2_6/SO1F∗1,
P2_13/TXD0F∗3
P6_14/INTP25/TA0_I14/TA0_O14
P2_6
-
P6_14
Ethernet PHY (P0RXD2)
P2_8
-
P2_3 (JP1-3)
SW4 (INTP1), JA1-8
P2_7
SW5 (INTP2),
3
7
8
9
10
∗1
P2_8/SI1F ,
P2_12/RXD0F∗3
P2_3/INTP1/ADTRG20∗2,
P1_3/INTP8/TA0_I3/TA0_O3∗3,
P5_8/LUDQM/TXD1F∗3
P2_7/INTP2/TA1_I3/SCK1F∗1,
_______
P4_15/CS3
11
12
∗3
JA2-23, JA5-13
P1_9/TA0_I9/TA0_O9∗1,
P4_6/A22/SO0F∗3
P2_1/CSI1F_RYI/CSI1F_RYO/TXD0
P1_9
-
P2_1
-
P1_10
-
P1_11
-
P1_12
-
P1_13
-
P1_14
-
P1_15
-
19
P1_10/TA0_O10∗1,
P4_7/A23/SCK0F∗3
P1_11/TA0_O11∗1,
P2_5/TA1_I1∗3
P1_12/TA0_O12∗1,
P1_14/TA0_O14∗3,
P1_1/INTP6/TA0_O1∗3
P1_13/TA0_O13∗1
P2_9/TA1_I5∗3
P1_14/TA0_O14∗1
P1_12/TA0_O12∗3
P1_15/TA0_O15∗1,
P2_4/TA1_I0/TA1_O0∗3
P1_1/INTP6/TA0_O1
P1_1
-
20
P6_5/TA0_O5∗1,
P6_5
EtherPHY(P0 TXD0)
21
P5_6/SDWE/TE1_BI∗3
P1_0/TE0_TI0/INTP5
P1_0
-
P1_2
JA6-14
P2_7
SW5(INTP2),
13
14
15
16
17
18
___________
∗1
24
P1_2/TA0_I2/TE0_TI1 ,
P5_7/INTP19/RXD1F/LLDQM∗3
P2_7/INTP2/TA1_I3/SCK1F∗1,
P1_8/TE0_ZI/INTP13/TA0_I8/TA0_
O8∗3
P5_0/A24/ESO0
P5_0
-
25
P1_4/TA0_I4/TE0_AI/INTP9∗1
P1_4
LED0
26
P1_6/D22/TA0_I6/TE0_BI/INTP11∗1,
P1_6
JA6-16
22
23
_______
P4_14/CS2
JA2-10, JA5-13
∗3
Notes: 1.These pins are connected to through-holes via zero-ohm resistors (installed by default).
2.These pins are connected to through-holes via zero-ohm resistors (installed by default) and jumpers.
3.These pins are connected to through-holes via zero-ohm resistors (NOT installed by default).
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 4of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3. Operational Specification
Table 3.3 Application Header (JA3) Pin Descriptions (1/2)
Pin No.
Signal Name
Signal connected to JA3 by default
Other connection
1
P3_0/A0
P3_0
-
2
P3_1/A1
P3_1
SDRAM (A0)
3
P3_2/A2
P3_2
SDRAM (A1)
4
P3_3/A3
P3_3
SDRAM (A2)
5
P3_4/A4
P3_4
SDRAM (A3)
6
P3_5/A5
P3_5
SDRAM (A4)
7
P3_6/A6
P3_6
SDRAM (A5)
8
P3_7/A7
P3_7
SDRAM (A6)
9
P3_8/A8
P3_8
SDRAM (A7)
10
P3_9/A9
P3_9
SDRAM (A8)
11
P3_10/A10
P3_10
SDRAM (A9)
12
P3_11/A11
P3_11
SDRAM (A10)
13
P3_12/A12
P3_12
SDRAM (A11)
14
P3_13/A13
P3_13
-
15
P3_14/A14
P3_14
-
16
P3_15/A15
P3_15
-
17
P0_0/D0
P0_0
SDRAM (DQ0)
18
P0_1/D1
P0_1
SDRAM (DQ1)
19
P0_2/D2
P0_2
SDRAM (DQ2)
20
P0_3/D3
P0_3
SDRAM (DQ3)
21
P0_4/D4
P0_4
SDRAM (DQ4)
22
P0_5/D5
P0_5
SDRAM (DQ5)
23
P0_6/D6
P0_6
SDRAM (DQ6)
24
P0_7/D7
P0_7
SDRAM (DQ7)
P4_12
-
P4_11
-
P4_13
-
P4_14
-
P0_8/D8
P0_8
SDRAM (DQ8)
30
P0_9/D9
P0_9
SDRAM (DQ9)
31
P0_10/D10
P0_10
SDRAM (DQ10)
32
P0_11/D11
P0_11
SDRAM (DQ11)
33
P0_12/D12
P0_12
SDRAM (DQ12)
34
P0_13/D13
P0_13
SDRAM (DQ13)
35
P0_14/D14
P0_14
SDRAM (DQ14)
36
P0_15/D15
P0_15
SDRAM (DQ15)
25
26
_____
P4_12/RD
______ ______
∗1
P4_11/WR/RW ,
___________
P5_6/SDWE/TE1_BI∗2
27
_______
P4_13/CS1∗1,
_______
P4_15/CS3∗2
28
_______
P4_14/CS2∗1,
_______
P5_2/CS4∗2
29
Notes: 1. These pins are connected to through-holes via zero-ohm resistors (installed by default).
2.These pins are connected to through-holes via zero-ohm resistors (NOT installed by default).
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 5of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3. Operational Specification
Table 3.4 Application Header (JA3) Pin Descriptions (2/2)
Pin No.
37
38
Signal Name
P4_0/A16/TA1_O8
∗1
P4_1/A17 ,
Signal connected to JA3 by default
Other connection
P4_0
-
P4_1
-
P4_2
-
_____________
P5_11/SCK1/REFRQ/TA1_O11∗2
39
P4_2/A18∗1,
____________
P5_13/HLDAK/TA1_O13∗2
40
P4_3/A19
P4_3
LED2
41
P4_4/A20∗1,
P4_4
LED3
P4_5
JA6-12
P4_6
SDRAM (BA0), JA6-9
P4_7/A23/SCK0F
42
∗2
P4_5/A21/SI0F∗1,
P5_0/A24/ESO0∗2
43
P4_6/A22/SO0F∗1,
P5_1/A25/ESO2∗2
44
P4_8/BUSCLK
45
P2_2/WAIT/RXD0∗1,
_________
P4_8
SDRAM (CLK)
P2_2
-
_______
P4_14/CS2∗2
46
P5_3/TA1_O3/SDCKE
47
P4_10/LUWR ∗1,
___________
P5_3
SDRAM (CKE)
P4_10
-
P4_9
-
P5_5
SDRAM (CAS), JA5-17
P5_4
SDRAM (RAS), JA5-10
P5_8/LUDQM/TXD1F∗2
48
__________
P4_9/LLWR∗1,
P5_7
/RXD1F/LLDQM/TA1_I7/TA1_O7∗2
49
50
_____________
P5_5/TE1_AI/SDCAS
_____________
P5_4/INTP16/SDRAS /TA1_I4
Notes: 1. These pins are connected to through-holes via zero-ohm resistors (installed by default).
2.These pins are connected to through-holes via zero-ohm resistors (NOT installed by default).
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 6of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3. Operational Specification
Table 3.5 Application Header (JA5) Pin Descriptions
Pin No.
Signal Name
Signal connected to JA5 by default
Other connection
1
P8_4/ANI10
P8_4
-
2
P8_5/ANI11
P8_5
-
3
ANI00
ANI00
-
4
ANI01
ANI01
-
5
P2_15/SDA1/CAN0TXD∗2
P2_15 (JP10-3)
U20 (TxD)
6
P2_14/SCL1/CAN0RXD∗2,
P2_14 (JP8-3)
U21 (A)
NC
-
P7_0/INTP26∗3
7
NC
8
NC
NC
-
9
P5_7/INTP19 /RXD1F/LLDQM
P5_7
SDRAM (DQML)
10
P5_4/INTP16/SDRAS/TA1_I4
P5_4
SDRAM (RAS), JA3-50
11
P2_4/TA1_I0/TA1_O0∗2,
P2_4 (JP4-3)
-
P2_5
-
__________
_______
∗3
P1_15/TA0_O15
12
P2_5/TA1_I1∗1,
P1_11/TA0_O11∗3
13
P2_7/TA1_I3/SCK1F
P2_7
JA2-10, JA2-23
14
P2_9/TA1_I5∗2,
P2_9 (JP7-3)
-
P1_13/TA0_O13∗3
15
P4_0/A16/TA1_O8
P4_0
-
16
NC
NC
-
P5_5
SDRAM (CAS), JA3-49
17
_____________
P5_5/TE1_AI/SDCAS
___________
_______
______
18
P5_6/SDWE/TE1_BI
P5_6
SDRAM (WE)
19
P5_10/INTP22/TA1_O10
P5_10
LCD (J6-6)
_____________
20
P5_11/SCK1/REFRQ/TA1_O11
P5_11
LCD (J6-4), JA6-10
21
P5_12/SO1/TA1_O12
P5_12
LCD (J6-11), JA6-8
22
P5_13/HLDAK/TA1_O13
P5_13
LCD (J6-12)
23
P5_14/HLDRQ/SI1/TA1_O14
P5_14
LCD (J6-13), JA6-7
24
P5_15/INTP27/TA1_O15
P5_15
LCD (J6-14)
____________
_____________
Notes: 1.These pins are connected to through-holes via zero-ohm resistors (installed by default).
2.These pins are connected to through-holes via zero-ohm resistors (installed by default) and jumpers.
3.These pins are connected to through-holes via zero-ohm resistors (NOT installed by default).
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 7of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3. Operational Specification
Table 3.6 Application Header (JA6) Pin Descriptions
Pin No.
Signal Name
1
P1_7/INTP12
2
P6_6/DMAAK0
Signal connected to JA6 by default
_______________
_______________
Other connection
P1_7
-
P6_6
Ethernet PHY (P0TXEN)
Ethernet PHY (P0TXD1)
3
P6_4/DMATC0
P6_4
4
NC
NC
-
5
RS232TX (JP5-4)
RS232TX (JP5-4)
-
6
RS232RX (JP2-4)
7
P5_14/HLDRQ/SI1/TA1_O14∗1,
_____________
P5_7/INTP19/RXD1F/LLDQM
8
RS232RX (JP2-4)
-
P5_14
J6-13 (LCD), JA5-23
P5_12
J6-11 (LCD), JA5-21
∗2
P5_12/SO1/TA1_O12∗1,
P5_8/LUDQM/TXD1F∗2
9
P4_6/A22/SO0F∗1,
P4_6
____________
SDRAM (BA0),
JA3-43
P2_1/CSI1F_RYI/CSIF_RYO/BCYST
/TXD0∗2
_____________
10
P5_11/SCK1/REFRQ/TA1_O11
P5_11
J6-4 (LCD), JA5-20
11
P4_7/A23/SCK0F
P4_7
SDRAM (BA1)
P4_5
JA3-42
P1_8
-
12
∗1
P4_5/A21/SI0F ,
_________
P2_2/WAIT/RXD0∗2
13
P1_8/TE0_ZI/INTP13/TA0_I8/TA0_O8∗
1
,
____________
P2_1/CSI1F_RYI/CSI_F_RYO/BCYST
/TXD0∗2
14
P1_2/TA0_I2/TE0_TI1
P1_2
JA2-22
15
P1_5/D21/TA0_I5
P1_5
LED1
16
P1_6/D22/TA0_I6/TE0_BI/INTP11
P1_6
JA2-26
∗2
17
P2_0/NMI
NC
-
18
NC
NC
-
19
NC
NC
-
20
NC
NC
-
21
NC
NC
-
22
NC
NC
-
23
5VCC∗2
NC
-
24
GND
GND
-
Notes: 1. These pins are connected to through-holes via zero-ohm resistors (installed by default).
2.These pins are connected to through-holes via zero-ohm resistors (NOT installed by default).
[Precautions on using application headers]
The signals connected to JA1-15 to JA1-22, JA2-20, JA6-1 and JA6-2 are also connected to the device U17 as the Ethernet
PHY signals. These signals cannot be used as other pin functions. When using these signals as other pin functions, remove the
zero-ohm resistor (R261) and the 22-ohm resistors between JA1-15, JA1-16, JA1-20 to JA1-22 (R61, R58, R259, R68, R70
respectively), and install a 22-ohm resistor to R276. When pull-ups and pull-downs are required for the signals of JA1-17 to
JA1-19, JA2-7, JA2-20, JA6-1 and JA6-2, use the resistor with up to 10k ohms. The operational guarantee does not cover any
remodeling including a remove/install of a zero-ohm resistor to change the application header signal connection.
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 8of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3.1.2
3. Operational Specification
USB Connectors (J1 and J3)
The R0K0F4022C000BR includes a series A-receptacle (J1) as USB host connector, and a series Mini-B receptacle (J3)
as USB function connector.
Figure 3.3 shows USB Connector (J1 and J3) Pin Assignments. Table 3.7 and Table 3.8 list USB host connector (J1)
pin names and USB function connector (J3) pin names respectively.
12345
Top view of the component side
J1
J3
Side view
1 2 3 4
Figure 3.3 USB connector (J1 and J3) Pin Assignments
Table 3.7 USB Host Connector (J1) Pin Names
Pin No.
Signal Name
1
VBUS
2
DM
3
DP
4
GND
Table 3.8 USB Function Connector (J3) Pin Names
Pin No.
Signal Name
1
VBUS
2
DM
3
DP
4
ID (connected to test pin)
5
GND
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 9of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3.1.3
3. Operational Specification
Ethernet Connector (J2)
The R0K0F4022C000BR includes an Ethernet connector (J2).
Figure 3.4shows the Ethernet connector (J2) pin assignments. Table 3.9 lists the Ethernet connector (J2) pin names.
Top view of the
Top view of the
component side
surface
Board edge
Board edge
J2
7 5 3 1
1 3 5 7
8 6 4 2
2 4 6 8
Figure 3.4 Ethernet Connector (J2) Pin Assignments
Table 3.9 Ethernet Connector (J2) Pin Names
Pin No.
Signal Name
Pin No.
Signal Name
1
TD+
2
TD−
3
TCT
4
RD+
5
RD−
6
RCT
7
N.C.
8
GND
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 10of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3.1.4
3. Operational Specification
CAN Connector (J4)
The R0K0F4022C000BR includes the CAN connector (J4) to execute CAN transmission and reception.
Figure 3.5 shows the CAN connector (J4) pin assignments. Table 3.10 lists the CAN connector (J4) pin names
Top view of the
component side
3
1
Board
edge
J4
Figure 3.5 CAN Connector (J4) Pin Assignments
Table 3.10 CAN Connector (J4) Pin Names
Pin No.
Signal Name
1
CANH（U20）
2
GND
3
CANL（U20）
Note: P2_14/SCL1/CAN0RXD and P2_15/SDA1/CAN0TXD of the V850E2/ML4 are also connected to the EEPROM and
SCL signal and SDA signal of the application header (JA1). When using these connections, switch the connection at
JP8 and JP10. P2_14/SCL1/CAN0RXD and P2_15/SDA1/CAN0TXD of the V850E2/Ml4 are also connected to CAN
signal of the application header (JA5), and can be used by installing the zero-ohm resistor. CAN connector (J4)
cannot be used they are connected to the application header side.
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 11of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3.1.5
3. Operational Specification
Serial Port Connector (J5)
The R0K0F4022C000BR includes the serial port connector (J5). The serial port connector (J5) has two options for wiring
on the R0K0F4022C000BR, using a male jack with the crossover cable, or a female socket with the straight cable by
removing and installing zero-ohm resistors R109, R111, R112, R113, R115, R117, R118 and R119 as appropriate. The
R0K0F4022C000BR installs resistors R111, R113, R115 and R119 to include a male jack with crossover cable by
default.
Figure 3.6shows the serial port connector (J5) pin assignment on crossover cable by a male jack. Table 3.11 lists the
serial port connector (J5) pin names on crossover cable by a make jack.
Top view of the component side
Board edge
9
5
6
1
J9
Side view
Board edge
9
5
6
1
Figure 3.6 Serial Port Connector (J5) Pin Assignments (on crossover cable by a male jack)
Table 3.11 Serial Port Connector (J5) Pin Names (on crossover cable by a male jack)
Pin No.
1
Signal Name
Pin No.
Signal Name
NC
6
DSR
2
RXD
7
RTS
3
TXD
8
CTS
4
DTR
9
NC
5
GND
Note: Pins 4 to 6, and Pins 7 to 8 are loop-back connected respectively.
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 12of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3.1.6
3. Operational Specification
LCD Connector (J6)
The R0K0F4022C000BR includes the LCD connector (J6).
Figure 3.7shows the LDC connector (J6) pin assignments, and Table 3.12 lists the LCD connector pin names.
Top view of the
component side
Board edge
J6
14
13
2
1
Figure 3.7 LCD Connector (J6) Pin Assignments
Table 3.12 LCD Connector (J6) Pin Names
Pin No.
Signal Name
Pin No.
Signal Name
1
GND
2
5VCC
3
NC
4
LCDRS（P5_11）
5
R/W (Pulled down by a 1kΩ resistor)
6
LCDE（P5_10）
7
NC
8
NC
9
NC
10
NC
11
LCDD12（P5_12）
12
LCDD13（P5_13）
13
LCDD14（P5_14）
14
LCDD15（P5_15）
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 13of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3.1.7
3. Operational Specification
External Power Supply Connectors (J7 and J12 to J14)
The R0K0F4022C000BR includes four external power supply connectors (J7and J12 to J14) to apply 5V, 3.3V, 1.2V
power, and the A/D converter power directly from external source, not via the DC power jack (J9). J7 and J12 to J14
connectors are not installed by default.
When operating the R0K0F4022C000BR by supplying 5V power from the external supply connector (J7), do not connect
the AC adaptor to the DC power jack (J9). When supplying 3.3V power from the external supply connector (J12) to the
board, remove the zero-ohm resistor, R155. Alternatively, remove the zero-ohm resistor, R156, to supply the A/D
converter power from the external supply connector (J13), or remove the zero-ohm resistor, R162, to supply 1.2V power
from the external supply connector (J14) to the board.
Figure 3.8 shows the external power supply connectors (J7 and J12 to J14) pin assignments,. Table 3.13 to Table
3.16 list the external power supply connectors (J7 and J12 to J14) pin names.
Top view of the
component side
Board
edge
VR1
J13
1 2
J12
1 2
J14
1 2
J7
1
2
J9
Board
edge
Figure 3.8 External Power Supply Connectors Pin Assignments
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 14of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3. Operational Specification
Table 3.13 External Power Supply Connector (J7) Pin Names
Pin No.
1
Signal Name
5VCC（5V power supply）
Pin No.
2
Signal Name
GND
Table 3.14 External Power Supply Connector (J12) Pin Names
Pin No.
1
Signal Name
EVDD（3.3V power supply）
Pin No.
2
Signal Name
GND
Table 3.15 External Power Supply Connector (J13) Pin Names
Pin No.
1
Signal Name
AVDD（5V power supply）
Pin No.
2
Signal Name
GND
Table 3.16 External Power Supply Connector (J14) Pin Names
Pin No.
1
Signal Name
IVDD（1.2V power supply）
Pin No.
2
Signal Name
GND
Note: When supplying 5V from the external power supply connector (J7), do not connect AC adapter to DC power jack
(J9). The R0K0F4022C000BR and AC adapter may be destroyed when the power is supplied from the external
power supply connector (J7) with the AC adapter connected.
When supplying 3.3V, 1.2V power and the A/D converter power from the external power supply connector (J12,
J13 and J14), make sure to remove the zero-ohm resistors, R155, R156 and R162. The R0K0F4022C000BR may
be destroyed when 3.3V, 1.2V and the A/D converter power is supplied from the external power supply connector
(J12, J13 andJ14) with these resistors installed.
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 15of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3.1.8
3. Operational Specification
DC Power Jack (J9)
The R0K0F4022C000BR includes a DC power jack (J9).
Figure 3.9shows the DC power jack pin assignment. Table 3.17 lists the DC power jack pin names.
Top view of the
component side
Board edge
J9
3
2
3
1
Figure 3.9 DC Power Jack (J9) Pin Assignments
Table 3.17 DC Power Jack (J9) Pin Names
Pin No.
Signal name
1
GND
2
GND
3
5VCC
3
5VCC
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 16of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3.1.9
3. Operational Specification
E1 Connector (J10)
The R0K0F4022C000BR includes a 14-pin E1 connector (J10) to connect the E1 emulator.
Figure 3.10 shows the E1 connector (J10) pin assignments. Table 3.18 lists the E1 connector (J10) pin names
Top view of the
component side
Board
edge
J10
1
2
13
14
Figure 3.10 E1 Connector (J10) Pin Assignments
Table 3.18 E1 Connector (J1-) Pin Names
Pin No.
Signal Name
Pin No.
Signal Name
1
TCK
8
VDD
2
GND1
9
TMS/FLMD1
3
TRST
10
RESET2
4
FLMD0
11
TRDY
5
TDO
12
6
NC1
13
7
TDI
14
_________
R20UT0778EJ0100 Rev.1.00
May 31, 2012
______________
__________
GND2
______________
RESET1
GND3
page 17of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3.1.10
3. Operational Specification
GND Connector (J15)
The R0K0F4022C000BR includes a GND connector (J15).
Figure 3.11 shows the GND connector (J15) pin assignments. Table 3.19 lists the GND connector (J15) pin names.
Top view of the
component side
Board edge
J10
1
2
13
14
J15
3 2 1
Figure 3.11 GND Connector (J15) Pin Assignments
Table 3.19 GND Connector (J15) Pin Names
Pin No.
Signal Name
1
GND
2
GND
3
GND
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 18of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3.2
3. Operational Specification
Operating Components
The R0K0F4022C000BR includes switches, jumpers, LEDs and a potentiometer as operating components.
3.2.1
Jumpers (JP1, JP2, JP4, JP5, JP7 to JP13)
The R0K0F4022C000BR provides eleven jumpers (JP1, JP2, JP4, JP5 and JP7 to JP13).
3.2.1.1
P2_3 Select Jumper (JP1)
JP1 is a jumper to specify whether to use the V850E2/ML4 P2_3 for USB function control or for INTP1 (SW4) and a
9-pin of the application header (JA2) on the board. Short-circuit pins 1 and 2 of JP1 to use the USB function connector
(J3), and short-circuit pins 2 and 3 of JP1 to use the P2_3 as INTP1 (SW4) and a 9-pin of the application header (JA2).
Table 3.20 shows the P2_3 select jumper (JP1) settings.
Table 3.20 P2_3 Select Jumper (JP1) Settings
Number
JP1
Setting
Description
1–2
Uses the USB function connector (J3)
2–3
Connects the V850E2/ML4 P2_3 to INTP1 (SW4) and a 9-pin of the application header
(JA2)
【Note】
3.2.1.2
: set by default
Serial Port Received Signal Select Jumper (JP2)
JP2 is a jumper to switch signal wires the serial port received. Short-circuit pins 1 and 2 of JP2 when connecting the
V850E2/ML4 P2_3 to the serial port connector (J5). Short-circuit pin 2 and 4 of JP2 to connect a 6-pin (RS232RX) of
the application header (JA6) to the serial port connector (J5).
Table 3.21 shows the serial port received signal select jumper (JP2) settings.
Table 3.21 Serial Port Received Signal Select Jumper (JP2) Settings
Number
JP2
Setting
1–2
2–4
Description
Connects the V850E2/ML4 P2_12/RXD0F to the serial port connector (J5)
Connects a 6-pin (RS232RX) of the application header (JA6) to the serial port connector
(J5)
【Note】
: set by default
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 19of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3.2.1.3
3. Operational Specification
P2_4 Select Jumper (JP4)
JP4 is a jumper to specify whether to use the V850E2/ML4 P2_4 for the USB function control or for an 11-pin of the
application header (JA5) on the board. Short-circuit pins 1 and 2 of JP4 to use the USB function connector (J3), and
short-circuit pins 2 and 3 of JP4 to use P2_4 as an 11-pin of the application header (JA5).
Table 3.22 shows the P2_4 select jumper (JP4) settings.
Table 3.22 P2_4 Select Jumper (JP4) Settings
Number
JP4
【Note】
3.2.1.4
Setting
Description
1–2
Uses the USB function connector (J3)
2–3
Connects the V850E2/ML4 P2_4 to an 11-pin of the application header (JA5)
: set by default
Serial Port Transmitted Signal Select Jumper (JP5)
JP5 is a jumper to switch signal wires the serial port transmitted. Short-circuit pins 1 and 2 of JP5 when connecting the
V850E2/ML4 P2_13/TXD0F to the serial port connector (J5), and short-circuit pins 2 and 4 of JP5 to connect a 5-pin
(RS232TX) of the application header (JA6) to the serial port connector (J5).
Table 3.23 shows the serial port transmitted signal select jumper (JP5) settings.
Table 3.23 Serial Port Transmitted Signal Select Jumper (JP5) settings
Number
JP5
Setting
Description
1–2
Connects the V850E2/ML4 P2_13/TXD0F to the serial port connector (J5)
2–4
Connects a 5-pin (RS232TX) of the application header (JA6) to the serial port connector
(J5)
【Note】
3.2.1.5
: set by default
P2_9 Select Jumper (JP7)
JP7 is a jumper to specify whether to use the V850E2/ML4 P2-9 for the USB host control or for a 14-pin of the
application header (JA5) on the board. Short-circuit pins 1 and 2 of JP7 to use the USB host connector (J1), and
short-circuit pins 2 and 3 of JP7 to use P2_9 as a 14-pin of the application header (JA5).
Table 3.24 shows the P2_9 select jumper (JP7) settings.
Table 3.24 P2_9 Select Jumper (JP7) Settings
Number
JP7
【Note】
Setting
Description
1–2
Uses the USB host connector (J1)
2–3
Connects the V850E2/ML4 P2_9 to a 14-pin of the application header (JA5)
: set by default
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 20of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3.2.1.6
3. Operational Specification
P2_10 Select Jumper (JP9)
JP9 is a jumper to specify whether to use the V850E2/ML4 P2_10 of the USB host control or for a 23-pin of the
application header (JA5) on the board. Short-circuit pins 1 and 2 of JP9 to use the USB host connector (J1), and
short-circuit pins 2 and 3 of JP9 to use P2_10 as a 23-pin of the application header (JA5).
Table 3.25 shows P2_10 select jumper (JP9) settings.
Table 3.25 P2_-10 Select Jumper (JP9) Settings
Number
JP9
【Note】
3.2.1.7
Setting
Description
1–2
Uses the USB host connector (J1)
2–3
Connects the V850E2/ML4 P2_10 to a 23-pin of the application header (JA5)
: set by default
CAN－EEPROM Select Jumper (JP8)
JP8 is a jumper to specify whether to connect the V850E2/ML4 P2_14/SCL1/CAN0RXD to the CAN connector (J4) and
a 6-pin of the application header (JA5), or to the EEPROM and a 26-pin of the application header (JA1) on the board.
Short-circuit pins 2 and 3 of JP8 when connecting the V850E2/ML4 P2_14/SCL1/CAN0RXD to the CAN connector (J4)
and a 6-pin of the application, and short-circuit pins 1and 2 of JP8 to connect it to the EEPROM and a 26-pin of the
application header (JA1).
Table 3.26 shows the CAN-EEPROM select jumper (JP8) settings.
Table 3.26 CAN-EEPROM Switch Jumper (JP8) Settings
Number
JP8
Setting
1–2
Description
Connects the V850E2/ML4 P2_14/SCL1/CAN0RXD to the EEPROM and a 26-pin of the
application header (JA1)
2–3
Connects the V850E2/ML4 P2_14/SCL1/CAN0RXD to the CAN connector (J4) and a
6-pinof the application header (JA5)
【Note】
3.2.1.8
: set by default
CAN－EEPROM Select Jumper (JP10)
JP10 is a jumper to specify whether to connect the V850E2/ML4 P2_15/SDA1/CAN0TXD to the CAN connector (J4)
and a 5-pin of the application header (JA5), or to the EEPROM and a 25-pin of the application header (JA1) on the board.
Short-circuit pins 2 and 3 of JP10 when connecting the V850E2/ML4 P2_15/SDA1/CAN0TXD to the CAN connector
(J4) and a 5-pin of the application header (JA5), and short-circuit pin 1 and 2 of JP10 to connect it to the EEPROM and a
25-pin of the application header (JA1).
Table 3.27 shows the CAN-EEPROM select jumper (JP10) settings.
Table 3.27 CAN－EEPROM Select Jumper (J10) Settings
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 21of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
Number
JP10
Setting
1–2
3. Operational Specification
Description
Connects the V850E2/ML4 P2_15/SDA1/CAN0TXD to the EEPROM and a 25-pin of the
application header (JA5)
2–3
Connects the V850E2/ML4 P2_15/SDA1/CAN0TXD to the CAN connector (J4) and a 5-pin
of the application header (JA4)
【Note】
3.2.1.9
: set by default
SDRAM Jumper (JP11)
JP11 is a jumper to specify whether to use the SDRAM or the signal multiplexed with the SDRAM connection signal on
the side of the application header. Short-circuit JP11 only when using the SDRAM. The signal multiplexed with the
SDRAM connection signal on the side of the application cannot be used.
Table 3.28 shows the SDRAM jumper (JP11) settings.
Table 3.28 SDRAM Jumper (JP11) Settings
Number
Setting
JP11
Short
Uses the SDRAM
Description
Open
Uses the multiplexed signal with the SDRAM connection signal on the side of the
application header 用
【Note】
3.2.1.10
: set by default
OCD Jumper (JP12)
JP12 should be open to use.
3.2.1.11
PG-FP5 Connection Jumper (JP13)
JP13 is a jumper to specify the connection of the PG-FP5, the V850 internal flash writing tool. Short-circuit pins 2 and 3
when using the PG-FP5, and short-circuit pins 1 and 2 in any other case of the PG-FP5.
Table 3.29 shows the PG-FP5 connection jumper (J13) settings.
Table 3.29 PG-FP5 Connection Jumper (JP13) Settings
Number
JP13
【Note】
Setting
Description
1–2
Uses other than PG-FP5
2–3
Uses the PG-FP5
: set by default
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 22of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3.2.2
3. Operational Specification
Switches
The R0K0F4022C000BR includes a user DIP switch (SW1), an operation mode setting DIP switch (SW2), four push
switches (SW3 to SW6), and an Ethernet PHY DIP switch (SW7).
Table 3.30 lists switches on the R0K0F4022C000BR. Table 3.31 lists settings of the operation mode setting DIP
switch (SW2).Table 3.32 lists settings of the V850E2/ML4 operation mode setting. Table 3.33 lists settings of the
Ethernet PHY setting DIP switch (SW7).
Table 3.30 Switches on the R0K0F4022C000BR
Number
Function
Remarks
SW1
User DIP switch (4/package)
Refer to 2.12 for details
SW2
Operation mode setting DIP switch 4/package)
Refer to Table 3.32 for settings
SW3
External interrupt switch (NMI)
Refer to 2.11 for details
SW4
External interrupt switch (INTP1 input and ADTRG input)
Refer to 2.11 for details
SW5
External interrupt switch (INTP2)
Refer to 2.11 for details
SW6
Reset switch
Refer to 2.15 for details
SW7
Ethernet PHY setting DIP switch (8/package)
Refer to Table 3.33 for settings
____________
Table 3.31 Operation Mode Setting DIP Switch (SW2) Settings
Number
SW2-1
SW2-2
SW2-3
SW2-4
【Note】
Setting
Function
ON
Set theV850E2/ML4 MODE3 pin to high
OFF
Set theV850E2/ML4 MODE3 pin to low
ON
Set theV850E2/ML4 MODE2 pin to high
OFF
Set theV850E2/ML4 MODE2 pin to low
ON
Set theV850E2/ML4 FLMD1 pin to high
OFF
Set theV850E2/ML4 FLMD1 pin to low
ON
Set theV850E2/ML4 FLMD0 pin to high
OFF
Set theV850E2/ML4 FLMD0 pin to low
: set by default
Table 3.32 Settings of the V850E2/ML4 Operation Mode Setting
SW2-1
SW2-2
SW2-3
SW2-4
(MODE3)
(MODE2)
(FLMD1)
(FLMD0)
OFF
OFF
OFF
OFF
Normal operation mode
("L")
("L")
("L")
("L")
(Connectable with the E1 emulator)
OFF
OFF
OFF
ON
Flash memory programming mode
("L")
("L")
("L")
("H")
OFF
OFF
ON
ON
Boundary scan mode
("L")
("H")
("H")
(Setting prohibited for the R0K0F4022C000BR)
("L")
Combinations other than listed above
【Note】
V850E2/ML4 operation mode
Setting prohibited
: set by default
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 23of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3. Operational Specification
Table 3.33 Ethernet PHY DIP Switch (SW7) Settings
Number
Setting
SW7-1
ON
SW7-2
Function
Set P0RXD3 pin to low
Description
Autoneg disabled, 100BaseT
OFF
Set P0RXD3 pin to high
Autoneg enabled, 100BaseT
ON
Set P0RXD2 pin to low
If Autoneg disabled:Half Duplex
OFF
Set P0RXD2 pin to high
ON
Set P0RXCLK pin to low
Disable Quick Autonegotiation
OFF
Set P0RXCLK pin to high
If Autoneg enabled: Quick Autonegotiation, shortest times
If Autoneg enabled:Parallel detect ends in half duplex
If Autoneg disabled: Full Duplex
If Autoneg enabled: Forced Full Duplex in parallel detect
SW7-3
If Autoneg disabled: Special Isolate. In this mode the Phys will not
set up a link unless programmed and enabled through the SMI.
SW7-4
SW7-5
SW7-6
SW7-7
SW7-8
ON
Set P0RXERR pin to low
Configure RMII Interface
OFF
Set P0RXERR pin to high
Configure MII Interface
ON
Set P0TXCLK pin to low
Standard Mode, “JK” required for Start of Frame detection
OFF
Set P0TXCLK pin to high
Fast Mode, Only “J” required for Start of Frame detection
ON
Set P0CRS pin to low
AUTOMDI-X disabled
OFF
Set P0CRS pin to high
AUTOMDI-X enabled
ON
Set P0RXD0 pin to high
Configures the upper two bits N and M of the Phy addresses:
OFF
Set P0RXD0 pin to low
00: device uses address 00xxx for SMI
ON
Set P0RXD1 pin to high
01: device uses address 01xxx for SMI
OFF
Set P0RXD1 pin to low
10: device uses address 10xxx for SMI
11: device uses address 11xxx for SMI
【Note】
: set by default
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 24of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3.2.3
3. Operational Specification
Potentiometer
The R0K0F4022C000BR includes a potentiometer to evaluate AN105 input.
Table 3.34 lists the information of the potentiometer model installed on the R0K0F4022C000BR. For more details, refer
to the datasheet provided from the manufacturer.
Table 3.34 Potentiometer
Number
VR1
3.2.4
Part Number
CT-6ETV10KΩ
Manufacturer
NIDEC Copal Electronics Corporation
LEDs
The R0K0F4022C000BR includes four user LEDs (LED0 to LED3), a USB host bus LED (LED4), three Ethernet PHY
LEDs (LED6 to LED8), and a power LED (LED9).
Table 3.35 lists LEDs on the R0K0F4022C000BR.
Table 3.35 LEDs on the R0K0F4022C000BR
Number
Color
Description/Remarks
LED0
Green
User LED0 (illuminates when P1_4 outputs low level signal)
LED1
Orange
User LED1 (illuminates when P1_5 outputs low level signal)
LED2
Red
User LED2 (illuminates when P4_3 outputs low level signal)
LED3
Red
User LED3 (illuminates when P4_4 outputs low level signal)
LED4
Yellow
USB host bus LED (illuminates when the 5VCC is supplied)
LED6
Yellow
Ethernet PHY LED: LINK
LED7
Yellow
Ethernet PHY LED: ACT
LED8
Yellow
Ethernet PHY LED: DUPLEX
LED9
Blue
Power LED (illuminates when the 5VCC is supplied)
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 25of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
3.3
3. Operational Specification
Dimensions
Figure 3.12 shows the R0K0F4022C000BR dimensions.
125mm
12φ×6
118mm
105mm
7.0φ×4
3.2φ×4
3.2φ×6
17mm
35mm
7mm
7mm
R3×4
70.5mm
79.5mm
85mm
150.5mm
163mm
170mm
Figure 3.12 R0K0F4022C000BR Dimensions
R20UT0778EJ0100 Rev.1.00
May 31, 2012
page 26of 26
V850E2/ML4 CPU Board R0K0F4022C000BR
Appendix
Appendix
R0K0F4022C000BR Schematics
R20UT0778EJ0100 Rev.1.00
May 31, 2012
A-1
1
2
3
4
5
V850E2/ML4 CPU board R0K0F4022C000BR SCHEMATICS
A
A
TITLE
PAGE
INDEX
CPU (V850E2/ML4), Clock, User-port
USB, LAN, SDRAM
CAN, Serial-port, EEPROM, LCD
UDI, Reset, Push-SW, Power
Application Header
B
1
2
3
4
5
6
Note:
Digital GND (GND)
Analog GND (AVss)
Not mounted
5VCC = Digital 5V
3VCC = Digital 3.3V
EVDD = 3.3V for CPU I/O
VDD = 3.3V for UVDD(USB) & DVDD(Debug)
OSCVDD = 3.3V for Oscillator
3AVDD = Analog 3.3V for uPD60610
1.2VCC = 1.2V
IVDD = 1.2V for CPU Core
PLLVDD = 1.2V for PLL
AVDD = Analog 3.3V or 5V for ADC
R
RA
C
CE
CP
L
C
=
=
=
=
=
=
B
Fixed Resistors
Resistor Array
Ceramic Caps
Tantalum Electrolytic Caps
Decoupling Caps
Inductor
C
D
D
CHANGE
Renesas Solutions Corp.
DRAWN
SCALE
DATE
1
2
CHECKED
DESIGNED
INDEX
( 1
/ 6
D-R0K0F4022C000BR_C-B
12-05-15
3
APPROVED
R0K0F4022C000BR
4
5
)
1
2
3
4
5
P4_9
P4_10
P4_11
P4_12
P4_13
P4_14
P4_15
P5_9
P5_9/INTP21
LCD
P6_0
P6_1
P6_2
P6_3
P6_4
P6_5
P6_6
P6_7
P6_8
P6_9
P6_10
P6_11
P6_12
P6_13
P6_14
P6_15
P5_2/ESO3/TA1_I2/SI0/CS4/TA1_O2
P5_3/INTP15/TA1_I3/TE1_TI0/CSI0_SSI/SDCKE/TA1_O3/ADCNV1
P5_4/INTP16/TA1_I4/TE1_TI1/CSI0_RYI/SDRAS/TA1_O4/CSI0_RYO/ADCNV2
P5_5/INTP17/TA1_I5/TE1_AI/RXD1/SDCAS/TA1_O5
P5_6/INTP18/TA1_I6/TE1_BI/SDWE/TA1_O6/TXD1
P5_7/INTP19/TA1_I7/TE1_ZI/RXD1F/LLDQM/TA1_O7
P5_8/INTP20/TA1_I8/LUDQM/TA1_O8/TXD1F
P5_9/INTP21/TA1_I9/CSI1_SSI/ULDQM/TA1_O9/DMAAK2
P5_10/INTP22/TA1_I10/CSI1_RYI/UUDQM/TA1_O10/DMATC2/CSI1_RYO1
P5_11/INTP23/TA1_I11/SCK1/REFRQ/TA1_O11/DMAAK4
P5_12/INTP24/TA1_I12/SO1/BUSRQ/TA1_O12/DMATC4
P5_13/INTP25/TA1_I13/HLDAK/TA1_O13
P5_14/INTP26/TA1_I14/HLDRQ/SI1/TA1_O14
P5_15/INTP27/TA1_I15/TA1_O15
75
76
77
78
79
80
81
82
83
84
91
92
93
94
95
96
P6_0/INTP0/ETH_CRS/TA0_I0/TE0_TI0/TA0_O0
P6_1/INTP1/ETH_COL/TA0_I1/TA0_O1
P6_2/INTP2/ETH_TXD3/TA0_I2/TE0_TI1/TA0_O2
P6_3/INTP3/ETH_TXD2/TA0_I3/TA0_O3
P6_4/INTP4/ETH_TXD1/TA0_I4/TE0_AI/DMATC0/TA0_O4
P6_5/ETH_TXD0/TA0_I5/DMATC1/TA0_O5
P6_6/ETH_TXEN/TA0_I6/TE0_BI/DMAAK0/TA0_O6
P6_7/ETH_TXCLK/TA0_I7/DMAAK1/TA0_O7
P6_8/ETH_TXER/TJ_I0/TA0_I8/TE0_ZI/TJ_O0/TA0_O8
P6_9/ETH_RXER/TJ_I1/TA0_I9/TJ_O1/TA0_O9
P6_10/ETH_RXCLK/INTP21/TA0_I10/TA0_O10
P6_11/ETH_RXDV/INTP22/TA0_I11/TA0_O11
P6_12/ETH_RXD0/INTP23/TA0_I12/TA0_O12
P6_13/ETH_RXD1/INTP24/TA0_I13/TA0_O13
P6_14/ETH_RXD2/INTP25/TA0_I14/TA0_O14
P6_15/ETH_RXD3/TA0_I15/TA0_O15
P7_0
P7_1
97
98
P7_0/ETH_MDC/TJ_I2/INTP26/TJ_O2
P7_1/ETH_MDIO/TJ_I3/INTP27/TJ_O3
[6] ANI_[11:0]
R28
2
ANI_5
10kΩ
1
3VCC
ANI_6
ANI_7
ANI_8
ANI_9
8
7
6
5
R30
R31
R32
R33
R34
_0Ω
22kΩ
22kΩ
22kΩ
22kΩ
1
2
3
4
R29
_22kΩ
SW1
A6S-4104
OMRON
3VCC
ANI_6
ANI_7
ANI_8
ANI_9
ANI_10
ANI_11
139
138
137
136
135
134
ANI00
ANI01
ANI02
ANI03
ANI04
ANI05
129
128
127
126
125
124
P8_0/ANI06
P8_1/ANI07
P8_2/ANI08
P8_3/ANI09
P8_4/ANI10
P8_5/ANI11
144
145
R35
0Ω
R36
0Ω
X1
X2
140
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
P1_8
P1_9
P1_10
P1_11
P1_12
P1_13
P1_14
P1_15
UDPH
UDMH
UDPF
UDMF
52
51
48
47
R7
R8
R9
R10
27Ω
27Ω
27Ω
27Ω
MDO0
MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7
MCKO
MSEO0
MSEO1
108
107
106
105
104
103
102
101
109
113
110
R11
R12
R13
R14
R15
R16
R17
R18
R19
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
EVTI
EVTO
114
115
DCK/TCK/FLSCK
DDI/TDI/FLSI/FLRXD
DDO/TDO/FLSO
121
118
117
R22
22Ω
DMS/TMS
DRST/TRST
TRDY
120
119
116
R25
22Ω
RESET
148
R250
R251
R252
R253
R254
R255
R256
22kΩ
22kΩ
22kΩ
22kΩ
22kΩ
22kΩ
22kΩ
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
RA3 MNR14_22kΩ
1
8
2
7
3
6
4
5
P0_4
P0_5
P0_6
P0_7
P0_8
P0_9
P0_10
P0_11
RA5 MNR14_22kΩ
1
8
2
7
3
6
4
5
P0_8
P0_9
P0_10
P0_11
RA6 MNR14_22Ω
1
8
2
7
3
6
4
5
D8
D9
D10
D11
P0_12
P0_13
P0_14
P0_15
RA7 MNR14_22kΩ
1
8
2
7
3
6
4
5
P0_12
P0_13
P0_14
P0_15
RA8 MNR14_22Ω
1
8
2
7
3
6
4
5
D12
D13
D14
D15
LED0
SML-310MT
P1_4
Application
Header
C1
22pF
R3
1.5kΩ
RA4
1
2
3
4
MNR14_22Ω
8
7
6
5
D0
D1
D2
D3
D4
D5
D6
D7
A
3VCC
SML-310MT
SML-310DT
SML-310VT
SML-310YT
Green
LED1
R4
SML-310DT 1.5kΩ
P1_5
:
:
:
:
Green
Orange
Red
Yellow
Orange
UDPH
UDMH
UDPF
UDMF
[3]
[3]
[3]
[3]
USB
MDO[7:0] [5]
MDO0
MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7
B
UDI, ROM-writer
MCKO [5]
MSEO0 [5]
MSEO1 [5]
EVTI# [5]
EVTO# [5]
TCK [5]
TDI [5]
TDO [5]
TMS [5]
TRST# [5]
TRDY# [5]
3VCC
RESET# [3,5,6]
3VCC
R26
22kΩ
R27
22kΩ
P2_[15:0] [5,6]
USB_CTRL[3:0]
P2_0/NMI
P2_1/INTP0/ADTRG00/CSI1F_RYI/BCYST/TXD0/CSI‚PF_RYO
P2_2/WAIT/ADTRG10/RXD0/CSI1F_SSI
P2_3/INTP1/ADTRG20/ULBE/ULWR/CSI1F_CS0
P2_4/ESO0/TA1_I0/UUBE/TA1_O0/UUWR/CSI1F_CS1
P2_5/ESO2/TA1_I1/TA1_O1/CSI1F_CS2
P2_6/ESO3/TA1_I2/SO1F/DMAAK3/TA1_O2/ADCNV0
P2_7/INTP2/TA1_I3/TE1_TI0/SCK1F/DMATC3/TA1_O3/ADCNV1
P2_8/INTP3/TA1_I4/TE1_TI1/SI1F/TA1_O4
P2_9/INTP4/TA1_I5/TE1_AI0/OCI/TA1_O5/CSI1F_CS3
P2_10/INTP5/TA1_I6/TE1_BI0/PPON/TA1_O6/CSI1F_CS4
P2_11/INTP6/TA1_I7/TE1_ZI0/UCLK/TA1_O7/CSI1F_CS5
P2_12/TJ_I0/SCL0/RXD0F/TJ_O0
P2_13/TJ_I1/ADTRG01/SDA0/TJ_O1/TXD0F
P2_14/TJ_I2/ADTRG11/SCL1/CAN0RXD/TJ_O2
P2_15/TJ_I3/ADTRG21/SDA1/TJ_O3/CAN0TXD
MODE3
MODE2
FLMD1
FLMD0
149
170
167
166
165
164
163
162
161
160
159
158
157
156
155
154
JP1
P2_0
P2_1
P2_2
USB_CTRL0
USB_CTRL1
3
USB_CTRL0
P2_5
P2_6
P2_7
P2_8
USB function's
VBUS interrupt
1
USB_CTRL1
USB_CTRL2
2
USB_CTRL3
2
P2_4/UDPF
HWP-3P-G
P2_9
3
4
3
23
22
1
2
3
4
JP9
3VCC
8
7
6
5
3
P2_9/OCI# [3]
1
FLMD0 [5]
FLMD1 [5]
CP1
0.1µF
2
GND OE
[3]
P2_13
[6] SCIaTX
JP5
FFC-4BMEP
HONDA
2
4
P2_13/TXD0F [4]
RS232TX [6]
1
3
JP8
P2_14
HWP-3P-G
P2_10
P2_10/PPON [3]
P2_15
3
P2_14/CAN0RXD
1
P2_14/SCL1 [4,6]
2
2
R42
22Ω
C
HWP-3P-G
[4,6]
JP10 HWP-3P-G
3
P2_15/CAN0TXD [4,6]
1
X1
SG-8002JF_48MHz
EPSON
4 VCC OUT 3
3VCC
P2_12/RXD0F [4]
RS232RX [6]
USB function's
Over-current interrupt
1
SW2
A6S-4104
OMRON
[6] SCIaRX
JP2
FFC-4BMEP
HONDA
1
2
3
4
USB function's
Pull-up registor ON/OFF#
1
JP7
P2_12
P2_3/INTP1 [3]
HWP-3P-G
P2_4
3
2
USB_CTRL2
USB_CTRL3
P2_11
P2_12
P2_13
P2_14
P2_15
HWP-3P-G
P2_3
2
JP4
R39
1MΩ
ANI_0
ANI_1
ANI_2
ANI_3
ANI_4
ANI_10
ANI_11
D[15:0] [3,6]
RA1 MNR14_22kΩ
1
8
2
7
3
6
4
5
P1_[15:0] [6]
X2
1
ROHM
RA2 MNR14_22Ω
1
8
2
7
3
6
4
5
P0_0
P0_1
P0_2
P0_3
P2_15/SDA1 [4,6]
P2_11
1
R40
R41
R37
R38
VR1
CT-6ETV10kΩ
COPAL
ANI_0
ANI_1
ANI_2
ANI_3
ANI_4
ANI_5
3
PLLVDD
188
187
184
183
182
181
180
177
176
175
174
173
172
171
22Ω
22Ω
22Ω
22Ω
AVDD
5
43
44
69
87
88
150
151
178
199
200
122
P5_2
P5_3
P5_4
P5_5
P5_6
P5_7
P5_8
P5_9
P5_10
P5_11
P5_12
P5_13
P5_14
P5_15
[3,6] P7_[1:0]
C
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
P5_0/ESO0/TA1_I0/SO0/A24/TA1_O0
P5_1/ESO2/TA1_I1/SCK0/A25/TA1_O1
R20
R21
R23
R24
Ethernet
99
111
190
189
[3,6] P6_[15:0]
Ethernet
142
P5_0
P5_1
[3,4,6] P5_[15:0]
SDRAM
OSCVDD
P4_8/BUSCLK
P4_9/LLBE/LLWR
P4_10/LUBE/LUWR
P4_11/WR/RW
P4_12/RD
P4_13/CS1
P4_14/CS2/DMAAK5/CSI1F_CS7
P4_15/CS3/DMATC5/CSI1F_CS6
22Ω
22Ω
B
49
198
197
196
195
194
193
192
191
R5
R6
55
56
57
58
59
60
61
62
63
64
65
66
71
72
73
74
Data-Bus
22kΩ
22kΩ
22kΩ
22kΩ
[3,6] P4_8/BUSCLK
P1_0/D16/TA0_I0/TE0_TI0/INTP5/TA0_O0
P1_1/D17/TA0_I1/OCI/INTP6/TA0_O1
P1_2/D18/TA0_I2/TE0_TI1/INTP7/TA0_O2
P1_3/D19/TA0_I3/INTP8/TA0_O3/PPON
P1_4/D20/TA0_I4/TE0_AI/INTP9/TA0_O4
P1_5/D21/TA0_I5/INTP10/TA0_O5
P1_6/D22/TA0_I6/TE0_BI/INTP11/TA0_O6
P1_7/D23/TA0_I7/INTP12/TA0_O7
P1_8/D24/TA0_I8/TE0_ZI/INTP13/TA0_O8
P1_9/D25/TA0_I9/INTP14/TA0_O9
P1_10/D26/TA0_I10/INTP15/TA0_O10
P1_11/D27/TA0_I11/INTP16/TA0_O11
P1_12/D28/TA0_I12/INTP17/TA0_O12
P1_13/D29/TA0_I13/INTP18/TA0_O13
P1_14/D30/TA0_I14/INTP19/TA0_O14
P1_15/D31/TA0_I15/INTP20/TA0_O15
PLLVSS
Red
SDRAM
DVDD
DVDD
P4_0/A16/INTP7/TA1_I8/TA1_O8/CSI0F_CS2
P4_1/A17/INTP8/TA1_I9/TA1_O9/CSI0F_CS1
P4_2/A18/INTP9/TA1_I10/TA1_O10/CSI0F_CS0
P4_3/A19/INTP10/TA1_I11/CSI0F_RYI/TA1_O11/CSI0F_RYO
P4_4/A20/INTP11/TA1_I12/CSI0F_SSI/TA1_O12
P4_5/A21/INTP12/TA1_I13/SI0F/TA1_O13
P4_6/A22/INTP13/TA1_I14/SO0F/TA1_O14
P4_7/A23/INTP14/TA1_I15/SCK0F/TA1_O15
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P0_8
P0_9
P0_10
P0_11
P0_12
P0_13
P0_14
P0_15
OSCVSS
Red
LED3 SML-310VT
P4_4
1
19
20
36
53
67
85
146
168
185
203
212
211
210
209
208
207
206
205
25
26
27
28
29
30
31
32
33
34
35
38
39
40
41
42
141
P4_0
P4_1
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
P4_8
3VCC
P0_0/D0
P0_1/D1
P0_2/D2
P0_3/D3
P0_4/D4
P0_5/D5
P0_6/D6
P0_7/D7
P0_8/D8
P0_9/D9
P0_10/D10
P0_11/D11
P0_12/D12
P0_13/D13
P0_14/D14
P0_15/D15
143
1.5kΩ
LED2 SML-310VT
P4_3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1.5kΩ
2
6
21
24
37
45
46
50
54
68
70
86
89
90
100
112
123
147
152
153
169
179
186
201
202
204
R1
P3_0/A0
P3_1/A1
P3_2/A2
P3_3/A3
P3_4/A4
P3_5/A5
P3_6/A6
P3_7/A7
P3_8/A8
P3_9/A9
P3_10/A10
P3_11/A11/CSI0F_CS7
P3_12/A12/CSI0F_CS6
P3_13/A13/CSI0F_CS5
P3_14/A14/CSI0F_CS4
P3_15/A15/CSI0F_CS3
AVREFM
AVSS
R2
PLLVDD
18
17
16
15
14
13
12
11
10
9
8
7
216
215
214
213
[3,6] P4_[15:0]
3VCC
1.2V
IVDD
130
132
A
1.2V
OSCVDD
UVDD
P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6
P3_7
P3_8
P3_9
P3_10
P3_11
P3_12
P3_13
P3_14
P3_15
Address
3.3V
VDD
AVDD
AVREFP
U1
V850E2/ML4
Renesas
3.3V
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
EVDD
3.3V/5V
[3,6] P3_[15:0]
3.3V
AVDD
133
131
P0_[15:0]
3
C2
22pF
AVDD
CP2
X10M000000S006
AEL
EVDD
CP3
+ CE1
0.1µF 0.1µF 4.7µF
CP4
OSCVDD
CP5
CP6
CP7
CP8
CP9
CP10 CP11 CP12 CP13 CP14
+ CE2
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 4.7µF
CP15
VDD
+ CE3
0.1µF 4.7µF
IVDD
CP16 CP17 CP18
+ CE4
0.1µF 0.1µF 0.1µF 4.7µF
PLLVDD
CP19 CP20 CP21 CP22 CP23 CP24 CP25 CP26 CP27 CP28 CP29 CP30
+ CE5
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 4.7µF
CP31
+ CE6
0.1µF 4.7µF
[6] X1
D
D
OSCVDD
UVDD
DVDD
CHANGE
Renesas Solutions Corp.
DRAWN
CHECKED
APPROVED
DESIGNED
R0K0F4022C000BR
CPU V850E2/ML4
( 2
SCALE
D-R0K0F4022C000BR_C-B
DATE
1
2
12-05-15
3
4
5
/ 6
)
1
2
3
4
5
3VCC
C8
R77
2
VBus
DD+
GND
FG3
FG2
FG1
FRAME
9
8
7
6
[2,5,6] RESET#
40
RESETB
R261
0Ω
D2
_HZM6.2Z4MFA
32
33
R78
_1MΩ
X3
1
3
C9
22pF
C10
22pF
X25M000000S006
AEL
25MHz : MII mode
50MHz : RMII mode
R81
CP39
0.1µF
OE
H
H
L
A
H
L
x
Y
H
L
Z
R45
SML-310MT
22Ω
LED8
R72
0Ω
XCLK0
XCLK1
R80
R271
R272
R273
4
3
3VCC
VDDIO
VDDIO
VDDIO
19
31
38
VDD33ESD
VDDA33REG
10
46
AVOUT15
VDDA15
VDDAPLL
45
9
47
DVOUT15
VDD15
37
11
49.9Ω-1/4W
49.9Ω-1/4W
P0TXCLK
P0TXEN
P0TXD0
P0TXD1
P0TXD2 / GPIO11
P0TXD3 / GPIO10
P0TXERR / GPIO9
10Ω-1%
10Ω-1%
30
25
26
27
28
29
35
6
7
R64
R262
22Ω
P0RXP
P0RXN
0.01µF
0.01µF
R71
3
4
J2
TLA-6T717W
TDK
1
2
3
4
5
6
7
8
TD+
TDTCT
RD+
RDRCT
N.C. FG
GND FG
9
10
C7
C17
P6_7
P6_6
P6_5
P6_4
P6_3
P6_2
P6_8
P0TXP
P0TXN
49.9Ω-1/4W
49.9Ω-1/4W
P0RXCLK / GPIO3
P0RXDV
P0RXD0
P0RXD1
P0RXD2 / GPIO8
P0RXD3 / GPIO7
P0RXERR
R60
R63
16
23
22
21
18
17
24
R62
R59
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
_10pF
_10pF
R65
R67
R66
R68
R69
R70
R259
12
15
34
_10pF
_10pF
P6_10
P6_11
P6_12
P6_13
P6_14
P6_15
P6_9
P0LINKLED / GPIO0
INT / GPIO4
GPIO14
C5
C6
P0CRS / GPIO6
P0COLSD / GPIO19
_22kΩ
1
2
3
5
TP1
USB_ID
PU
PU
PU
PU
PU
PU
PD
PD
39
42
R276
1kΩ
5
4
3
1µF
1.8kΩ
100kΩ
100kΩ
1.5kΩ
22kΩ
[2] P2_4/UDPF
U18
EVDD HD74LV1GT126A
Renesas
1 OE
2 A
Y
5 VCC
GND
R75
R76
R74
B
1
R73
[2] P2_3/INTP1
[2] UDMF
[2] UDPF
4
:
:
:
:
:
:
:
:
22Ω
22Ω
C3
C4
J3
54819-0572
MOLEX
P6_15
P6_14
P6_10
P6_9
P6_7
P6_0
P6_12
P6_13
16
15
14
13
12
11
10
9
P6_15/P0RXD3
P6_14/P0RXD2
P6_10/P0RXCLK
P6_9 /P0RXERR
P6_7 /P0TXCLK
P6_0 /P0CRS
P6_12/P0RXD0
P6_13/P0RXD1
USB (Function)
VIH(Min)=EVDD*0.8=2.64V
ID
1
2
3
4
5
6
7
8
MDC
MDIO
R61
R58
3AVDD
B
+
+
+
0.1µF
10µF
4.7kΩ
4.7kΩ
4.7kΩ
4.7kΩ
4.7kΩ
4.7kΩ
4.7kΩ
4.7kΩ
13
14
P6_0
P6_1
+
CP35
CE8
5
4
3
R56
R57
SW7
A6FH-8102
OMRON
R263
R264
R265
R266
R267
R268
R269
R270
D1
_HZM6.2Z4MFA
4.40V*1.8kR/(1kR+1.8kR)=2.829V
5.00V*1.8kR/(1kR+1.8kR)=3.214V
5.25V*1.8kR/(1kR+1.8kR)=3.375V
P7_0
P7_1
[2,6] P6_[15:0]
3VCC
0.1µF
0.1µF
10µF
5
A
CP64
CP65
CE25
7
6
B'0000
LinkA (GPIO0)
FD (GPIO14)
MUX 100BT/10BT (Not used)
Activity (GPIO4)
3AVDD
R277
FG2
FG1
FRAME
U17
uPD60610
Renesas
330Ω
330Ω
2
1
VBus
DD+
GND
[2,6] P7_[1:0]
R47
R44
1
2
3
4
[2] UDMH
[2] UDPH
15kΩ
15kΩ
J1
UBA-4R-D14T-4D
JST
:
:
:
:
:
P5_9/INTP21
0.1µF
0.1µF
10µF
CP32
0.1µF
+ CE7
150µF/16V
Green
Orange
Red
Yellow
LED_MODE
LED0
LED1
LED2
LED3
CP37
CP38
CE10
5
NC2
:
:
:
:
SML-310MT
NC1
SML-310MT
SML-310DT
SML-310VT
SML-310YT
Ethernet
LED6
4
USB (Host)
0.1µF
0.1µF
0.1µF
10µF
6
CP34
CP33
CP36
CE9
7
3VCC
P0AGND
P0AGND
GNDAREF
GNDAPLL
IN
GND OUT1
LED4
SML-310MT
1.5kΩ
GNDIO
GNDIO
FLG
3
R48
5
8
43
48
2
R49
22kΩ
8
20
36
[2] P2_9/OCI#
A
OUT2
EXTRES
ATP
TEST
REGOFFD
EN
1.5kΩ
1
R50
[2] P2_10/PPON
12.4kΩ, 1% 1
22kΩ
2
22kΩ
41
22kΩ
44
R43
0Ω
SML-310MT
5VCC
U16
MIC-2025-2YM
MICREL
LED7
EN : Active-low
FLG : Active-low, Open-drain output.
330Ω
MIC-2025-2YM
EXTRES : Must be connect to GND via 12.4Kohm resister
REGOFFD : Regulator disable for digital, Hi: Regulator OFF, Low: ON
ATP, TEST : Must be connect to GND
[2,6] D[15:0]
[2,6] P4_[15:0]
P4_[7:0] = A[23:16]
[2,6] P3_[15:0]
P3_[15:0] = A[15:0]
SDRAM (16MB)
3VCC
P3_12
P3_11
P3_10
P3_9
P3_8
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
_22kΩ
22kΩ
22kΩ
22kΩ
22kΩ
22kΩ
22kΩ
R83
R84
R85
R86
R87
R88
JP11
HWP-2P-G
1
2
R82
C
21
20
BA1
BA0
35
22
34
33
32
31
30
29
26
25
24
23
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
19
18
17
16
CS
RAS
CAS
WE
P5_2
P5_4
P5_5
P5_6
P5_8/LUDQM
P5_7/LLDQM
P5_8
P5_7
39
15
DQMH
DQML
P5_3/SDCKE
P5_3
37
38
CKE
CLK
[2,6] P4_8/BUSCLK
R90
R91
_22kΩ
_22kΩ
CP40
_18pF
28
41
54
R89
22kΩ
VSS
VSS
VSS
P5_2/CS4#
P5_4/SDRAS#
P5_5/SDCAS#
P5_6/SDWE#
6
12
46
52
P4_7
P4_6
VSSQ
VSSQ
VSSQ
VSSQ
U19
MT48LC8M16A2
Micron
[2,4,6] P5_[15:0]
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
53
51
50
48
47
45
44
42
13
11
10
8
7
5
4
2
NC1
NC2
40
36
VDD
VDD
VDD
1
14
27
VDDQ
VDDQ
VDDQ
VDDQ
3
9
43
49
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
C
3VCC
3VCC
CP41
0.1µF
CP42
0.1µF
CP43
0.1µF
CP44
0.1µF
CP45
0.1µF
CP46
0.1µF
CP47
0.1µF
+ CE11
4.7µF
D
D
CHANGE
Renesas Solutions Corp.
DRAWN
CHECKED
APPROVED
DESIGNED
R0K0F4022C000BR
USB, LAN, SDRAM
( 3
SCALE
D-R0K0F4022C000BR_C-B
DATE
1
2
12-05-15
3
4
5
/ 6
)
1
2
3
4
5
3VCC
CAN
3VCC
3VCC
R100
22kΩ
R102
0Ω
[2,6] P2_14/CAN0RXD
CP49
0.1µF
TxD
VCC
5VCC
3
5VCC
U21
SN74LVC1T45DCK
TI
1 VCCA VCCB 6
2 GND
DIR 5
3 A
B 4
5VCC
R101
22kΩ
5
NC
GND
MODE
CANH
2
8
7
4
RxD CANL
6
CP48
0.1µF
J4
B3P-SHF-1AA(LF)(SN)
JST
1
2
3
CP50
0.1µF
3.3V<-5V
R95
4.7kΩ
R96
4.7kΩ
R97
_22kΩ
EEPROM(64KB)
_22kΩ
_22kΩ
_22kΩ
3VCC
1
U22
AT24C64B
ATMEL
[2,6] P2_14/SCL1
6
SCL
[2,6] P2_15/SDA1
5
SDA
7
WP
4
GND
R103
120Ω-1/4W
R104
22kΩ
A2
A1
A0
3
2
1
VCC
8
A
Device address [0xA0(W), 0xA1(R)]
3VCC
22kΩ
22kΩ
22kΩ
U20
HA13721RPJE
RENESAS
R92
22kΩ
R93
0Ω
[2,6] P2_15/CAN0TXD
CP51
0.1µF
R105
R106
R107
A
R98
R99
R94
3VCC
3VCC
CP52 0.1µF
[2] P2_12/RXD0F
C1+
C1C2+
C15
0.47µF 6
C2-
15
13
12
10
R116
22kΩ
R1OUT
T1IN
T2IN
R2OUT
GND
[2] P2_13/TXD0F
2
C12
0.1µF 4
5
18
R110
22kΩ
3VCC
C13
_0.1µF
3
C11
0.47µF
C14
0.47µF
B
Character-LCD
Serial-port
V-
7
NC
NC
14
11
R1IN
16
R111
0Ω(M)
(1)
5
T1OUT
17
R112
0Ω(F)
(2)
4
T2OUT
8
R113
0Ω(M)
(3)
3
R2IN
9
R115
0Ω(M)
(4)
2
R117
0Ω(F)
(5)
1
R118
0Ω(F)
R109
J5
MAX3222CPW
TI
R274 R275
22kΩ 22kΩ
[2,3,6] P5_[15:0]
9 (6)
8 (7)
R114
R119
ERNI 154188
154236
P5_11
LCDRS
P5_10
LCDE
P5_12
P5_13
P5_14
P5_15
LCDD12
LCDD13
LCDD14
LCDD15
6 (9)
0Ω(M)
JPN
RSK
Serial connector
mount tab = GND
:for Male connector only
RW
0Ω
7 (8)
MALE
FEMALE
J6
SSM-107-LM-DV-P-TR
Samtec
5VCC
0Ω(F)
100kΩ
1kΩ
V+
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R120
R121
19
R108
22kΩ
SHDN_
10
EN_
11
1
VCC
U23
B
:for Female connector only
C
C
D
D
CHANGE
Renesas Solutions Corp.
DRAWN
CHECKED
APPROVED
DESIGNED
R0K0F4022C000BR
CAN, Serial-port, EEPROM, LCD
( 4
SCALE
D-R0K0F4022C000BR_C-B
DATE
1
2
12-05-15
3
4
5
/ 6
)
1
2
3
4
5
P2_[15:0] [2,6]
3VCC
R122
10kΩ
220Ω
1
1
6
6
SW3
B3S-1000
1
6
SW4
B3S-1000
R257 _0Ω
R130
4.7kΩ
P2_3
0Ω
P2_3/INTP1
D3
1N4148W
FLMD0
EVTO
EVTI
R153
R154
22Ω
22Ω
17
11
13
MCKO
MSEO0
MSEO1
21
23
25
27
29
31
33
35
MDO0
MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7
5
2
4
R143
10kΩ
CP59
0.1µF
1
2
37
38
NC1
NC2
NC3
NC4
15
18
19
20
MDO8
MDO9
MDO10
MDO11
MDO12
MDO13
MDO14
MDO15
22
24
26
28
30
32
34
36
EN
R139
31.6kΩ
D4
MBRM110L
220Ω
U15A
HD74LV1GW07A
1
1
6
6
R146
R144
4.7kΩ
0Ω
P2_7
+ CE18
2.2µF
5VCC
D5
1N4148W
5
U14B
HD74LV1GW17A
3
CP58
0.01µF
VIN
+ CE20
R148
10kΩ
10µF/25V
4
4
R149
22kΩ
3VCC
+ CE17
10µF/16V
10µF/16V
R140
10kΩ
Vout = Vref * (R1+R2) / R1
= 0.8 * (5.1kR+10kR) / 10kR = 1.208V
L2
VLCF4020T-4R7N1R2
TDK
P2_7/INTP2
U25
INTP2
SWITCH
+ CE16
SW
6
FB
GND
3
2
EN
R147
5.1kΩ
D6
MBRM110L
1.2VCC
+ CE19
+ CE21
10µF/16V
220µF/6.3V
B
R150
10kΩ
LM2734X
NS
R151
22kΩ
Open-drain
8
FB
GND
3
2
3VCC
3VCC
U14A
HD74LV1GW17A
3
4
SW5
B3S-1000
RESET
SW
1
3VCC
3VCC
GND1
GND2
GND3
GND4
10
14
16
R138
10kΩ
10µF/25V
2
3VCC
4
VIN
+ CE15
6
C23
LM2734X
0.1µF NS
2
12
14
VCC
22Ω
U11C
HD74LV1GW07A
Vout = Vref * (R1+R2) / R1
= 0.8 * (31.6kR+10kR) / 10kR = 3.382V
L1
VLCF4020T-4R7N1R2
TDK
BOOST
TCK
TMS
TDI
TDO
TRST
TRDY
CP54
0.01µF
U24
5
CP57
0.1µF
6
10
R145
R152
MDO0
MDO1
MDO2
MDO3
MDO4
MDO5
MDO6
MDO7
R132
CP55
0.1µF
3VCC
5
3
5
7
9
6
12
U10C
HD74LV1GW17A
CP56
0.1µF
8
TCK
VDD
TMS/FLMD1
TDI
NC1
TDO
RESET2
TRST
TRDY
GND1
FLMD0
GND2
RESET1
GND3
J11
_2-5767004-2(OCD)
Tyco
JP12
HWP-2P-G_None
4
3VCC
3VCC
U14C
HD74LV1GW17A
3VCC
U15C
HD74LV1GW07A
EVDD
R155
CP60
0.1µF
0Ω
1
CP61
0.1µF
2
2
1
3VCC
5
3VCC
1
2
R141
22kΩ
R258
+ CE14
2.2µF
R142
22kΩ
3VCC
[2] MCKO
[2] MSEO1
[2] MSEO0
U11B
HD74LV1GW07A
3
4
5VCC
INTP1
SWITCH
Open-drain
[2] EVTO#
[2] EVTI#
U10B
HD74LV1GW17A
3
A
LED9
UB1111C
Blue
1
2
J10
HTST-107-01-L-DV
Samtec
1
9
7
5
3
11
4
13
J9
KLDX-SMT2-0202-A
Kycon
4
3
2
1
3VCC
E1
TCK
TMS
TDI
TDO
TRST#
TRDY#
B
220Ω
TP5
1
5VCC
+ CE13
10µF/25V
R128
1kΩ
1
2
R129
10kΩ
R131
5VCC
1
2
+ CE12
2.2µF
5
_22kΩ
NMI
SWITCH
CP53
0.1µF
Output
R137
R136
10kΩ
2
22kΩ
[2]
[2]
[2]
[2]
[2]
[2]
R134
R135
R133
10kΩ
_22kΩ
_22kΩ
3VCC
J7
_A2-2PA-2.54DSA
HRS
Open-drain
3VCC
10
13
15
16
System Power
P2_0/NMI
TP2
EVDD
OSCVDD
2
12
14
[2] FLMD1
[2] FLMD0
3VCC
4
11
SI/RxD
VDD1
SO/TxD
VDD2
SCK
H/S
VDE(NC)
CLK
RFU-1(NC)
Not used1
FLMD1 Not used2
FLMD0
GND
RESET
Vpp
P2_0
0Ω
3
4
3
5
7
8
9
R126
J8
_7616-6002PL
3M
A
R127
PGFP5
R125
R123
4.7kΩ
1
_0Ω
_0Ω
3
4
R124
U11A
HD74LV1GW07A
BOOST
3VCC
1.2VCC
3VCC
U10A
HD74LV1GW17A
L3
3.3V Ext.
BLM21PG300SN1
J12
_A2-2PA-2.54DSA
1
2
VDD
L4
UVDD, DVDD
+
[2] MDO[7:0]
BLM21PG300SN1
CE22
10µF/16V
HRS
3AVDD
L5
uPD60610
BLM21PG300SN1
AVDD Ext.
3VCC
3VCC
CP62
0.1µF
Cd
5
JP13
HWP-3P-G
5
3
4
1
2
AVDD
L6
1
BLM21PG300SN1
TP3
AVDD
C
+
CE23
10µF/16V
HRS
1
R159
0Ω
R160
100Ω
6
RESET# [2,3,6]
2
3
OUT
2
1
GND
VCC
NC
NC NC
8
R158
4.7kΩ
1
3
R161
10kΩ
IN
4
2
7
R157
15kΩ
U27
CP63
0.1µF
J13
_A2-2PA-2.54DSA
1
2
Power On Reset
C
R156
0Ω
U26
HD74LV1GT08A
Renesas
1.2VCC
IVDD
R162
0Ω
1
SW6
B3S-1000
C16
0.1µF
RNA51957BFP
3
L7
1.2V Ext.
U15B
4
3
TP4
IVDD
PLLVDD
BLM21PG300SN1
J14
_A2-2PA-2.54DSA
1
2
4
HD74LV1GW07A
+
A
L
H
Y
L
Z
CE24
10µF/16V
HRS
5VCC
CQ1
3VCC
CQ2
CQ3
CQ4
CQ5
EVDD
CQ6
CQ7
CQ8
CQ9
1.2VCC
J15
XG8S-0331
OMRON
1
2
3
CQ10 CQ11 CQ12 CQ13 CQ14 CQ15 CQ16 CQ17 CQ18
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
VSS - AVss
L8
BLM21PG300SN1
D
D
CHANGE
Renesas Solutions Corp.
DRAWN
CHECKED
APPROVED
DESIGNED
R0K0F4022C000BR
UDI, Reset, Push-SW, Power
( 5
SCALE
D-R0K0F4022C000BR_C-B
DATE
1
2
12-05-15
3
4
5
/ 6
)
1
2
4
5
D[15:0]
[2,3] D[15:0]
[2] P1_[15:0]
[2,5] P2_[15:0]
P1_[15:0]
P1_[15:0]
P2_[15:0]
P2_[15:0]
P3_[15:0]
[2,3] P3_[15:0]
[2,3] P4_[15:0]
[2,3,4] P5_[15:0]
A
3
[2,3] P6_[15:0]
[2,3] P7_[1:0]
[2] ANI_[11:0]
P4_[15:0]
P4_[15:0]
P5_[15:0]
P5_[15:0]
P6_[15:0]
P6_[15:0]
P7_[1:0]
P7_[1:0]
ANI_[11:0]
ANI_[11:0]
A
ANI[11:6]=P8_[5:0]
3VCC
P3_0
P5_9
R166
_0Ω
R169
_0Ω
ANI_6
ANI_8
P6_0
P6_2
P6_8
P6_13
P2_10
[2,4] P2_15/SDA1
P6_11
R172
0Ω
R175
_0Ω
5VCC
1
3
5
7
9
11
13
15
17
19
21
23
25
JA1
_FFC-26BMEP
HONDA
2
4
6
8
10
12
14
16
18
20
22
24
26
ANI_7
ANI_9
P6_1
P6_3
P6_9
P6_15
R163
0Ω
R164
R165
_0Ω
_0Ω
R167
ANI_10
ANI_0
P2_3
P1_14
[2,4] P2_15/CAN0TXD
P5_10
P5_14
P5_7
_0Ω
R171
_0Ω
R173
0Ω
P4_0
P5_5
P5_10
P5_12
P5_14
P6_12
P2_14/SCL1 [2,4]
P2_0
P5_15
P1_3
P2_3
P5_8
P4_6
P1_9
P4_7
P1_10
P1_1
P1_12
P1_14
P1_12
P1_14
P1_1
R179
0Ω
R182
R184
_0Ω
_0Ω
P2_4
P1_15
R186
0Ω
R188
_0Ω
R192
_0Ω
R194
R200
0Ω
_0Ω
R196
0Ω
R201
R203
_0Ω
0Ω
R204
R209
_0Ω
_0Ω
R207
0Ω
R183
1
3
5
7
9
11
13
15
17
19
21
23
25
P6_14
_0Ω
P1_0
P1_8
P2_7
P1_4
P4_13
P4_15
C
P4_2
P5_13
P4_4
P4_7
P4_6
P5_1
R217
_0Ω
R219
0Ω
R221
R226
_0Ω
R232
0Ω
R233
_0Ω
R234
0Ω
R235
_0Ω
R236
0Ω
R237
_0Ω
D0
D2
D4
D6
P4_12
P4_14
P2_2
P4_0
P4_10
P5_8
P5_5
R241
_0Ω
R243
0Ω
R246
0Ω
R247
_0Ω
D8
D10
D12
D14
P3_0
P3_2
P3_4
P3_6
P3_8
P3_10
P3_12
P3_14
0Ω
P2_6
R187
R190
_0Ω
0Ω
P2_8
R193
R197
_0Ω
0Ω
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
JA3
_FFC-50BMEP
HONDA
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
0Ω
R178
_0Ω
5VCC
R199
_0Ω
R195
_0Ω
R202
R205
0Ω
_0Ω
R206
0Ω
R211
_0Ω
R213
R218
0Ω
_0Ω
R220
R222
0Ω
0Ω
R223
R224
_0Ω
0Ω
R225
R229
_0Ω
0Ω
R230
_0Ω
SCIaTX [2]
P3_1
P3_3
P3_5
P3_7
P3_9
P3_11
P3_13
P3_15
D1
D3
D5
D7
D9
D11
D13
D15
P5_14
P5_7
SCIaRX [2]
P2_7
P4_15
P2_0
R189
0Ω
R191
_0Ω
R198
_0Ω
P1_7
P2_1
P6_4
[2] RS232TX
P2_5
P1_11
P4_7
P2_9
P1_13
P1_5
P5_0
0Ω
0Ω
R228
R185
R238
0Ω
R239
R240
_0Ω
0Ω
R242
_0Ω
R244
0Ω
R245
R248
_0Ω
0Ω
R249
_0Ω
P2_4
P1_15
P4_6
P2_1
P5_6
P6_5
ANI_11
ANI_1
P5_4
R168
0Ω
R170
_0Ω
R174
R177
_0Ω
0Ω
R180
0Ω
R181
_0Ω
P2_5
P1_11
P5_6
P5_11
P5_13
P5_15
P7_0
R176
X1 [2]
JA2
_FFC-26BMEP
HONDA
2
4
6
8
10
12
14
16
18
20
22
24
26
JA5
_FFC-24BMEP
HONDA
2
4
6
8
10
12
14
16
18
20
22
24
P2_7
[2,3,5] RESET#
B
1
3
5
7
9
11
13
15
17
19
21
23
R212
0Ω
R215
_0Ω
P2_14/CAN0RXD
[2,4]
P2_9
P1_13
B
_0Ω
AVDD
R260
AVDD
1
3
5
7
9
11
13
15
17
19
21
23
JA6
_FFC-24BMEP
HONDA
2
4
6
8
10
12
14
16
18
20
22
24
P6_6
RS232RX [2]
P5_11
P1_2
P1_6
R208
0Ω
R210
_0Ω
R214
_0Ω
R216
0Ω
P5_12
P5_8
P2_2
P4_5
P1_2
P5_7
P1_6
P4_14
P4_14
P5_2
P1_8
R227
0Ω
P2_1
R231
_0Ω
C
P4_11
P5_6
P4_1
P5_11
P4_5
P5_0
P4_9
P5_7
P4_3
P4_8
P5_3
P5_4
D
D
CHANGE
Renesas Solutions Corp.
DRAWN
CHECKED
APPROVED
DESIGNED
R0K0F4022C000BR
Application Header
( 6
SCALE
D-R0K0F4022C000BR_C-B
DATE
1
2
12-05-15
3
4
5
/ 6
)
This page is intentionally left blank
REVISION HISTORY
Rev.
Date
1.00
May 31, 2012
V850E2/ML4 CPU Board R0K0F4022C000BR User's Manual
Description
Page
–
Summary
First edition issued
V850E2/ML4 CPU Board R0K0F4022C000BR User's Manual
Publication Date: Rev.1.00 May 31, 2012
Published by:
Renesas Electronics Corporation
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700, Fax: +44-1628-651-804
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2012 Renesas Electronics Corporation. All rights reserved.
Colophon 1.2
16
V850E2/ML4 CPU Board
R0K0F4022C000BR
R20UT0778EJ0100