Download EPE Online Magazine

Regular Clinic
Circuit
Surger y
Ian Bell
Logic Level Conversion
EPE Chatzone contributor
F“IREQUENT
Amr Bekjit posted the following question:
recently bought a GPS module and its
datasheet states that the input and output
pins work at LV TTL (Low Voltage TTL)
levels. Now the worrying thing for me is
that the GPS module is said to be a 5V version. Will I be able to interface to this module with something like a PIC, which uses
5V signals?”.
I think that in the end Amr discovered
that the GPS module was compatible with
his 5V PIC, but his question raises the general issue of logic level conversion, which
we will discuss this month. For many years
most digital ICs either used exclusively 5V
supplies or were happy working at 5V
(within a larger possible range). However,
modern technology demands have driven
supply voltages lower and lower so we
now have ICs and subsystems (such as displays and GPS modules) that work on
other voltages such as 3·3V, 2·5V, 1·8V,
1·5V and 1·2V. Thus it is not uncommon to
find that two key devices in your design
require different supply voltages and hence
have potentially incompatible logic levels.
Defining Levels
We’ll start by looking at what we mean
by logic levels. In simple terms it is what
voltage is associated with a logic 1 and a
logic 0, but we have to be a bit more precise than that when considering how we
actually represent 1 and 0 in a real-life
electronic circuit. We could use two voltages, say +5V for logic 1 and 0V for logic
0, but this is arbitrary. It could be -2V for 0
and +2V for 1, or 0V for 1 and +5V for 0.
In general, if the more positive voltage is
used for logic 1 we refer to this as positive
logic and if the more negative voltage is
used for logic 1 we have negative logic. We
can also build logic circuits using currents
to represent 1s and 0s.
Most ICs that you are likely to encounter
will use voltage signals and positive logic.
If we select 5V for logic 1 and 0V for logic
0 then what does 4.9V mean? In real circuits we have to define a range of voltages
that represent a valid logic level, say 0V to
2V for 0, and 3V to 5V for 1. We need to
do this because we cannot build circuits
which handle precisely fixed voltages
under varying conditions of loading, temperature and factors affecting manufacture,
particularly as they must be as small and as
fast as possible.
52
In general, logic gates will accept a
given range of inputs as 1 or 0 and are
guaranteed to produce a smaller range of
possible output voltages, closer to the ideal
voltage. This means that each gate tends to
restore the voltage towards the ideal for
that logic level. This is illustrated in Fig.1.
In this article we will illustrate logic
interfacing using two inverters connected
together. In practice the input and output
can be from any logic device in the appropriate technology.
these are the logic technology (e.g. CMOS
and TTL) and the supply voltage. Different
technologies may pose problems with
incompatibility even on the same supply
voltage. This is illustrated in Fig.2 which
shows two possible problems in this situation – poor noise margin and mismatched
logic ranges.
Noise Margin
The difference between the worst case
output level and worst acceptable input
level for a given logic value is called the
noise margin. This figure indicates how
well the gate can cope with disturbances
(such as external electrical interference)
without losing the correct value of the
input data.
In order to define noise margin more
precisely we need to take note of minimum
and maximum voltages for logic 0 (Low,
L) and logic 1 (High, H) at both the input
and the output of the gate, as follows:
Input Voltages
Maximum Logic 0 - VILmax
Maximum Logic 1 - VIHmax
Minimum Logic 0 - VILmin
Minimum Logic 1 - VIHmin
Fig.1. Logic Levels and Noise Margins.
The output range of a gate for logic 0
and 1 is smaller than acceptable input
range, thus restoring the voltage level
to a more ideal one.
Output Voltages
Maximum Logic 0 - VOLmax
Maximum Logic 1 - VOHmax
Minimum Logic 0 - VOLmin
Minimum Logic 1 - VOHmin
We can then define noise margins for
logic 0 (NML) and logic 1 (NMH)
NML = VILmax - VOLmax
NMH = VOHmin - VIHmin
If the voltage is in between the defined
logic levels for any reason (except for the
brief time when switching between levels)
then we have an undefined logic value and
the circuit may behave unpredictably or
even suffer damage.
Incompatible Logic
Now we have defined some basics we
can look at the problems of connecting different gates together. There are two key
things that can be different and hence
cause us potential interfacing problems;
Fig.2. Example incompatible circuits:
different technologies on the same
supply. Logic 0 output range of technology 1 is too large for technology 2 –
not all valid 0 outputs from gate 1 will
be recognised by gate 2. Logic 1 is ok,
but the logic margin is very low, the
logic 1 level will be sensitive to noise.
Everyday Practical Electronics, August 2006