Download OLED TV SERVICE MANUAL

Internal Use Only
North/Latin America
Europe/Africa
Asia/Oceania
http://aic.lgservice.com
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OLED TV
SERVICE MANUAL
CHASSIS : OD01J
MODEL : 15EL9500
15EL9500-ZA
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL63267401 (1004-REV00)
Printed in Korea
CONTENTS
CONTENTS .............................................................................................. 2
PRODUCT SAFETY ................................................................................. 3
SPECIFICATION ....................................................................................... 6
ADJUSTMENT INSTRUCTION ................................................................ 9
BLOCK DIAGRAM...................................................................................14
EXPLODED VIEW .................................................................................. 15
SVC. SHEET ...............................................................................................
Copyright ©2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-2-
LGE Internal Use Only
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by
in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance
Leakage Current Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.
It will also protect the receiver and it's components from being
damaged by accidental shorts of the circuitry that may be
inadvertently introduced during the service operation.
If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.
When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10mm away from PCB.
Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.
AC Volt-meter
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
Leakage Current Cold Check(Antenna Cold Check)
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
Copyright ©2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-3-
To Instrument’s
exposed
METALLIC PARTS
0.15 uF
Good Earth Ground
such as WATER PIPE,
CONDUIT etc.
1.5 Kohm/10W
When 25A is impressed between Earth and 2nd Ground
for 1 second, Resistance must be less than 0.1 Ω
*Base on Adjustment standard
LGE Internal Use Only
SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service
manual and its supplements and addenda, read and follow the
SAFETY PRECAUTIONS on page 3 of this publication.
NOTE: If unforeseen circumstances create conflict between the
following servicing precautions and any of the safety precautions on
page 3 of this publication, always follow the safety precautions.
Remember: Safety First.
General Servicing Precautions
1. Always unplug the receiver AC power cord from the AC power
source before;
a. Removing or reinstalling any component, circuit board
module or any other receiver assembly.
b. Disconnecting or reconnecting any receiver electrical plug or
other electrical connection.
c. Connecting a test substitute in parallel with an electrolytic
capacitor in the receiver.
CAUTION: A wrong part substitution or incorrect polarity
installation of electrolytic capacitors may result in an
explosion hazard.
2. Test high voltage only by measuring it with an appropriate high
voltage meter or other voltage measuring device (DVM,
FETVOM, etc) equipped with a suitable high voltage probe.
Do not test high voltage by "drawing an arc".
3. Do not spray chemicals on or near this receiver or any of its
assemblies.
4. Unless specified otherwise in this service manual, clean
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable
non-abrasive applicator; 10 % (by volume) Acetone and 90 %
(by volume) isopropyl alcohol (90 % - 99 % strength)
CAUTION: This is a flammable mixture.
Unless specified otherwise in this service manual, lubrication of
contacts in not required.
5. Do not defeat any plug/socket B+ voltage interlocks with which
receivers covered by this service manual might be equipped.
6. Do not apply AC power to this instrument and/or any of its
electrical assemblies unless all solid-state device heat sinks are
correctly installed.
7. Always connect the test receiver ground lead to the receiver
chassis ground before connecting the test receiver positive
lead.
Always remove the test receiver ground lead last.
8. Use with this receiver only the test fixtures specified in this
service manual.
CAUTION: Do not connect the test fixture ground strap to any
heat sink in this receiver.
Electrostatically Sensitive (ES) Devices
Some semiconductor (solid-state) devices can be damaged easily
by static electricity. Such components commonly are called
Electrostatically Sensitive (ES) Devices. Examples of typical ES
devices are integrated circuits and some field-effect transistors and
semiconductor "chip" components. The following techniques
should be used to help reduce the incidence of component
damage caused by static by static electricity.
1. Immediately before handling any semiconductor component or
semiconductor-equipped assembly, drain off any electrostatic
charge on your body by touching a known earth ground.
Alternatively, obtain and wear a commercially available
discharging wrist strap device, which should be removed to
prevent potential shock reasons prior to applying power to the
unit under test.
Copyright ©2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
2. After removing an electrical assembly equipped with ES
devices, place the assembly on a conductive surface such as
aluminum foil, to prevent electrostatic charge buildup or
exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder ES
devices.
4. Use only an anti-static type solder removal device. Some solder
removal devices not classified as "anti-static" can generate
electrical charges sufficient to damage ES devices.
5. Do not use freon-propelled chemicals. These can generate
electrical charges sufficient to damage ES devices.
6. Do not remove a replacement ES device from its protective
package until immediately before you are ready to install it.
(Most replacement ES devices are packaged with leads
electrically shorted together by conductive foam, aluminum foil
or comparable conductive material).
7. Immediately before removing the protective material from the
leads of a replacement ES device, touch the protective material
to the chassis or circuit assembly into which the device will be
installed.
CAUTION: Be sure no power is applied to the chassis or circuit,
and observe all other safety precautions.
8. Minimize bodily motions when handling unpackaged
replacement ES devices. (Otherwise harmless motion such as
the brushing together of your clothes fabric or the lifting of your
foot from a carpeted floor can generate static electricity
sufficient to damage an ES device.)
General Soldering Guidelines
1. Use a grounded-tip, low-wattage soldering iron and appropriate
tip size and shape that will maintain tip temperature within the
range or 500 °F to 600 °F.
2. Use an appropriate gauge of RMA resin-core solder composed
of 60 parts tin/40 parts lead.
3. Keep the soldering iron tip clean and well tinned.
4. Thoroughly clean the surfaces to be soldered. Use a mall wirebristle (0.5 inch, or 1.25 cm) brush with a metal handle.
Do not use freon-propelled spray-on cleaners.
5. Use the following unsoldering technique
a. Allow the soldering iron tip to reach normal temperature.
(500 °F to 600 °F)
b. Heat the component lead until the solder melts.
c. Quickly draw the melted solder with an anti-static, suctiontype solder removal device or with solder braid.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.
6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
(500 °F to 600 °F)
b. First, hold the soldering iron tip and solder the strand against
the component lead until the solder melts.
c. Quickly move the soldering iron tip to the junction of the
component lead and the printed circuit foil, and hold it there
only until the solder flows onto and around both the
component lead and the foil.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.
d. Closely inspect the solder area and remove any excess or
splashed solder with a small wire-bristle brush.
-4-
LGE Internal Use Only
IC Remove/Replacement
Some chassis circuit boards have slotted holes (oblong) through
which the IC leads are inserted and then bent flat against the
circuit foil. When holes are the slotted type, the following technique
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique
as outlined in paragraphs 5 and 6 above.
Removal
1. Desolder and straighten each IC lead in one operation by gently
prying up on the lead with the soldering iron tip as the solder
melts.
2. Draw away the melted solder with an anti-static suction-type
solder removal device (or with solder braid) before removing the
IC.
Replacement
1. Carefully insert the replacement IC in the circuit board.
2. Carefully bend each IC lead against the circuit foil pad and
solder it.
3. Clean the soldered areas with a small wire-bristle brush.
(It is not necessary to reapply acrylic coating to the areas).
"Small-Signal" Discrete Transistor
Removal/Replacement
1. Remove the defective transistor by clipping its leads as close as
possible to the component body.
2. Bend into a "U" shape the end of each of three leads remaining
on the circuit board.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding
leads extending from the circuit board and crimp the "U" with
long nose pliers to insure metal to metal contact then solder
each connection.
Power Output, Transistor Device
Removal/Replacement
1. Heat and remove all solder from around the transistor leads.
2. Remove the heat sink mounting screw (if so equipped).
3. Carefully remove the transistor from the heat sink of the circuit
board.
4. Insert new transistor in the circuit board.
5. Solder each transistor lead, and clip off excess lead.
6. Replace heat sink.
Circuit Board Foil Repair
Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
board causing the foil to separate from or "lift-off" the board. The
following guidelines and procedures should be followed whenever
this condition is encountered.
At IC Connections
To repair a defective copper pattern at IC connections use the
following procedure to install a jumper wire on the copper pattern
side of the circuit board. (Use this technique only on IC
connections).
1. Carefully remove the damaged copper pattern with a sharp
knife. (Remove only as much copper as absolutely necessary).
2. carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
3. Bend a small "U" in one end of a small gauge jumper wire and
carefully crimp it around the IC pin. Solder the IC connection.
4. Route the jumper wire along the path of the out-away copper
pattern and let it overlap the previously scraped end of the good
copper pattern. Solder the overlapped area and clip off any
excess jumper wire.
At Other Connections
Use the following technique to repair the defective copper pattern
at connections other than IC Pins. This technique involves the
installation of a jumper wire on the component side of the circuit
board.
1. Remove the defective copper pattern with a sharp knife.
Remove at least 1/4 inch of copper, to ensure that a hazardous
condition will not exist if the jumper wire opens.
2. Trace along the copper pattern from both sides of the pattern
break and locate the nearest component that is directly
connected to the affected copper pattern.
3. Connect insulated 20-gauge jumper wire from the lead of the
nearest component on one side of the pattern break to the lead
of the nearest component on the other side.
Carefully crimp and solder the connections.
CAUTION: Be sure the insulated jumper wire is dressed so the
it does not touch components or sharp edges.
Diode Removal/Replacement
1. Remove defective diode by clipping its leads as close as
possible to diode body.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and if
necessary, apply additional solder.
Fuse and Conventional Resistor
Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.
3. Solder the connections.
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.
Copyright ©2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-5-
LGE Internal Use Only
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range
This specification is applied to the OLED TV used OD01J chassis.
2. Requirement for Test
Each part is tested as below without special appointment.
1) Temperature: 25 ºC ± 5 ºC(77 ºF ± 9 ºF), CST: 40 ºC ± 5 ºC
2) Relative Humidity : 65 % ± 10 %
3) Power Voltage
: Standard input voltage (AC 100-240 V~ 50 / 60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with
BOM.
5) The receiver must be operated for about 5 minutes prior to the adjustment.
3. Test method
1) Performance: LGE TV test method followed
2) Demanded other specification
- Safety: CE, IEC specification
- EMC:CE, IEC
4. Module specification(General)
No.
Item
Specification
Measurement
Remark
1
Screen Size
15 inch
2
Aspect Ratio
16:9
Diagonal
3
AMOLED
15 inch WXGA AMOLED
4
Storage Environment
Temp.: -20 deg ~ 60 deg
5
Input Voltage
-0.3 ~ 14 Vdc
At 25 ºC
6
Power Consumption
32 W
Typica (Logic : 6 W, EL= 26 W)
HD
Humidity : 10 % ~ 90 %
Copyright ©2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-6-
LGE Internal Use Only
5. Model General Specification
No.
1.
Item
Market
Specification
Remarks
EU(PAL Market-36Countries)
DTV & Analog (Total 36 countries)
(UK/Italy/Germany/France/Spain/Sweden/Finland/Netherland/Belgium/
Luxemburg/Greece/Denmark/Czech/Austria/Hungary/Switzerland/Croatia
Turkey/Norway/Slovenia/Poland/Portugal/Ireland/Moroco/Latvia/Estonial/
Lithuania/Rumania)
DTV (MPEG2/4, DVB-C) : 2 Countries
Swenden/ Finland
Analog Only - 7 countries
(Russia/Slovakia/Bosnia/Serbia/Bulgaria/Latvia/Albania/Kazakhstan)
2.
Broadcasting system
1) PAL-BG
2) PAL-DK
3) PAL-I/I’
4) SECAM L/L’
5) DVB-T/C (ID TV)
3.
Receiving system
Analog : Upper Heterodyne
G DBV-T
Digital : COFDM , QAM
- Guard Interval(Bitrate Mbit/s)
1/4, 1/8, 1/16, 1/32
- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 4/5, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 4/5, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 4/5, 5/6, 7/8
G DVB-C
- Symbolrate :
4.0Msymbols/s to 7.2Msymbols/s
- Modulation
16QAM, 64-QAM, 128-QAM and 256-QAM
4.
Mini - HDMI Input (1EA)
HDMI1-DTV
5.
USB
DVIX
6.
USB B
For Service
Copyright ©2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
Support HDCP
-7-
LGE Internal Use Only
6. Module optical specification
No.
Item
Specification
Min.
Typ.
Max.
1.
Viewing Angle [CR>10]
Right/Left(Up/Down)
2.
Luminance
Luminance (cd/m2)
180
200
Uniformity Variation
70
80
50,000
100,000
3.
Contrast Ratio
CR
4.
CIE Color Coordinates
White
Free
Wx
0.285
Wy
0.299
RED
Rx
0.667
Ry
Typ.
0.333
Typ.
Green
Gx
-0.03
0.230
+0.03
Blue
Remark
Degree
Gy
0.675
Bx
0.145
By
0.065
1) Contrast Ratio(CR) is defined mathematically as :
CR = Surface Luminance at all white pixels / Surface Luminance at all black pixels
It is measured at center 1 point.
2) Surface luminance is determined after the unit has been ‘ON’ and 3minutes after lighting the module in a dark environment at
25°C ± 2 °C. Surface luminance is the luminance value at center 1 point across the AMOLED surface 50 cm from the surface with
all pixels displaying white.
3) The variation in surface luminance , d WHITE is defined as :
- d WHITE(9P) = Minimum(Lon1,Lon2,..., Lon9) / Maximum(Lon1,Lon2..., Lon9)
Where Lon1 to Lon9 are the luminance with all pixels displaying white at 9 locations.
4) Image sticking
When it changes into pattern-B after a 1 hour drive by pattern-A, it disappears within 5 seconds.
7. HDMI Input
(1) DTV Mode
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
Proposed
1.
720*480
31.469 / 31.5
59.94 / 60
27.00 / 27.03
SDTV 480P
2.
720*576
31.25
50
54
SDTV 576P
3.
1280*720
37.500
50
74.25
HDTV 720P
4.
1280*720
44.96 / 45
59.94 /60
74.17 / 74.25
HDTV 720P
5.
1920*1080
33.72 / 33.75
59.94 /60
74.17 / 74.25
HDTV 1080I
6.
1920*1080
28.125
50.00
74.25
HDTV 1080I
7.
1920*1080
26.97 / 27
23.97 / 24
74.17 / 74.25
HDTV 1080P
8.
1920*1080
33.716 / 33.75
29.976 / 30.00
74.25
HDTV 1080P
9.
1920*1080
56.250
50
148.5
HDTV 1080P
10.
1920*1080
67.43 / 67.5
59.94 / 60
148.35/148.50
HDTV 1080P
Copyright ©2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-8-
Remark
LGE Internal Use Only
ADJUSTMENT INSTRUCTION
1. Application Range
(2)
This specification sheet is applied to all of the OLED TV with
OD01J chassis.
(3)
2. Designation
1) The adjustment is according to the order which is
designated and which must be followed, according to the
plan which can be changed only on agreeing.
2) Power Adjustment: Free Voltage
3) Magnetic Field Condition: Nil.
4) Input signal Unit: Product Specification Standard
5) Reserve after operation: Above 5 Minutes (Heat Run)
Temperature : at 25 ºC ± 5 ºC
Relative humidity : 65 % ± 10 %
Input voltage : 220 V, 60 Hz
6) Adjustment equipments: Color Analyzer(CA-210 or CA110), Pattern Generator(MSPG-925L or Equivalent), DDC
Adjustment Jig equipment, service remote control.
7) Push The “IN STOP” key - For memory initialization.
Please Check the Speed :
To use speed between
from 200KHz to 400KHz
5) Click “Auto” tab and set as below
6) Click “Run”.
7) After downloading, check “OK” message.
(4)
filexxx.bin
(5)
(7)
.OK
(6)
Case1 : Software version up
1. After downloading S/W by USB, TV set will reboot
automatically
2. Push “In-stop” key
3. Push “Power on” key
4. Function inspection
5. After function inspection, Push “In-stop” key.
Case2 : Function check at the assembly line
1. When TV set is entering on the assembly line, Push
“In-stop” key at first.
2. Push “Power on” key for turning it on.
-> If you push “Power on” key, TV set will recover
channel information by itself.
3. After function inspection, Push “In-stop” key.
* USB DOWNLOAD (*.epk file download)
1) Put the USB Stick to the USB socket.
2) Automatically detecting update file in USB Stick
- If your downloaded program version in USB Stick is Low,
it didn’t work. But your downloaded version is High, USB
data is automatically detecting.
3) Show the message “Copying files from memory”.
3. Main PCB check process
* APC - After Manual-Insult, executing APC
* Boot file Download
1) Execute ISP program “Mstar ISP Utility” and then click
“Config” tab.
2) Set as below, and then click “Auto Detect” and check “OK”
message
If “Error” is displayed, Check connection between
computer, jig, and set.
3) Click “Read” tab, and then load download file (XXXX.bin)
by clicking “Read”
(1)
fi lexxx.bin
4) Click “Connect” tab. If “Can’t” is displayed, check
connection between computer, jig, and set.
Copyright ©2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-9-
LGE Internal Use Only
4. Total Assembly line process
4) Updating is staring.
4.1. Adjustment Preparation
· W/B Equipment condition
CA210 : CH 17(OLED), Test signal : Inner pattern (85IRE)
· Above 30 minutes H/run in the inner pattern. (“power on” key
of adjust remote control)
Cool
13,000
K
X=0.269(±0.002)
Medium
9,300
K
X=0.285(±0.002)
Warm
6,500
K
Y=0.273(±0.002)
Color
Teperature
Y=0.293(±0.002)
X=0.313(±0.002)
Y=0.329(±0.002)
* Connecting picture of the measuring instrument
(On Automatic control)
Inside PATTERN is used when W/B is controlled. Connect to
auto controller or push Adjustment R/C POWER ON ->
Enter the mode of White-Balance, the pattern will come out.
Full White Pattern
CA-210
COLOR
ANALYZER
TYPE: CA-210
RS-232C Communication
5) Uploading completed, The TV will restart automatically.
6) If your TV is turned on, check your updated version and
Tool option.(explain the Tool option, next stage)
* If downloading version is more high than your TV have,
TV can lost all channel data. In this case, you have to
channel recover. if all channel data is cleared, you didn’t
have a DTV/ATV test on production line.
* Auto-control interface and directions
1) Adjust in the place where the influx of light like floodlight
around is blocked. (illumination is less than 10 lux).
2) Adhere closely the Color Analyzer (CA210) to the module
less than 10 cm distance, keep it with the surface of the
Module and Color Analyzer’s prove vertically.(80° ~ 100°).
3) Aging time
- After aging start, keep the power on (no suspension of
power supply) and heat-run over 5 minutes.
- Using ‘no signal’ or ‘full white pattern’ or the others,
check the back light on.
* After downloading, have to adjust Tool Option again.
1) Push "IN-START" key in service remote controller
2) Select “Tool Option 1” and Push “OK” button.
3) Punch in the number. (Each model hax their number)
Model
Tool option1
Tool option2
Tool option3
Tool option4
15EL9500
59648
512
49312
3328
• Auto adjustment Map(RS-232C)
RS-232C COMMAND
[CMD ID DATA]
Wb 00
00
White Balance Start
Wb 00
ff
White Balance End
4) Completed selecting Tool option.
RS-232C COMMAND MIN
3.1. Function Check
* Check display and sound
- Check Input and Signal items. (cf. work instructions)
1) TV
2) AV (SCART1/SCART2/ CVBS)
3) COMPONENT (480i)
4) RGB (PC : 1024 x 768 @ 60hz)
5) HDMI
6) PC Audio In
* Display and Sound check is executed by Remote control
Copyright ©2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
CENTER
[CMD ID DATA]
Cool
Mid
Warm
R Gain
jg
Ja
jd
G Gain
jh
Jb
je
B Gain
ji
Jc
jf
R Cut
MAX
(DEFAULT)
Cool
Mid
Warm
00
172
192
192
192
00
172
192
192
192
00
192
192
172
192
64
64
64
128
G Cut
64
64
64
128
B Cut
64
64
64
128
- 10 -
LGE Internal Use Only
** Caution **
Color Temperature : COOL, Medium, Warm.
One of R Gain/G Gain/ B Gain should be kept on 0xC0, and
adjust other two lower than C0.
(when R/G/B Gain are all C0, it is the FULL Dynamic Range
of Module)
- Auto Download
• After enter Service Mode by pushing “ADJ” key,
• Enter EDID D/L mode.
• Enter “START” by pushing “OK” key.
* Manual W/B process using adjusts Remote control.
• After enter Service Mode by pushing “ADJ” key,
• Enter White Balance by pushing “ G ” key at “6. White
Balance”.
* Edid data and Model option download (RS232)
* After done all adjustments, Press “In-start” button and
compare Tool option and Area option value with its BOM, if
it is correctly same then unplug the AC cable. If it is not
same, then correct it same with BOM and unplug AC cable.
For correct it to the model’s module from factory Jig model.
* Push the “IN STOP” key after completing the function
inspection. And Mechanical Power Switch must be set
“ON”.
Item
CMD1 CMD2 Data0
Download
A
A
0
0 When transfer the ‘Mode In’,
A
E
00 10 Automatically Download
‘Mode In’
Download
Carry the command.
(The use of a internal pattern)
- Manual Download
4.2. DPM operation confirmation
(Only Apply for MNT Model)
Check if Power LED color and Power Consumption operate
as stanard.
• Set Input to RGB and connect D-sub cable to set.
• Measurement Condition: 100-240V~, 50 / 60 Hz.
• Confirm DPM operation at the state of screen without Signal.
4.3. DDC EDID Write (HDMI 256Byte)
* Caution
1) Use the proper signal cable for EDID Download
- Digital EDID : Pin3 exists
2) Never connect HDMI & D-sub Cable at the same time.
3) Use the proper cables below for EDID Writing
4) Download HDMI1, HDMI2, separately because HDMI1 is
different from HDMI2
For HDMI EDID
DVI-D to HDMI or HDMI to HDMI
• Connect HDMI Signal Cable to HDMI Jack.
• Write EDID Data to EEPROM(24C02) by using DDC2B
protocol.
• Check whether written EDID data is correct or not.
* For SVC main Assembly, EDID have to be downloaded to
Insert Process in advance.
4.4. EDID DATA
Item
1) All Data : HEXA Value
2) Changeable Data :
*: Serial No : Controlled / Data:01
**: Month : Controlled / Data:00
***:Year : Controlled
****:Check sum
Copyright ©2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 11 -
Condition
Data(Hex)
Manufacturer ID
GSM
1E6D
Version
Digital : 1
01
Revision
Digital : 3
03
LGE Internal Use Only
1) HD HDMI EDID data
00
0
1
2
3
4
5
6
7
8
9
00
FF
FF
FF
FF
FF
FF
00
1E
6D
01
03
80
73
41
78
0A
CF
74
A3
57
4C
B0
23
4C
A1
08
00
81
C0
61
40
45
40
31
40
01
01
2C
10
c
A
B
C
D
a
E
F
09
48
30
01
01
01
01
01
01
02
3A
80
18
71
38
2D
40
58
40
36
00
7E
8A
42
00
00
1E
01
1D
00
72
51
D0
1E
20
50
6E
28
55
00
7E
8A
42
00
00
1E
00
00
00
FD
00
3A
60
3E
1F
46
10
00
0A
20
20
20
20
20
20
05
14
03
02
02
90
22
A0
B0
d
d
80
03
20
F1
4E
15
01
26
80
18
01
f
00
9E
• Press “Power on” key of service remocon.
(Baud rate : 115200 bps)
• Connect RS232 Signal Cable to RS-232 Jack.
• Write Serial number by use RS-232.
• Must check the serial number at the Diagnostics of SET UP
menu. (Refer to below).
b
20
70
5. Model name & Serial number D/L
12
01
e
20
21
10
1F
84
13
15
07
50
09
57
07
71
1C
16
20
58
2C
25
00
72
8A
42
00
1D
00
80
51
DO
0C
20
40
80
35
00
72
8A
f
C0
42
00
00
1E
8C
0A
D0
8A
20
E0
2D
10
10
3E
96
00
D0
7E
8A
42
00
00
18
02
3A
80
18
71
38
2D
40
58
2C
E0
45
00
7E
8A
42
00
00
1E
01
1D
80
D0
72
1C
16
20
F0
10
2C
25
80
7E
8A
42
00
00
9E
00
00
00
00
00
F9
5.1. Signal TABLE
* Detail EDID Options are below
Product ID
CMD
Model Name
HEX
EDID Table
DDC Function
HD Model
0000
00 00
Digital
Serial No: Controlled on production line.
Month, Year: Controlled on production line:
ex) Monthly : ‘02’ -> ‘02’
Year : ‘2009’ -> ‘13’
Model Name(Hex):
MODEL
LG TV
00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20
Vendor Specific(HDMI)
HDMI1
65030C001000011D
ADL
DATA_1
...
Data_n
CS
DELAY
No.
Adjust mode
CMD(hex)
LENGTH(hex)
Description
1
EEPROM WRITE
A0h
84h+n
n-bytes Write (n = 1~16)
* Description
FOS Default write : <7mode data> write
Vtotal, V_Frequency, Sync_Polarity, Htotal, Hstart, Vstart, 0,
Phase
Data write : Model Name and Serial Number write in
EEPROM,.
Checksum: Changeable by total EDID data.
MODEL NAME(HEX)
ADH
5.2. Command Set
MODEL NAME(HEX)
INPUT
LENGTH
CMD : A0h
LENGTH : 85~94h (1~16 bytes)
ADH : EEPROM Sub Address high (00~1F)
ADL : EEPROM Sub Address low (00~FF)
Data : Write data
CS : CMD + LENGTH + ADH + ADL + Data_1 +…+ Data_n
Delay : 20ms
5.3. Method & notice
A. Serial number D/L is using of scan equipment.
B. Setting of scan equipment operated by Manufacturing
Technology Group.
C. Serial number D/L must be conformed when it is produced
in production line, because serial number D/L is mandatory
by D-book 4.0.
Copyright ©2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 12 -
LGE Internal Use Only
* Manual Download (Model Name and Serial Number)
If the TV set is downloaded by OTA or Service man, Sometimes
model name or serial number is initialized.(Not always)
There is impossible to download by bar code scan, so It need
Manual download.
1) Press the ‘instart’ key of ADJ remote controller.
2) Go to the menu ‘5.Model Number D/L’ like below photo.
3) Input the Factory model name(ex 42LH4000-ZA) or Serial
number like photo.
4) Check the model name Instart menu -> Factory name
displayed (ex 42LH4000-ZA)
5) Check the Diagnostics (DTV country only) -> Buyer model
displayed (ex 42LH4000)
Copyright ©2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 13 -
LGE Internal Use Only
RS-232C
XC5000
IC600
LNA
IC1002
Copyright ©2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
MAX3232CDR
IC701
DRXK
(IC601)
Tuner_SCL I2C
Tuner_SDA I2C
IF_AGC I2S
V_MAIN, SIF
FE_TS_ Data
(LGE3369A)
IC100
- 14 DP, DM
I2S
I2C
Host Address[0:7]
Touch Key
HDMI1
USB
L/R
SERIAL FLASH
IC103
NAND Flash
IC102
DDR2 SDRAM
(512MB)
IC301
Digital amp
(NTP3100-L)
IC700
OLED Panel
EEPROM
(HDCP)IC400
EEPROM
(IC104)
4Ch LVDS (10 bit)
DDR2 SDRAM
(1G)
IC300
IR (light logo)
DDR2 Address[0:12]
DDR2 Data[0:15]
DDR2 Address[0:12]
DDR2 Data[0:15]
FRC
(LGE7329A)
IC901
DDR2 (512MB * 2)
IC1000/1001
BLOCK DIAGRAM
LGE Internal Use Only
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
100
200
400
300
600
500
LV1
A2
700
800
900
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by
in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
Copyright
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 15 -
LGE Internal Use Only
IC102
HY27US08121B-TPCB
+3.3V
NAND FLASH MEMORY
+3.3V
001:H28 S6_Reset
NC_8
VCC_1
VSS_1
OPT
+3.3V
R113
1K
NC_9
10K
CLE
/PF_CE1
ALE
OPT
R100
10K
WE
/PF_WE
WP
NC_11
R123
1K
C
Q101
KRC103S
B
PF_WP
NC_12
NC_13
E
R99
10K
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
35
15
34
16
33
32
17
PF_ALE
R108
R103
0
NC_14
NC_15
18
31
19
30
20
29
21
28
22
27
23
26
24
25
AR100
PCM_A[7]
I/O6
PCM_A[6]
I/O5
PCM_A[5]
D4
I/O4
AA15
PCM_A[4]
AC6
Y10
C102
10uF 6.3V
PRE
PCM_A[0-7,10-11]
VCC_2
ISP_RXD_SOC
VSS_2
C103
SCL
0.1uF
NC_22
ISP_TXD_SOC
SDA
NC_20
AR101
PCM_A[3]
I/O2
PCM_A[2]
PCM_D[5]
Y11
PCM_D[6]
Y12
PCM_D[7]
Y13
PCM_A[0]
AB16
PCM_A[1]
AC15
PCM_A[2]
AC14
PCM_A[3]
AB14
PCM_A[4]
NC_21
I/O3
AC12
PCM_A[5]
AB8
PCM_A[6]
AC13
PCM_A[7]
AA9
AB5
AA4
PCM_A[1]
I/O1
PCM_A[10]
V4
PCM_A[11]
Y4
PCM_A[0]
I/O0
AB9
22
NC_19
AA7
+5V_GENERAL
AD6
NC_17
NC_16
/PCM_OE
AR103
/PCM_CE
R189
33
AA14
R190
33
AB18
R191
33
Y5
R192
33
AB15
R193
10K
AA10
R194
10K
AC8
R195
33
AC7
R196
33
AA5
R197
33
W4
R198
33
T4
AE6
AF6
/PF_CE1
+3.3V_ST
AA12
/PF_OE
+24V
3
OPT
1
2
+3.3V_ST
+3.3V_ST
4
SW101
R146
0
22
AR102
/PF_WE
AA11
AC9
PF_ALE
SWITCH
Y14
PF_WP
AB11
/F_RB
R135
30K
1%
R131
10K
IC105
R158
100
MAX810RTR
VCC
POWER_DET
3
2
20pF
PCMD0/CI_D0
E6
PCMD1/CI_D1
1
EEPROM_SCL
EEPROM_SDA
Q104
2SC3052
B
SDA0
SCL0
10K
PCMD3/CI_D3
AE11
PCMD4/CI_D4
SPI_DI
PCMD5/CI_D5
SPI_DO
PCMD6/CI_D6
/SPI_CS
PCMD7/CI_D7
SPI_CK
ISP_RXD_SOC
S6_Reset
C106
10uF
6.3V
R159
10K
OPT
ISP_TXD_SOC
DBG_RX
R181
R182
33
33
D11
R183
R184
33
AB21
33
AC21
R178
R179
22
J1
IC103
VCC
SPI_CS
AD11
R16
33
SPI_CK
SPI_DO
USB_DM
PCM_A3/CI_A3
B5
PCM_A4/CI_A4
USB_DP_1
PCM_A5/CI_A5
USB_DM_1
PCM_A6/CI_A6
USB_DM_2
PCM_A7/CI_A7
USB_DP_2
USB
A5
AC10
AB10
+3.3V_ST
PCM_A8/CI_A8
PM GPIO Assignment Recommended by MStar
PCM_A9/CI_A9
10K
R34
PCM_A10/CI_A10
PCM_A11/CI_A11
3.3K
R32
R35
100
PCM_A12/CI_A12
LOGIC_POWER_ONR41
100
R44
PCM_A13/CI_A13
22
J2
R180
22
W5
GPIO_PM1/GPIO135
/PCM_OE
GPIO_PM2/GPIO136
PCM_REG/CI_CLK
GPIO_PM3/GPIO137
PCM_WAIT/CI_WACK
GPIO_PM4/GPIO138
/PCM_IRQA
GPIO_PM5/INT1/GPIO139
/PCM_WE
GPIO_PM6/INT2/GPIO140
PCM_IOWR/CI_WR
GPIO131/LDE/SPI_WPn1
PCM_IOR/CI_RD
GPIO130/LCK
GPIO132/LHSYNC/SPI_WPn
/PF_CE0
GPIO60/PCM2_RESET/RX1
/PF_CE1
GPIO62/PCM2_CD_N/TX1
V5
R45
F5
100
POWER_ON
R46
G5
100
LOGO_LED
R29
100
H5
R42
F6
DBG_RX
100
POWER_DET
G6
Interrupt for ISP Wake up in STB Mode
H6
AC17
AB17
R21
+3.3V
100
100
AF11
R23
AA18
R24
33
AA17
R25
33
Flash_WP_1
+3.3V
SDA1
SCL1
/PF_OE
/PF_WE
PF_ALE
I2C for Tuner_5V
PF_AD15
E7
LHSYNC2/I2S_OUT_MUTE/RX1
LVSYNC/GPIO133
F8
22
DBG_TX
POWER_DET
OPT
GPIO_PM0/GPIO134
PCM_CD/CI_CD
/PCM_CE
100
PANEL_POWER_ON
E5
PCM_RST/CI_RST
UART2_TX/SCKM
GPIO79/LVSYNC2/TX1
UART2_RX/SDAM
UART2_RX/GPIO84
DDCR_DA
UART2_TX/GPIO85
UART1_RX/GPIO86
UART1_TX/GPIO87
DDCA_CLK
DDCA_DA
GPIO42/PCM2_CE_N
UART_TX2
TS0_D2
NCP810 : Open Drain
TS0_D3
TS0_D5
R136
5.1K
1/10W
5%
C6
FE_TUNER_SCL
33
R30
FE_TUNER_SDA
F9
F10
USB_OCD
5V Tolerance
A6
B6
AF5
AF10
AA8
TS0_D0
MAX810 : CMOS
1
33
R31
AC18
GPIO43/PCM2_IRQA_N
UART_RX2
TS0_D4
16V
0.1uF
C109
SPI_DI
33
USB_DP
TS0_D1
GND
33
R15
PCM_A2/CI_A2
NCP803SN293
R132
OPT
R14
AE12
AF12
PCM_A1/CI_A1
DDCR_CK
R185
DBG_TX
3
0
PCM_A0/CI_A0
E
C105
4.7uF
10V
R133
2
R18
TESTPIN/GND
PCMD2/CI_D2
F_RBZ
22
R164 100
C
R155
RESET
GND
RESET
20pF
C13
A3
PCM_A14/CI_A14
NC_18
/PF_CE0
POWER DETECT
XIN
XOUT
AC16
22
NC_23
B3
HWRESET
+5V_GENERAL
AA16
NC_24
R33
1M
PCM_D[5-7]
I/O7
X12
44
14
NC_10
+3.3V_ST
5
C12
NC_25
R143
2.7K
0.1uF
C100
R128
OPT
1K
NC_7
45
IC100
LGE3369A (SATURN6 NON RM)
PCM_A[0-7]
NC_26
R142
2.7K
CE
4
NC_27
R38
15K
OPT
RE
/PF_OE
/PF_CE0
46
OPT
R/B
47
12MHz
3.9K
NC_5
NC_6
R129
1K
R127
/F_RB
NC_4
2
3
ISP FOR BOOT
R37
15K
NC_2
NC_3
48
OPT
R163
/PF_CE0
H : Serial Flash
L : NAND Flash
/PF_CE1
H : 16 bit
L :
8 bit
1
NC_28
OPT
R160
NC_1
TS0_D6
TS0_D7
TS0_SYNC
TS0_VLD
Y8
Y9
AB7
AA6
AB6
U4
AC5
AC4
AD5
AB4
TS0_CLK
AB19
TS1_D0
Serial FLASH MEMORY
for BOOT
EEPROM
PWM0
AB13
PWM1
AB12
AD12
7
HOLD#
33
WP#
3
6
SCLK
SPI_CK
10 : BOOT 51
11 : BOOT RISC
L101
E1
1
8
2
7
3
6
4
5
VCC
C104
0.1uF
R161
WC
Q100
KRC103S
4
5
E2
SI
SPI_DI
E
R134
0 VSS
R175
0
R176
0
A4
KEY2
B4
F4
E4
R157
EEPROM_SDA
C107
8pF
50V
C4
R177 OPT 0
+3.3V
PWM0
R162
1K
PWM2
PWM1
BUF_TS_SYN
AC19
BUF_TS_VAL_ERR
AA19
BUF_TS_CLK
C10
PWM3
ET_TXD0
SAR0
ET_TX_CLK
SAR1
ET_RXD0
ET_TXD1
SAR2
ET_RXD1
SAR3
ET_TX_EN
IRIN
ET_MDC
OPT
100
100
B11
A9
R13
R26
C11
OPT
C9
B10
EEPROM_WP
A10
B9
0
R27
4:S5
FE_RESET
A11
ET_COL
GPIO44
R187
100
R188
0
D7
TUNER_RESET
R10
0
E11
LNA_SWITCH_SEL
NTP_MUTE
R48
100
E8
R11
100
E10
AMP_RST
MEMC_RESET
1K
22
C108
R148
8pF
50V
D6
D7
E11
B9
D10
OPT
OPT
R172
4.7K
R174
OPT
R170
R166
OPT
R168
D5
I2C
TS1_CLK
BUF_TS_DATA[0]
AA20
D9
Touch_Test
D6
JTEG
PWM1
AC11
1K
OPT
22
R145
SDA
0
TS1_VLD
ET_MDIO
SCL
EEPROM_SCL
R199
PWM0
1K
OPT
R156
GND
SB_MUTE
KEY1
IR
C
0 B
Soft_Reset
+3.3V
E0
OPT
2
IC104
M24512-WMW6G(REV.B)
OPT
R173
SO
R115
0
OPT
L100
VCC
OPT
R171
8
1K
R169
R107
10K
R101
R102
Stand-by GPIO(SAR[0-3])
OPT
R167
1
+3.3V
SPI_DO
AA13
MCU BOOT STRAP
BLM18PG121SN1D
CS#
SPI_CS
+3.3V
R165
Flash_WP_1
+3.3V
IC101
MX25L3205DM2I-12G
0.1uF
C101
R117
4.7K
+3.3V
TS1_SYNC
C5
GPIO96
GPIO88
GPIO90/I2S_OUT_MUTE
GPIO91
GPIO97
GPIO98
GPIO99
GPIO103/I2S_OUT_SD3
GPIO102
+3.3V
R1026
4.7K
+3.3V
10K
4.7K
4.7K
R152
R153
R114
1K
MODEL_OPT_0 (D6) : LCD (H) / PDP (L)
MODEL_OPT_1 (D7) : FRC (H) / NO FRC (L)
R118
R110
10K
OPT
0
PCM_A[11]
JTINT
R119
0
PCM_D[5]
/JTRST
R120 OPT
0
PCM_D[7]
JTCK
R121 OPT
0
/PCM_CE
JTMS
R122
0
/PCM_OE
JTDO
R124
0
PCM_A[10]
PULL UP is applied on the FRC
MODEL_OPT_2 (E11) : LED NORMAL (H)
+3.3V
NO LED NORMAL (L)
MEMC_SDA
R138
33
MEMC_SCL
R139
33
FE_DEMOD_SDA
R140
33
FE_DEMOD_SCL
R141
33
MODEL_OPT_3 (B9) : FHD (H) / HD (L)
PULL UP is applied on the JACK
OPT
R43
3.3K
R106
R147
2.7K
R144
2.7K
+3.3V
SDA0
SCL0
R47
0
JTDI
EEPROM_SDA
R125
0
PCM_D[6]
/RST
R111
10K
PANEL_RESET
EEPROM_SCL
A7
GPIO67
R12
100
B8
GPIO68
USB_CTL R39
1K
C
B
Q12
2SC3052
OPT
E
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
OLED
FLASH/GPIO
09.08.31
1
9
LGE Internal Use Only
+1.26V_VDDC
Audio Mute
C238
0.1uF
C242
0.1uF
C246
0.1uF
C249
0.1uF
C252
0.1uF
C255
0.1uF
C258
0.1uF
C261
0.1uF
C264
0.1uF
C267
0.1uF
C270
0.1uF
C273
0.1uF
C247
0.1uF
C250
0.1uF
C253
0.1uF
C256
0.1uF
C259
0.1uF
C262
0.1uF
C265
0.1uF
C269
0.1uF
C272
0.1uF
C275
10uF
C276
0.1uF
C277
0.1uF
C279
0.1uF
R215
10K
+3.3V_ST
+1.26V_VDDC
D200
ENKMC2838-T112
A1
C235
0.1uF
16V
SB_MUTE
C
AMP_MUTE
007:Y15
A2
C239
0.1uF
C243
0.1uF
NTP_MUTE
C240
0.1uF
L205
BLM18PG121SN1D
C244
0.1uF
C248
0.1uF
C251
0.1uF
C254
0.1uF
IC100
LGE3369A (SATURN6 NON RM)
C257
0.1uF
C260
0.1uF
C263
0.1uF
C266
0.1uF
C268
0.1uF
C271
0.1uF
C274
10uF
C278
0.1uF
C280
0.1uF
C287
0.1uF
C291
0.1uF
C299
0.1uF
C295
0.1uF
C60
0.1uF
C62
0.1uF
C61
0.1uF
VDDC : 970mA
+1.26V_VDDC
+3.3V
R1027
4.7K
R1028
4.7K
LVA0P
G2 RXA0P
G3 RXA0N
LVA1P
H3 RXA1P
G1 RXA1N
SDA2
R942
0
SCL2
R943
0
AE16
F1 RXACKP
F2 RXACKN
H1 RXA2P
H2 RXA2N
A1 DDCD_A_DA
B2 DDCD_A_CK
A2 HOTPLUG_A
LVA0M
LVA1M
LVA2P
LVA2M
LVA3P
LVA3M
LVA4P
AD16
AD15
AF16
AF15
AE15
AD13
AF14
AF13
AE13
LVA4M
D2 RXB1P
D3 RXB1N
LVB1P
E1 DDCD_B_DA
F3 DDCD_B_CK
OPT
E2 HOTPLUG_B
R944
0
CK+_HDMI1
CK-_HDMI1
D0+_HDMI1
D0-_HDMI1
D1+_HDMI1
D1-_HDMI1
D2+_HDMI1
D2-_HDMI1
HDMI_SDA_1
HDMI_SCL_1
HPD1
CEC_REMOTE
LVB1M
LVB2P
LVB2M
LVB3P
LVB3M
LVB4P
RXCCKP
AD8
RXCCKN
RXC0P
RXC0N
AF9
RXC1P
AE9
RXC1N
AE10
RXC2P
AD10
RXC2N
AUL0
0
AE7
DDCD_C_DA
AF7
AUR1
0
100
DDCD_C_CK
AUL1
R204
100
N2 HSYNC0/SC1_ID
N1 VSYNC0/SC1_FB
P2 RIN0P/SC1_R
R3 GIN0P/SC1_G
47
R209
47
47
R210
C201
OPT
0.047uF
OPT
0.047uF
C202
OPT
0.047uF
C200
002:Z22;009:R28
F7
MEMC_RXE2+
002:Z23;009:R28
L9
MEMC_RXE2-
002:Z23;009:R28
L10
MEMC_RXE3+
002:Z25;009:Q28
L11
MEMC_RXE3-
002:Z25;009:Q28
MEMC_RXE4+
002:Z26;009:Q28
MEMC_RXE4-
002:Z25;009:Q28
AF20
AE19
AD17
AF18
AF17
AE17
R2 GINM
002:Z24;009:Q28
L14
002:Z24;009:R28
L15
R211
47
C203
0.047uF
M1 CVBS4/S-VIDEO_Y
M2 CVBS6/S-VIDEO_C
R213
47
C208
0.047uF
R214
47
C209
0.047uF
R212
100
100
C206
0.047uF
C207
0.047uF
R207
N3 CVBS5
M3 CVBS7
W1 CVBS0/RF_CVBS
Y3 VCOM0
Y2 CVBSOUT0/SC2_MNTOUT
AA2 CVBSOUT1
GND_12
H18
VDDC_7
H19
VDDC_8
H20
VDDC_9
J20
VDDC_10
K20
VDDC_11
L20
VDDC_12
M20
VDDC_13
P7
VDDC_14
R7
VDDC_15
T7
GND_15
MEMC_RXO1+
002:Z18;009:U28
M9
VDDC_16
GND_16
VDDC_17
002:Z18;009:U28
T22
VDDC_18
MEMC_RXO2+
002:Z18;009:U28
M10
GND_17
MEMC_RXO2-
002:Z18;009:U28
M11
VDDC_19
GND_18
MEMC_RXO3+
002:Z20;009:T28
M12
VDDC_20
MEMC_RXO3-
002:Z20;009:T28
M13
MEMC_RXO4+
002:Z21;009:S28
M14
002:Z21;009:T28
M15
M16
MEMC_RXOC+
MEMC_RXOC-
M17
002:Z19;009:T28
002:Z19;009:T28
N9
N10
Y1
N11
AE1
N12
AF3
N13
AE3
N14
GND_19
VDDC_21
GND_20
VDDC_22
GND_21
VDDC_23
GND_22
VDDC_24
GND_23
VDDC_25
GND_24
VDDC_26
N16
N17
N18
P4
P9
SIF0P
W2
0.1uF
C223
0.1uF
R230
R231
47
47
FE_SIF
004:C13
P13
P14
SPDIF_IN
P15
5V_HDMI_1
E9
P16
SPDIF_OUT
P17
P18
VDDP_1
GND_28
VDDP_2
GND_29
VDDP_3
GND_30
VDDP_4
GND_31
VDDP_5
GND_32
VDDP_6
VDDP_7
GND_33
AD1
AD2
R12
R221 OPT
R222 OPT
100
R13
100
I2S_OUT_WS
I2S_OUT_BCK
I2S_OUT_SD
A8
R223
22
B7
R224
22
C7
R225
22
D8
R226
22
C8
R227
100 OPT
I2S_IN_SD
C229
22pF
OPT
+3.3V
K4
VCLAMP
REFP
REFM
C210
C225
H4
J4
G4
REXT
C227
0.1uF
0.1uF
R216
0.1uF
390
AE5
AUCOM
AUVRM
AUVRP
AUVAG
C211
0.1uF
AE4
AF4
AD4
C212
10uF 10V
C213
0.1uF
C214
1uF
4.7uF
C215
C232
22pF
OPT
C237
22pF
OPT
R15
W11
W12
W19
W20
W22
Y22
H11
H12
N20
P20
W9
W10
+3.3V_AVDD
GND_34
GND_35
GND_36
L201
BLM18PG121SN1D
W7
007:K22
R17
MS_LRCK
007:K16
R18
MS_SCK
MS_LRCH
007:K16
007:K17
T5
T9
T10
T11
T12
+1.8V_DDR
GND_38
G12
AVDD_DDR_1
AVDD_DDR_3
GND_40
AVDD_DDR_4
GND_41
AVDD_DDR_5
GND_42
AVDD_DDR_6
GND_43
AVDD_DDR_7
GND_44
AVDD_DDR_8
GND_45
AVDD_DDR_9
GND_46
AVDD_DDR_10
GND_47
AVDD_DDR_11
G13
GND_48
AVDD_MEMPLL_1
GND_49
AVDD_MEMPLL_2
GND_50
T17
T18
U5
W13
Y21
AA23
C297
0.1uF
0.1uF
H13
H14
H15
H16
AVDD_DDR : 18.31mA
W14
W15
W16
W17
AVDD_MEMPLL_3
L202
BLM18PG121SN1D
T20
C284
V20
C289
0.1uF 0.1uF
C293
C51
0.1uF
0.1uF
+3.3V
GND_52
GND_53
GND_54
AVDD_LPLL : 4.69mA
L203
BLM18PG121SN1D
R20
AVDD_LPLL
+3.3V_AVDD_MPLL
GND_56
GND_57
AVDD_MEMPLL : 23.77mA
+3.3V
W18
GND_51
H7
AVDD_MPLL
GND_58
C282
C285
10uF
10V
GND_59
0.1uF
GND_60
C296
C53
0.1uF
0.1uF
AVDD_MPLL : 7.76mA
GND_61
+3.3V
GND_62
GND_64
AVDD_33_2
GND_65
AVDD_33_3
GND_66
AVDD_33_4
GND_67
AVDD_33_5
AVDD_33 : 281mA
L204
BLM18PG121SN1D
J7
AVDD_33_1
T13
T16
C288
H17
GND_63
T14
AVDD_AU : 36.11mA
AVDD_AU
GND_37
GND_55
AUDIO_MASTER_CLK
VDDP : 102.3mA
H10
R16
T15
C226
0.1uF
1%
Check
C231
22pF
OPT
R14
OPT
AC1
AUOUTL2/SC2_LOUT
OPT
R235
22K
AUOUTR2/SC2_ROUT
R11
OPT
C245
0.01uF
AUOUTL1/SC1_LOUT
R10
AD3
OPT
R234
22K
AUOUTR1/SC1_ROUT
R9
AF2
V22
VDDP_8
R4
AF1
AUOUTR0/HP_ROUT
V7
H9
GND_27
P11
P12
SIF0M
U22
+3.3V_VDDP
GND_26
AVDD_DDR_2
C222
U20
VDDC_27
GND_39
W3
U7
GND_25
N15
P10
I2S_OUT_MCK
T1 CVBS3/SIDE_CVBS
T2 VCOM1
GND_11
D20
VDDC_6
L18
J5 VSYNC2
U3 CVBS1/SC1_CVBS
U2 CVBS2/SC2_CVBS
GND_10
D19
VDDC_5
002:Z17;009:V28
C241
0.01uF
U1 BIN2P/COMP_PB+
V3 SOGIN2
GND_9
D18
VDDC_4
MEMC_RXO0-
AUR2
AUL2 AE2
AA1
AUR3
AB1
AUL3
AB2
AUR4
AC2
AUL4
AB3
AUR5
AC3
AUL5
AUOUTL0/HP_LOUT
V1 RIN2P/COMP_PR+
V2 GIN2P/COMP_Y+
GND_7
D17
VDDC_3
GND_13
GND_14
L1 RIN1P/DSUB_R
L3 GIN1P/DSUB_G
K1 BIN1P/DSUB_B
L2 SOGIN1
GND_6
D16
VDDC_2
L17
F11
K3 HSYNC1/DSUB_HSYNC
K2 VSYNC1/DSUB_VSYNC
GND_5
L12
R1 BIN0P/SC1_B
P3 SOGIN0/SC1_CVBS
P1 RINM
T3 BINM
GND_4
VDDC_1
002:Z17;009:U28
MEMC_RXO4-
AD18
GND_3
MEMC_RXO0+
MEMC_RXO1-
AF19
GND_2
GND_8
AA3
AUR0
R203
J3 CEC
MEMC_RXE1-
N4
R201
HOTPLUG_C
E18
M18
R200
R208
AD19
LVBCKM
AF8
AD7
AD20
AE18
LVBCKP
E17
002:Z23;009:R28
L16
LVB4M
AE8
AD9
LVB0M
E16
002:Z22;009:S28
MEMC_RXE1+
MEMC_RXEC-
AE20
LVB0P
002:Z22;009:S28
MEMC_RXE0-
MEMC_RXEC+
AD14
LVACKM
C1 RXB0P
C2 RXB0N
E3 RXB2P
D1 RXB2N
OPT
R945
0
LVACKP
MEMC_RXE0+
L13
AE14
C3 RXBCKP
B1 RXBCKN
TV/MNT
C283
0.1uF
IC100
LGE3369A (SATURN6 NON RM)
HDMI
FE_VMAIN
+3.3V
+3.3V_VDDP
+1.8V_DDR
K7
L7
M7
C292
C294
0.1uF
0.1uF 0.1uF 0.1uF 0.1uF
C298
C50
C55
C52
0.1uF
N7
+3.3V
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
L206
W8
AVDD_DM : 0.03mA
AVDD_DM
H8
+3.3V
L200
BLM18PG121SN1D
AVDD_OTG : 22.96mA
BLM18PG121SN1D
C56
C54
0.1uF
AVDD_USB
C281
2.2uF
10V
C286
C290
0.1uF
0.1uF
0.1uF
Close to IC
as close as possible
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
OLED
AVIN/LVDS/PWR
09.08.31
2
9
MSD3368GV
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
DDR2 1.8V By CAP - Place these Caps near Memory
C341
0.1uF
C338
0.1uF
0.1uF
0.1uF
C337
0.1uF
C336
0.1uF
C335
C333
0.1uF
C334
0.1uF
0.1uF
C332
0.1uF
C331
0.1uF
C330
10uF
C328
0.1uF
C329
0.1uF
C327
0.1uF
C326
0.1uF
C325
0.1uF
C324
C322
C321
0.1uF
10uF
C323
0.1uF
0.1uF
C320
0.1uF
C318
0.1uF
C316
0.1uF
C315
0.1uF
C314
0.1uF
C312
10uF
C313
0.1uF
C311
0.1uF
C310
0.1uF
C309
0.1uF
C308
0.1uF
C307
0.1uF
C306
0.1uF
C304
C302
C301
C300
0.1uF
10uF
+1.8V_DDR
PI Result
+1.8V_DDR
H9
SDDR_D[6]
DQ6
SDDR_D[7]
DQ7
F9
SDDR_D[8]
DQ8
C8
SDDR_D[9]
DQ9
C2
F1
SDDR_D[10]
DQ10
D7
SDDR_D[11]
DQ11
D3
SDDR_D[12]
DQ12
D1
SDDR_D[13]
DQ13
D9
SDDR_D[14]
DQ14
DQ15
B1
B9
A1
VDD4
E1
VDD3
SDDR_A[1]
SDDR_A[1]
SDDR_A[10]
A2
SDDR_A[2]
N2
A3
SDDR_A[3]
N8
A4
SDDR_A[4]
A5
SDDR_A[5]
N7
A6
SDDR_A[6]
P2
A7
SDDR_A[7]
P8
A8
SDDR_A[8]
P3
A9
SDDR_A[9]
M2
A10/AP
SDDR_A[10]
P7
A11
SDDR_A[11]
R2
A12
SDDR_A[12]
L2
BA0
L3
BA1
L1
BA2
J8
CK
SDDR_CK
VDD1
R1
K8
CK
/SDDR_CK
K2
CKE
A9
K9
ODT
VDDQ9
C1
L8
CS
VDDQ8
C3
K7
RAS
VDDQ7
C7
L7
CAS
VDDQ6
C9
K3
WE
ADDR2_A[12]
ADDR2_A[7]
ADDR2_A[0]
ADDR2_A[2]
SDDR_A[2]
ADDR2_A[4]
ADDR2_A[6]
56
R322 56
SDDR_A[11]
SDDR_A[8]
R323
ADDR2_A[4]
A13
ADDR2_A[5]
A23
ADDR2_A[6]
C12
ADDR2_A[7]
B23
ADDR2_A[8]
B12
ADDR2_A[9]
C23
ADDR2_A[11]
ADDR2_A[12] A24
ADDR2_BA[0]
C24
56
R307
ADDR2_BA[1]
B24
R308
ADDR2_BA[2]
D24
56
R309
ADDR2_MCLK
B14
56
SDDR_BA[1]
1%
R347
1K
C22
ADDR2_A[10] B22
ADDR2_A[11] A12
ADDR2_A[8]
56
ADDR2_A[3]
R306
SDDR_BA[0]
1%
R344
1K
C319
1000pF
1K 1%
B13
AR301
SDDR_A[0]
OPT
1%
0.1uF
A22
ADDR2_A[2]
ADDR2_A[9]
SDDR_A[12]
SDDR_CKE
R301
C13
ADDR2_A[1]
SDDR_A[7]
SDDR_A[6]
R303
VDDQ10
ADDR2_A[0]
SDDR_A[4]
J9
M9
ADDR2_A[1]
A_DDR2_A0
B_DDR2_A0
A_DDR2_A1
B_DDR2_A1
A_DDR2_A2
B_DDR2_A2
A_DDR2_A3
B_DDR2_A4
A_DDR2_A5
B_DDR2_A5
A_DDR2_A6
B_DDR2_A6
A_DDR2_A7
B_DDR2_A7
A_DDR2_A8
B_DDR2_A8
A_DDR2_A9
B_DDR2_A9
A_DDR2_A11
B_DDR2_A10
B_DDR2_A11
A_DDR2_A12
B_DDR2_A12
A_DDR2_BA0
B_DDR2_BA0
A_DDR2_BA1
A_DDR2_BA2
A_DDR2_MCLK
22
B_DDR2_A3
A_DDR2_A4
A_DDR2_A10
B_DDR2_BA1
B_DDR2_BA2
T26
BDDR2_A[0]
AF26
BDDR2_A[1]
BDDR2_A[1]
T25
BDDR2_A[2]
BDDR2_A[10]
AF23
BDDR2_A[3]
T24
BDDR2_A[4]
AE23
BDDR2_A[5]
R26
BDDR2_A[6]
AD22
BDDR2_A[7]
R25
BDDR2_A[8]
AC22
BDDR2_A[9]
AD23 BDDR2_A[10]
R24
TDDR_A[9]
BDDR2_A[3]
TDDR_A[0]
A0
M8
TDDR_A[1]
TDDR_A[1]
A1
M3
TDDR_A[10]
TDDR_A[2]
A2
M7
TDDR_A[3]
56
AR311
BDDR2_A[5]
TDDR_A[5]
TDDR_A[12]
BDDR2_A[12]
56
BDDR2_A[7]
BDDR2_A[0]
TDDR_A[2]
BDDR2_A[4]
TDDR_A[4]
56
BDDR2_A[11] R326
AE22 BDDR2_A[12]
TDDR_A[0]
BDDR2_A[2]
BDDR2_A[6]
BDDR2_A[11]
TDDR_A[7]
AR313
BDDR2_A[8]
R327
TDDR_A[8]
56
AC23
BDDR2_BA[0]
R328
56
AC24
BDDR2_BA[1]
R329
56
AB22
BDDR2_BA[2]
R330
BDDR2_MCLK
R331
V25
B_DDR2_MCLK
R310
/ADDR2_MCLK
A14
56
R311
ADDR2_CKE
D23
V24
/A_DDR2_MCLK
A_DDR2_CKE
/B_DDR2_MCLK
AB23
OPT
22
BDDR2_CKE
R333
56
+1.8V_DDR
SDDR_ODT 56
R312
ADDR2_ODT
D14
/SDDR_RAS
56
R313
/ADDR2_RAS
D13
/SDDR_CAS
56
R314
/ADDR2_CAS
D12
/SDDR_WE
56
R315
/ADDR2_WE
D22
A_DDR2_ODT
OPT
/A_DDR2_CAS
/A_DDR2_WE
/B_DDR2_CAS
TDDR_A[5]
A5
N3
A6
N7
TDDR_A[7]
A7
P2
A8
P8
A9
P3
TDDR_A[10]
A10/AP
M2
TDDR_A[11]
A11
P7
TDDR_A[12]
A12
R2
BA0
L2
BA1
L3
NC4
L1
R349
TDDR_MCLK
TDDR_CKE
512M bit
G8
DQ0
TDDR_D[0]
G2
DQ1
TDDR_D[1]
H7
DQ2
TDDR_D[2]
H3
DQ3
TDDR_D[3]
H1
DQ4
H9
DQ5
TDDR_D[5]
F1
DQ6
TDDR_D[6]
F9
DQ7
C8
DQ8
TDDR_D[8]
C2
DQ9
TDDR_D[9]
D7
DQ10
D3
DQ11
D1
DQ12
TDDR_D[12]
D9
DQ13
TDDR_D[13]
B1
DQ14
TDDR_D[14]
B9
DQ15
A1
VDD5
E1
VDD4
J9
VDD3
CK
J8
M9
VDD2
CK
K8
R1
VDD1
CKE
K2
R346
ODT
R334
56
K9
A9
VDDQ10
CS
L8
C1
VDDQ9
U25
/BDDR2_RAS
R335
56
/TDDR_RAS
RAS
K7
C3
VDDQ8
U24
/BDDR2_CAS
R336
56
/TDDR_CAS
CAS
L7
C7
VDDQ7
/BDDR2_WE
R337
56
/TDDR_WE
WE
K3
C9
VDDQ6
AB24
OPT
VDDQ5
E9
E9
VDDQ5
VDDQ4
G1
G1
VDDQ4
VDDQ3
G3
G3
VDDQ3
G7
VDDQ2
G9
VDDQ1
VDDQ1
G9
SDDR_DQS0_P
56
R316
ADDR2_DQS0_P
B18
UDQS
SDDR_DQS1_P
56
R317
ADDR2_DQS1_P
C17
F3
LDM
B3
SDDR_DQM0_P
56
R318
ADDR2_DQM0_P
C18
UDM
SDDR_DQM1_P
56
R319
ADDR2_DQM1_P
A19
SDDR_DQS0_N
56
R320
ADDR2_DQS0_N
A18
SDDR_DQS1_N
56
R321
ADDR2_DQS1_N
B17
VSS5
A3
VSS4
E3
E8
LDQS
VSS3
J3
A8
UDQS
VSS2
N1
VSS1
P9
R3
R7
NC6
A2
NC1
E2
NC2
R8
NC3
ADDR2_D[11]
ADDR2_D[0]
B15
SDDR_D[12]
ADDR2_D[12]
ADDR2_D[1]
A21
ADDR2_D[9]
ADDR2_D[2]
A15
ADDR2_D[14]
ADDR2_D[3]
B21
ADDR2_D[4]
ADDR2_D[4]
C21
SDDR_D[3]
ADDR2_D[3]
ADDR2_D[5]
C14
SDDR_D[1]
ADDR2_D[1]
SDDR_D[9]
56
AR305
SDDR_D[14]
VSSQ10
B2
VSSQ9
B8
VSSQ8
A7
VSSQ7
D2
VSSQ6
D8
VSSQ5
E7
VSSQ4
F2
VSSQ3
F8
VSSQ2
H2
VSSQ1
H8
SDDR_D[4]
SDDR_D[6]
J7
SDDR_D[15]
VSSDL
+1.8V_DDR
56
AR304
ADDR2_D[15]
SDDR_D[8]
ADDR2_D[8]
ADDR2_D[10]
SDDR_D[10]
SDDR_D[13]
J1
VDDL
ADDR2_D[6]
56
AR306
ADDR2_D[13]
ADDR2_D[6]
C20
ADDR2_D[7]
C15
ADDR2_D[8]
C16
C19
ADDR2_D[9]
ADDR2_D[10] B16
ADDR2_D[11] B20
SDDR_D[7]
ADDR2_D[7]
SDDR_D[0]
ADDR2_D[0]
ADDR2_D[12] A20
ADDR2_D[13] A16
ADDR2_D[14] B19
SDDR_D[2]
ADDR2_D[2]
ADDR2_D[15] A17
SDDR_D[5]
ADDR2_D[5]
B_DDR2_DQS1
A_DDR2_DQM0
B_DDR2_DQM0
A_DDR2_DQSB0
A_DDR2_DQSB1
SDDR_D[11]
B_DDR2_DQS0
A_DDR2_DQS1
A_DDR2_DQM1
AR303
NC5
A_DDR2_DQS0
A_DDR2_DQ0
A_DDR2_DQ1
AB26
BDDR2_DQS0_P
R338
56
AA26
BDDR2_DQS1_P
R339
56
AC25
BDDR2_DQM0_P
R340
56
AC26
BDDR2_DQM1_P
R341
56
AB25
BDDR2_DQS0_N
R342
56
AA25
BDDR2_DQS1_N
R343
56
B_DDR2_DQM1
B_DDR2_DQSB0
B_DDR2_DQSB1
B_DDR2_DQ0
B_DDR2_DQ1
A_DDR2_DQ2
B_DDR2_DQ2
A_DDR2_DQ3
B_DDR2_DQ3
A_DDR2_DQ4
B_DDR2_DQ4
A_DDR2_DQ5
B_DDR2_DQ5
A_DDR2_DQ6
B_DDR2_DQ6
A_DDR2_DQ7
B_DDR2_DQ7
A_DDR2_DQ8
B_DDR2_DQ8
A_DDR2_DQ9
B_DDR2_DQ9
A_DDR2_DQ10
B_DDR2_DQ10
A_DDR2_DQ11
B_DDR2_DQ11
A_DDR2_DQ12
B_DDR2_DQ12
A_DDR2_DQ13
B_DDR2_DQ13
A_DDR2_DQ14
B_DDR2_DQ14
A_DDR2_DQ15
B_DDR2_DQ15
BDDR2_D[0]
BDDR2_D[11]
TDDR_D[11]
AE26
BDDR2_D[1]
BDDR2_D[12]
TDDR_D[12]
W24
BDDR2_D[2]
BDDR2_D[9]
AF24
BDDR2_D[3]
BDDR2_D[14]
AF25
BDDR2_D[4]
BDDR2_D[4]
V26
BDDR2_D[5]
AE25
BDDR2_D[6]
W26
BDDR2_D[7]
Y26
AD25
Y25
BDDR2_D[8]
BDDR2_D[9]
BDDR2_D[10]
AE24 BDDR2_D[11]
AD26 BDDR2_D[12]
TDDR_DQM0_P
TDDR_DQM1_P
TDDR_DQS0_N
TDDR_DQS1_N
LDQS
F7
UDQS
B7
LDM
F3
UDM
B3
A3
VSS5
LDQS
E8
E3
VSS4
UDQS
A8
J3
VSS3
N1
VSS2
P9
VSS1
B2
VSSQ10
B8
VSSQ9
A7
VSSQ8
D2
VSSQ7
R3
NC6
R7
NC1
A2
NC2
E2
TDDR_D[14]
AR307
56
TDDR_D[4]
BDDR2_D[3]
TDDR_D[3]
BDDR2_D[1]
TDDR_D[1]
BDDR2_D[6]
56
AR310
BDDR2_D[15]
BDDR2_D[8]
NC3
R8
TDDR_D[6]
D8
TDDR_D[15]
TDDR_D[8]
BDDR2_D[10]
VSSDL
J7
+1.8V_DDR
TDDR_D[10]
TDDR_D[13]
BDDR2_D[13]
AR308
56
TDDR_D[7]
BDDR2_D[7]
AD24 BDDR2_D[14]
AA24 BDDR2_D[15]
BDDR2_D[0]
TDDR_D[0]
BDDR2_D[2]
TDDR_D[2]
BDDR2_D[5]
NC5
TDDR_D[9]
BDDR2_D[13]
Y24
TDDR_DQS0_P
TDDR_DQS1_P
AR309
W25
BDDR2_D[0-15]
G7
LDQS
B7
ADDR2_D[0-15]
VDDQ2
F7
56
TDDR_D[7]
TDDR_D[10]
TDDR_D[11]
TDDR_D[15]
OPT
BDDR2_ODT
/B_DDR2_WE
TDDR_D[4]
+1.8V_DDR
U26
B_DDR2_ODT
/B_DDR2_RAS
N8
N2
TDDR_A[6]
TDDR_BA[1]
TDDR_BA[2]
R348
/A_DDR2_RAS
A4
0
R332
+1.8V_DDR
TDDR_A[4]
TDDR_BA[0]
/BDDR2_MCLK
B_DDR2_CKE
A3
TDDR_A[9]
TDDR_A[11]
56
TDDR_A[3]
TDDR_A[8]
TDDR_A[6]
22
22
J2
AR312
BDDR2_A[9]
ADDR2_A[10]
SDDR_A[9]
OPT
VDD2
56
56
AR302
SDDR_BA[2]
R300
1K
R325
SDDR_A[0]
A1
M7
N3
C317
R324
1K 1%
A0
M3
+1.8V_DDR
VDD5
R305 1K 1%
M8
OPT
SDDR_D[15]
1G bit
A_MVREF
ADDR2_A[3]
TDDR_D[0-15]
H1
DQ5
VREF
D15
ADDR2_A[5]
SDDR_A[3]
OPT
H3
DQ4
AR300
SDDR_A[5]
IC301
H5PS5162FFR-S6C
TDDR_A[0-12]
DQ3
SDDR_D[4]
VREF
C339 C340
0.1uF 1000pF
R345
150
SDDR_D[3]
SDDR_D[5]
J2
IC100
LGE3369A (SATURN6 NON RM)
BDDR2_A[0-12]
H7
+1.8V_DDR
ADDR2_A[0-12]
G2
DQ2
SDDR_A[0-12]
G8
DQ1
150
R302
SDDR_D[0-15]
DQ0
SDDR_D[1]
SDDR_D[2]
C305
C303 1000pF
IC300
HY5PS1G1631CFP-S6
SDDR_D[0]
0.1uF
R304
+1.8V_DDR
VDDL
J1
VSSQ6
E7
VSSQ5
F2
VSSQ4
F8
VSSQ3
H2
VSSQ2
H8
VSSQ1
TDDR_D[5]
56
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
OLED
DDR2
09.08.31
3
9
DDR
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
5V_HDMI_1
C
Q401
2SC3052
BODY_SHIELD
20
18
Reserved
17
SDA
16
15
SCL
CEC
14
DDC/CEC GND
13
TMDS Clock-
12
TMDS Clock+
11
TMDS Clock Shield 10
TMDS Data0-
9
TMDS Data0+
8
TMDS Data0 Shield
7
TMDS Data1-
6
TMDS Data1+
5
TMDS Data1 Shield
4
TMDS Data2-
3
TMDS Data2+
2
TMDS Data2 Shield
1
VDD[+5V]
RESERVED
+5V_GENERAL
R403
1K
HOT_PLUG_DETECT
R401
2K
SDA
R417
0
R418
0
Q400
SSM6N15FU
D403
HDMI_SDA_1
R412
SOURCE1
HDMI EDID EEPROM(2Kbit)
ENKMC2838-T112
HDMI_SCL_1
SCL
R427
68K
5V_HDMI_1
C401
0.1uF
16V
CEC_REMOTE
0
GATE1
HDMI_CEC
CEC
R413
DDC/CEC_GND
C416
0.1uF
16V
0
CK-_HDMI1
R419
TMDS_CLK-
R454
10K
0
CK+_HDMI1
TMDS_CLK_SHIELD
R421
0
TMDS_DATA0-
R422
0
R423
0
R453
100
D0-_HDMI1
1:AO24
EEPROM_WP
1:E32;I9
HDMI_SCL_1
D0+_HDMI1
TMDS_DATA0+
TMDS_DATA0_SHIELD
D1-_HDMI1
R424
TMDS_DATA1-
0
1:E33;I9
D1+_HDMI1
R456
10K
R457
10K
WP
R459
33
SCL
R460
33
SDA
HDMI_SDA_1
8
1
7
2
6
3
5
4
6
2
5
3
4
IC400
CAT24WC08W-T
R436
4.7K
A0 1
A1
HDMI_CEC
DRAIN1
A2
VSS
GATE2
8
2
7
3
6
4
5
R442
4.7K
VCC
WP
SCL
DRAIN2
EEPROM_SCL
22
R443
SDA
C403
IC402
CAT24C02WI-GT3
VCC
TMDS_CLK+
1
R435
9.1K
D400
+5V Power
+3.3V
+3.3V_HDMI_ST
HPD1
E
19
Hot plug Detect
For CEC
R429
10K
B
R444
22
EEPROM_SDA
SOURCE2
0.1uF
A0
R416
OPT
A2
0
HDCP EEPROM
C402
220pF
50V
A1
GND
VSS
TMDS_DATA1+
TMDS_DATA1_SHIELD
R425
0
TMDS_DATA2-
R426
0
D2-_HDMI1
D2+_HDMI1
TMDS_DATA2+
TMDS_DATA2_SHIELD
[TOUCH CONTROL]
DC2R019JA3
P402
JK401
12507WS-08L
UI_HW_PORT(TYPE C)
L400
CB3216PA501E
+3.3V_ST
+3.3V_ST
1
JP11
C408
1000pF
50V
C407
0.1uF
16V
GND
SDA1
2
JP12
R461
0
SDA1
3
JP13
SCL1
SCL1
0
R462
KEY1
KEY1
0
R464
0
Touch_Test
[IR & LED]
KEY2
4
2
3
OPT
ENABLE
USB_CTL
C415
10uF
10V
2
JP22
R455
10K
2
3
C418
1000pF
50V
C417
0.1uF
16V
4
USB_OCD
R404
100
USB_DM
IR
9:M15
C404
100pF
50V
USB_DP
4
3
+5V_ST
C409
0.1uF
+5V_GENERAL
001:AI16
5
9
.
L615
CB3216PA501E
VIN
GND
R458
47
D401
CDS3C05HDMI1
5.6V
8
JP18
JP20
L402
MLB-201209-0120P-N2
5
6
JP25
5.6V
FAULT/
1
$0.18
180
R451
C414
0.1uF
16V
5
1
USB DOWN STREAM
UAR27-4K2300
P401
C413
10uF
10V
6
7
1
+5V_EXT
R452
4.7K
ZD401
CDS3C05HDMI1
VOUT
ILIMIT
Touch_Test
R465
4.7K
+3.3V_P
IC401
6
JP16
KEY2
P400
MIC2009YM6-TR
Soft_Reset
JP17
TF12-9S-0.5SH
L401
MLB-201209-0120P-N2
5
JP15
OPT
R463
Soft_Reset
USB JACK
4
JP14
7
8
D402
CDS3C05HDMI1
5.6V
JP27
R405
0
9
LOGO_LED
C405
0.1uF
16V
C406
1000pF
50V
10
OE1
A0
USB +5V Over Current Protection -->
USB Jack
FE_TS_CLK
A1
FE_TS_VAL_ERR
A2
FE_TS_SYNC
A3
FE_TS_SERIAL
R661
10K
R662
10K
A4
A5
A6
A7
GND
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
+3.3V
IC606
74LVC541A(PW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
C966
0.1uF
16V
OE2
Y0
AR604
33
1/16W
BUF_TS_CLK
9:M15
Y1
Y2
Y3
9:M15
BUF_TS_VAL_ERR
9:M15
BUF_TS_SYN
9:M15
BUF_TS_DATA[0]
Y4
Y5
Y6
Y7
OLED
HDMI/IR/USB
09.08.31
4
9
LGE Internal Use Only
I2C Address : C2
+5V_GENERAL
+3.3V_P
+5V_TUNER
+3.3V_TU
+3.3V_TU
+3.3V_TU_LNA
Analog Supply Max Current(+3.3V/Operating ) : 250mA
(+1.8V/Operating ) : 75mA
Digital Supply Max Current ( +1.8V/Operating ) : 75mA
+3.3V_TU
16V
0.1uF
C639
L621
C689
0.1uF
16V
16V
0.1uF
C626
SDA
C635
0.1uF
16V
SCL
33
VDDD_2
32
EXTREF
XC5000
X600
31.875MHz
ADDRSEL
VDDC_1
10
27
DDI2
GND_4
11
26
VDDC_5
VDDC_2
12
25
DDI1
FE_TS_ERR
2
5
C660
0.1uF
16V
3
4
R627
47
FE_TS_VAL_ERR
R623
FE_TUNER_SCL
C645 C646 R624
18pF 18pF 100
50V 50V
+3.3V_P
+5V_GENERAL
IC602
24
16
23
X2
28
22
29
9
21
GND_7
8
VDDA_3
20
30
19
X1
7
17
31
GND_3
VDDA_2
6
1
FE_TUNER_SDA
34
IC600
5
100
FE_TS_VAL
R629
4.7K
50V
18pF
C644
VI2C
VDDC_6
VREF_N
VREF_P
VDDC_7
VDDC_8
REXT
RESET
37
38
39
40
41
42
GND_9
VDDC_9
VDDA_7
44
45
VDDA_8
35
4
16V
0.1uF
C619
16V
0.1uF
C623
16V
0.1uF
C621
16V
0.1uF
C625
VDDD_1
TESTMODE
16V
0.1uF
C628
GND_6
VDDA_6
VDDC_4
GND_5
VDDC_3
C975
0.47uF
25V
VDDA_5
SC156515M-1.8TR
+3.3V_TU
+1.8V_TU
VIF
C617
0.1uF
16V
LNA_SWITCH_SEL
48
2
15
C614
0.1uF
16V
IN1
14
OPT
GND_8
3
C616
0.1uF
16V
R628
4.7K
36
GND_1
+3.3V_TU
+3.3V_TU
1
IN2
L605
GND_2
1008CS-821XGLC
EXTCHOKE
+3.3V_TU
IC605
NL17SZ08DFT2G
VDDA_1
13
50V
3.9pF
C965
46
C613
1000pF
50V
C695
120pF
50V
20ms
Active Low
16V
0.1uF
C629
R610
4.99K
1%
VAGC
C603
120pF
50V
C612
0.1uF
16V
OUTPUT
L603
0603CS-12NXGLW
C615
0.1uF
16V
4
12nH
390nH
3
VOUT
L604
0603CS-R39XGLW
5
C694
39pF
50V
6
L607
0603CS-R27XGLW
VM
1
2
VCC
270nH
GND
270nH
D600
RCLAMP0502B
L600
0603CS-R27XGLW
RF_IN
C692
0.1uF
16V
C693
56pF
50V
C604
39pF
50V
C601
56pF
50V
INPUT
50V
1000pF
C618
+1.8V_TU
IC1002
TB7601TU
10
R615
16V
0.1uF
C638
+1.8V_TU
16V
0.1uF
C622 C624
16V
0.1uF
47
+3.3V_TU
16V
0.1uF
C620
VDDA_4
+3.3V_TU_LNA
TUNER_RESET
16V
0.1uF
C631
16V
0.1uF
C627
BAP70-02
43
C688
0.1uF
16V
18
C650
0.1uF
16V
SIF
C649
0.1uF
16V
2.7K
R616
500
C643
18pF
50V
L616
BLM18PG121SN1D
C637
0.1uF
16V
L614
BLM18PG121SN1D
+1.8V_TU
L606
LQH32MN2R2K23L
C632
0.1uF
16V
VIN
OPT
R637
1K
C642
0.1uF
16V
C633
0.1uF
16V
R611
1K
EN
2
4
1
5
VO
R639
ADJ 15K
1%
R640
8.2K
1%
3
C661
22uF
10V
C663
0.1uF
16V
GND
C671
100uF
16V
C673
10uF
10V
C675
0.1uF
16V
IF_AGC
C630 1/16W
0.1uF 5%
16V
+5V_TUNER
+3.3V_DVDD_P
TUNER_SIF_IF_N
+3.3V_TU
1:C9
TUNER_CVBS_IF_P
R608
390
C609
0.1uF
16V
IC604
AP1117E18G-13
IF_N
004:D6
+1.2V_P
XO
XI
VSSAH_OSC
49
VDDAH_OSC
VDDH_4
51
50
52
53
VSSL_4
VDDL_4
TDO
TMS
TCK
TDI
VSSH_4
54
55
56
57
58
59
60
61
I2C_SDA2
48
PDN
C653
0.1uF
2
47
PDP
C654
0.1uF
3
46
VDDAL_AFE2
45
VSSAL_AFE2
44
SIF
43
CVBS
42
VDDAH_CVBS
GPIO1
4
47
MSTRT
5
47
MERR
6
VSSH_1
7
VDDH_1
8
41
VSSAH_CVBS
9
40
INP
INN
FE_TS_CLK R644
47
MCLK
R645
R643
47
MVAL
10
39
47
MD0
11
38
VSSAH_AFE1
MD1
12
37
VDDAH_AFE1
MD2
13
36
VDDAL_AFE1
FE_VMAIN
C676
0.1uF
16V
IF_P
IF_N
R660
6.8K
IC603
SC4215ISTRT
+1.2V_P
NC_1
C648
0.027uF
R638
20K
C606
6.8pF
50V
VIN
16V
2.2uF
C662
R658
4.7K
8
1
2
7
3
6
4
5
GND
ADJ
VO
R641
20K
R2
R642
10K
R1
V0 = 0.8(R1+R2) / R2
C677
100uF
16V
NC_3
C680
0.1uF
16V
16V
2.2uF
C664
R659
C
100
+3.3V_DVDD_P
+5V_TUNER
OPT
R654
4.7K
R656
100
C647
0.1uF
16V
R657
100
50V
10pF
C640
R655
4.7K
OPT
R609
390
C610
0.1uF
16V
EN
C666
1uF NC_2
10V
+3.3V_DVDD_P
ISA1530AC1
Q600
C679
22uF
10V
+3.3V_P
E
B
2.7uH
+1.8V_TU
IF_AGC
32
31
SAW_SW
30
29
28
VSSL_3
27
VDDL_3
VDDH_3
VSSH_3
I2C_SDA1
MD7
MD6
I2C_SCL1
MD5
VSSH_2
26
RF_AGC
25
33
24
16
23
VDDL_2
22
IF_AGC
21
VSSAL_AFE1
34
20
35
15
19
14
18
MD3
VSSL_2
390
R604
R605
62
1
IC601
DRX3913K-XK
2
OUT
C652
1000pF
50V
R635
ADJ/GND
GND
0
L601
MLF1608A2R7J R602
680
TUNER_CVBS_IF_P
1
+3.3V_DVDD_P
VSSL_1
17
+5V_TUNER
004:D6
3
C657
0.1uF
16V
+1.2V_DVDD_P
VDDL_1
MD4
FE_TS_CLK
FE_TS_VAL
FE_TS_SERIAL
C
C608
0.1uF
16V
IN
20.25MHz
I2S_WS
VDDH_2
ISA1530AC1
Q601
B
Rev(9)
C152,155
18pF=>13pF=>15pF
C651
1000pF
50V
R636
FE_TS_SYNC
FE_TS_ERR
E
63
64
R634
4.7K
390
R606
0
R607
FE_SIF
004:D6
I2C_SCL2
C
+5V_TUNER
C611
0.1uF
16V
C634
15pF
50V
+3.3V_AVDD_P
GPIO2
C607
6.8pF
50V
VSYNC
B
I2S_CL
2.7uH
C636
15pF
50V
X601
+3.3V_DVDD_P
ISA1530AC1
Q602
TUNER_SIF_IF_N
I2S_DA
004:D6
E
RSTN
L602
MLF1608A2R7J R603
680
FE_RESET
3.3V Block
+1.0V BLOCK
+3.3V_P
+3.3V_P
50V
10pF
C641
+1.2V_P
+3.3V_AVDD_P
+1.2V_DVDD_P
L610
500
L608
500
+3.3V_DVDD_P
L612
500
IF_P
C655
10uF
10V
C
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
C658
0.1uF
16V
C659
0.1uF
16V
C668
0.1uF
16V
C667
10uF
10V
C674
10uF
10V
C678
0.1uF
16V
C683
0.1uF
16V
C685
0.1uF
16V
FE_DEMOD_SDA
ISA1530AC1
Q603
B
FE_DEMOD_SCL
E
OLED
Chip Tuner
09.08.31
5
9
Tuner
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
For protect Peak noise
L704
AD-8770
D700
1N4148W
100V
OPT
+24V_AMP
OPT
R714
3.3
C715
22000pF
50V
+3.3V
2S
5.6
SPK_L+
EAP60684501
2F
C747
0.1uF
50V
C737
390pF
50V
1S
C729
10uF
35V
0.01uF
50V
C738
390pF
50V
R719
D701
1N4148W
100V
OPT
R728
4.7K
C745
0.47uF
50V
1F
C733
OPT
C727
0.1uF
50V
C725
0.1uF
50V
R718
P701
007:AA18
C752
0.01uF
50V
SMW200-04
R732
3.3
SPEAKER_L
SPK_R-
1
007:AG22
SPK_R+
2
007:AG24
SPK_L-
007:AG19
R733
C748
0.1uF
50V
R729
4.7K
5.6
3.3
C753
0.01uF
50V
SPK_L- 007:AA18
C712
1uF
25V
L701
AD
4
DVSS_1
5
VSS_IO
6
CLK_I
7
VDD_IO
8
9
AGND_PLL
10
002:V8
MS_LRCK
002:V8
MS_SCK
001:L3;004:Y11
SDA1
001:L3;004:Y11
SCL1
PVDD1B_2
PVDD1B_1
OUT1B_2
OUT1B_1
PGND1B_2
PGND1B_1
BST1B
VDR1B
48
47
46
45
44
43
PVDD1A_1
49
EAN60664001
39
PGND2A_2
38
PGND2A_1
37
OUT2A_2
36
OUT2A_1
35
PVDD2A_2
34
PVDD2A_1
33
PVDD2B_2
11
32
PVDD2B_1
12
31
OUT2B_2
DVDD_PLL
13
30
OUT2B_1
TEST0
14
29
PGND2B_2
NTP-3100L
SPK_R+ 007:AA17
C731
22000pF
L705
D702
1N4148W
100V
OPT
50V
R720
2S
C746
0.47uF
50V
EAP60684501
2F
1S
C740
390pF
50V
D703
1N4148W
100V
OPT
C754
AD-8770
5.6
C739
390pF
50V
LFM
C749
R730
0.1uF
50V
4.7K
0.01uF
50V
R734
SPEAKER_R
3.3
R735
1F
R721
5.6
C750
R731
0.1uF
50V
4.7K
3.3
C755
0.01uF
50V
SPK_R- 007:AA17
R706
100
R704
100
R705
100
R707
100
R708
C711
10uF
10V
28
PGND2B_1
26
27
BST2B
VDR2B
25
FAULT
24
MONITOR_2
23
MONITOR_1
22
MONITOR_0
21
SCL
20
SDA
19
BCK
18
WCK
17
16
+24V_AMP
C705
0.1uF
16V
OPT
MS_LRCH
IC700
C728
25V1uF
AVDD_PLL
+1.8V_AMP
002:V8
PVDD1A_2
BST2A
15
OPT
C704
10uF
6.3V
OUT1A_1
VDR2A
40
DGND_PLL
3.3K
51
50
NC
41
3
DVDD
100pF
50V
C708
1000pF
50V
R702
OUT1A_2
42
2
RESET
SDATA
C706
PGND1A_1
1
VDR1A
DVSS_2
C702
0.1uF
16V
R700
0
MLB-201209-0120P-N2
MLB-201209-0120P-N2
C700
10uF
10V
OPT
L700
C709
0.1uF
C726
1uF
25V
BST1A
+1.8V_AMP
+1.8V_AMP
52
R703
0
002:V8 AUDIO_MASTER_CLK
53
PGND1A_2
56
C707
1000pF
50V
54
100
55
R701
AMP_RST
4
SPK_L+
007:AG26
001:AA9
3
C724
22000pF
50V
C723
1uF
25V
C714
0.1uF
16V
C734
C735
0.1uF
50V
0.1uF
50V
C741
10uF
35V
RF_IN&DC POWER
+24V
C730
22000pF
50V
JK800
KCN-ET-2-0104
+3.3V_ST
OPT
C722
33pF
50V
OPT
R711
RF_IN
C713
33pF
50V
R740
22K
S
+24V_AMP
G
R742
27K
DC_GND
R717
10K
2
Q701
JP31
AO3407A
C
0
C710
33pF
50V
C761
2.2uF
50V
1
POWER_DET
0
R710
100
C760
0.1uF
50V
RF_IN
DC_POWER
R726
B
Q700
2SC3052
R709
33K OPT
3
AMP_MUTE
R743
10K
JP32
10K
E
RF_SHIELD
002:C25
4
5
MCLK SDATA WCK BCK TP is necessory
C880
0.047uF
D
L702
CPI2520NHL3R3ME
C
B
Q702
POWER_ON
E
C762
0.01uF
50V
C718
10uF
35V
C721
0.01uF
50V
AO3407A Vgs : 10.8V
SHIELD
Monitor0_1_2 TP is necessory
RS-232C
+5V_ST
L703
BLM18PG121SN1D
C1+
16V
0.33uF
C720
C2+
C2-
V-
DOUT2
RIN2
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
1/10W
5%
P700
DBG_RX
VCC
C736
0.1uF
16V
KJA-UB-0-0020
DBG_TX
USB DOWN STREAM
C1-
1
1/10W
R716
5%
6.2K
IC701
MAX3232CDR
V+
C719
0.33uF
16V
R715
6.2K
0.33uF
C717
0.047uF
25V
C716
1
GND
RxD
D704
ADUC30S03010L
30V OPT
DOUT1
RIN1
ROUT1
R713
100
R712
100
50V
220pF
C743
TxD
2
3
4
50V
220pF
C744
5
DIN1
6
DIN2
D705
ADUC30S03010L
30V OPT
ROUT2
USB
Serial Port
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
OLED
AUDIO
09.08.31
6
9
AUDIO/ADAPTER/232C
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
FROM ADAPTER TO MAIN BOARD
24V->12V
+5V_ST
7
R1
FB
S2
S3
G
D8
8
1
D7
7
2
$0.12
3
6
4
5
D6
FB
22
R895
VIN_1
8
$0.21
7
5
6
FREQ
R893
200K
GND
1/8W
1%
C808
0.1uF
50V
+5V_ST
PGND
L897
4.7uH
VIN
R955
200K
1/16W 1/16W
1%
1%
AGND
C972
22uF
16V
SP-7850_4.7
C896
10uF
10V
NR8040T3R6N
C974
0.1uF
50V
C897
10uF
10V
10K
S
Vout=0.8*(1+R1/R2)
D
FB
10K
R813
+5V_GENERAL
R827
30K
1%
R2
OPT
Placed on SMD-TOP
C837
0.1uF
16V
Cin
C846
22uF
10V
OPT
GND
IN
C843
22uF
10V
BS
+1.8V_DDR
IC807
SC4215ISTRT
NC_1
Q807
L805
500
R803
120K
+3.3V
IC803
MP2212DN
Close to IC
C834
10uF
10V
5
+1.8V for Saturn6 DDR
R1
C807
0.1uF
16V
C876
22uF
10V
C818 100pF 50V
R826
39K 1%
G
560
R806
R804
10K
C873
0.1uF
16V
COMP
+1.8V_MEMC for DDR
R832
POWER_ON
EN
6
Vout=0.8*(1+R1/R2)
+5V_ST
AO3407A
2A
LX_1
C854
2200pF
50V
L814
120-ohm
Q801
2SC3052
L821
3.6uH
LX_2
C898
0.1uF
50V
+5V_GENERAL
C819
10uF
10V
OPT
7
4
L894
3.6uH
C973
22uF
16V
2
3
FB
Placed on SMD-TOP
8
NR8040T3R6N
R897
51K
D5
close to IC811
1
18K
R853
S1
C894
220pF
50V
4
+5V_EXT
IC810
AOZ1073AIL
C809
3.3uF
50V
1/16W
5%
GND
5
3
COMP
1%
18K
R898
4
1%
BG
IC812
Si4800BDY
C971
1uF
25V
EN
R950
120K
1.6K 6.8K
R952 R951
6
1%
1/8W
22
R954
5%
1/16W
3
1%
R854
100K
VIN_2
9
R856
47K
1%
BST
10
2
D802
Vout = ((R1+R2)X0.8)/R2
R2
R956
4.7
1
SW_2
POWER_ON
$0.37
VCC
C970
1uF
50V
real output : 12.3V
R857
5.6K
1%
+24V
1%
1/16W
2
SW_1
+12V
R953
10K
EN/SYNC
EP_GND
47K
R896
IN
8
IC893
MP4460DQ-LF-Z
11
1
Switching noise reducing [MPS recommend]
MBRA340T3G
close to pin
R824
68K
SW
BST
0.1uF
50V
C969
10uF
35V
C967
0.1uF
50V
R858
10K
C879
THERMAL
IC811
MP8670DN-LF-Z
+5V_Normal
+12V
R894
100K
+24V
1
8
2
7
3
6
4
5
EN/SYNC
R841
3.3K
+1.8V_MEMC
L809
3.6uH
SW_2
EN
VIN
C859
22uF
10V
SW_1
C863
22uF
10V
Cout
C874
10uF
10V
C855
0.1uF
50V
NC_2
C877
0.47uF
25V
C875
0.1uF
16V
2
7
3
6
4
5
GND
R847
12K
1%
ADJ
VO
NC_3
C888
22uF
10V
R848
9.1K
1%
C892
0.1uF
16V
R1/R2 : 27K / 20K => Vout=1.88
R1/R2 : 15K / 12K => Vout=1.80
R1/R2 : 12K / 9.1K => Vout=1.85
Placed on SMD-TOP
R831
10
1%
8
OPT
VCC
R830
0
1
C853
1uF
16V
+1.26V Core for URSA
IC809
+5V_GENERAL
R2
APE8953MP
S6 core 1.26V volt
1.5mA
+5V_GENERAL
EN
+3.3V
+1.8V_MEMC
C869
1uF
16V
470K
R815
+12V
30K
R816
R809
33K
B
+1.26V_VDDC
OPT
R823
R1
10K
1/16W
R825
22K 1%
FB
OPT
E
R822
75K
1/8W
1%
C822
1000pF
50V
Q806
AO4813
+12V_PANEL
S2
C811
0.1uF
16V
C806
0.01uF
25V
C815
22uF
16V
8
1
D2_2
G2
2
7
D2_1
S1
3
6
D1_2
C829
0.1uF
16V
C IN
C838
22uF
10V
1
GND
IN
OPT
C842
22uF
10V
BS
2
3A
7
3
6
4
5
R812
10K
5
EN/SYNC
SW_2
SW_1
C845
22uF
10V
VCC
C839
0.1uF
50V
4
25V
0.01uF
C885
VOUT_2
C871
10uF
6.3V
R844
1K
C856
0.1uF
+3.3V
Placed on SMD-TOP
+5V_GENERAL
L813
CIC21J501NE
C840
1uF
10V
R839
10K
+3.3V
+3.3V_ST
R811
10K
STAND-BY +3.3V
3
1
C821
0.1uF
16V
C810
0.1uF
16V
C841
10uF
10V
ADJ/GND
C844
0.1uF
16V
3
1
IC806
MP2212DN
Close to IC
C866
560pF
50V
OPT
C860
0.1uF
16V
IC804
AP1117E33G-13
IN
2
100pF 50V
R837
R1 56K 1/10W 1%
+3.3V_AVDD_MPLL
18K
R8361/10W
1%
IC801
IN
C816
10uF
10V
C889
10uF
6.3V
Placed on SMD-TOP
Vout=0.8*(1+R1/R2)
AP1117E18G-13
ADJ/GND
C887
10uF
6.3V
C814
IC800
+3.3V_AVDD
OPT
C849
22uF
L810
120-ohm
AP1117E33G-13
C805
10uF
6.3V
5
1/10W
1%
VOUT_1
0
10
1/10W
1%
+5V_ST
C802
10uF
6.3V
3
R1/R2 = 12K/20K => Vout=1.28
C824
1000pF
50V
+3.3V
+5V_GENERAL
OUT
6
R1
R852
33K
FB
L895
BLM18SG121TN1D
L816
3.6uH
R821
D1_1
Q804
2SC3052
LOGIC_POWER_ON
C801
0.1uF
16V
2
+1.26V_MEMC
600 mA
+12V_LOGIC
C832
0.1uF
16V
330K
R820
OPT
R810
10K
4
470K
R819
G1
+3.3V_ST
C800
10uF
10V
7
Placed on SMD-TOP
NR8040T3R6N
R862
1
1
22K 1%
Close to IC
8
+12V
2
C868
10uF
6.3V
C891
0.47uF
25V
R2
Placed on SMD-TOP
L801
CB3216UA121
3
VIN
8
GND
Vout=0.8*(1+R1/R2)
1%
1/10W
27K
R846
Q800
2SC3052
+12V
IN
POK
VCNTL
Vout=0.8*(1+R1/R2)
R890
IC805
MP2212DN
C
R805
10K
R801
30K
Replaced Part
CIC21J501NE
Q802
2SC3052
PANEL_POWER_ON
L812
R829
1/10W
10K
C872
0.1uF
16V
OPT
L896
BLM18PG121SN1D
+12V
C899
100pF
50V
2026 mA
1%
1/10W
30K
R845
ADJ/GND
+3.3V_ST
FB
1
8
2
7
3
6
4
5
GND
L817
3.6uH
SW_2
+3.3V_HDMI_ST
2
OUT
NR8040T3R6N
IN
L811
120-ohm
SW_1
Placed on SMD-TOP
+1.8V_AMP
OUT
C850
10uF
6.3V
C827
10uF
6.3V
C830
0.1uF
16V
C852
0.1uF
16V
D804
C861
0.1uF
16V
C865
22uF
10V
OPT
BS
VCC
C881
0.1uF
50V
100V
1N4148W_DIODES
C882
10uF
6.3V
C883
0.1uF
16V
C884
22uF
10V
R842
Placed on SMD-TOP
R838
10
1/10W
1%
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
EN/SYNC
R2
0
C878
1uF
10V
OLED
Power
09.08.31
7
9
POWER
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
100
100
R922
R928
100
100
URSA_B-[1]
URSA_B+[1]
URSA_B-[0]
URSA_B+[0]
URSA_ACK-
URSA_A-[3]
R927
URSA_ACK+
R921
URSA_A+[3]
100
URSA_A-[2]
100
+3.3V
URSA_A+[2]
100
R926
URSA_A-[1]
100
R920
P900
TF05-51S
URSA_A+[1]
100
R925
URSA_A-[0]
+3.3V
R924
100
R919
URSA_A+[0]
R918
M_XTALO
C901
20pF
M_XTALI
MEMC_RXO0-
MEMC_RXO0+
MEMC_RXO1-
MEMC_RXO1+
MEMC_RXO2-
MEMC_RXO2+
MEMC_RXOC-
MEMC_RXOC+
MEMC_RXO3-
MEMC_RXO3+
MEMC_RXO4-
MEMC_RXO4+
MEMC_RXE0-
MEMC_RXE0+
MEMC_RXE1-
MEMC_RXE1+
MEMC_RXE2-
MEMC_RXE2+
MEMC_RXEC-
X900
12MHz
MEMC_RXEC+
M_XTALI
C900
20pF
MEMC_RXE3-
M_XTALO
MEMC_RXE3+
1M
MEMC_RXE4-
R905
MEMC_RXE4+
XTAL
+3.3V
1
2
R939
4.7K
1:AO17
3
PANEL_RESET
4
C921
LVDS_SEL
C943
C944
1uF
C952
10uF
C957
0.1uF
C953
0.1uF
C956
0.1uF
10
11
LVDS_SEL
820
REXT
LVB1M
LVB1P
LVB0M
LVB0P
GPIO_4
GPIO_6
LVA4M
LVA4P
LVA3M
LVA3P
LVACKM
LVACKP
LVA2M
LVA2P
LVA1M
LVA1P
LVA0M
LVA0P
AVDD_PLL
GND_2
GPIO_8
GPIO_9
GPIO_12
GPIO[25]
SCLM
SDAM
GPIO_1
GPIO_2
XIN
XOUT
GPIO_14
GPIO_13
GND_5
AVDD_LVDS_2
RO0N
RO0P
RO1N
RO1P
RO2N
RO2P
ROCKN
ROCKP
RO3N
RO3P
RO4N
RO4P
GND_6
AVDD_LVDS_1
RE0N
RE0P
RE1N
RE1P
RE2N
RE2P
RECKN
RECKP
RE3N
RE3P
RE4N
LG
(VESA)
URSA_B-[2]
12
URSA_B+[2]
13
D12
C14
C13
A13
B13
D7
D9
B12
A12
C12
C11
A11
B11
B10
A10
C10
C9
A9
B9
G8
F10
D11
D13
E11
N7
D6
D5
A14
B14
D3
D4
K16
K15
H7
G11
B8
A8
C8
C7
A7
B7
B6
A6
C6
C5
A5
B5
H8
F11
B4
A4
C4
C3
A3
B3
B2
A2
C2
GPIO[9]
G1
E3
GPIO_10
GND_14
K8
D2
GPIO_3
VDDC_1
E5
GPIO[10]
E2
GPIO[11]
F2
[E1]
[D1]
17
C15
URSA_B+[2]
B15
LVB2M
URSA_B-[2]
A15
LVBCKP
URSA_BCK+
URSA_BCK-
F3
A16
LVBCKM
GPIO[13]
G2
B16
LVB3P
URSA_B+[3]
GPIO[22]
M4
C16
LVB3M
URSA_B-[3]
GPIO[23]
M5
D15
LVB4P
GPIO[14]
G3
D16
LVB4M
20
23
E15
LVC0P
H4
E16
LVC0M
GPIO[19]
J4
E14
LVC1P
GPIO[20]
K4
F14
LVC1M
GPIO[21]
L4
F16
LVC2P
VDDP_2
J6
F15
LVC2M
GND_7
H9
G15
LVCCKP
GND_15 K9
G16
LVCCKM
URSA_A-[1]
G14
LVC3P
URSA_A+[1]
MDATA[20]
H1
H16
LVC4P
MDATA[19]
H2
H15
LVC4M
J15
LVD0P
J16
LVD0M
J14
LVD1P
K14
LVD1M
GND_3
L14
LVD2P
MDATA[30]
K2
L15
LVD2M
AVDD_DDR_2
K6
L16
LVDCKP
DQM[3]
K3
M16
LVDCKM
DQM[2]
L1
F8
GND_10
J8
M15
LVD3P
C929
URSA_DQSB3
URSA_DQ[31]
URSA_DQ[24]
C925
0.1uF
URSA_DQ[26]
URSA_DQ[29]
LVD4P
AVDD_DDR_4
L6
N15
LVD4M
VDDP_3
L8
H10
H6
VDDC_5
M1
N6
GPIO[24]
DQSB[3]
M2
E12
GPIO[7]
AVDD_DDR_5
L7
D14
GPIO[6]
MDATA[31]
M3
F12
GPIO[5]
MDATA[24]
N1
E13
GPIO[4]
GND_11
J9
F13
GPIO[3]
MDATA[26]
N2
G13
GPIO[2]
MDATA[29]
N3
H13
GPIO[1]
L10
J13
GPIO[0]
K12
PWM0
L12
PWM1
K13
CSZ
M12
SDO
M13
SDI
MDATA[23]
P1
URSA_DQ[16]
MDATA[16]
R1
URSA_DQ[18]
MDATA[18]
T1
URSA_DQ[21]
MDATA[21]
T2
MCLK[0]
R2
MCLKZ[0]
P2
L13
SCK
GND_1
G7
N14
GPIO[30]
L9
N13
N5
N12
[N12]
C949
42
43
JP8
44
L907
120OHM
+3.3V
0.1uF
45
46
C959
0.1uF
16V
C960
1000pF
50V
47
R940
0
R941
0
48
SDA2
SCL2
49
50
51
52
GPIO[29]
GPIO[28]
G6
M11
N11
N10
N9
P16
R16
T16
P15
R15
T15
P14
R14
T14
P13
R13
T13
H11
J7
P12
R12
T12
P11
J11
R11
T11
P10
R10
K11
T10
P9
K7
R9
T9
F7
K10
N8
P8
R8
T8
P7
R7
L11
T7
P6
R6
T6
C919
T3
0.1uF
N4
P5
ODT
URSA_ODT
R5
MVREF
T5
AVDD_MEMPLL
P4
0.1uF
J10
C923
R4
URSA_MCLK
URSA_MCLKZ
[L9]
[N4]
41
16V
D809
N16
[N5]
40
+12V_LOGIC
0.8A(Typ)
C964
10uF
L3
URSA_DQ[23]
PI Result
39
C963
1000pF
50V
M14
DQSB[2]
[N13]
38
L908
120OHM
C962
0.1uF
16V
L2
LVD3M
AVDD_DDR_6
37
0.1uF
AVDD_33_1
DQS[2]
DQS[3]
0.1uF
K1
JP1
+12V_PANEL
3.4A[300nit](Typ)
C955
G9
MDATA[25]
URSA_DQS3
35
30V
OPT
LGE7329A
URSA_DQ[30]
GND_8
34
36
J3
URSA_DQ[25]
0.1uF
33
URSA_A+[0]
J2
0.1uF
C926
31
32
D808
MDATA[28]
30
URSA_A-[0]
C961
10uF 16V
MDATA[27]
URSA_DQ[28]
J1
28
29
1K
URSA_DQ[27]
IC901
H3
27
URSA_A+[2]
1K
OPT
MDATA[22]
26
URSA_A-[2]
R934
MDATA[17]
URSA_DQ[22]
25
0.1uF
1K
R936
URSA_DQ[17]
24
URSA_ACK+
1K
R937
URSA_DQ[19]
LVC3M
C954
OPT
R935
URSA_DQ[20]
H14
22
URSA_ACK-
G4
F6
21
URSA_A+[3]
GPIO[18]
VDDC_2
19
URSA_A-[3]
GPIO[17]
C928
18
URSA_B+[0]
0.1uF
16V
C932
16
URSA_B-[0]
LVB2P
AVDD_33_2
15
URSA_B+[1]
GPIO[12]
T4
URSA_DQ[0-31]
C1
E10
GPIO_11
C916
10uF
C911
10V
22uF
C909
0.1uF
0.1uF
C905
C907
GPIO_7
GND_4
URSA_DQS2
0.1uF
GPIO_5
D10
0.1uF 0.1uF
+3.3V
D8
URSA_B-[1]
F9
URSA_DQSB2
C906
DISM
(JEIDA)
10uF
G10
URSA_DQM2
0.1uF
LOW
F4
URSA_DQM3
C902
HIGH
E4
C924
C903
C951
10uF
GPIO[16]
PI Result
Placed on SMD-TOP
10uF
R931
9
URSA_BCK+
GPIO[15]
L901
BLM18PG121SN1D
8
D1
F1
P3
10V
C914
0.1uF
16V
E1
R3
+1.8V_MEMC
C910 10uF
+3.3V
1K
C908 10uF
R907
7
30V
OPT
0.1uF
R906
OPT
1K
6
URSA_BCK-
GPIO[8]
SCLS
1K
A1
SDAS
C931
R904
0.1uF
C941
C937
0.1uF
0.1uF
10uF
C933
RE4P
R915
100
100
B1
R914
MEMC_SDA
MEMC_SCL
R903
OPT
1K
URSA_B-[3]
14
1K
+3.3V
R911
OPT
Q900
2SC3052
URSA_B+[3]
C950
+3.3V
5
R938
LVDS_SEL
1:AO32
0.1uF
PI Result
R910
100
100
0.1uF
C934
C927
C917
0.1uF
10uF 10V
C930
10uF
C913
C915 0.1uF
22uF
10V
C912
L903
R929
R923
Placed on SMD-TOP
BLM18PG121SN1D
+3.3V
0.1uF
C945
+1.26V_MEMC
0.1uF
PI Result
VDDC_4
RESET
GND_17
GPIO[27]
GPIO[26]
MCLKZ[1]
MCLK[1]
MDATA[5]
MDATA[2]
MDATA[0]
MDATA[7]
MDATA[13]
MDATA[10]
MDATA[8]
MDATA[15]
DQSB[1]
DQS[1]
VDDP_1
GND_9
DQSB[0]
DQS[0]
DQM[0]
DQM[1]
C948
0.1uF
0.1uF
C947
C946
0.1uF
AVDD_DDR_1
MDATA[14]
MDATA[9]
MDATA[12]
MDATA[11]
AVDD_DDR_3
MDATA[1]
GND_13
MDATA[3]
VDDC_3
MDATA[4]
MDATA[6]
0
R930
URSA_DQ[5]
URSA_DQ[2]
URSA_DQ[0]
MDS62110207
URSA_DQ[7]
URSA_DQ[13]
URSA_DQ[10]
URSA_DQ[8]
URSA_DQ[15]
URSA_DQ[14]
URSA_DQ[9]
URSA_DQ[12]
URSA_DQ[11]
URSA_DQ[6]
URSA_A[7]
URSA_A[12]
URSA_A[9]
URSA_A[5]
URSA_A[10]
URSA_A[1]
URSA_A[11]
URSA_A[8]
URSA_A[6]
URSA_A[4]
URSA_A[2]
URSA_A[0]
C918
C922
1uF
URSA_A[3]
URSA_DQ[1]
M5
MDS62110207
GPIO8
PWM1
PWM0
I2C
HIGH
LOW
EEPROM
HIGH
HIGH
LOW
SPI
HIGH
HIGH
HIGH
M6
MDS62110207
URSA_DQ[0-31]
M_SPI_DI
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
HIGH
M_SPI_CK
URSA_MCLKZ1
56
URSA_MCLK1
56
R909
URSA_DQSB1
R908
DIO
URSA_DQS1
CLK
URSA_DQSB0
5
URSA_DQ[3]
6
4
M3
HOLD
URSA_RASZ
3
VCC
URSA_DQS0
WP
GND
7
URSA_DQM0
10K
8
2
URSA_DQM1
R902
1
MEMC_RESET 1:Z22
M4
URSA_A[0-12]
DO
MDS62110207
100
MDS62110207
URSA_MCLKE
CS
56
URSA_BA0
56
R901
URSA_BA1
R900
M1
MDS62110207
M2
URSA_WEZ
M_SPI_DO
URSA_CASZ
M_SPI_CZ
CONTACT TO MODULE FOR EMI
R932
URSA_DQ[4]
W25X20AVSNIG
M_SPI_CK
10K
0.1uF
0.1uF
C904
IC900
10K
R917
+3.3V
0.1uF
SPI FLASH
M_SPI_DI
R933
C940
C939
C938
C936
C935
10K
R916
0.1uF 0.1uF 0.1uF 0.1uF
M_SPI_DO
+3.3V
0.1uF
GND_16
MCLKE
MADR[3]
C942
MADR[7]
MADR[9]
MADR[12]
MADR[5]
AVDD_DDR_7
MADR[10]
MADR[1]
BADR[0]
BADR[1]
WEZ
MADR[11]
MADR[8]
MADR[6]
GND_12
MADR[4]
MADR[2]
CASZ
RASZ
C920
MADR[0]
M_SPI_CZ
0.1uF
OLED
FRC / LVDS
09.08.31
8
9
LGE Internal Use Only
resonance Compensation
DDR2 1.8V By CAP - Place these Caps near Memory
+1.8V_MEMC
+1.8V_FRC_DDR
+1.8V_MEMC
+1.8V_FRC_DDR
+1.8V_FRC_DDR
+1.8V_FRC_DDR
C1052
0.1uF
0.1uF
0.1uF
C1051
0.1uF
C1050
C1048
0.1uF
C1049
0.1uF
C1047
0.1uF
C1046
0.1uF
C1045
C1042
0.1uF
0.1uF
0.1uF
C1041
0.1uF
C1040
0.1uF
C1039
C1037
0.1uF
C1038
0.1uF
0.1uF
C1036
0.1uF
C1034
0.1uF
C1035
0.1uF
C1033
10uF
C1032
0.1uF
C1031
0.1uF
C1030
0.1uF
C1029
0.1uF
C1028
10uF
C1027
10V
C1026
C1025
10uF
C1024
0.1uF
0.1uF
C1022
0.1uF
0.1uF
C1020
0.1uF
C1019
0.1uF
C1018
0.1uF
C1017
0.1uF
C1016
10uF
C1015
0.1uF
0.1uF
C1014
C1013
0.1uF
C1012
0.1uF
C1011
0.1uF
C1010
0.1uF
C1009
0.1uF
C1008
0.1uF
C1007
10uF
C1006
10V
C1005
C1004
10uF
0.1uF
C1003
0.1uF
0.1uF
C1002
0.1uF
C1001
C1000
BLM18PG121SN1D
L1000
PI Result
56
DDR_DQ[26]
DDR_DQ[29]
AR1003
URSA_DQ[23]
DDR_DQ[23]
DDR_DQ[16]
URSA_DQ[16]
56
URSA_DQ[21]
DDR_DQ[18]
DDR_DQ[21]
H7
DDR_DQ[19]
DQ3
H3
DDR_DQ[20]
DQ4
H1
DDR_DQ[21]
DQ5
H9
DDR_DQ[22]
DQ6
F1
DDR_DQ[23]
DQ7
F9
DDR_DQ[24]
DQ8
C8
DDR_DQ[25]
DQ9
C2
DDR_DQ[26]
DQ10
D7
DDR_DQ[27]
DQ11
D3
DDR_DQ[28]
DQ12
D1
DDR_DQ[29]
DQ13
D9
DDR_DQ[30]
DQ14
B1
DDR_DQ[31]
DQ15
B9
+1.8V_FRC_DDR
J2
M8
A0
DDRB_A[0]
M3
A1
DDRB_A[1]
M7
A2
DDRB_A[2]
N2
A3
N8
A4
DDRB_A[4]
N3
A5
DDRB_A[5]
N7
A6
DDRB_A[6]
P2
A7
DDRB_A[7]
P8
A8
DDRB_A[8]
P3
A10/AP
DDRB_A[10]
A11
DDRB_A[11]
R2
A12
DDRB_A[12]
L2
BA0
L3
BA1
A1
VDD4
E1
VDD3
J9
J8
CK
VDD2
M9
K8
CK
K2
CKE
VDD1
R1
K9
ODT
VDDQ10
A9
L8
CS
VDDQ9
C1
K7
RAS
VDDQ8
C3
L7
CAS
VDDQ7
C7
K3
WE
VDDQ6
VDDQ5
DDRB_A[1]
URSA_A[1]
22
AR1005
DDRB_A[7]
22
URSA_A[7]
DDRB_A[0]
DDRB_A[4]
AR1006
22
DDRB_A[6]
DDRA_A[3]
22
DDRA_A[1]
DDRA_A[12]
22
DDRA_A[7]
URSA_A[7]
URSA_A[5]
URSA_A[5]
URSA_A[0]
URSA_A[2]
URSA_A[2]
URSA_A[0]
AR1013
DDRA_A[0]
URSA_A[4]
URSA_A[6]
22
DDRA_A[6]
URSA_A[6]
URSA_A[4]
B_URSA_RASZ
URSA_RASZ
URSA_RASZ
B_URSA_CASZ
DDRB_A[11]
URSA_CASZ
URSA_A[11]
URSA_A[8]
URSA_CASZ
URSA_A[8]
DDRB_A[8]
B_URSA_BA1
R1003
R1004
DDRA_A[5]
DDRA_A[2]
AR1010
22
22
URSA_MCLK
URSA_MCLKZ
22
URSA_ODT
22
DDRA_A[11]
009:AB4
URSA_MCLK1
009:AB4
URSA_MCLKZ1
010:Q14;009:J10
R1021
1K 1%
1000pF
C1043
0.1uF
C1044
M8
DDRA_A[1]
A1
M3
DDRA_A[2]
A2
M7
A3
N2
DDRA_A[4]
A4
N8
DDRA_A[5]
A5
N3
DDRA_A[6]
A6
N7
DDRA_A[7]
A7
P2
DDRA_A[8]
A8
P8
A9
P3
DDRA_A[10]
A10/AP
M2
DDRA_A[11]
A11
P7
DDRA_A[12]
A12
R2
DDRA_A[9]
A_URSA_RASZ
010:V9
010:Y14;009:J10
A0
A_URSA_CASZ
DDRA_A[8]
URSA_A[11]
009:J11
J2
DDRA_A[0]
DDRA_A[3]
DDRA_A[4]
A_URSA_BA0
22
009:J10
B_URSA_MCLKE
010:T10
R1005
DDRA_A[9]
URSA_A[12] AR1012
AR1007
B_URSA_BA0
DDRA_A[10]
URSA_A[9]
URSA_A[12]
DDRB_A[5]
DDRB_A[2]
AR1011
URSA_A[1]
URSA_A[10]
URSA_A[3]
URSA_A[9]
DDRB_A[12]
URSA_A[3]
URSA_ODT
R1012
R1013
A_URSA_BA1
22
22
A_URSA_MCLKE
R1014
22
BA0
L2
BA1
L3
G8
DQ0
G2
DQ1
DDR_DQ[1]
H7
DQ2
DDR_DQ[2]
H3
DQ3
DDR_DQ[3]
H1
DQ4
DDR_DQ[4]
H9
DQ5
DDR_DQ[5]
F1
DQ6
DDR_DQ[6]
F9
DQ7
DDR_DQ[7]
C8
DQ8
DDR_DQ[8]
C2
DQ9
D7
DQ10
DDR_DQ[10]
D3
DQ11
DDR_DQ[11]
D1
DQ12
DDR_DQ[12]
D9
DQ13
DDR_DQ[13]
B1
DQ14
DDR_DQ[14]
B9
DQ15
DDR_DQ[15]
A1
VDD5
E1
VDD4
CK
J8
J9
VDD3
CK
K8
M9
VDD2
CKE
K2
R1
VDD1
ODT
K9
CS
L8
A9
VDDQ10
K7
C1
VDDQ9
CAS
L7
C3
VDDQ8
WE
K3
C7
VDDQ7
C9
C9
VDDQ6
E9
E9
VDDQ5
G1
VDDQ4
G3
VDDQ3
G7
VDDQ2
G9
VDDQ1
VDDQ4
G1
VDDQ3
G3
VDDQ2
G7
VDDQ1
G9
F7
LDQS
B7
UDQS
F3
LDM
B3
UDM
B_URSA_RASZ
B_URSA_CASZ
B_URSA_WEZ
R1006
R1007
R1008
R1009
56
56
56
56
VSS5
A3
E8
LDQS
R1010
56
VSS4
E3
A8
UDQS
R1011
56
VSS3
J3
VSS2
N1
P9
VSSQ10
B2
VSSQ9
B8
VSSQ8
A7
VSSQ7
D2
VSSQ6
D8
VSSQ5
E7
VSSQ4
F2
VSSQ3
F8
VSSQ2
H2
VSSQ1
H8
010:R16
010:R16
010:T10
010:X16
A_URSA_RASZ
010:X16
A_URSA_CASZ
010:V8
URSA_DQS2
009:J14
009:X4
URSA_DQS0
URSA_DQS3
009:J13
009:Y4
URSA_DQS1
URSA_DQM2
009:J15
009:X4
URSA_DQM0
URSA_DQM3
009:J15
009:W4
URSA_DQM1
URSA_DQSB2
009:J14
009:X4
URSA_DQSB0
URSA_DQSB3
009:J13
009:Y4
URSA_DQSB1
L1
NC4
R3
NC5
B_URSA_BA0
URSA_BA0
NC6
B_URSA_BA1
A2
NC1
E2
NC2
R8
NC3
010:Q14
B_URSA_MCLKE
010:Q13
B_URSA_WEZ
J1
VDDL
56
LDQS
F7
R1016
56
UDQS
B7
R1017
56
LDM
F3
R1018
56
UDM
B3
R1019
56
LDQS
E8
A3
VSS5
R1020
56
UDQS
A8
E3
VSS4
J3
VSS3
N1
VSS2
P9
VSS1
B2
VSSQ10
B8
VSSQ9
A7
VSSQ8
D2
VSSQ7
NC4
NC5
R3
URSA_BA1
010:T9;009:R4
NC6
R7
URSA_MCLKE
010:T9;009:T4
URSA_WEZ
010:T8;009:R4
NC1
A2
NC2
E2
22
010:V10;009:S4
URSA_BA0
A_URSA_BA0
010:AA15
010:V10;009:R4
URSA_BA1
A_URSA_BA1
010:AA15
010:V10;009:R4
URSA_MCLKE
URSA_WEZ
22
L1
010:T9;009:S4
AR1009
010:V10;009:T4
VSSDL
R1015
AR1008
+1.8V_FRC_DDR
J7
A_URSA_WEZ
A_URSA_MCLKE
010:Z14
A_URSA_WEZ
010:Y13
NC3
+1.8V_FRC_DDR
R8
D8
VSSDL
VDDL
J7
J1
DDR_DQ[0]
DDR_DQ[9]
URSA_DQ[8]
DDR_DQ[10]
URSA_DQ[10]
DDR_DQ[13]
URSA_DQ[13]
DDR_DQ[7]
AR1015
DDR_DQ[0]
56
URSA_DQ[7]
URSA_DQ[0]
DDR_DQ[2]
URSA_DQ[2]
DDR_DQ[5]
URSA_DQ[5]
DDR_DQ[11]
AR1016
URSA_DQ[11]
56
DDR_DQ[12]
DDR_DQ[9]
URSA_DQ[9]
DDR_DQ[14]
DDR_DQ[6]
DDR_DQ[1]
URSA_DQ[12]
URSA_DQ[14]
AR1017
URSA_DQ[6]
56
URSA_DQ[1]
DDR_DQ[3]
URSA_DQ[3]
DDR_DQ[4]
URSA_DQ[4]
+1.8V_FRC_DDR
RAS
R7
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
URSA_A[10]
AR1004
DDRB_A[3]
DDRB_A[9]
DDRB_A[9]
M2
P7
VDD5
VSS1
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
A9
DDRB_A[3]
DDRB_A[10]
URSA_DQ[15]
56
DDR_DQ[8]
DDR_DQ[0-15]
DDR_DQ[24]
URSA_DQ[29]
URSA_DQ[18]
DDR_DQ[31]
G2
DQ2
R1023
OPT
AR1002
URSA_DQ[24]
DQ1
VREF
150
DDR_DQ[20]
G8
DDR_DQ[17]
DDR_DQ[18]
VREF
DDRA_A[0-12]
DDR_DQ[19]
56
URSA_DQ[31]
AR1014
DDR_DQ[15]
H5PS5162FFR-S6C
DDRB_A[0-12]
DDR_DQ[17]
URSA_DQ[20]
URSA_DQ[26]
DDR_DQ[22]
DQ0
150
AR1001
URSA_DQ[17]
DDR_DQ[16]
OPT
R1000
DDR_DQ[30]
URSA_DQ[22]
URSA_DQ[0-31]
IC1001
DDR_DQ[25]
URSA_DQ[30]
URSA_DQ[19]
H5PS5162FFR-S6C
DDR_DQ[28]
56
DDR_DQ[16-31]
URSA_DQ[25]
1K 1%
1K 1%
1K 1%
URSA_A[0-12]
R1001
R1002
DDR_DQ[27]
URSA_DQ[28]
0.1uF
AR1000
URSA_DQ[27]
C1021
IC1000
1000pF
C1023
URSA_DQ[0-31]
R1022
+1.8V_FRC_DDR
+1.8V_FRC_DDR
VSSQ6
E7
VSSQ5
F2
VSSQ4
F8
VSSQ3
H2
VSSQ2
H8
VSSQ1
OLED
FRC DDR2
09.08.31
9
9
LGE Internal Use Only