Download Goldstar FC200 service manual

Goldstar FC200 service
manual
CHAPTER
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CHAPTER
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Scanned and converted to PDF by HansO, 2001
INDEX
1. HARDWARE CONFIGURATION
2. BASIC FUNCTION SPECIFICATION
3. CARTRIDGE
4. ADDRESS MAP
5. CONCEPTION OF THE SLOT
6. EXPLANATION OF MAIN CIRCUIT
7. CIRCUIT DIAGRAN
8. PARTS LOCATION Е
14
18
23
28
41
53
1 General Specification
*CFU Z-8304 avr Equivalence
‘MEMORY | В ROM “2KE(MSX BASIC)
RAM 64KB
“CRT DISPLAY TEXT MODE 40chr«24line
GRAPHIC MODE 256:192dots
COLOR ibcolor
"CMT Ш — EFSK METHOD
1200/2400 baud rate
*SOUND FUNCTION | 3 octave,3 tones output
“KEYBOARD Alphanumeric,graphic symbol
code symbols
"FLOPPY DISK 54" supporting(MSX-DOS formatting)
34 Te
‘PRINTER - 8 bit parallet(Centronics)
“ROM Cartridge — В 1/0 bus
+
Game cartridge,expansion bus cartridge
Joystick 1 or 2
ia
1. 2 SYSTEM CONFIGURATION
MINIMUM
SOUND OUTPUT . VIDEO OUTPUT CARTRIDGE SLOT}
JOYSTICK Z80A — 10M 32KB
PSG RAM 64KB
vDP РР]
CASSETTE KEYBOARD
° SOFTWARE SUPPORT AREA
PRINTER OUTPUT
JOYSTICK
ко
VIDEO OUTPUT CARTRIDGE SLOT EXPANSION
| CASSTTE
CARTRIDGE
ZBOA “ROM 32KB
PSG RAM G4KB
VDP РР]
KEYBOARD
«The number of the slot is maxinum 16 containing system
1 LSI
“Cru
“VD
SPEC,
780A of equivalence
CLOCK 3.37994 MZ
1 WALT SIGNAL is inserted after each Mi
cvele.
THMS9 1 2UNL
AY - 31-8910
INTEL -BZ5%A
7. 2 MEMO
RO
” RA
* There
access 256kH ROM, RAM.
ye memo
+ Basic ROM exists farm
From FFFFH to lower
iY
td
М
is 4 basic slot
PY arca.
details.
MSX BASIC INTERPRETER 32KU
USER RAM :64k6
VIDÉO RAM: 10KI3
in system, and the systoen can
And it can have maximum 1M
OO00H to 7FFFFH,and RAM exists
address.Refer Lo Chapter 4. for
2. 3 INTERRUPT
* NMÍ---Not use, MSX UASIC has RaM HOOK.
2 INT--- VDP or cartridge bus can input external inter-
YDP
INT
rupt signal .VDP inputs interrupt signl
to CPU on every 1/50 sec, then CPU restarts
From 0038H.
INTERRUPT CIRCUIT EXAMPLE.
J
, DISPLAY MODE
1
Li TMSO129NL
« Chaflavcter ‘ulptharcumeric-graphiec symbols (8:3 dots)
16 colors
«Color
« sprite possible ”
x Displav mode table
MODE | RESOLUTION | SIZE|NO | COLOR] SPRITE! DI PLAY
GRAPHIC 1 12404192 |18:8 1256| 16 | о | 024
GRAPHIC 2 [240-192 18.8 (7651 16 | O | 29-04
MULT! COLOR| 64 «<48D1k ans | - [ 16 | 0 | 29<24
Ш | 39424
| 240x192
TEXT ¡8x6 |256]20f16| *
x NO: THE NUMBER OF PATTERN
2, 5 DISPLAY MIANACTER CODE
010 {0 0 {00001 }1 {1 (1 {1 F3 ia fa
< - |
D/0/0/0/0}1|1 1 1 j0 jo j0 j0 |1 |1 }1 |!
pre
S100 rojo 1111 J0f0 (1 [1 [0 (0 (1 A]
©
о): |0] 3 1073 |0 11 10 |1 |0 11 }0 j1 jo |1
Lower 4 Bit | О 11213 14 15 16 |7 18 19 | А [В 1С | ОТЕ ЦЕ
olololala lez + (2/0 [@p | Ip Is IE la lA a |=
ojlolo|i 11/94! 13 О {а 19 {Ule |i 17 в |+
ото 1 | 012 | @ + п Т2 в | К ГЫ | т |е (Е ТЬ | Т + {>
0 0f1]1]3 ie #13 | с | 5 [ста [А | 5 |613 я | <
о) 10| ога | ф | 5 |4 | р) т | а 1 | 8 | 5 | п | © | zip
olıf of 1] sie %|s{E|Ulefuld|d|{N|D о
i * | | J
о 1 | 1101618 & | 6 | ЕМУ | гру | 8 | Ва | 0 +
A E —
ofI|I|1)7|*— TG Wig pw |b ou т | =
11 0} 0/ 0/8 1 (| 8j H{X|h|x|e [5 {6/9 \ | $ | °
в ОГО! > OH 911 Ylilyle oli | + |] *
| ey |
11011101 EG Ye 3 |211 |: |е ТО | х w(nie
Ed
iTofililalablal: Ix)rix)r Ir Lela|—L в
i pr oa
1| 1j; 0/0/C|? |< рН ЕЕ | КО 1 n
jiji] | -|=pMII (mi III (AE %, 6 |
— ‹ - _
Пао) о| Е |) |. | >| мл |» | = | А) Р| << ia | ela
Ppp vp) Fb [| 70) jet at ALS [>] 8 A | ews
- 10 -
>. 9 PRINTER INTERFACE
. STANDARD 5 nit parallel,
ı LEVEL TTL
+ CONNECTOR CAMPRENOL 1A PIN
-~
' SIGNAL TABLE |
TERMINAL NOI SIGNAL] PIN CONNECTION
1 ¡FESTA |
"оо | PDBO |
3 |FDBR1 1
4 ipppz | 7 65 43 2 1
ra TOTO
6 1PoB4 | |
— ти ЗОО
> | PDB6 | 14 13 12 11 103 8
9 | PDBY | —
10 | NC | |
11 (BUSY | I |
pin arrangement toward the system
12 | NC |
13 | NC |
14 |! GND |
2. 10 THE LIST OF CONNECTOR
| TERMINAL NAME | SPEC/STANDARD
VIDEO OUTPUT |
COMPOSITE SIGNAL OUTPUT| RCA 2 PIN CONNECTOR
RF SIGNAL | | RCA 2 PIN CONNECTOR
CASSETTE od DIN 8 PIN CONNECTOR
GENERAL 1/0 PORT | AMP 9 PIN CONNECTOR |
PRINTER | AMPHENOL 14 PIN CONNECTOR
CARTRIDGE BUS | 2.54 PITCH,50 PIN CONNECTOR
AUDIO OUTPUT [ RCA 2 PIN CONNECTOR |
3. 1
BLOCK DIAGRAM
CPU
(2-80
COMPATABLES|
|
ROM
32K8
RAM
64KB
PRINTER
CH INTERFACE
PRINTER
CONNECTOR
iC
ROM PACK
SLOT
CONNECTOR (50 PIN}
FOR ROM CARTRIDGE
LIGHT PEN
INTERFACE
|
KEY BOARD
PP}; CASSETTE
| ° 8255 | INTERFACE O)
- CMTIN
REM
CMTOUT
VDP V-RAM |
9129 16KB _
VIDEO
Y
В RF OUTPUT
PSG RE
AY -3-8910 MODULATOR
т AUDIO
OUTPUT
EXPASION
BOX
{5Q pin}
O LIGHT PEN
DO
JOYSTICK
CONNECTOR
3.2 CARTPIDGE EUS
>1shat
ee ны очей ле и НЫ ——] o кеше тей Hi — Не ее тен ее Че жен gy gly pki Mar.
[= токе ен НР ет = = ен ен = бт ен тт ее ее ее ен ре т ен -
HC, $ STGRAL FAME 170 O, ¡o SIGHAL HAME HA
1 СОВЫ 0 2 сев x
3 CEl1z2d4) G 4 SLTEL ‘HD Cl
5 Reserved +1 — 6 RES (HD С
2 WAIT (MY +2 I 8 ТНГ СЫ) «2 я I
a M1 CHD J 10 EUSDIR I
11 1ORGH MD О 12 MERG CH) x O
13 WR UMD C 14 RD HD $ CG
15 PESET СМ) G 16 COMP, VIDEO 5
17 Ag C 18 815 C
19 all С 20 A1O О
21 A7 0 22 AS D
23 12 C 24 AS Ci
25 Al: О 25 R13 С.
27 Al С 23 AU o
29 AS G 3d AZ o
31 as © 32 Ad О
33 D1 170 34 DO 1/0
35 D3 1/0 35 DZ 1/0
37 DS 10 33 D4 | 1/0
39 | D7 1/0 40 | De | 1/0 :
41 GHD — 42 CLOCK (3, SemHz) o
43 END - 44 SW1 —
45 +S - dE SW2 —
47 +5U ~ 498] +120 —
+= SUNDIN I 50 -12U Do
*1 :“Reserved" means that this pin is evohibited to be
+2
oFren collector state
3,3 CARTRIDSE BUS SIGHAL FUNCTION
MO STEAL HAE CONTENTS
1 Del (H) ROM 4000H+7FFFH ADDR. SELECTION SIGHMAL
2 C32 (1D ROM 8000H~RFFFH ADDR. SELECTION SIGHAL
3 C512 ND | ROM 4000H-BFFFH ADOR. SELECTION SIGHAL
4 Su TSL CD SLOT SELECTION SIGHAL EACH SLOT
= Reserved |
E RFSH (4) REFRESH CYCLE SIGMAL
7 WATT CH) WAIT REQUEST SIGHAL TO CPU
3 THT CHD INTERRUPT REQUEST SIGHAL TO CPU
3 MI CD MACHINE LANGUAGE FETCH CYCLE
10 BUSDIR DATA BUS DIRECTION SIGNAL
11 IORG CH) ` | INPUT/OUTPUT REQUEST SIGHAL
12 IMERGI(H) MEMORY REQUEST SIGNAL
13 WR (HD WRITE CYCLE SIGNAL
14 RD CH) | READ CYCLE SIGHAL
15 RESET (MD CPU RESET SIGHAL
16 COMP. UTDEO COMPOSITE VIDEO SIGHAL
17-32 180-815 ADDRESS BUS SIGNAL
55-40 100-02? | DATA BUS SIGNAL
$1, 43 [GHD SIGHAL GROUND
42 CLOCK CPU CLOCK: 3, SOMHz |
i4, 46 15W1, SWZ FOR SYSTEM, PROTECTION 8: AUTO RESET
45, 47 | +5 +5 POWER
48 +124 +120 POWER |
43 SUHDIH EXTERNAL SOUND IMPUT(-Sdbm)
30 1-12Uu -12U POWER | |
Ad. 1
vy The following diagram is Che memory map.
dad;
| ©000
‚ 8000
CPU
MEMORY
MEMORY MAD
A000
8000
0000
32K8
SYSTEM
| ROM
MSX
BASIC
|
SLOT #0
SYSTEM
SLOT
64KB
RAM
BASIC
EXPAN-
SION
|
CARTRIDGE
SLOT # 2
RAM
SLOT
SLOT # 3
EXPANSIN
SLOT
LU
DIS LE.
DO
co
HO
AB
AU
98
90
50
(6)
|
JO ADRS
Wm nn еб
DIV Pee
PP]
psa СС 5
——
VDP
PRINTER
RS-232C
=
1
lo ADRIRWI (ONTENT EE
81198 |W [VRAM DATA WRITE [9129
(1? |VRAM DATA. READ |
81199 |W | COMMAND, ADDRESS SET |
IR STATUS READ | Ш
КНАО [W [ADDRESS LATCH [AY -3-8910
&HAT |W [DATA WRITE |
8HAZ | R [DATA READ {
RHAB |W |PORT-A DATA WRITE |8255a
| R READ |
&HA9 |W |PORT-B DATA WRITE |
IR | Ш read |
EHAA |W |PORT-C DATA WRITE |
IR | | — READ |
&HAB. |W |MODE SET | |
18196 |W | STROBE OUTPUT(bO) |LATCH OUT
‚IR [STATUS INPUTCDI) [BUSY '1°
&H91 |W | PRINT DATA
| LATCH OUT |
„анны = 9
д, PPL mi ASSLGNNENT
PORT DET EY НАМ FUNCT HON
© ese | star 1 TOR 609060 pr
A О £55 SION E FOR DODD FF
}
To lo CS | SLOT 1D FOR: A0DO- THEY
'3 (1 ESTI
А оо ese | SLOT 1D FOR 8000-BFFF
a CU
ds ma ww me n= cro — -— же o aa = еее a AE 4 2 жел сотые се
G 10 CS’. | SLOT ID FOR CONO FFFF
2m 2m DfEE = RL OT =su ru I OSD RE RE EA Ral MS Ll a an am al lm =
E = нее. E A TT
с 0 O KBU LEYSCAN. OUTPUT
i KI3 1
2 KU2
3 KB3
A O | CASON | CASSETTE MOTOR ONCL=0N) |
5 To CASW | CASSETTE WRITE SIGNAL
6 O CAPS | DRIVES [APS INDICATER
7 О SOUND | ONE BIT OUTPUT FOR EXTRA
SOUND _QUTPUT _ _
воет o iE at ome
TOE се AA EEE SE mm ae
Nm me det Mm rel mm a
Fuzz TREE AE == 55 a om AE 1 Gr 2 Em о RE ER SE EEE SEE SE ==
4.4 PSG HIT ASSIGNHENT
PORT BIT 1/0 CONNCECTOR JOYSTICK
AJA RR wy
JA 1 42 FwWD2
| e] BACK]
| JA ay BACK2
o 33-3 al LEFT 1
АВ rw LEFTZ
3 J3 A 1 RIGHT
JA-4 x2 RIGHT2
4 | J3 6 1 — TRGAÍ
| J4-6 x2 TRGAZ
5 | J3-7 xl TRGB1
JA-7 2 TRGB2
6 i KEY MATRIX SELECTOR
7 ! CSAR (CASSETTE READ SIGNAL)
B 0 O J3-6 3
] J3-7 x3
2 JA 6 x73
3 JA 7 x 3
4 J3-8
5 JA4--8
6 PORT-A INPUT SELECT
;
TT TTTTTTOTTTTRETSTSSSSESRERESSUUSERDECDSRHES OZEINETOTNNISImIESESsEHE THR=
*1 VALID ONLY WHILE PORT-B/BIT-6 IS L
x2 VALID ONLY WII: PORT-B/BIT-6 1S И
+3 SET H FF NOT USED AS AN QUTPUT. OPEN CLLECTOR OUTPUT.
*OTHER PINS ON J3,JA
J3-5,J4-5 ‚БУ
J3-9,J4-9 GNb
*4 1s not supplied in the minimum configuration.
5.1 RAM EXPANSION
MSX BASIC requires a continous area PH memory From PIE to
Fhe lower memory arre: Expaias ion KAM should he located just
under the existing RAM to make à conlinuous Fea avallable
to BASIC,
When (he minima memory systen configuration conlains BK NAM
from E000-FFFE memory must stilt be incremented by- 16h as
the SLOT SELLCI SIGNAL works on a 16K unit basis. tn this
case the original Bk of HAM are not used and the сохраним! OI
of results in 4 total of tek memorv not Zak.
There are two kinds of 16k RAM cartridges avatlable. one is
for the 8K RAM minimum system and Lhe other for thuse machine
which comes with 16k RAM.While both cartridges contain 16k of
RAM they must not be confused with one another and care mast
be taken that they are installed properly.
Computers wilh BK RAM to start with use 16K RAM from ВЕНЕ to
COOU.
Computers with 16k RAM to start with use 16k RAM Expansion
Cartridges with RAM from BFFF to 8000.
MSX BASIC OCCUPIES THE RaM from 8000 to РРР and cannot use
RAM from 6000 Lo 7EPE.
5, 2 LON EXPANSION
The four slots which come with Lhe minimum system are called.
the BASIC SLOTS and from each of these BASIC SLOTS other stots
can be added to expand the system. To select an expanded slot,
the BASIC SLOT to which is belong must First be selected.
this is not necessary in systems lu which Chere is a Function
which can inhibit the BASIC SLOT.
Up to four slats can be connected Lo each BASIC SLOT
without using a buffer. five or more slols can be connected
using the buffer For Lhe cartridge bus.
Since the CPD cannot! distinguish whether a cartridge is before
or after the butter,a circuit which accepts a signal from tte
cartridge to distiaguish the derection of the buffer is
installed. The signal from Che cartridge is called BHSDIR.
Nu some cases, however this signal is ol necessary and the
cartridge circuit can be simpliticd using:
In some cases, however this stgonal Es nat neressarv and Che
cartridge circuit can be simplified masia;
HIYA cartridge which accepts hat
never sends data to the CPHIN this “se Cin
birf ter always warkas outwire und Lever award,
(2) A memory eartridaoe.
N
In his case, Che bus derection can be
distinguished from the sigonals availanblecSiot
Select , Memory Request, Read Write)
Thus ROM cartridaes can be made Inexpensivelv.
3. SLOT
WHAT 1S A "SLOT"?
The word "slot” is used here with a special meanima, Mt does
tot refer to the cartridye connector slot familiar to Apple 2
users. Slob here is somewhat similar to a memory lank because
it is a block of 64k of memory.1t is also similar to a "hard-
ware slot” because the CPU names each slot and selects a slot
au the cartridge bus is called the "Slot Select Signal”,
Note that we are discussing Lhe slot fran the point. of view
of software and the number of phvsical cartridge siots wit}
be discussed in anuvther section.
8255 7415153 7405139 __
YOD——————e ELTSLo
PAO CSaL ECO 1 Y A
PA | ESO Taco vid———— Us[:
—pAZi. SU ‘С! >, 8 ‚
РАЗ CSIH aC Y2D)———————— 5 TS?
Pad CS2L 1C? a
pas | 6S2H loco YaD——— 50813
PAS | ica
par aca
ES
ATA A EQ
8255 и
Chip Select А15 B
_ AFSH
iG
2G
CARTRIDGE SLOT EXPANSION OX
>. A EXPANSION STO CERCHEER EXANPR E
BUSOIR : |
-O— TO EACH
~ EXPANSION SLOT
Ze BUSDIR
DATA BUS 9 ———
De-Dr A DA BUSCA
AD
O > O
pis | 0 ps o
LA Lo” Ad y
ADDRESS BUS ESS
AR A IN 70 ADDEN
~ LT O HICODER
e SIRCUIT
a a CIRCU
SLTS SITSL ue
Ss — EXPANSION D> +0 1/0 CARTRIDGE
_— SLOT >
SUSLISIELECT 5 > FACIL. EXPANSION SLOT
CIRCUIT SON SELECT
Dd
WHY ISE SEOs 7
On a system witle on ordinary bank memory setp, every device
бо Lhe same memory Pe receives Lhe same select signals.
This makes It impossible ta put two ar more devices an the
ste OPeral Fon ar even diumaigges it.
Using slots makes il possible Lo put several edvices in the
same address bat in difreroel slots. [CU siso makes 16 possithle
Lo pul programs in ilu same ares.
As a result,the stot makes for a more rlexible environment
and adds mote expandability Lo the system.
«xx EXPANSION CARTRIDGE
SELECT SIGNAL CIRCUIT
„чей
aectss OF EFFF ADRS): MREQ-RD+-SLTSEL
—— =
mr an
ACCESS OF EFTE ADRS). MREQ- WR- SLTSEL
74LS 74LS 74LS
273 193 139
: CLK +
DATA BUS fd 7 2Y —— 8 YD ——
B ' 2 eee
-—d16 с ID —
Co — 26
CLR
RESET ZU An Ax
MREQ
RESTE ACCESS OF TE ADRS)
с.
6.
1. CPI SLOT CTRPCUTT
CPUIIZ-30 clock ls derived from the »ideo disrlay
rroçcessor THS5S91253.
Usins the TP G3(25C1815) In main reset circuit, turnina
the rover switch on made ne3ative rulse, set CPU and
other rrocessor resetted. |
MSX system has four stots br the SLOT SELECTION method.
Each slot consists of E4kD.
+SLOT Ho :MSX BASIC INTERPRETER ROM VERSION 32KB
*SLOT H1 :EXTERMAL CARTRIDGE SLOT
*SLOT H2 SX SYSTEM INTEPHAL D-RAM 641KB
4SLOT HX3 "EXTERHAL EXPALHSIOH SLOT
Amone the evransion and cartridae slot slanals“SQ rins).
CPU address and control sianals are connected thraueh
the HEY BUFFER (74L33567+d4), but not the DATA BUSCDO-D>?.
2.5LOT SELECTIOH CIRCUIT
Slot selection set throuah PORT & of the P.P.I chtr°
INTEL 22550) by the DATA BUS ‘DQ-D7).
The PORT A In the P.P.I LSI ts wired to G-to-2 ENCODER
(7405153) bv the S-bit raraltet Line.
SLOT SELECTION ls derendins on the content of PORT A
register In P.P. 1
As examrle, [* you want to select the SLOT H3NDDRESS:
4000HEX-7EFFHEX), You should write a data <CHEX? to the
PORT A reaister In Р.Р. т,
If vou inrut Chex data to PORT m of P.P.I chir <INTEL
8755), it alloys access of MS% PASIC INTERFRETER In
SLOT HO, internat D-RAM in SLOT #2 and external cartridae
POM in SLOT #3. (for examrle, assembly Lanauase OUT PORTA:
ОСН is Inserted)
6.
6. 4
3. POWER Of) RESET
As You turn on the rower switch PROGRAM COUNTER’ s
content Is set tn OCOCH.
Thts realster's content set to the evstem ROM throuah
the address Line ‘N0-5A15) and PORT N realster In P.P.I
is set OH. |
8-bit raratlel Line of PORT N Ils connected to 8-to-2
EHCODER (7113153) and CSOL bit, CSOH bit Is selected by
2-to-2 EHCODER ‘74151539,
This slanal ls wired to dual 2-to-1 DECODER (7415139).
In DECODER 1Y0(nesatlive) slanal Is active, SLOT HO is
selected,
Therefore the content of 0000H address in MSX system
РОМ is read by the CPU,
VIDEO DISPLAY PROCESSOR: TMS9129HL
+ D.P. SPECIFICATION |
CDP IS DESIGNED TO INTERFACE DIRECTLY WITH THE
THS4416-15C16k+4BIT) D-PAN,
IT IS H-CHAMNEL MOS LSI DEVICE USED IM VIDEO SYSTEMS
WHERE DATA DISPLAY OM A RASTER-SCAMIED HOME COLOR т. U
OR COLOR MONITOR IS DESIRED,
THIS DEVICE GENERATES ALL HECESSARY VIDEO, COMTROL AMD
SYMCHROMIZATION SIGHALS AMD ALSO CONTROLS THE STORAGE
» RETRIEVAL AND REFRESH OF DISPLAY DATA IN THE DYNAMIC
SCREEN REFRESH MEMORY.
TMS3123HL HAS A 625 LINE FORMAT FOR USE WITH THE EUROPEAN
PAL SYSTEM AHD OPERATES ONLY IN A MOMINTERLACED MODE.
, THE VDP HAS FOUR VIDEO DISPLAY MODE
TEXT MODE, GRAPHIC ONE MODE, GRAPHIC TWO MODE, MULTICOLOR
TT q _ em
MODE RESOLUTION PATTERN | PATTERN |COLOB] SPRITE| DISPLAY
SIZE MO.
GRAPHIC 1 | 192+256 s+a 255 16 OK | Z4LINE*
PIXEL. DOT | 32 COL.
GRAPHIC 2 | 1924256 a+8 768 16 ok 124 LINE
PIXEL DOT +32 COL.
HULTICOLOR 48464 4+4 = 15 ок 124 LINE
BLOCK DOT 32 COL.
TEXT 1924256 a6 256 16 NO |24 LINE
PIXEL DOT 40 COL.
—— р
— ADDRESS BUS. >
BLOCK DIAGRAM
OF TMS9I29
Сей CS pr
RAM ROM CPU E w vpp — g
ак 9123 vRAF
|
1 | 16 A}
DATA BUS
VIDEO KGB VIDEO
ENCODER — |MATRIX| |ЕМСОВЕВ
| Om
VIDEO RGB MOD
MONITOR MONITOR |
TV
LEP interreurt
The LP imterrurt quteut rin Is used to generate an
Interrurt at the end of each active-~displar scan,
which is about ever» 1750 second far the TMS9129,
The interruct outrut Is active «when the Interrurt
Enable bI4<IEN in the UDP resister | Is a "1" and
the F bit of the status resistey ts a "1".
Intérrurts are cleaved when the status realster ls
read.
#0PU-—UDP INTERFACE
The LDP communicates with the CPU via an 9-bit
bidirectional data bus.
Three control tines, decoded from the CPJ address and
enable Lines. determines interpretation of the bus,
Throuah the bus, CPU can write to U-RaM, read from
BEAM write ta UDP realsters, and read the UDP status
reaister, The UDP also senerates Interrupt sisnat after
ever» refresh of the TW display If the interrurt Is
enabled,
#UDP-URAM INTERFACE
The UDP can use either TMS1116-15{(16k*1) or TMS4416—-15-/20
(15kK*4) dynamic PRAMs. ADAC) ls used for the eiahth RAM
address bit in the TMS4416-15720 Ras, but nat for the
ТУР 165. |
Since the early write crcle Is used br the МОР, @ an the
THZ4416 must be tied to ground,
The UDP accesses ur to 16, 334kb»yte of US usina a 14-bit
Eis address. The UDP fetches data from the LIRAM In order
to rrocess the wideo imase.
The UDP alsa stores data In or read out data from the URANM
durine a CPU-URAM data transfer. The UDP automatically
refreshes ihe LRM,
THE IDP-LIRAM INTERFACE COHSISTS OF À BIDIFECTIONAL S-BIT
DATA BUS AHD THREE CONTROL LINES (RAS. CHS, RW).
THE UDP READS FROM AD WRITES DATA TO THE VŸ-RAH ON THE
LIPAM DATA BUS. THE VDP OUTPUTS THE NDDRESS TO THE URAM OF
THE URaM ADDRESS BUS,
THE URAM LOW NDDORESS IS OUTPUT WHEN PAS IS ACTIVE (LOW)
THE COLUMII ADDRESS IS OUTPUT WHEN CAS IS NCTIVE (LOW).
DATA IS OUTPUT TO THE WRaM WHEN R7W IS NCTIVE LOW).
4CPU CLOCK, GEHERNT ITOH
7 33 pr
x il
VDP Pe
VC Ch+ALPRI
?
The UDP senerates CPU clock 13, Serz?.
A fundamental freauency, rarallel—mode X-TAL Is used as
the freauenc” reference for the internal clock osciltatotr,
which Is the master time base for all system orerations.
This master clock ls divided by two to senerate the pixel
clock (5. 3MHz? and br three to rrovide the CPUCLK (3. SOMHZ2 .
+CPY INTERFACE
The UDP interface to the CPU usina an B~bit bidirectional
data bus, three control Lines, and an Iinterrurt,
1.write data brtes to URAM |
Z. read data bytes from MRAM
3Z write to one of the S-UDP write ant? yresisters
4 read the VDP status register
The tyre and direction of data transfers are control bv
the CSW, CSP, and mode inputs, ‘|
SW ls the CPU to VDP write select.
When it is activeilow, the 8 bits on CDD-CD? are strobed
inta the “DH.
SR is the CPU from UDP read select.
When it ts active (Lou), the VDP outputs B bits on CDO-CD/
to the CPU.CSW and CSR should newer be simultaneously
Low at the same time. If both are Low » the VDP outruts data
еп CDO-CD? and Latches Invalld data,
Made determines the source or destination of a read or LY |
data transfer.Made is normally tled to a CPU Low address,
ADO.
= пены ин = т
+CPU-UDP DATA TRANSFERS
OPERATION
3
CSW CSR MODE
WRITE TO VDP RES.
BYTE
BYTE
1 DATA WRITE
2 REG. SELECT
WRITE TO URBAN
BYTE
BYTE
BYTE
1 ADDR. SETUP
2 ADDR, SETUP
3 DATA WRITE
AS
D3
READ
EYTE
ERCM UDA REG.
1 DATA READ
Ds
READ
BYTE
BYTE
BYTE
FROM VBOM
1 ADDR. SETUP
2 ADDR. SETUP
3 DATA READ
AS
D3
0 1
0 1
o 1 1
o 1 1
a 1 0
1 0 1
o 1 1
go 1 1
1 0 a
tr. ЕКО МАММА ОРНАМЕНТ
Rear
SZ25A PINCUTIONAT BESCRIRIETON
GENERAL
The SZS9Aa ds ar progiramaite peripheral inrertacec Pridevico designed
tor use Dit microcompnt er sistemas. Pta Funcion Es that of a general
purpose 1/0 component to interface peripheral emi puent in
themicrocomputer зум! ем bus. The functional configuration
of the B255A is programmed by the system software so that
normally no external logic is necessary to interface
peripheral devices or structures.
DATA 8US BUFFER
This 3-state bidirectional 8-bit is used го interface
the 3255A to the svstem data bus. Data is transmitted or
received by the bufrer upon execution of input or output
instructions bv the CPU.Control words and status infor-
mation are alsc transferred through the data bus buffer.
Read/Write and Control logic.
The function of this block is to manage all of th internal
and external transfers of both data and control or status
words. It accepts inputs from the CPU Address and cont-
rol busses ‘and in turn, issues commands to both of the
control groups. | | |
(CS)
Chip select.a “low” on this input pin enables the communi -
cation between the 8255A and the CPU,
CRD)
READ. A "low"on this input pin enables the 8255A to send
the data or statusinformation to the CPU on the
data bus, In essence, it allows the CPu to "read from the
82534
(WR)
NRITE.A "low" on this input pin enables the CPU to write
data or control words into the 8255A/
CAO and AJO
Port select a amd portsetect 1. These Input signals, in cone
function with the RD and WR input soni tol the selection of
one of the three parts or the control word registers. hey |
are normally connected to The least significant bits of the
address bus CAO and AL)
H255A DASIC OPERATION
AL AO [RDIWRICS ENPUT OPERATION CREAD
na 0 - maa am жел
UV О ТО БЕ [JO [PORE A DATA BUS
071 To 11 To fort no DATA TS
mA we —— | шлет ежи, RS re A EE ima a ————— бог ‚
170 Te 11 T0 [romt € “DATA ВОЗ
DOT | TONTPRUT OPERATION
Po] | tWRETIS)
о о [1 10 10 IDATA RIS--PORT A
1 lo 10 [DATA BUS--PORT B
чан =
4 0 11 [0 10 TDATA Inis-- Port C
1 1 |1 lo fo IDATA BUS. "CONTROL
© | | 1 IDISABLI FNCTION
xx |x ix [1 [DATA BUS--3 STATE
à 1 {0 [1 {0 [ILLEGAI CONDITON
"x x 11 [1 [0 [DATA BUS--3 STATE
—
—
York.
(RESET)
Reset.A "high on this input clears the control register and all
ports(A,B,C) are set La the input mode.
Group A and Group B controls
The functional configuration of each port is programmed DY
the systems software. inn essence, the CPU "outuputs"
a control word to the 8255A.The control word contains
information such as "mode", "bit set”, "bit reset” etc,
that, initialize Lhe functional configuration of the 8255A.
Fach of Ih control biocks(Group A dnd Group B) accepts
“commands” from the internal data bus and issues the
‘proper commands to its associated ports.
Control Group A-Port A and Port С upper C7-Ca)
Control Group B-Port B and. Port C lower{(C3-C0)
The Control word Register can only be writleen into.No
read operation of the congfol word register is,aliowed.
Ports A Band ©
The AZ55A contains three 8- bit portstA,h, and СО .АТЬ can
ber cobntiqured 1h swide Var bel of Funelional charac
teristics by the suvslom software but each has ILS owns
Special teatures or personality” бо Cfuaerther enhance Che
power and tlexibitity ot the B255A.
Fort _A.One 5- bit data output lateh/buf fer and one 88-bit
data tnput Табе.
Port HB, One 8-bil dara input/eutput latch/buffer and one
S-bit data input buffer,
Port С. One 8-bit data output latch/buffer and one 8-
bit data input buffer (no latch for input).This port cad
be divided into two 4-bit ports under the modé control.
Each A-bit port contains a 4-bit latcech and it can be used
for the control signal outputs and status signal inputs in
conjunction with ports A and B.
8255A OPERATIONAL DESCRIPTION.
MODE SELECTION
There are three basic modes of operation that cab be sele-
cted by tlie system software:
Mode O-Basic Input/Output —
Mode 1-Strobed Input /Output
Mode 2-Bi-Directional bus
when the reset input goes "high" all ports will be set to
the input mode(i.e., all 24 lines will be in the high im-
pedence state).After the reset is removed the 8255A can
remain in the input mode with no additional initialization
required.During the execution of the system program any of
the other modes may be selected using a single output instruc-
tion.This allows a single 8255A to service a variety of
peripheral devices with asimple software maintenance routine.
The modes for Port A and Port B can be separately defined,
while Port C is divided into two portions as required by the
Port A and Port B definitions.All of the output registers,in-
cluding the status flip-flops,will be reset whenever the
mode is changed. Modes may be combined so that their
functional detinitton can be "tailored" to almost any [/0
structure. for instance Group B can be programmed in
Mode O to monitor simple switch closings or display compu-
tational results,Group A could be programmed in mode 1
to monitor a Kevboard or tape reader on un Tnterrupt de | Ven
basis. The mode definilions and passitile mode combinations
may seem confusing ol Hirst hbul ¿fir a cursory review of
the complete device operation i simple, logical 1/0 ap-
prouch will surface.The design OF the HZODA kis taken toto
account things such us elf ricient o javoul and completo
functional flexibility to support almost any peripheral
device with no external logic.Such design represents
the maximum use of the available pins.
tr. 5
ax PSGODrogammabl eo Sound Generator о) х жж
FEATURES
Full software control of sound gener
¡Interfaces to most 6 bit microprocessors,
Three independent lv Programmed Analog Oulput
Two 8-bit General purpose 1/0 Ports
Single +5 volt supply
BASIC FUNCTIONS
Data Address 7--0
These 8 lines comprise the 88-bit bidirectional bus used by the
.
microprocessor to send both data and addresses to the PSG and to
recelve data from the PSG.IN the data mode,DA7-DAO correspond
to Register Array bits B7--BO.In the address mode ,DA3--DAO select
the register number (0--17,) and a DA7--DA4 in conjunction with
address inputs A9 and A8 for the high order address(chip select)
RESET (input) |
For initialization/power-on purposes,applying a logic "0"{(ground)
to the RESET pin will reset all registers to "0" .The reset pin is
provided with an on-chip pull-up resistor.
CLOCK(input) |
This TTL-compatible input supplies the timing reference for the
TONE, NOISE and ENVELOPE GENERATORS.
BDIR,BC2,BC1Cinput):
Bus Direction, Bus control 2,1
BDIR!IBCZ|BC1 | PSG FUNCTION
O | 1 | o | INACTIVE
O | 1 | 1 | READ FROM PSG
1 {| 1 | O IWRITE TO PSG
1 ! 1 | 1 {| LATCH ADDRESS
ANALOG CHANNEL A,B,C' output)
Each of these signals is the output of its corresponding D/A converter,
and complex sound waveshape generated bv the PSG.
ICA7- 1080 Cínput - output; 10B7-10BNCinput “onf puto
input ‘OUT put A7-AU,Br-BO
Lach of these two parallel input-output pop $ provides % hits of parall
data to” tren Lhe PSG-CPU bus from to any external devices
connected to Che LOA or TO pins. Each pia is provided with an on-
chip pull-up resistor,so that when in the “input” mode, all pins will
read normally high. Therefore, Che recommended method for scan-
ning external switches would be to ground Lhe input bit.
44 +FC-200 PINER PART LISTA4:
Fl
FUSE, 2500 28
— —— re ER a SE DE a
С’ СТ NO. DESCRIPTION & SPECIFICATION
IC] IC, REGULATOR STR 9005
Ice ТС, REGULATOR $1-3122
IC3 IC, RESULATOR EL-7912
D1 DIODE, BRIDE RE-401
D2 DIODES, BRID3E DBA 20B
D3 DIODE, RECTIFIER 1H4001
C1~C2 С, СЕ 4700MF 161! CED4
cs C.CE 100MF 16 CEO4
сб CCE 100MF 25 CED4
C3-C4 С, СЕ 1000ME 251 CEDA
с? С, СЕ 470MF 25! CE04
R1 R: CARBON FILM 4.7k—] 1.744
J1-J4 WIRE, COPPER TIN-COATED -
Wi COMM. AY, POWER TO MAIN FC-200
Wz COMP. AY, REMOTE FC-200
жи ey. UE A tnt,
pe Y A A a —
CCT HO.
"CT NO. DESC. %: SPEC — DESC.4 SPEC.
UL CPU, Z-808 ZILOG uz UDP, TMS9129NL PAL UDP
13 P.S.G.AY-3-8910 G.I U4 P.P, I, 182550 INTEL
USA: B ROM: M-ROM BASIC US-17 D-RAM, TMS4416-15 T.I
U14-U21 — D-RAM, HM4864-2DC 64Kx1 U26, 33, 48 QUAD MUX, 74LS157
U34 DECODER, 74LS145 U43 CUAD MUX, 74LS157
44 DECODER, 74LS133 U27 DUAL MPX, 74LS15S3
45 DECODER, 7415138 U23-U31 HEX BUFFER, 741.5367
23, 38,40 D-F/F, 74L974 U43 HEY, BUFFER, 7415367
25, 36, 37 OR, 741532 U4S NOR, 74LS02
U3S, 42 AND, 741.508 U33 MAND, 74L500
32 HEX INVERT. » 74HCU04P U47, 50 HEX IMVERT., 74LS04
U41 CPEM COLL. » 741.809 U28 2-0P AMP, MPC4559C NEC
U22 e-D F/F, 74L8374 | U24 CUAD BUFFER, 74LS125
HICSOO1 —HYBRID IC, HICSO001 CS3 TRIMMER CAP... T203R300E
RELAY RELAY, DS1M~DCSY QL~G3 TR, KTC18153R
D2 DIODE, SWITCHING 1N4148 D1 DIODE, ZENER FIRS. 1-B
CS4 CERAMIC CAP. , 33PF CSS CERAMIC CAP, 470PF SOU
CS? ELECTRO-CAP. , 4. 7MF 160 css | ELECTRO-CAP. .220MF 151
(42,52 CERAMIC CAP. ,0.1MF SOU RS0--55 R ARRAY, 2.2K+10 1744
R21~R24 R ARRAY, LOK+4 1744 R25-R40 R ARRAY, 10K+8 1/74W
RS, 12,15 RESISTOR, L0K-J 1/4W R4, 10 RESISTOR, 4. ?K-J 1/44
F13, 47,48 RESISTOR, 10K-J 1/44 RE, 9 RESISTOR, 220-7 1/4
RL, 2,18 RESISTOR: 2. 2K-J 1/4W R14 RESISTER, 5. 2K-I 1/4W
R3, 13,16 RESISTER, 1K-J 1/4W R20 RESISTOR, 3. ?K-J 1/4W
РБ RESISTOR, 1K~J 1/4W RS RESISTOR, 5. 1K-J 1/4W
R4Z-R44 RESISTOR, 470-J 1/4W REO RESISTOR, 22K-J 1/4W
R11 RESISTOR, 120-7 1/4W Ras RESISTOR, 330-J 1/4W
PCB COMM. CONN, S0P 980-050-039 EXP. CONN. CoN, SOP 6201-050-258
PRT COMM, CONM, 14P 57L-40140-770B P1-P2 COMM, ZP MLX 5045-020
KBD CONH. COMM, 11P MLX 5267-11A KBD COMM. CONM, 12P NLX 5267-120
PWR COMM, COMM, 4P MLX 5289-04A JOY COMM. COMM, 3P SUB-D TYPE
JACK RCA 1P S$-1558 —— SOCKET DIN 8P TCS-4480-01
R45 RESISTOR: 8. 2K~J 1/4W F1~F3 EMI FILTER, DSS310-5SDL2
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