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Download DisplayPort IP Core User Guide
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UG-01131 2015.05.04 Sink Interfaces Interface rx_mgmt Port Type AV-MM rx_mgmt_ IRQ irq Clock Domain Port rx_mgmt_address[8:0] Input rx_mgmt_chipselect Input rx_mgmt_read Input rx_mgmt_write Input rx_mgmt_ writedata[31:0] Input rx_mgmt_readdata[31:0] Outp ut rx_mgmt_waitrequest Outp ut rx_mgmt_irq Output clk clk Direction 5-7 Description Avalon-MM interface for embedded controller Interrupt for embedded controller Table 5-3: Transceiver Management Interface Interface Port Type Clock Domain Port Direction Description xcvr_ Clock mgmt_clk N/A xcvr_mgmt_clk Input Transceiver management clock clk_cal N/A clk_cal Input Calibration clock rx_link_rate[1:0] Output rx_link_rate_ 8bits[7:0] Outp ut rx_reconfig_req Outp ut rx_reconfig_ack Input rx_reconfig_busy Input rx_ reconfig Clock Conduit xcvr_mgmt_ clk Transceiver link rate reconfiguration handshaking Note: Value of rx_link_rate[1:0]: 0=1.62Gbps, 1=2.70Gbps, 2=5.40Gbps; value of rx_link_rate_8bits[7:0]: 0×06=1.62Gbps, 0×0a=2.70Gbps, 0×14=5.40Gbps DisplayPort Sink Send Feedback Altera Corporation
