Download Triple-Speed Ethernet MegaCore Function User Guide

UG-01008
2015.06.15
Programming an FPGA Device
2-3
To compile your design, click Start Compilation on the Processing menu in the Quartus II software. You
can use the generated .qip file to include relevant files into your project.
Related Information
Quartus II Help
More information about compilation in Quartus II software.
Programming an FPGA Device
After successfully compiling your design, program the targeted Altera device with the Quartus II
Programmer and verify the design in hardware. For instructions on programming the FPGA device, refer
to the Device Programming section in volume 3 of the Quartus II Handbook.
Related Information
Device Programming
Generated Files
The type of files generated in your project directory and their names may vary depending on the custom
variation of the MegaCore function you created.
Table 2-1: Generated Files
File Name
<variation_name>.v or
<variation_name>.vhd
Description
A MegaCore function variation file, which defines a VHDL or
Verilog HDL top-level description of the custom MegaCore
function. Instantiate the entity defined by this file inside your
design. Include this file when compiling your design in the
Quartus II software.
<variation_name>.bsf
Quartus II symbol file for the MegaCore function variation.
You can use this file in the Quartus II block diagram editor.
<variation_name>.qip and
Contains Quartus II project information for your MegaCore
function variations.
<variation_name>.sip
<variation_name>.cmp
A VHDL component declaration file for the MegaCore
function variation. Add the contents of this file to any VHDL
architecture that instantiates the MegaCore.
<variation_name>.spd
Simulation Package Descriptor file. Specifies the files required
for simulation.
Testbench Files (in <variation_name>_testbench folder)
README.txt
Read me file for the testbench design.
generate_sim.qpf and
Dummy Quartus II project and project setting file. Use this to
start the Quartus II in the correct directory to launch the
generate_sim_verilog.tcl and generate_sim_vhdl.tcl files.
generate_sim.qsf
generate_sim_verilog.tcl and
generate_sim_vhdl.tcl
Getting Started with Altera IP Cores
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A Tcl script to generate the DUT VHDL or Verilog HDL
simulation model for use in the testbench.
Altera Corporation