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UM10518
NXP Semiconductors
Chapter 10: LPC11Exx USART
Table 182. Fractional Divider setting look-up table
10.5.14.1.1
FR
DivAddVal/
MulVal
FR
DivAddVal/
MulVal
FR
DivAddVal/
MulVal
FR
DivAddVal/
MulVal
1.000
0/1
1.250
1/4
1.500
1/2
1.750
3/4
1.067
1/15
1.267
4/15
1.533
8/15
1.769
10/13
1.071
1/14
1.273
3/11
1.538
7/13
1.778
7/9
1.077
1/13
1.286
2/7
1.545
6/11
1.786
11/14
1.083
1/12
1.300
3/10
1.556
5/9
1.800
4/5
1.091
1/11
1.308
4/13
1.571
4/7
1.818
9/11
1.100
1/10
1.333
1/3
1.583
7/12
1.833
5/6
1.111
1/9
1.357
5/14
1.600
3/5
1.846
11/13
1.125
1/8
1.364
4/11
1.615
8/13
1.857
6/7
1.133
2/15
1.375
3/8
1.625
5/8
1.867
13/15
1.143
1/7
1.385
5/13
1.636
7/11
1.875
7/8
1.154
2/13
1.400
2/5
1.643
9/14
1.889
8/9
1.167
1/6
1.417
5/12
1.667
2/3
1.900
9/10
1.182
2/11
1.429
3/7
1.692
9/13
1.909
10/11
1.200
1/5
1.444
4/9
1.700
7/10
1.917
11/12
1.214
3/14
1.455
5/11
1.714
5/7
1.923
12/13
1.222
2/9
1.462
6/13
1.727
8/11
1.929
13/14
1.231
3/13
1.467
7/15
1.733
11/15
1.933
14/15
Example 1: UART_PCLK = 14.7456 MHz, BR = 9600
According to the provided algorithm DLest = PCLK/(16 x BR) = 14.7456 MHz / (16 x 9600)
= 96. Since this DLest is an integer number, DIVADDVAL = 0, MULVAL = 1, DLM = 0, and
DLL = 96.
10.5.14.1.2
Example 2: UART_PCLK = 12.0 MHz, BR = 115200
According to the provided algorithm DLest = PCLK/(16 x BR) = 12 MHz / (16 x 115200) =
6.51. This DLest is not an integer number and the next step is to estimate the FR
parameter. Using an initial estimate of FRest = 1.5 a new DLest = 4 is calculated and FRest
is recalculated as FRest = 1.628. Since FRest = 1.628 is within the specified range of 1.1
and 1.9, DIVADDVAL and MULVAL values can be obtained from the attached look-up
table.
The closest value for FRest = 1.628 in the look-up Table 182 is FR = 1.625. It is
equivalent to DIVADDVAL = 5 and MULVAL = 8.
Based on these findings, the suggested USART setup would be: DLM = 0, DLL = 4,
DIVADDVAL = 5, and MULVAL = 8. According to Equation 3, the USART’s baud rate is
115384. This rate has a relative error of 0.16% from the originally specified 115200.
10.5.15 USART Oversampling Register
In most applications, the USART samples received data 16 times in each nominal bit time,
and sends bits that are 16 input clocks wide. This register allows software to control the
ratio between the input clock and bit clock. This is required for smart card mode, and
provides an alternative to fractional division for other modes.
UM10518
User manual
All information provided in this document is subject to legal disclaimers.
Rev. 3.4 — 8 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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