Download SSC-210 SERVICE MANUAL

MN1-S001
VERSION
1
SSC-210 VET
SERVICE MANUAL
SHANGHAI ALOKA MEDICAL EQUIPMENT CO.,LTD
CONTENTS
SECTION 1. PRINCIPLE OF OPERATION
1-1 UNIT INDENTIFICATION
page 3
UNIT INDENTIFICATION
1-2 SYSTEM PRINCIPLE
page 5
SYSTEMPRINCIPLE
1-3 PROBE UST-5813-5
page 9
PROBE UST-5813-5
1-4 TX & RX UNIT EP393200
page 11
TX & RX UNIT
1-5 DSC UNIT EP-1894 EP-1895 EP-392800 EP-2241
page 15
DSC UNIT
1-6 MONITOR PC0017
page 27
CIRCUIT DIAGRAM
SECTION 2. MANITENANCE AND TROUBLESHOOTING
2-1 DISASSEMBLING MANUAL
2-2 WAVE FORM DIAGRAM
2-3 TROUBLESHOOTING
page 28
DISASSEMBLING MANUAL
page 34
WAVE FORM DIAGRAM
page 65
TROUBLESHOOTING
SECTION 3. PARTS LIST
page 87
2
PARTS LIST
SECTION 1.
PRINCIPLE OF OPERATION
1-1 UNIT INDENTIFICATION
3
1-1. UNIT IDENTIFICATION
4
SECTION 1.
PRINCIPLE OF OPERATION
1-2 SYSTEM PRINCIPLE
5
1-2 Basic Block Diagram
Basic block diagram and system block diagram are in Fig.1-2-1 and Fig.1-2-2 respectively
General operation of each block is described below.
1) Transmitter & Receiver
This block provides the BURST wave by receiving the control signal transmitted from DSC.
It generates the transmission trigger TRIG 1 to 8, based on this BURST wave RIG 1 to 8 are
send to probe.. Received echo 1 to 8 sent from Probe are amplified under the control of
GAIN and STC, and sent to DSC as ECHO VIDEO signal.
2) Probe
The probe has eight blocks of circuits consisting of the transmitter amp, receiver preamp,
8-channal analogue multiplexer and counter. TRIG1 to 8 sent from Transmitter & Receiver
is amplified by the transmitting amp. So as to generate the pulse for driving the transducer.
The echo signal received by the transducer is amplified by the preamplifier and sent to
Transmitter & Receiver Board. Analogue multiplexers are connected to 64 elements of
transducers and perform the electronic scan by the control signal.
6
3) DSC
Ultrasound echo video signal sent from Transmitter & Receiver is converted to 4-bit digital
data by A/D converter.
Converted video data of 8 pixels are stored and they are written in image Memory at the
same time.
Memory address for writing are generated synchronizing with Ultrasound transmission
timing.
On the other hand, Memory address for reading are generated synchronizing with
TV-scanning signal.
Data of 8 pixels are also read out at the same time and using parallel-sirial conversion, Data
of each pixel can be obtained
Two Line Memory are provided on MEMORY PCB, each Line Memory can store each
video data of one Ultrasound scan line.
Post-process by line-to-line-interpolation is preformed by adding Data read out from Image
Memory and Data read out from Line Memory.
Ultrasound image is smoothed by this processing method.
Digital ultrasonic data are added with graphic data read out Graphic Memory, gray-scale
data and composite sync signal sent from Control PCB, and then sent to D/A converter to be
Converted to analogue TV signal(composite video).
Such a series of operations are controlled by the control signal generated at Control PCB.
CONNECTOR DIAGRAM
7
FRONT
PANEL
GAIN. STC
ECHO VIDEO
TRANSMITTER
&
RECEIVER
DIGITAL
SCAN
CONVERTER
CONTROL SIG.
TECEIVING
ECHO
Tx TRIG.
SWITCH
INFORMATION
COMPO. VIDEO
TV
MONITOR
PROBE
Fig. 1-2-1 SSC-210VET BASIC BLOCK DIAGRAM -1
EP393200
EP-1894
BURST
OST
DELAY
LINE
DELAY
LINE
FOCAL
POINT
SELECT
FOCAL
POINT
SELECT
ADDER
PHASE
CONTROL
LOG
AMP
S.T.C.
VIDEO
AMP
LOW
PASS
FILTER
TX REQ
GEN
X'TAL
OSC
A/D
CONVERTER
VIDEO
OUT
IMAGE
MEMORY
¡À5V
+5V ¡À12V
ADDRESS
TIMING
PHASE
CONTROL
¡À12V
FAR
GAIN
GAIN
TV
ADDRESS
PRE
AMP
TIMING
GENERATOR
ADDRESS
CONTROL
D/A
CONVERTER
EP-1895
MEMORY
CONTROL
¡À5V
¡À12V
NEAR
GAIN
TX AMP
DETECT
MULTIPLEXER
EP392800
¡À5V
¡À30V
+5V
GRAPHIC
MEMORY
ADDR.
BUS
DATA
BUS
MPU
KEY
BOARD
EP-2241
ARRAY
TRANSDUCERS
TV
MONITOR
PC0017
ISOLATION
TRANSFORMER
AC100~
120V
POWER
SUPPLY
EP-1882
REMOTE
FREEZE
UST-5813-5
Fig. 1-2-2 SYSTEM BLOCK DIAGRAM
8
SECTION 1.
PRINCIPLE OF OPERATION
1-3 PROBE UST-5813-5
9
1-3
PROBE UST-5813-5
Probe is composed of Array transducers, where 64 transducers are arranged linearly
and two PC boards. Each PC board consists of four hybrid Ics having the functions of the
transmitter amp, and receiver preamp, four 8-chanel analogue multiplexers and two 4 bit×2
counters.
1) Scan Control
Signals CTRL 1 to 8 from Transmitter & Receiver board are used as clock inputs of
4-bit binary counter.
3 bits out of 4 bit counter output control SCAN ADDRESS as a decode signal of
Analogue Multiplexer.
2)
Transmission
Signals TRIG 1 to 8 from Transmitter & Receiver board are amplified by the
transmitter amp and are supplied as the input of the Analogue Multiplexer. This
multiplexer has 8 channels. One multiplexer makes selection of 8 transducers. One
selected transducer is driven by receiving the signal from the transmitting amp. The
same operation is performed in 8circuits. But when the focal point is near, 6 transducers
are driven.
3) Reception
Echoes reflected in a living body are received by the selected 8 transducers and supplied
to the input of the receiver preamplifier after passing through Mulltiplexer. Amplified
echoes are sent to Transmitter & Receiver board via the probe cable.
10
SECTION 1.
PRINCIPLE OF OPERATION
1-4 TX & RX UNIT EP393200
11
1-4 TX & RX UNIT EP393200
Transmitter and Receiver Board is composed of Transmitter which sends the transmission
trigger to Probe by the control of DSC, and Receiver which sends the received echo to DSC after
the control of GAIN and STC. Block diagram of Transmitter & Receiver Board is shown in Fig.
1-4-1.
1)
Transmission
Pulse which oscillated in BURST oscillator circuit becomes pulse having delay of the
specified by passing through the delay line. This delayed pulse is selected and send to Probe to
drive the transducer, and ultrasonic beams are focus system, by the electronic focus system. In the
electronic focus system, by sending beams from both sides of transducers in one block in order,
ultrasonic beam is focused as if the block were arranged in concave.
In this system two focal points are available in depth direction. Either one can be selected by FR
RATE switch on the front panel. 114 ultrasonic beams can be obtained by shifting the position of
transducers one by one to shift the position of the position of the ultrasonic beam.
2)
Reception
REC SIGNAL send from probe must be composed after phase-alignment because the
distance between the echo source and each transducer is different. The phase is aligned by using
Delay line. At this time, two beams(right and left), which shift to the right and left respectively by
1/2 pitch of the transducer against the beam center, are obtained.
Consider about FAR focus. the delay amount for the echo received by transducer NO.1 at Right
and the delay amount for the echo received by NO.8 at Left must be the same. Delay amount for
the echo received by transducer NO.1 at Left and delay value for the echo received by NO.1 at
Right are the same. Similarly, 2 corresponds to 7, 3 to 6 and 4 to 6. Selection of Right and Left is
controlled by the analogue switch. Signals whose phases have aligned by the above-described
method are added and pass through LOG AMP, Detector circuit to set the maximum amplitude of
the signal to 2v. Then, it is sent to DSC.
3) Generation of the BURST wave
Pulse for driving are oscillated by BURST oscillator circuit. The transmission position of the
driving pulse is determined by TXRQ/signal supplied from DSC and the oscillation frequency
depends on the frequency of Probe.
4) Address Control
When the FRAME RATE switch is set UP,4-bit signal CTRLA to CTRLD, are generated using
TXRQ/ as clock input of the binary counter. CTRLA to CTRLD are used for phase control and
CTRLA to CTRLC are also used as input code of Decoder. Decoder output CTRL1 to CTRL8 are
sent to the binary counter for the address control of Probe. 3-bit output of the binary counter is
used as the switch code of Multiplexer. When the RATE switch is set OFF, the above signal are
generated based on NEAR/ instead of TXRQ1.
5) 8-channel Mutiplexer
12
Since 6 to 8 transducers are used in one block, the distance between the echo source and each
transducer is different. Thus, the phase of echo signal must be aligned. 8-channel Multiplexer is
used for phase alignment.
6)
Log Amp.
Received echoes after phase aligned and added are log-compressed by Log Amp circuit.
Signals amplified or attenuated by +60db, +30db,0db, and –30db by High Frequency amp., Buffer
and Attenuator are log-added by Log Ic to obtain Log output with dynamic range of 120db. Log
output are taken out from two output terminals(phase is different by π(rad)). Each signal is
amplified and sent to Detector circuit with the amplitude uniform.
7)
STC
STC SIG. is generated by STC SIG Generator and sent to Detector. The sound pressure of the
reflected echo from a living body depends on diagnostic depth and other conditions. Therefore, in
order to obtain the best diagnostic image at each time, set the amplitude of the received echo to the
optimum level by adjusting GAIN, NEAT and FAR in the front panel.
8)
Detector
Information of the received echo can be obtained as an envelope of the received signal. The
output signal of Log amp is detected by Detector circuit and sent to Video circuit.
9)
Video Amp
Video Amp circuit amplifies the signal to obtain the output voltage required for input to TV
monitor. Also, by zero Level Hold circuit, the video amp output is always kept to 0v standard.
10) Explanation of each timing signal
USBLK Used as the basic signal for generating STC SIGNAL. Also this is used as the
control signal of zero level hold circuit for the video signal. CTRLA to C Used as 3-bit input code
of 8-channel Multiplexer which is used for phase alignment of the reception/transmission signal.
This is also used as the input code of Decode generating CTRL1 to 8 which is sent to Probe.
CTRLD Used as the signal for selecting Right or Left in Micro-Angel sector method which is
performed in reception. T1 to T4 These are source of “TRIGx”which are sent to Probe, and
obtained by delaying the signal oscillated by BURST oscillator by the specified amount. Delay
amount is T1≤T2≤T3≤T4. TRIG 1 to 8 Signals obtained by such a way where T1~4 signals
pass through Matrix circuit, composed of eight 8-channel multiplexers, and are controlled by
CTRLA~C.
13
CTRL A¡«C
ADDRESS
CONTROL SIG.
GENERATOR
IC14
CTRL1¡«8
DFRST
TO PROBE
FRST
NEAR/
DFC/
from
ADC&DAC
8-CHANNEL
MULTIPLEXER
IC15
BUFFER
8-CHANNEL
MULTIPLEXER
IC16
BUFFER
8-CHANNEL
MULTIPLEXER
IC17
BUFFER
8-CHANNEL
MULTIPLEXER
IC18
BUFFER
8-CHANNEL
MULTIPLEXER
IC19
BUFFER
8-CHANNEL
MULTIPLEXER
IC20
BUFFER
8-CHANNEL
MULTIPLEXER
IC21
BUFFER
8-CHANNEL
MULTIPLEXER
IC22
BUFFER
TRIG1
TR8,16
TRIG2
TR7,15
PHASE
CONTROL SIG.
GENERATOR
IC1,2,13
CTRL A¡«C
TRIG3
TR6,14
CTRL A¡«D
US BLK
BURST
TXRQ/
from
ADC&DAC
TRANSMITTER&RECEIVER(2/2)
IC3¡«6,48
FOCUS POINT
AMPLIFIER
OSCILATOR
DELAY LINE
BUFFER
SELECTOR
HIC1
TRIG4
TR5,13
HIC1
IC7¡«12
NEAR/
from
ADC&DAC
TRIG5
TR4,12
TRIG6
TR3,11
TRIG7
TR2,10
TRIG8
TR1,9
Fig. 1-4-1 TRANSMITTER & RECEIVER BLOCK DIAGRAM
NEAR/
CTRL D
TRANSMITTER&RECEIVER(1/2)
NEAR/
from
PROBE
CTRL A¡«C
TRANSMITTER
&
RECEIVER(1/2)
REC1
8-CHANNEL
MULTIPLEXER
IC23
REC2
8-CHANNEL
MULTIPLEXER
IC24
ELEMENT
ADDER
SELECT
HIC12
SELECT
IC31¡«33
TR17,18
FOCUS POINT
IC34¡«41
DELAY LINE
DL2
BUFFER
TR19,20
HIGH FREQ.
HIGH FREQ.
AMP. (+30dB)
AMP. (+30dB)
HIC3
HIC4
REC3
8-CHANNEL
MULTIPLEXER
IC25
REC4
8-CHANNEL
MULTIPLEXER
IC26
+60dB
+30dB
0dB
REC5
8-CHANNEL
MULTIPLEXER
IC27
LOGARITHMIC
AMPLIFIER
IC42
DETECTOR
HIC5
ANALOG
SWITH
IC43
GAIN SIG
from
FRONT PANEL
8-CHANNEL
MULTIPLEXER
IC28
8-CHANNEL
MULTIPLEXER
IC29
EHO VIDEO
to
ADC&DAC
ANALOG
IC45
FAR SIG
ZERO LEVEL
STC SIG.
HOLD
GENERATOR
IC43,44
HIC7
NEAR SIG
ANALOG
SWITCH
REC7
HIC6
-30dB
SWITCH
REC6
VIDEO
AMPLIFIER
TRANSMITTER US BLK
&
RECEIVER(1/2)
IC47
REC8
8-CHANNEL
MULTIPLEXER
IC30
Fig. 1-4-1 TRANSMITTER & RECEIVER BLOCK DIAGRAM (2/2)
14
SECTION 1.
1-5
D.S.C.
PRINCIPLE OF OPERATION
UNIT
15
1-5.
DSC
1-3-1. GENERAL
1) This DSC unit is exclusive for linear-scan method designed for handy-type
electronic linear scan diagnostic equipment.
2) This DSC unit is composed of three PC boards and one switchboard Power
Consumption is approx. 10w.
3) Image Memory has memory capacity of 480*256*4 bits, and Graphic Memory
For caliper and ID indication has a capacity of 256*256*1 bits. Information of
two memories are displayed on TV screen as a composed image.
4) DSC unit controls the transmission timing of the ultrasonic wave and
Transmission position. Transmission stops in the picture freezing condition.
5) For the change of number of scanning lines, that is change between
525 lines/60Hz and 625 lines/60Hz,a crystal and 2 ROM Ics must be replaced.(A Crystal is
soldered. Rom is equipped on an IC socket.)
1-5-2
Composition
1) DSC module is composed of three PC boards for circuits (280*140mm) and PC board for
switches (131*44mm), and the following voltage and capacitance are required as a desired power
source.
DSC block diagram is shown in Fig.1-5-1
PC unit
EP-1894 ADC, DAC (280*150*10mm) 1 piece
EP-1895 Memory (280*150*10mm) 1 piece
EP-392800 Control (280*150*10mm) 1 piece
EP-2241 Key Board (131*44*15mm) 1 piece
Required power source
DC + 5V ±５％　Ａｐｐｒｏｘ．　１．５Ａ
DC –5V ±５％　Ａｐｐｒｏｘ．　７０ｍＡ
DC+12V ±２０％　Ａｐｐｒｏｘ．　５０ｍＡ　16
EP-1894 ADC. DAC
J202
BUF.
I
EXT OUT
7F
EP-1895
J204
US IN
I
6A
4A,4B,4C,4D
5A,5B,5C,5D
1A,1B,1C,1D
A/D
CONVERTER
LPF
4
S/P
CONVERTER
32
MEMORY
4
P/S
CONVERTER
1V
5E
SELECTOR
4
A2
F0/
Refference
6E
J203
4E
3A,3B,3C,3D
32
IMAGE
MEMORY
4
Y2
4
4
4
A1G1
SFT
¦
²
D-FF
4
O-FF
4
7B
ADDRESS
MULTIPLEXER
RA00
~
RA07
READ
ADDRESS
GEN
MONITOR
RAST
RACK
GDT
CBLK/
4
CSYC/
I/O
LWE1/
LCE1/
WA00
~
WA13
6G
HA00~HA09
WRITE
7C
ADDRESS 7D
GEN
9B
LINE
MEMORY
4
I/O
LWE0/
CCE0/
FS/
8A
I
6F
F0/
LINE
MEMORY
7A,7B,7C,7D
X'TAL
CLOCK
GEN
BUF.
7A
LWE1/
LWE0/
HA00~HA09
HA03~HA8
I/V
2G
SMPL/
RATE
MULTIPLIER
D/A
Y1
G2
A0~A7
1A,2E
7
Fs
6F
X1,1F
ADDRESS
GEN
HA00~HA09
VA00~VA13
TIMING
GEN
F0
5E,5F,6F,7B
IRQ
6A,8F
5B,5C,6B,6C,6D
MPU
(6802)
NOTE:
ADDRESS
MULTIPLEXER
shows VIDEO flow
GRAPHIC
MEMORY
2A
MPU BUS
shows CONTROL signal
PROGRAM
ROM
P/S
CONVERTER
8A,8B,8D,8E
I/O
INTERFACE
EP-2241
KEY BOARD
4D
KD0~KD3
KEY SWITCH
MATRIX
KS0~KS3
4A
3F
S1~S21
EP392800 CONTROL
Fig. 1-5-1 DSC BLOCK DIAGRAM
17
S
REMOTE
FREEZE
SIGNAL
A0-A7
FULL NAME OF SIGNAL
Address
EXPRANATION OF ACTION
SOURCE AND ROUTE
OF SIGNAL
OF SIGNAL
Multiplexed image memory
MEMORY
EXPRANATION OF ACTION
SOURCE AND ROUTE
OF SIGNAL
OF SIGNAL
Graphic memory address
Select graphic memory address
CONTROL
Graphic data
Parallel graphic data
CONTROL
GDT
Graphic data
Serial graphic data
CONTROL→MEMORY
CONTROL
GMA
Graphic memory address select
TV address select signal
CONTROL
SIGNAL
FULL NAME OF SIGNAL
GA00-GA12
GD0-GD7
MEMORY
address
AD0-AD3
A/D Data
A/D Converter output
AR00-AR13
Address
CAS
Column address strobe
D. Ram CAS signal
CONTROL→MEMORY
GRAM
Graphic memory select
Graphic memory select by MPU
CONTROL
CBLK
Composite blank
TV Blanking signal
CONTROL→MEMORY
GREN
Graphic enable
Graphic display enable
CONTROL
CHGO-CHG5
Change
Focus exchange data
ADC.DAC→ＭＥＭＯＲＹ　GSFT
Graphic sift clock
P/S Converter sift clock
CONTROL
COL
Column address
D.Ram column address
ＭＥＭＯＲＹ　GWT
Graphic write timing
Graphic write timing for MPU
CONTROL
select
GY0-GY3
Gray scale data
Gray scale data,16levels
MEMORY
GYEN
Gray scale enable
Gray scale display enable
CONTROL→MEMORY
MPU
Address
CSYC
Composite sync
TV Synchronous signal
ＣＯＮＴＲＯＬ→ＡＤＣ．ＤＡＣ
D0-D7
Data
MPU Data
CONTROL
HA00-HA09
Horizontal address
TV Horizontal direction address
CONTROL→MEMORY
Horizontal reset
TV Horizontal address reset
CONTROL
Horizontal line type select
CONTROL
DA1-DA7
D/A Data
D/A Converter input
AD.DAC
HRST
DFC
Focus
Focus control
ADC.DAC→Ｔｘ＆Ｒｘ　HSL0-HLS3
Horizontal select
DFON
Focus on
Focus control
CONTROL→MEMORY
IMEN
Image enable
US Image display enable
CONTROL→MEMORY
DYNF
Focus
Focus control
MEMORY→ＡＤＣ．ＤＡＣ
INH
Inhibit
Graphic memory access inhibit
CONTROL
E
Enable
MPU Enable signal
CONTROL
ET
Enable T
Rate multiplier output
ADC.DAC→ＭＥＭＯＲＹ　IO
Input,Output
I/O interface select signal
CONTROL
EXT.OUT
External output
TV signal output 2Vp -p
KD0-KD3
Key switch drive
Key board matrix drive
CONTROL→ＫＥＹ　ＢＯＡＲＤ
at open Zo=75 ohm
ＡＤＣ．ＤＡＣ
KS0-KS7
Key switch sense
Key board matrix sense
CONTROL←ＫＥＹ　ＢＯＡＲＤ
Fo=Fs,525Lines=10.08MHz
ADC.DAC→ＣＯＮＴＲＯＬ　LCE0-LCE1
Line memory chip enable
Line memory chip enable
MEMORY
625Lines=10.08MHz
→ＭＥＭＯＲＹ　LCNT
Level control
Video level control
MEMORY
Fo,Fs
System clock
by MPU
FRST
Frame reset
US Frame synchronous signal
ＡＤＣ．ＤＡＣ→Ｔｘ＆Ｒｘ　LD0-LD7
Line data
Line memory data
MEMORY
FSTT
Frame reset
US Frame synchronous signal
ＭＥＭＯＲＹ→ＡＤＣ．ＤＡＣ　LMEN
Line memory enable
Line memory access enable
CONTROL→MEMORY
FSYC
Frame reset
US Frame synchronous signal
ＭＥＭＯＲＹ→ＣＯＮＴＲＯＬ　LMP
Lamp
Freeze lamp drive
CONTROL→KEY BOARD
Full pixel
Select 480 pixels or 416 pixels
ＣＯＮＴＲＯＬ　LOWC
Low contrast
Contrast level control
NOT USED
Freeze request
Freeze control
ＣＯＮＴＲＯＬ→ＭＥＭＯＲＹ
LTV
Latch video data
S/P Converted data latch clock
MEMORY
LWE0-LWE1
Line memory write enable
Line memory write enable
MEMORY
FULL
FZRQ
NOTE: In the circuit diagram,”/”indicates “Low”active of signal polarity.
18
D.S.C
SIGNAL
EXPRANATION
D.S.C
EXPRANATION OF ACTION
SOURCE AND ROUTE
OF SIGNAL
OF SIGNAL
Magnify
US Image display size select
CONTROL→ADC.DAC
Memory data
Image memory data,
MEMORY
SIGNAL
FULL NAME OF SIGNAL
MAG
MD00-MD31
Monitor out
TV Signal for internal
TRST
FULL NAME OF SIGNAL
Timing reset
TSYC
Tx synchronous
SOURCE AND ROUTE
OF SIGNAL
OF SIGNAL
Memory basic timing
CONTROL→ＭＥＭＯＲＹ
Tx Timing signal
CONTROL→ＭＥＭＯＲＹ
→ＡＤＣ．ＤＡＣ　Tx REQ
Tx Request
MPCK
MPU Clock
MPU Clock,Fo/16
CONTROL
TXRT0-TXRT1
Tx Rate
MSEL0-MSEL3
Memory select
Graphic memory chip select
CONTROL
USIN
US Image input
NEAR
Near focus operation
Near focus state
ADC.DAC→Ｔｘ＆Ｒｘ　Near focus state
ＭＥＭＯＲＹ→ＡＤＣ．ＤＡＣ
Near focus state
EXPRANATION OF ACTION
ADC.DAC
TV monitor
NERF
EXPRANATION
reset signal
8 pixel in parallel
MON1.OUT
SIGNAL
SIGNAL
Tx Timing signal
ＡＤＣ．ＤＡＣ→Ｔｘ＆Ｒｘ　Tx Rate select
NOT USED
Analog video signal input
Ｔｘ＆Ｒｘ→ＡＤＣ．ＤＡＣ　from Rx
VA00-VA09
Vertical address
TV Vertical direction address
MEMORY
00-07
Output
Output data from sampling ROM
ADC.DAC
VD0-VD3
Video data
Serial video data
ＡＤＣ．ＤＡＣ→ＭＥＭＯＲＹ　PED
Pedestal
TV Pedestal
CONTROL→MEMORY
VMA
Valid memory address
MPU VMA signal
ＣＯＮＴＲＯＬ　R/W
Read/Write
MPU R/W Signal
CONTROL
VRST
Vertical reset
TV Vertical counter reset signal
ＣＯＮＴＲＯＬ
RA00-RA07
Read address
Image memory read address
MEMORY
WA00-WA13
Write address
Image memory write address
MEMORY
RACK
Read address clock
Read address counter clock
CONTROL→MEMORY
WE
Write enable
D.RAM we Signal
CONTROL→ＭＥＭＯＲＹ
RACKE
Read address clock enable
Read address counter clock enable
CONTROL
WEN
Write enable
Image memory Read/Write
MEMORY
RAME
RAM enable
Graphic memory enable
CONTROL
RAS
Row address strobe
D.RAM RAS Signal
CONTROL→MEMORY
RAST
Read address set
Read address counter reset signal
CONTROL→MEMORY
RASTE
Read address set enable
Read address counter reset enable
CONTROL
RCHG
Read exchange
Read focus exchange data
CONTROL→MEMORY
select
READ
Grahpic memory read signal
CONTROL
P/S Converter output signal
MEMORY
SD0-SD3
Serial data
SF0-SF1
Spare function
Spare signal
KEY BOARD
SFT
Shift
S/P converter clock
MEMORY
SMPL
Sample
A/D Converter clock
ADC.DAC
SYC
Synchronous
MPU clock synchronous signal
CONTROL
19
Write state
Image memory write address
MEMORY
select
WSTO
ADC.DAC
READ
WRT
Write strobe
DSC Control register write
strobe
625
625 Lines
625 Lines/50Hz TV System
CONTROL
1-5-3
1)
Operation
EP-1894
a)
A/D
ADC,DAC
conversion
Video signal from Transmitter/Receiver is input to the “US IN”terminal and fed into
the analog input terminal of A/D converter IC6A after passing through the low-pass
filter (fc=2.5MHz).Since the loss of the low-pass filter is approx.6dB,though the
signal level at the input side is 0 to 2V,that at the output side is 0 to 1V.
Since the REF voltage of A/D converter is set to 1V and four bits are the conversation
bits, the output of “0000”is obtained when the signal of 0V is input to “US IN”, and
the output of “1111”is obtained in case of +2V input.
The clock of A/D converter is fixed to 1/2FS.A/D converted video data are latched in
IC2F once and then sent to S/P converter in Memory Unit.
b)
D/A conversion
Digital video signal read out from Image Memory is fed to the input terminal of D/A
converter IC7A to be converted to the analog signal.
Since the output of D/A converter is current –output ,the current-to-voltage
conversion is performed by Ope amp IC7B to obtain 2vp-p composite video signal.
This output passes through Buffer IC7F, and becomes the external output “EXT
OUT”. On the other hand, this output is divided by 2 and sent to CRT through the
analog switch IC7D and Buffer IC6F.
c)
Rate Multiplier
8-bit rate multiplier is used to decide the sampling rate corresponding to each probe
and diagnostic distance. The constant corresponding to each diagnostic distance is
read out from ROM 2E, and added by the system clock “FS”. When the added result
is over 255, its carry signal is generated to be sampling clock of data. Though A/D
conversion is performed at a constant interval (1/2 FS),writing in Image Memory is
performed at the timing of carry signal. Also, changing point information at the
dynamic focus and transmission time interval corresponding to each diagnostic
depth are sent out from ROM 2E,and supplied to each control circuit
20
US IMAGE SIGNAL
US IN
LOW PASS
NO
FILTER
CONVERTER
FC=2.5MHz
( 4 bit )
REFERRNCE
1V
DIGITAL VIDEO DATA
VD 3~1
1/2 Fs
RATE
SYSTEM CLOCK
1S
TX CONTROL DATA & SAMPLING TIMING
TXRT 1,0 , CNG 5~0
ET
MULTIPLIER
1A, 2E
GAIN CONTROL
CONT
DIGITAL TV SIGNAL
DA 7~1
D/A
I/V
CONVERTER
CONVERTER
( 8 bit )
7A
ATTENAT&R
7B
BUFFER
( 6dB )
6F
REFERENCE
¡Ö1mA
BUFFER
7F
Fig. 1-5-2 ADC DAC BLOCK DIAGRAM
21
EXT TV SIGNAL OUT
EXT OUT (ANALOG)
Z0=75¦¸ 2VP*P
TV MONITOR OUT
MONI. OUT (ANALOG)
Z0=LOW 1VP*P
2)
EP-1895 Memory
a) Image Memory
Image Memory is composed of S/P converters, Memory and P/S Converters. S/P
converters and P/S Converters are not required fundamentally. But since the operation
speed of Memory is slower than the input/output speed of data, these circuits work as
interface to write and read out 8-pixel data collectively.
A/D converted data are taken in Shift Register IC1A to 1D in S/P converters by the
clock “SFT”synchronizing with the sampling clock.
When 8-pixel data are taken into Shift Register, they are latched in IC2A to 2D for
written into Memory. 8-pixel data latched at the time except the time for reading for
the TV indication are written in Memory.
Reading out for the TV display, 8 pixel that are same as the number of pixel at writing
in are read out and loaded in Shift Register IC3A to 3D in P/S Converters. Loaded
data are shifted out one pixel by one pixel by the system clock “F0”and pass through
Buffer IC. Then in Correlation circuit, IC4E,5E,6F and 6G, the average of the addition
with the data of previous line is obtained, and is added with the TV timing signal,
gray-scale data and graphic data, then sent to D/A converter.
b) Image Memory Address
Memory addresses for writing and reading are required independently. Write address
is generated by IC8B, 7C, 7D and 9B. Read address is generated by IC8A. Write
address is counted up by the output of Rate Multiplier “ET”. IC8A performs control at
every 8 pixels, IC7C and 7D generate the address in the depth direction and IC9B
generates the memory address in the lateral direction.
The first-order bit of IC9B is sent to transmitter/receiver as the synchronous signal of
1 frame of ultrasound image. Also, the address in the depth direction is compared with
the information of focus change point sent from Rate Multiplier unit and performs the
changing point control at the dynamic focus.
Since read address is synchronous with the TV signal, only address in the lateral
direction is generated by IC8A and for the address in the depth direction, TV timing
addresses HA08 to HA03 are used in common
Write address and read address are selected by Muliplexer IC6C, 6D, 7A and 7B and
required one is supplied to Memory.
22
c) Gray Scale
Gray Scale Generator is composed of 2 stages of 4-bit counter IC5F and 5G, and
generates 16-level gray scale signal at a rate of 30 pixels/level.
4-bit (16 levels) gray scale data are sent to D/A converter together with the image data.
d) System Clock
The system clock which is the basic clock of the whole DSC “FS, F0”is generated by
a Crystal and logical gate IC 1F.
TV TIMING
CBLK. CSYC. PED
1A.1B.1C.1D
DIGITAL VIDEO DATA
VD 3~0
3A.3B.3C.3D
S/P
CONVERTER
MD31~00
IMAGE
MEMORY
RAS
CAS
WE
MD31~00
IMEN
F0
A7~0
SFT.LTV
BASIC MEMORY TIMING
RAS, CAS, WE, IMEN, CMEN
MEMORY
CONTROL
6E.6G.6F.4E
P/S
CONVERTER
CORRELATOR
MA09~00
WRT
COL
ADDRESS Text 7A.7B
Text 6C.6D
MUX
GYEN.GDT
GRAY SCALE
GENERATOR
F0
5F
WA13~00
KA07~00
HA08~03
LTV
WRITE
ADDRESS
D/A DATA
DA7~1
CMEN
FS
4G
WRITE TIMING
TSYNC, RCHG, ET
CHG3~0
+
TX
CONTROL
WA13~00
7C.7D.9B.3F
TX TIMING
FRST.TXR0.DTC.NEAR
3E
CLOCK
FS
READ TIMING
RAST, RACK
READ
ADDRESS
X'TAL CLOCK
GENERATOR
RA06~00
8A
SYSTEM CLOCK
Fs.F0
X1,1F
TV ADDRESS
NA09~00, RA07
GRAY SCALE CONTROL
GYEN, GDT
Fig. 1-5-3 MEMORY BLOCK DIAGRAM
3)
EP-392800 CONTROL
a)
Memory Timing
Basic timing required for the operation of the image memory is obtained by IC5E,
7E and 6E. The system clock F5 is divided by 16 by IC5E to obtain the address of
Timing ROM 7E.
Data for timing signals required for the operation of Image Memory, RAS, CAS, WE,
etc. are programmed in ROM. Data read out with a period of F0 are latched by IC6E
and sent to Memory Control and other units.
23
b) TV timing
Blanking signal and synchronous signal which compose TV signal are generated by
IC6F, 5F, 7B, 7C, 8F, 7F, 6A and 7A. Also the timing signal for reading out data from
Image Memory is generated. System clock F0 is divided by 640 by IC5E, 6F and 5F
to generate the address in the horizontal direction of TV scan and this generated
address is supplied to Timing ROM 8F.
Horizontal blank, horizontal synchronous signal and memory timings required for
TV signal are programmed in ROM. Data read out with a period of F0×1/8 are
latched by IC7F and supplied to each circuit.
IC7B and 7C divide 1H of TV by 525 or 625 to generate the TV address in the
vertical direction, and generated address is supplied to ROM 6A. Vertical blank,
vertical synchronous signal and control signal for memory read address are
programmed in ROM. Data read out at every 1H are latched by IC7A and supplied to
each circuit.　Address in the horizontal direction and vertical direction are also used as the address
of Graphic Memory.
c) Graphic Memory
Graphic Memory is an overlay memory to display caliper mark and ID information
on TV screen. Since Graphic Memory is accessed by both TV read and MPU,
Address Multiplexer IC6D, 6C, 6B and 5C selects the address.
In case of TV read, TV H and V addresses are select. Graphic data read out from
Graphic Memory IC8E, 8D ,8B and 8A are loaded in IC4D for P/S conversation, and
after shifted out with a clock period of 1/2F0 they are sent to D/A converter.
When MPU accesses Graphic Memory, address multiplexer selects the MPU address
“AR”, and data line “D7 to D0”is connected to the data line of Memory by IC3D to
make reading and writing possible.
d) DSC Control
All of condition controls of DSC are performed by internal MPC, IC2A. The
program for MPU is stored in EP-ROM, IC4A and the capacity is approx . 4k byte.
The control input of DSC (switch information, etc.) is input to MPU via IC3F.
Control information (freeze control, picture selection, focus selection etc.) out of the
processed results are latched in IC3E and supplied to each part.
The information to be displayed graphically (ID code, mark etc.) are displayed on
24
TV screen by writing in Graphic Memory in bit-image.
The transmission time interval corresponding to each probe and diagnostic depth
(transmission repetition cycle) is determined by IC2C, 2B and 1B and the timing
signal “TSYC”is generated.
TX CONTROL DATA
TXRT1.0
CLOCK
To
TV
TIMING
ADDRES
5E 5F
SYSTEM TIMING
RAS,CAS,WE,IMEN,CMEN,GYEN,PED,CBLK,CSYC,RAST,RACK,TSYC,RCNG
GENERATOR
6F 7B
6A,8F
TV ADDRESS
HA09¡«00£¬RA07
5B,5C,6B,6C,6D
VA07¡«00
MA08¡«0A
8A,8B,8D,8E
ADDRESS
MUX
AR
12¡«00
GRAPHIC
GA10¡«00
D7¡«0
MPU
GRAM
1/2R0
SYSTEM
MPU BUS
D0¡«7
AR12¡«00
D7¡«0
(8 Kbyte)
4A
Fig. 1-5-4
WST0
I/O
(CE)
SYSTEM CONTROL
CONTROL
AR15¡«00
D7¡«0
PROGRAM ROM
GRAPHIC DATA
GDT
CONVERTER
(6802)
2A
4)
P/S
MEMORY
IRQ
CLOCK
MPCK
4D
INTERFACE
FZRQ,FULL,MAG,UFON
3E
I/O SIGNAL
KD8¡«0£¬KS7¡«0,CMP
3F
CONTROL BLOCK DIAGRAM
EP-2241 KEY BOARD
This is the switch circuit where key switch for controlling DSC is placed at the
intersecting point of “KD”and “KS”lines.
S21 (freeze switch) with LED is used for the indication of ON-OFF condition of
freeze. At freezing, this LED lights up. Since the switch employs rubber-contract,
the contact resistance is higher by several hundreds ohms.
4 switch input terminals from the external equipment (for DIST, FR RATE etc.),
“4~1”and a common terminal to the switch “C”are provided.
Since all of switch information are taken in MPU, performance of operation
depending on the switch condition is controlled by the program of MPU.
“ S21 (Freeze Switch) and K1 (Relay for remote freeze control) are assemble in
parallel.
25
EXT. SW INPUT
R, F/R, DIST, L, SW COM
SW SCAN
KD 3/~0/
FOOT SW
LED DRIVE 15V
KEY SW
RW DATA
KS 7/~0/
MATRIX
S1~S22
FREEZE
INDICATOR
LMP/
S23, K1
Fig. 1-5-5 KEY BOARD BLOCK DIAGRAM
26
SECTION 1.
1-6
PRINCIPLE OF OPERATION
MONITOR
from
TIME BASE
COMP
VIDEO
IP-0503-TV
VIDEO
INPUT
TR1,2,18
CONTRAST
VIDEO
AMPLIFIER
TR3,4,17
...CRT
V1
G1 G2
G4
BRIGHT
SYNC
SEPARATOR
TR5,6
BACKPORCH
CLAMP
TR7~9
HV
FOCUS
HV
DETECT
CD10,11,19
AFC &
H OSC
TR10~12
H OUTPUT
TR13
H DEFRECTION
YOKE
L5
V OSC
TR15,16,IC2
V OUTPUT
IC2
V DEFRECTION
YOKE
L5
Fig. 1-5-6 TV MONITOR BLOCK DIAGRAM
27
FLY BACK
TRANSFORMER
T2
SECTION 2.
MAINTENANCE AND TROUBLESHOOTING
2-1. DISASSEMBING MANUAL
28
1．tilt machine to one side, dismantle three fixed screws of the bottom.
dismantle the screws
bottom
2．open machine’s upper cover.
Open machine’s
upper cover.
29
3．utile the connector
4．dismantle two screws and then open the plate which to fix pc board.
dismantle
screws
30
the
5. remove the plate.
6．dismantle the screws, then remove EP-393200,EP-1894,EP-1895,EP-392800pc board.
EP-39320
EP-1895
EP-392800
EP-1894
31
7．disconnect P108,P109,P104,P206,P204,P102, then EP-393200 can be removed；disconnect
P201,P202,P203,P205, then EP-1894can be removed；disconnect P301,P302 then EP-1895 can be
removed;
disconnect P402 then EP-392800 can be removed.
J402
J206
J105
J104
J303
J205
J302
J204
J109
J203
J401
J108
J505
J202
J301
J201
J102
32
8．remove the probe connector.
remove the probe
connector.
9．remove the EP-393200 (disconnect P108,P109,P104,P206,P204,P102 first).
J102
remove the
EP-393200.
P104
P108
P109
33
SECTION 2.
MAINTENANCE AND TROUBLESHOOTING
2-2. WAVE FORM DIAGRAM
34
TRANSMITTER & RECEIVER EP-393200
CONDITION)
CONDITION)
RATE:OFF
RATE:OFF
FRST/
J105 ⑦
TXRQ/
J105 ⑤
DIST:OFF
DIST:OFF
35
NEAR/
J105 ③
DFC/
J105 ①
CONDITION)
RATE:OFF
USBLK
TP1
USBLK
TP1
DIST:OFF
IC 3-4
CONDITION)
RATE:OFF
DIST:OFF
36
IC 3-13
IC 6-1
CONDITION)
RATE:OFF
DIST:OFF
IC 6-6
IC 6-8
CONDITION)
RATE:OFF
DIST:OFF
37
IC 5-11
CONDITION)
RATE:OFF
DIST:OFF
USBLK
TP2
38
TP1
TP3~TP10
39
TP15
CONDITION)
GAIN:MAX
NEAR:MAX
FAR:MAX
STC
CONDITION)
GAIN:MAX
NEAR:MIN
40
FAR:MIN
TP14
RATE:UP
STC
CONDITION)
GAIN:MIN
NEAR:MIN
FAR:MIN
TP14
RATE:UP
REC1~REC6
41
J109
TP12
TP13
ADC & DAC EP-1894
US
42
IN
J204-①
MONI.OUT
CONDITION)
RATE:OFF
DIST:OFF
43
J203-①
FSTT/
IC1F-９
TSYC/
IC1F-５
CONDITION)
CONDITION)
RATE:OFF
RATE:OFF
NERF/
IC1F-１２
DYNF/
IC1F-２
TXRT/
IC1E-２
TXRT/
IC1E-１９
DIST:OFF
DIST:OFF
44
CONDITION)
CONDITION)
RATE:OFF
RATE:OFF
CHG 5
IC1E-１６
CHG 4
IC1E-５
DIST:OFF
DIST:OFF
45
CHG 3
IC1E-９
CHG 2
IC1E12
CONDITION)
CONDITION)
RATE:OFF
RATE:OFF
CHG 1
IC1E-６
CHG 0
IC1E15
DIST:OFF
DIST:LONG
46
TXRT/1
IC1E-2
TXRT/0
IC1E-19
CONDITION)
CONDITION)
RATE:OFF
RATE:OFF
CHG 5
IC1E-１６
CHG 4
IC1E-５
CHG 3
IC1E-９
CHG 2
IC1E12
DIST:LONG
DIST:LONG
47
CONDITION)
RATE:OFF
CHG 1
IC1E-６
CHG 0
IC1E15
DIST:LONG
FS/
IC1B-１１
IC1A-４
CONDITION)
RATE:OFF
DIST:OFF
48
CONDITION)
RATE:OFF
ET/
IC1A-２
RCHG/
IC1A-１３
DIST:OFF
RCHG/
IC1A-１５
IC1A-６
CONDITION)
RATE:OFF
DIST:OFF
49
FS/
IC1B-１１
IC1A-４
CONDITION)
CONDITION)
RATE:OFF
RATE:OFF
DIST:OFF
DIST:OFF
50
ET/
IC1A-２
RCHG/
IC1A-１３
RCHG/
IC1A-１５
IC1A-６
CONDITION)
MEMORY
RATE:OFF
DIST:OFF
EP-1895
CONDITION)
DIST:OFF
51
LTV/
IC2D-１１
WEN/
IC2D-１
CONDITION)
CONDITION)
LWE0/
IC6F-１０
LCE0/
IC6F-８
WEN/
IC7G-６
COL/
IC7F-６
DIST:OFF
DIST:OFF
52
CONDITION)
CONTROL
RAS
IC7G-１
CAS
IC7F-１０
DIST:OFF
EP-392800
53
HRST/
IC7F-１２
LMEN
IC7F-１５
54
CBLK/
IC7F-１６
CSYC/
IC7F-１９
GYEN
IC7F-２
GREN
IC7F-５
55
IMEN
IC7F-６
PED
IC7F-９
HRST/
IC7F-１２
LMEN
IC7F-１５
56
CBLK/
IC7F-１６
CSYC/
IC7F-１９
GYEN
IC7F-２
GREN
IC7F-５
57
IMEN
IC7F-６
PED
IC7F-９
TRST
IC6E-１２
RAS
IC6E-１５
CAS
IC6E-１６
WE
IC6E-１９
INH
SYC
58
IC6E-２
IC6E-５
GMA
GWT
HRST
RACKE
59
IC6E-６
IC6E-９
IC7D-１
IC7D-２
60
RASTE
IC7D-５
RACK
IC7D-１１
RAST
IC7D-８
HRST
RACKE
61
IC7D-１
IC7D-２
GSFT
IC4D-７
GLD
IC4D-１５
62
INH
IC2D-１２
SYC
IC2D-１３
HA0/
IC2E-１０
MPCK
IC2E-８
MPCK
FO/
IC2A-３９
IC2B-２
IC2B-６
63
TSYC/
IC2B-１１
IC2B-１２
TSYC/
64
IC2B-１３
SECTION 2.
2-3.
MAINTENANCE AND TROUBLESHOOTING
TROUBLESHOOTING
65
Troubleshooting
2-3-1 Troubleshooting policy
In the following the procedure to locate the trouble occurred in the equipment is described. In
chapter 2-3-2 the trouble locating procedure for each unit is described. In chapter 2-3-3 faulty
phenomena appeared on CRT are considerable to be defective and principal observing points are
described. In chapter 2-3-4 the trouble shooting concerning to TV monitor is described.
Prior to commence the repair work, the followings should be checked:
(1) Mechanical damage on the equipment and cables.
(2) Connecting condition of the connectors, etc.
(3) Damage pf parts.
(4) Dust, water drop or other external causes.
Notices on repairman:
(1) In order to prevent circuit elements from damage, the power line should be OFF when cables
and PCB are to be mounted or dismounted.
(2) Pay the utmost attention to the high potential at TV monitor.
(3) To observe the waveform, draw out the PCB and lay on in insulating sheet.
2-3-2 Procedure to Locate Trouble for Each Unit
The equipment consists of Power Supply unit, Ultrasound Picture Processor unit. Probe unit and
TV Monitor unit. For each unit, trouble an be located as follow:
(1) Power Supply Unit
Confirm DC power supply voltage to be rated value as shown by Table2-3-1. If the power
supply voltage is less than the rated value, separate the power supply circuit from other PCB and
measure the voltage independently.
Thus the cause of the voltage drop, failure of the power supply circuit or other PCB. Can be
judged.
(2) Ultrasound image processing block
The block is generally divided into two of Transmitter/Receiver unit (EP-393200) and D.S.C
unit (EP-1894, EP-1895, EP-392800).
To the Transmitter/Receiver unit signals of TX RQ/, FR ST/, NEAR/ and DFC/ are sent from
D.S.C unit through J105. Only the above four signals are the control signals(timing signals) sent to
Transmitter/Receiver unit from outside.
By comparing those signals and output signal ECHO VIDEO(TP15) with the waveform in
section2-3, it’s possible to judge whether the falt is in Transmitter/Receiver unit or in D.S.C unit.
(3) Probe Unit
Confirm that ±5v,　±30v are supplied.
Confirm that the transmit trigger TRIG 1~8 and control signal CTRL 1~8 are input and observe
the waveform of the received echoes REC 1~8 to judge the condition l~8 to judge the condition of
66
the probe. As it is difficult to judge the cause of the trouble such as loss of echo image, decreased
sensitivity, noise, etc. only through the waveform observation, or to judge whether it is attributable
to the probe or main body side, the test with a new probe is recommendable. To confirm the loss
of echo image, the probe check methods as shown by Fig.2-3-1 is effective.
For the sensitivity check, RMI PHAMTOM Type 412, etc. are used and the sensitivity is judged
from the tomogram..
When the probe is judged as failure, replacement of transducer or repayment inside the probe is
impossible.
Table 2-3-1 DC POWER SUPPLY VOLTAGE
CONNECTOR NO.
J102
3 pin
4
J102
1
4
J102
DC VOLTAGE
+5V
GND
+5V
GND
SUPPLY TO
MOS,H IC
EP-1893C
LOG IC, OP AMP
EP-1671-1
H IC
EP-1672-1
(UST-5020)
LOG IC, OP AMP
2
4
+12V
GND
7
4
5
4
9
4
-12V
GND
+30V
GND
-30V
GND
J201
1
6
+5V
GND
A/D CON, D/A CON
TTL, OP AMP
J201
5
6
2
6
5
3
-5V
GND
+12V
GND
+5V
GND
A/D CON, D/A CON
OP AMP
A/D CON, D/A CON
MOS
TTL, MEMERY
ROM
EP-1894
4
3
+12V
GND
TV-MONITOR
PC0017
J102
J102
J102
J201
J301
W1
EP-1893C
H IC
H IC
MULTIPLEXER
67
EP-1671-1
EP-1672-1
(UST-5020)
EP-1895
Probe check
1. Apply ultrasound jelly on surface of probe, then set a coin and move slowly in the surface.
2. ECHO slide aside on the screen according to the coin. ECHO should not leap nor appear at two
position or more.
Ｐｒｏｂｅ　ｓｕｒｆａｃｅ
Ｃｏｉｎ
Ｍｏｎｉｔｏｒ
ｓｃｒｅｅｎ
Ｆｉｇ．　２－３－１　ＰＲＯＢＥ　ＣＨＥＣＫ
Ｔａｂｌｅ　２－３－２　ＭＯＮＩＴＯＲ　ＩＮＰＵＴ　ＳＩＧＮＡＬ
ＣＯＮＮＥＣＴＯＲ　ＮＯ．
ＳＩＧＮＥＬ
ＵＰＣ－１３６６Ａ
ｗ１　１ｐｉｎ
２ｐｉｎ
（ＧＮＤ）
Ｔ＝６３．５ｕｓ　（５２５　Ｌｉｎｅｓ）
Ｔ＝６４ｕｓ　（６２５ｌｉｎｅｓ）
ｗ１　４ｐｉｎ
３ｐｉｎ
＋１２Ｖ　ＤＣ
ＧＮＤ
(4) TV Monitor Unit
As a DC coupled monitor is adopted, the screen does not brighten at all. Unless the composite
68
video signal is input or video component is not included in the composite video signal.
If the image does not indicate properly even when the input signals of PC0017 “W1” on
IP-0503-TV are recognized +12V and composite video as shown in Table 2-3-2, The monitor unit
should be judged as failure.
2-3-3 Classifies troubleshooting methods by the case of trouble. This section consists of as
follows:
1) Symptom:… … … … … … … … … … … Describes symptom of trouble.
2) Cause of failure… … … … … … … ...Lists the unit or PCB that is considered to be defect.
3) Main points of checking… … … … … Lists the points to be checked for judgment of faulty PCB.
* Refer also to section2-2 “Waveform diagrams”
Phenomena which are not considered as faults under special
condition.
It rarely happens that because of instantaneous power interruption or great drop down of power
voltage (-10% or lower), panel switches does not operate correctly. This is caused by abnormal
operation of microprocessor, due to lowered power voltage.
To restore the condition, turn off the power once and after two or three seconds turn on the power
again. The above condition occurs due to the characteristic of the circuit and it’s not considered as
a fault.
However if the normal operation cannot be restored when the power is turned on again, it is a fault.
TROUBLE OF WHOLE IMAGE ON MONITOU SCREEN
EX.1 1) symptom:
Nothing appears on the screen.
2) Causes of failure:
Failure of ±5V, +12V Power supply (EP-1882)
Failure of composite VIDEO
(EP-1894)
Failure of TV-Monitor
(IP-0503-TV)
Breakage of the cable or contact failure of connector.
69
3) Main points of checking:
EP-1882 J502 ±5V DC +12VDC
EP-1894 J203 1 PIN (MONI.OUT)
TV-Monitor → Refer to chapter 2-3-4 IP-0503-TV troubleshooting.
EX.2 1) symptom:
Ultrasound image, scale marker and gray scale bar
are not displayed, unless raster bright on the screen
2) Causes of failure:
System clock generator does not generate Fs nor Fo. (EP-1895)
Defect of A/D Converter circuit (EP-1894)
Failure of TV-Monitor
3)
Main points of checking:
EP-1895 IC1F 8 pin (FO)
EP-1894 J203 1 pin (MONI.OUT)
TV-Monitor → Refer to chapter 2-3-4 IP-0503-TV troubleshooting.
EX.3 1) symptom:
Picture is displayed in disorder, or picture flows on
the monitor
2) Causes of failure:
Level of TV-signal is low or too high. (EP-1894)
Sync failure of TV-Video signal (EP-392800)
System clock generator dose not generate stable clock.
3) Main points of checking:
EP-1894
J203 1 pin
EP-1895
IC1F 8 pin
(MONI.OUT)
(FO)
70
TROUBLE OF ULTRASOUND IMAGE
EX.4 1) symptom:
Raster, scale marker and gray scale bar are displayed,
but Ultrasound image is not displayed on the screen.
2) Causes of failure:
Failure of ±30V, -12V Power supply (EP-1882)
Failure of Probe
Defect of Tx & Rx circuit
Defect of A/D Converter circuit
Defect of Image memory circuit.
(UST-5813-5)
(EP-393200)
(EP-1894)
(EP-1895)
3) Main points of checking:
EP-1882 J502 ±30V DC -12VDC
EP-1882 J502 P102
EP-393200 TP3~TP10 (TRIG 1~TRIG 8)
EP-393200 IC23~IC30 each 3 pin (REC 1~REC 8)
EP-393200 TP15 (ECHO VIDEO)
EP-1894 Out of A/D Converter IC6A 2,5,7 pin
EP-1894 Data line of echo video data
EP-1895 Data line of echo video data
EX.5 1) symptom:
At a certain part of the Ultrasound image area,
sensitivity is excessively low or not at all.
2) Causes of failure:
Defect of Tx & Rx phase control circuit
Failure of Probe
3) Main points of checking:
EP-393200 IC14 (CTRL1~CTRL8)
EP-1894 IC13 (CTRLA~CTRLD)
71
(EP-393200)
(UST-5813-5)
EX.6 1) symptom:
Sensitivity of whole Ultrasound image is excessively
low.
2) Causes of failure:
Failure of ±30V Power supply
(EP-1882)
Defect of Tx & Rx Control circuit
Defect of Receiving circuit
Defect STC circuit
Failure of Probe
(EP-393200)
(EP-393200)
(EP-393200)
(UST-5813-5)
3) Main points of checking:
EP-1882 J502 ±30V DC
EP-393200 TP3~TP10 (TRIG 1~TRIG 8)
EP-393200 TP15 (ECHO VIDEO)
EP-393200 TP14 (STC OUT)
EX.7 1) symptom:
When probe is touched, indication of noise is
increased.
2) Causes of failure:
Poor shielding of Probe
Breakage of cable or contact failure of Probe
(UST-5813-5)
(UST-5813-5)
3) Main points of checking:
Check mechanical damage of contact terminal of connector.
EX.8 1) symptom:
Leakage of other parts of Ultrasound image.
2) Causes of failure:
Defect of Address control circuit
Breakage of Probe cable
Failure of Probe
(EP-393200)
3) Main points of checking:
EP-393200 IC14 (CTRL1~CTRL8)
72
EX.9 1) symptom:
Bright vertical line runs sometimes in Ultrasound
image area.
2) Causes of failure:
Delay time of transmitting or receiving is not stable.
(Defect of Delay line)
(EP-393200)
Defect of Tx & Rx circuit
(EP-393200)
Failure of Probe
3) Main points of checking:
EP-393200 TP12
(ECHO VIDEO)
EP-393200 TP3~TP10 (TRIG 1~TRIG 8)
EX.10 1) symptom:
Gain control dose not work
2) Causes of failure:
Defect of HIC (DHVD014)
Defect of RV1~RV3
(EP-393200)
3) Main points of checking:
EP-393200 TP1,TP14 (US BLK,STC SIG)
USI-141 RV1~RV3
EX.11 1) symptom:
Black and white stripes are displayed in the
Ultrasound image area, but image is not displayed
2) Causes of failure:
Defect of Transmission control circuit (EP-1895, EP-392800)
Defect of Freeze circuit
(EP-392800)
3) Main points of checking:
EP-1895 IC9B 8 pin
IC9C 6 pin
EP-392800 IC2B 11 pin
IC2E 11 pin
IC2D 6 pin
(FSYC)
(TSYC/)
(R CHG/)
73
EX.12 1) symptom:
Ultrasound image is not indicated in formation unless
transmitting pulse is indicated on screen.
2) Causes of failure:
Ultrasound transmitting timing dose not correspond with
memory address of image data.
3) Main points of checking:
EP-1895 IC8F
6 pin (FSTT)
EP-1894
J206
7 pin (FRST)
EX.13 1) symptom:
A portion of Ultrasound image area is flickering.
2) Causes of failure:
Defect of A/D Converter circuit
Defect of Image memory
Defect of Line interpolation circuit
(EP-1894)
(EP-1895)
(EP-1895)
3) Main points of checking:
EP-1894 Data line of echo video data
EP-1895 Data line of echo video data
EP-1895 IC7G 11 pin
(RAS/)
IC7G 8 pin
(WE/)
IC7G 6 pin
(CAS/)
74
TROUBLE OTHER THAN ULTRASOUND IMAGE
EX.14 1) Symptom:
Freeze function is not effective
2) Causes of failure:
Defect of Freeze switch
Defect of I/O Interface circuit
(EP-2241)
(EP-392800)
3) Main points of checking:
EP-2241 S21
EP-392800 IC3E 9 pin
IC2D 3 pin
IC2D 6 pin
EX.15 1) Symptom:
(FZRQ)
(FSYC)
Gray scale bar is not displayed on the screen
2) Causes of failure:
Defect of scale generator circuit
(EP-1895)
3) Main points of checking:
EP-1895 IC5F 3 pin
IC5F 2 pin
IC5F 6 pin
IC5F 7 pin
(GY0)
(GY1)
(GY2)
(GY3)
EX.16 1) Symptom:
Abnormal display of scale marker, ID code and
caliper marker.
2) Causes of failure:
Defect of Graphic memory circuit
3) Main points of checking:
EP-392800 IC4B 10 pin
IC1E
5 pin
(EP-392800)
(ADDRESS SELECT)
(GDT)
75
2-3-4.
IP-0503-TV
TROUBLESHOOTING
To employ this service manual:
1. Determine defective circuit by referring to Symptoms and Checkpoints.
2. Refer to checking procedure for the particular circuit to determine cause and correction.
CONTENTS
1. Symptoms and Checkpoints
2. Circuit Checking Procedure
1. Video Amplifier Circuit
2. Sync. Separator Circuit
3. Back porch Clamp CIRCUIT
4. Vertical Deflection Circuit
5. AFC, Horizontal Oscillator & Drive Circuit
6. Horizontal Output Circuit & High Voltage Circuit
7.CRT Circuit
3. Etc.
-1 Circuit Diagram
-2 Component Layout
-3 Parts List
1.
Symptoms and Checkpoints
(Fig.1)
a. No raster
(see following page)
b. Raster obtained, but no picture
c. Blanking line visible
d. Fuse opens
(see following page)
e. Both horizontal and vertical sync. Unstable
f. Horizontal sync. Defective
g. Vertical sync. Defective
h. Raster becomes single horizontal line
i. Raster becomes single vertical line
j. Horizontal amplitude insufficient of excessive
k. Vertical amplitude insufficient or linearity poor
l. Picture out of focus
m. Image small
n. Upper portion of picture curved
o. Jittering
p. Ringing
q. Video amplifier circuit
r. Sync. Separator circuit
76
s. Vertical deflection circuit
t. Horizontal oscillator & drive circuit
u. Horizontal output & high voltage circuit
v. CRT circuit
w. Back porch clamp circuit
(AFC)
No Raster
(Fig.2)
a. Inspect horizontal oscillator & drive circuit
b. Check for drive waveform at TR13 base
c. Inspect output & high voltage circuit
d. CRT heater lighter?
e. Check for horizontal deflection pulse
f. Check for high voltage supply to CRT
g. CRT high voltage supply within specifications?
h. CRT defective.
i. Check for open fuse.
a
q
a
d
i
e
j
m
b
c
b
r
d
c
e
f
k
s
f
g
l
g
t
h
i
h
u
j
Fig. 2
k
v
l
m
a
n
b
o
p
j.
k.
l.
m.
w
Fig. 3
Fig. 1
Inspect power supply voltage
Inspect high voltage output circuit
Inspect CRT circuit
See following checking procedure (Fig. 3)
Fuse Opens (Fig.3)
a. Power supply voltage within specifications?
b. This type of defect is generally in horizontal output circuit.
77
ok
2. Circuit Checking Procedure
1. Video Amplifier Circuit
Cause of malfunction can be easily determined by sequentially inspecting waveforms and voltages
from first to last stage
a
Fig.4
b
e
m
c
f
n
d
g
o
h
p
i
q
j
r
k
s
l
Fig. 4
a. No picture
b. Raster obtain
c. Voltage present at TR3 base? (2.0V~2.4V)
d. R13, R15 open: Inspect backporch clamp circuit.
e. Waveform present at TR3 collector?
f. Waveform present at TR3 base?
g. Waveform present at TR17 base?
h. Waveform present at TR18 emitter?
i. Waveform present at TR2 collector?
j. Waveform present at TR2 base?
k. Waveform present at TR1 base?
l. C1 open, R2 open.
m. R19 open.
n. TR3, TR4 defective.
o. R84 open, TR17 defective, C57 open.
p. R9, R81 open; C2, C56 open.
q. TR18 defective.
r. TR2 defective.
s. TR1 defective, R3, R4 open.
Blanking line visible
Inspect R58, R59, R60, R72, CD4, CD12, C55
78
2. Sync. Separator Circuit
This circuit obtains sync. Components from composite video signal. Outputs are supplied to
horizontal and vertical circuits. For this reason, such complaints as “both H & V sync. Absent”or
“weak sync.” Are generally limited to this section. Determine the cause of malfunction is also
relatively easy.
********
Unstable Sync. (Fig. 5)
a. Both horizontal and vertical sync. defective?
b. Vertical sync. defective?
c. Can single image be obtained by adjusting H.HOLD?
d. Inspect horizontal oscillator circuit.
e. Inspect sync. separator circuit.
f. By adjusting V.HOLD, dose picture roll upwards and downwards?
g. Inspect vertical oscillator circuit.
h. Inspect AFC circuit.
i. Inspect integrator circuit.
R27
+
R22
68K
a
C7
1/50
a
e
b
f
220
C8
R23
680K
j
R24
8.2K
g
c
h
k
l
m
n
TR6
2SC458
0.0047u
SYNC.
R26
240
i
+B
100
C9
47/16
TR5
2SA844
R21
+
TR1
R25
100K
R28
680
o
d
Base
Collector
TR5
Fig.5
Inspection Sequence Example:
j. Both H & V sync. absent.
k. Waveform present at TR6 base?
l. TR6 defective; R28, R29 open.
m. Waveform present at TR5 base?
n. TR5 defective; R24 R26 open.
o. C7 open; R21 open.
79
Emitter
1V
11V
11.8V
11V
11.9V
11V
TR6
This circuit make brightness of block level fixed and get always stable video, not due to changes
of contrast, when video signal would be input.
a
b
g
c
h
d
i
e
j
f
Fig.6
Fig. 6
a. No picture and No raster
b. Voltage present at TR9 collector? (2.0V~2.4V)
c. Waveform present at TR9 base?
d. Waveform present at TR8 base?
e. Waveform present at TR7 base?
f. R29, C10 open.
g. Inspect video amplifier circuit.
h. TR9 defective.
i. TR8 defective. R36, C15 open.
j. TR7 defective. R31, C12 open.
4. Vertical Deflection Circuit (Fig. 7)
(1). Raster becomes single horizontal line.
This symptom occurs when sawtooth wave current is not applied to deflection coil. Inspect
circumferential parts of IC and opened resistor and shorted or opened condenser.
(2). Insufficient vertical amplitude.
Symptom produced when amplitude of sawtooth wave current in vertical deflection coil is
insufficient. IC, RV3 defective and Inspect circumferential parts.
(3). Vertical Linearity Poor.
This symptom is produced by insufficient linearity of sawtooth wave current in deflection coil.
a. Current
b. Picture
c. Bottom
d. Center
e. Top
80
(A) Correct (B) Bottom of picture contracts
© Top of picture contracts
f. Poor vertical linearity
g. Does linearity change with V.LIN VR(RV4) adjustment?
h. Is picture affected by V.HEIGHT VR(RV3) adjustment?
i. IC defective.
j. Inspect C50, C51, jR67, RV4.
k.Inspect C47, R65, R66, RV3.
R92
470
V.HOLD
+B
RV2
50K
C44
0.047
C45
R86
1.5K
R87
2.2K
2
TR16
2SA844
6
5
R61
820
0.001
TR15
2SC458
R62
220
10
IC2
8
9
+
C48
100
R63
33K
+
R90
2.2K
R91
4.7K
R85
8.2K
C45
0.022
R89
2.7K
R68
1.8K
C49
47U
+
R88
2.7K
TR6 E
+ C40
10U
+
5
LA1385
4
7
C52
2200
C53
0.022
R69
1K
1
+
C59
220/16
C46
1/35
L101
LS28
+
CD13
1S2076
C50
4.7U
RV3 20K
R64
2.7K
C51
2.2U
R66
R67
RV4
15K
3.3K
5K
R65
2.7K
C54
0.01
+
C61
+ C55
4.7U
CD14
1S2076
R70
R71
680
R72
470
V.SIZE
TR3 E
Base
TR15
TR16
Collector
0.7V
12V
0V
2V
12V
0V
2
1
Emitter
3
4
5
12V
6
11.9V
7
12V
8
6V
9
4V
3V
1.2V
0V
1.2V
11.9V
10
b
c
ad
e
C
B
A
f
g
j
h
k
i
Fig.7
81
5. Horizontal Oscillator & Drive Circuit (AFC)
(Fig.8)
(1) Horizontal Sync. Breakup
Turning the H. HOLD control can provide an indication of the type of malfunction.
a. Phase discriminator circuit
b. Horizontal Oscillator Circuit
c. Single picture can be obtained with difficulty, then slips horizontally.
d. Number of horizontal lines numerous can be reduced, but single picture not obtained.
e. Horizontal lines numerous and picture completely unobtainable.
f. Slanted lines from right downward indicate oscillator frequency too high.
g. Slanted lines from left downward indicate oscillator frequency too low.
h. Horizontal sync. Breakup
i. Comparator waveform (B) applied to phase discriminator?
j. Does point (A) potential vary with variation of L1?
k. Oscillator circuit defective.
l. Inspect C22, C23, R57, FBT
m. Phase discriminator circuit defective; inspect R56, CD5, CD6, TR10.
Determining oscillator circuit multifunction:
Observe direction of slanted lines to determine high or low oscillator frequency.
1. If oscillator frequency is high, inspect components which raise oscillator transistor(TR11)
base potential.
2. If oscillator frequency is low, inspect components which lower oscillator transistor(TR11)
base potential.
If AFC smoothing circuit (C24, C25, R47) in phase discriminator circuit output is defective,
wavy picture or unstable horizontal sync. Can be produced.
(2) No raster
(Horizontal oscillation stopped)
This symptom develops when horizontal drive pulse is not applied to horizontal output
transistor base. Difficulty can be determined by tracing the waveform.
Check procedure
n. Horizontal oscillation stopped.
o. Waveform present at TR12 collector?
p. Waveform present at TR12 base?
q. Waveform present at TR11 collector?
r. Inspect TR4, L1, R56, R52.
s. Inspect from drive transformer to H.OUT TR base.
t. Inspect R56, T1, TR12, C30.
u. R53 open.
82
* C18
C22
CAP
+
B
FBT 7
R57
50V IU
2.2K
R55 100
+B
R56
R41
470
220
R47
2.2K
TR13 B
L1
C25
0.068
R40
56K
TR10
2SC458
C20
0.01
CD5
1S2076
R43
5.6K
+
LS22
C22
C24
0.047
R50 27
R48
C28
16V
47U
C30
0.033
TR11
4.8K
C10
0.0047
+
C26
0.01
47U
16V
TR6 E
T1
LP-54
2SA844
A
R44
5.6K
R51
330
C21
0.01
CD6
1S2076
R42
390
TR12
2SD667
R53
580
C23
0.0047
R52
580
GND
R45
1.8K
R46
RV1 5K
3.3K
BASE
COLLECTOR
EMITTER
TR10
9Vp-p (-3.4V)
6.5 Vp-p (10.5V)
4.0 Vp-p (0.5V)
4Vp-p (10.9V)
9 Vp-p (1.3V)
2.5 Vp-p (11V)
0.6Vp-p (0.3V)
5.2 Vp-p (3.2V)
TR11
TR12
(0V)
c
a
f
d
b
e
g
n
h
i
l
o
s
j
m
p
t
q
u
k
r
Fig. 8
83
6. Horizontal Output Circuit and High Voltage Circuit (Fig.9)
Malfunctions which can be attributed to this circuit are:
(1). No raster
This symptom occurs when high voltage is not applied to CRT. Possible causes are deflection
pulse not applied to flyback transformer primary or defective flyback transformer or high voltage
rectifier.
(2). Fuse open when power or high voltage rectifier.
This symptom is caused by excessive +B current due to defects of following components.
TR13 C-E short, CD9 short
C31,C32,C36 short
Check with VOM
FBT short
(3). Horizontal deflection stopped (vertical line produced)
This occurs when sawtooth wave current is nit applied to deflection yoke. Suggested
checkpoints are open L2,L3,L101.
(4). In the case that ringing and jittering cause:
It is phenomenon that vertical line is found on lower part (on left side) and/or a little noise
cause. CDLL and/or flyback transformer (FBT) might be broken.
R20
E-2799BA V101
+B
4
4.7K
3
TR31
2
1,5
6
7
T-2
LP-SS
CD9
V06C
6
7
T1
DRIVE
TRANS
1
TR13
2SD1163
C31
C32
C33
0.022U
630V
0.0047U
630V
10U 25V
C34
CD10
R76
5.6K
CD7
CD8
V06C
RGP-15G
RU-18
R95
91K
+
C58
RV5
1M
C39
0.047U
630V
2
C35
1U 50V
RV8
R77
15
L2 LS29
50K
R75
15K
CD19
R30
8
BRIGHT
3
RGP-15G +
C36
-
330U 25V
L3
C60
160V
CD20
HIT33
10U
LS-27
L5
R93
10K
LS28
2
1
R101
CD10
560
RGP-15G
CD11
RG1G
L4
LS20
75V
TR19 2SC1912
64.7V
C38
160V
10U
R96
4.7K
66V
CD17
HIT33
+5V
CD18
HIT33
Base
Collector
TR13
4.8V
100V
Fig.9
84
Emitter
0V
C37
0.068U
-
7. CRT Circuit (Fig.9)
Main problems affecting this circuit are abnormal power supply to CRT and defective CRT.
Malfunction are easily determined due to the small number of parts.
(1). No raster (normal high voltage supplied to CRT)
Observe if heater is glowing. If heater does not glow, inspect open R20 and for possible open
heater.
(2). Brightness does not vary when BRIGHTNESS control is rotated,
This occurs when cathode potential is not varied by BRIGHTESS control rotation. Possible
causes are R75, open RV6, RV102 defective.
85
MAINTENANCE:
(1). Cleaning on Picture Tube
As Picture Tube is always apt to adhere dusts in air
because static electricity rise, and also the resolution
would therefore be lowered, please keep cleaning periodically.
(2). Caution on Checking:
It is necessary for you to take care in its treating,
because transistor is very weak in electric shock and is
suddenly broken when voltage over at rated is put on.
As especially Horizontal Circuit is of high power-electric -circuit,
and as a little abnormal of handling cause some times transistor broken,
please do not check high voltage
caused by means of making spark with screw driver, etc.
If such tester would not be available, while removing
CRT Socket, please check cause of high voltage removing
connector after putting on connector and after discharge
voltage charged in CRT by means of nearing lead-wire
which is on earth to Anode of CRT.
MANUAL:
Operation of Adjustment-Buttons on the printed circuit board
H. HOLD : When the picture is offset, or slanting stripes
(RV1)
and bars appear, adjust “H. HOLD”control.
V. HOLD : When the picture is overlapped or rolling up
(RV2)
or down, adjust “H. HOLD”control.
CONTRAST: When the picture contrast is too weak or too
(RV7)
strong, adjust “CONT.”control.
BRIGHTNESS: When the picture contrast is too bright or too
(RV8)
dark, adjust “BRIGHT.”control.
V. LIN:
When the pattern is distorted at the top or bottom,
(RV4)
adjust “VV.LIN.”control.
V. HEIGHT:
When the center circle of the pattern is eggy,
(RV3)
adjust “V.HEIGHT.”control.
H. RRO:
When the pattern is offset, or stripes and bars
(L1)
appear and cannot be corrected with Hold control,
adjust “H. RRO.”Control
FOCUS:
When the pattern is blurred or out of focus,
(RV5)
adjust “FOCUS”control.
86
SECTION 3.
PARTS LIST
USI-141 MECHANICAL PARTS LIST
NO PARTS
TYPE AND DESCRIPTION
1.1 Monitor PCB Unit
PC-0017Ｎ（NTSC）
1.2 Monitor PCB Unit
PC-0017P（PAL)
2 CRT(include coil）
C5M13P4GH
3 Power PCB Unit
EP-1882Ｇ
4 A/D＆D/A　PCB Unit
EP-1894-7
5 DSC　PCB Unit
EP-1895E-6
6.1 MPU　PCB Unit (NTSC)
EP392801
6.2 MPU　PCB Unit (PAL)
EP392800
7 RX/TX　PCB Unit
EP-393200A
8 KEY　Unit
EP-2241
9.1 Power transformer（include connector）R65-02-7-1(120V)
9.2 Power transformer（include connector）R65-95-3-2(220V)
10 Fuse (100V)用
T　1A　250V
11 Probe (include PCB)
UST-5813-5
12 PANEL
MM179205U
13 BOTTEM
MM102779
14 UPPER COVER(include handle）
MM102510
87
NUM
BER
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
REFERENCE
NTSC
PAL
AAV(NTSC)
PAL
AAV(NTSC)
PAL
Contact us
Shanghai Aloka Medical Equipment Co., Ltd.
56 Jingang Rd.,Jinqiao Export Processing Area,
Pudong, Shanghai China
Address:
P.C:
201206
Tel:
0086-21-50325678
Fax:
0086-21-58346433
Company：
[email protected]
[email protected]
Finance Dept：
[email protected]
Administrator Dept:
[email protected]
Technology Dept：
Human Resource Dept： [email protected]
[email protected]
IT：
88