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bdiGDB for GNU Debugger, BDI3000 (ARM11 / Cortex)
User Manual
51
3.4.1 Command list
"MD
"MDH
"MDB
"MDAPB
"MDAHB
"DUMP
"MM
"MMH
"MMB
"MMAPB
"MMAHB
"MT
"MC
"MV
[<address>] [<count>]
[<address>] [<count>]
[<address>] [<count>]
<addr> [<cnt>]
<addr> [<cnt>]
<addr> <size> [<file>]
<addr> <value> [<cnt>]
<addr> <value> [<cnt>]
<addr> <value> [<cnt>]
<addr> <value>
<addr> <value>
<addr> <count>
[<address>] [<count>]
"RD
"RDUMP
"RDALL
"RDCP
"RDFP
"RDBG
"RM
"RMCP
"RMFP
"WDBG
[<name>]
[<file>]
display target memory as word (32bit)",
display target memory as half word (16bit)",
display target memory as byte (8bit)",
display APB memory (32bit)",
display AHB/AXI memory (32bit)",
dump target memory to a file",
modify word(s) (32bit) in target memory",
modify half word(s) (16bit) in target memory",
modify byte(s) (8bit) in target memory",
modify APB memory (32bit)",
modify AHB/AXI memory (32bit)"
memory test",
calculates a checksum over a memory range",
verifies the last calculated checksum",
display general purpose or user defined register",
dump all user defined register to a file",
display all ARM registers ",
[<cp>] <number>
display CP register, default is CP15",
display floating point register",
<nbr> [<cnt>]
display core debug register",
{<nbr>|<name>} <value> modify general purpose or user defined register",
[<cp>] <number><value> modify CP register, default is CP15",
<number> <value>
modify floating point register",
<nbr> <value>
modify core debug register",
"MODE {usr|sys|hyp|svc|abt|und|mon|irq|fiq} set processor mode",
"SECURE
Cortex-A: switch from nonsecure to secure state",
"NONSECURE
Cortex-A: switch from secure to nonsecure state",
"MMU
"DTLB
"ITLB
"LTLB
"ATLB
"DTAG
"ITAG
{ENABLE | DISABLE}
<from> [<to>]
<from> [<to>]
<from> [<to>]
<from> [<to>]
<from> [<to>]
<from> [<to>]
"RESET [HALT | RUN [time]]
"GO
[<pc>]
"CONT <cores>
"TI
[<pc>]
"HALT [<cores>]
"BI <addr>
"BI <addr> [<mask>]
"CI [<id>]
"BD [R|W] <addr>
"BDH [R|W] <addr>
"BDB [R|W] <addr>
"BDM [R|W] <addr> [<mask>]
"CD [<id>]
"INTDIS
"INTENA
enable /
ARM1136:
ARM1136:
ARM1136:
ARM1136:
ARM1136:
ARM1136:
disable
display
display
display
display
display
display
MMU via control register",
Data TLB entries",
Inst TLB entries",
Lockable Main TLB entries",
Set-Associative Main TLB entries",
L1 Data Cache Tag(s) ",
L1 Inst Cache Tag(s) ",
reset the target system, change startup mode",
set PC and start current core",
restart multiple cores (<cores> = core bit map)"
single step an instruction",
force core(s) to debug mode (<cores> = core bit map)"
set instruction breakpoint",
Cortex-A: set instruction breakpoint",
clear instruction breakpoint(s)",
set data watchpoint (32bit access)",
set data watchpoint (16bit access)",
set data watchpoint ( 8bit access)",
Cortex-A: set data watchpoint with address mask",
clear data watchpoint(s)",
disable target interrupts while running",
enable target interrupts while running (default)",
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