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Figure 3-3: K28.5+ with Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 3-4: Eye Diagram, 10% Pre-Emphasis, 20" FR4, Worst-Case Conditions . . . . . . . . 108
Figure 3-5: Eye Diagram, 33% Pre-Emphasis, 20" FR4, Worst-Case Conditions . . . . . . . . 108
Figure 3-6: MGT Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 3-7: Power Supply Circuit Using Approved Regulator . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 3-8: Power Filtering Network on Devices with Internal and External Capacitors. . 113
Figure 3-9: Example Power Filtering PCB Layout for Four MGTs, in Device with
Internal Capacitors, Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 3-10: Example Power Filtering PCB Layout for Four MGTs, In Device with
External Capacitors, Top Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 3-11: Example Power Filtering PCB Layout for Four MGTs, in Device with
External Capacitors, Bottom Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 3-12: Single-Ended Trace Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 3-13: Microstrip Edge-Coupled Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 3-14: Stripline Edge-Coupled Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 3-15: AC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 3-16: DC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 3-17: LVPECL Reference Clock Oscillator Interface . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 3-18: LVPECL Reference Clock Oscillator Interface (On-Chip Termination) . . . . 121
Figure 3-19: LVDS Reference Clock Oscillator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 3-20: LVDS Reference Clock Oscillator Interface (On-Chip Termination) . . . . . . . 121
Chapter 4: Simulation and Implementation
Figure 4-1: XC2VP2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 4-2: XC2VP50 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Appendix A: RocketIO Transceiver Timing Model
Figure A-1: RocketIO Transceiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure A-2: RocketIO Transceiver Timing Relative to Clock Edge . . . . . . . . . . . . . . . . . . . . 135
Appendix B: 8B/10B Valid Characters
Appendix C: Related Online Documents
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RocketIO™ Transceiver User Guide
UG024 (v2.4) August 25, 2004