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Download Texas Instruments TMS320C6202 User's Manual
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TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 D D D Highest Performance Fixed-Point Digital Signal Processor (DSP) TMS320C6202 – 4-ns Instruction Cycle Time – 250-MHz Clock Rate – Eight 32-Bit Instructions/Cycle – 2 000 MIPS VelociTI Advanced Very Long Instruction Word (VLIW) ’C6200 CPU Core – Eight Highly Independent Functional Units: – Six ALUs (32-/40-Bit) – Two 16-Bit Multipliers (32-Bit Result) – Load-Store Architecture With 32 32-Bit General-Purpose Registers – Instruction Packing Reduces Code Size – All Instructions Conditional Instruction Set Features – Byte-Addressable (8-, 16-, 32-Bit Data) – 32-Bit Address Range – 8-Bit Overflow Protection – Saturation – Bit-Field Extract, Set, Clear – Bit-Counting – Normalization 3M-Bit On-Chip SRAM – 2M-Bit Internal Program/Cache – Two 128K-Byte Blocks Offer Improved Concurrency Block 0: 128K Bytes Memory-Mapped Block 1: 128K Bytes Direct-Mapped Cache/Memory-Mapped – 1M-Bit Dual-Access Internal Data (128K Bytes) – Two 64K-Byte Blocks Offer Improved Concurrency D D D D D D D D D D D 32-Bit External Memory Interface (EMIF) – Glueless Interface to Synchronous Memories: SDRAM or SBSRAM – Glueless Interface to Asynchronous Memories: SRAM and EPROM Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel Flexible Phase-Locked-Loop (PLL) Clock Generator 32-Bit Expansion Bus – Glueless/Low-Glue Interface to Popular PCI Bridge Chips – Glueless/Low-Glue Interface to Popular Synchronous or Asynchronous Microprocessor Buses – Master/Slave Functionality – Glueless Interface to Synchronous FIFOs and Asynchronous Peripherals Three Multichannel Buffered Serial Ports (McBSPs) – Direct Interface to T1/E1, MVIP, SCSA Framers – ST-Bus-Switching Compatible – Up to 256 Channels Each – AC97-Compatible – Serial-Peripheral-Interface (SPI) Compatible (Motorola) Two 32-Bit General-Purpose Timers IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible 352-Pin BGA Package (GJL Suffix) 384-Pin BGA Package (GLS Suffix) 0.18-µm/5-Level Metal Process – CMOS Technology 3.3-V I/Os, 1.8-V Internal ADVANCE INFORMATION D Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI is a trademark of Texas Instruments Incorporated. Motorola is a trademark of Motorola, Inc. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright 1999, Texas Instruments Incorporated ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 GJL 352-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) ADVANCE INFORMATION AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 2 5 4 7 6 9 8 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 GLS 384-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW ) AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 2 2 5 4 7 6 9 8 POST OFFICE BOX 1443 11 10 12 13 15 17 19 21 14 16 18 20 22 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 description The TMS320C62x DSPs (including the TMS320C6202 device) are the fixed-point DSP family in the TMS320C6000 platform. The TMS320C6202 (’C6202) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. The ’C6202 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of two 128K-byte blocks, with one block configured as memory-mapped program space, and the other block user-configured as cache or memory-mapped program space. Data memory consists of two 64K-byte blocks of RAM. The peripheral set includes three multichannel buffered serial ports (McBSPs), two general-purpose timers, an expansion bus (XB) that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The ’C6202 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. device characteristics Table 1 provides an overview of the ’C6202 DSP. The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. Table 1. Characteristics of the ’C6202 Processors CHARACTERISTICS DESCRIPTION Device Number TMS320C6202 On-Chip Memory 2 Mbit Program Memory (organized as 2 blocks) 1 Mbit Data Memory (organized as 2 blocks) Peripherals 3 Multichannel Buffered Serial Ports (McBSP) 2 General-Purpose Timers External Memory Interface (EMIF) Expansion Bus (XB) Cycle Time 4 ns Package Type 27 mm × 27 mm, 352-Pin BGA (GJL) 18 mm × 18 mm, 384-Pin BGA (GLS) Nominal Voltage 1.8 V Core 3.3 V I/O TI is a trademark of Texas Instruments Incorporated. Windows is a registered trademark of the Microsoft Corporation. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 ADVANCE INFORMATION With performance of up to 2000 million instructions per second (MIPS) at a clock rate of 250 MHz, the ’C6202 offers cost-effective solutions to high-performance DSP programming challenges. The ’C6202 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32–bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The ’C6202 can produce two multiply-accumulates (MACs) per cycle for a total of 500 million MACs per second (MMACS). The ’C6202 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 functional block diagram Timers Interrupt Selector McBSPs XB Control DMA Control EMIF Control Data Memory Peripheral Bus Controller Data Memory Controller DMA Controller Expansion Bus (XB) Interface PLL ADVANCE INFORMATION CPU EMIF Power Down Program Memory Controller BootConfig. Program Memory/Cache 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 CPU description The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see Figure 1 and Figure 2). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. Another key feature of the ’C6200 CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The ’C6200 CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 5 ADVANCE INFORMATION The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the ’C6200 CPU from other VLIW architectures. TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 CPU description (continued) Program Memory 32-Bit Address 256-Bit Data Á Á External Memory Interface ADVANCE INFORMATION ÁÁÁÁ ÁÁ Á Á Á ’C62x CPU Program Fetch Control Registers Instruction Dispatch Instruction Decode Data Path A Register File A Data Path B Register File B ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁ Á Á Á ÁÁ ÁÁ ÁÁ Á Á Á Á ÁÁ ÁÁ Test .L1 .S1 .M1 .D1 .D2 .M2 .S2 .L2 Emulation Interrupts Data Memory 32-Bit Address 8-, 16-, 32-Bit Data Figure 1. TMS320C62x CPU Block Diagram 6 Control Logic POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Additional Peripherals: Timers, Serial Ports, etc. TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 ÁÁÁÁ Á Á ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ Á ÁÁ ÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁ ÁÁ Á ÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ ÁÁ Á ÁÁÁÁ Á Á ÁÁÁÁ Á Á ÁÁÁÁ ÁÁ ÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁ ÁÁÁÁ Á Á ÁÁÁÁ Á ÁÁÁÁ Á ÁÁ ÁÁÁÁ src1 .L1 Á ST1 Data Path A src2 dst long dst long src long src long dst dst .S1 src1 8 8 32 8 Register File A (A0–A15) src2 .M1 dst src1 src2 LD1 Á Á DA1 DA2 LD2 .D1 .D2 dst src1 src2 2X 1X src2 src1 dst src2 .M2 src1 dst src2 Data Path B src1 dst long dst long src Register File B (B0–B15) .S2 ST2 Á long src long dst dst .L2 src2 ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ADVANCE INFORMATION CPU description (continued) 8 32 8 8 src1 Control Register File Figure 2. TMS320C62x CPU Data Paths POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 signal groups description CLKIN CLKOUT2 CLKOUT1 CLKMODE0 CLKMODE1† CLKMODE2† Clock/PLL Reset and Interrupts PLLV PLLG PLLF ADVANCE INFORMATION TMS TDO TDI TCK TRST EMU1 EMU0 RSV4 RSV3 RSV2 RSV1 RSV0 IEEE Standard 1149.1 (JTAG) Emulation DMA Status DMAC3 DMAC2 DMAC1 DMAC0 Power-Down Status PD Reserved Control/Status † For GLS devices only Figure 3. CPU Signals 8 POST OFFICE BOX 1443 RESET NMI EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 IACK INUM3 INUM2 INUM1 INUM0 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 signal groups description (continued) Asynchronous Memory Control 32 Data CE3 CE2 CE1 CE0 EA[21:2] BE3 BE2 BE1 BE0 TOUT1 TINP1 Memory Map Space Select 20 Synchronous Memory Control Word Address HOLD/ HOLDA Byte Enables SDA10 SDRAS/SSOE SDCAS/SSADS SDWE/SSWE HOLD HOLDA EMIF (External Memory Interface) Timer 0 Timer 1 ADVANCE INFORMATION ED[31:0] ARE AOE AWE ARDY TOUT0 TINP0 Timers McBSP0 McBSP1 CLKX1 FSX1 DX1 Transmit CLKR1 FSR1 DR1 Receive CLKS1 Clock Transmit CLKX0 FSX0 DX0 Receive CLKR0 FSR0 DR0 Clock CLKS0 McBSP2 Transmit CLKX2 FSX2 DX2 Receive CLKR2 FSR2 DR2 Clock CLKS2 McBSPs (Multichannel Buffered Serial Ports) Figure 4. Peripheral Signals POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 signal groups description (continued) 32 XD[31:0] XBE3/XA5 XBE2/XA4 XBE1/XA3 XBE0/XA2 XRDY Data Clocks Byte-Enable Control/ Address Control I/O Port Control XHOLD ADVANCE INFORMATION XHOLDA XFCLK XOE XRE XWE/XWAIT XCE3 XCE2 XCE1 XCE0 Arbitration Expansion Bus Host Interface Control Figure 4. Peripheral Signals (Continued) 10 XCLKIN POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 XCS XAS XCNTL XW/R XBLAST XBOFF TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions SIGNAL NAME PIN NO. TYPE† DESCRIPTION GJL GLS C12 B10 I Clock Input CLKOUT1 AD20 Y18 O Clock output at full device speed CLKOUT2 AC19 AB19 O Clock output at half of device speed • Used for synchronous memory interface CLKMODE0 B15 B12 I CLKMODE1 – A9 I CLKMODE2 PLLV‡ – A14 D13 C11 PLL analog VCC connection for the low-pass filter PLLG‡ D14 C12 I A§ A§ PLLF C13 A11 A§ PLL low-pass filter connection to external components and a bypass capacitor CLOCK/PLL CLKIN Clockk mode Cl d selects l t (Note: (N t CLKMODE1 and d CLKMODE2 selects l t are for f GLS devices d i only) l ) • Selects whether the CPU clock frequency = in ut clock frequency x4 or x1 input PLL analog GND connection for the low-pass filter JTAG EMULATION AD7 Y5 I TDO AE6 AA4 O/Z JTAG test-port mode select (features an internal pullup) ADVANCE INFORMATION TMS JTAG test-port data out TDI AF5 Y4 I JTAG test-port data in (features an internal pullup) TCK AE5 AB2 I JTAG test-port clock TRST AC7 AA3 I JTAG test-port reset (features an internal pulldown) EMU1 AF6 AA5 I/O/Z EMU0 AC8 AB4 I/O/Z RESET K2 J3 I Device reset NMI L2 K2 I Nonmaskable interrupt • Edge-driven (rising edge) EXT_INT7 V4 U2 I External interrupts • Edge-driven (rising edge) O Interrupt acknowledge for all active interrupts serviced by the CPU O Active interrupt identification number • Valid during IACK for all active interrupts (not just external) • Encoding order follows the interrupt-service interru t service fetch fetch-packet acket ordering Emulation pin 1, pullup with a dedicated 20-kΩ resistor¶ Emulation pin 0, pullup with a dedicated 20-kΩ resistor¶ RESET AND INTERRUPTS EXT_INT6 Y2 U3 EXT_INT5 AA1 W1 EXT_INT4 W4 V2 IACK Y1 V1 INUM3 V2 R3 INUM2 U4 T1 INUM1 V3 T2 INUM0 W2 T3 POWER-DOWN STATUS PD AB2 Y2 O Power-down modes 2 or 3 (active if high) † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground ‡ PLLV and PLLG are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins. § A = Analog Signal (PLL Filter) ¶ For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-kΩ resistor. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 11 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE† DESCRIPTION GJL GLS A9 C8 I Expansion bus synchronous host interface clock input O Expansion bus FIFO interface clock output EXPANSION BUS XCLKIN ADVANCE INFORMATION XFCLK B9 A8 XD31 D15 C13 XD30 B16 A13 XD29 A17 C14 XD28 B17 B14 XD27 D16 B15 XD26 A18 C15 XD25 B18 A15 XD24 D17 B16 XD23 C18 C16 XD22 A20 A17 XD21 D18 B17 XD20 C19 C17 XD19 A21 B18 XD18 D19 A19 XD17 C20 C18 XD16 B21 B19 XD15 A22 C19 XD14 D20 B20 XD13 B22 A21 XD12 E25 C21 XD11 F24 D20 XD10 E26 B22 XD9 F25 D21 XD8 G24 E20 XD7 H23 E21 XD6 F26 D22 XD5 G25 F20 XD4 J23 F21 XD3 G26 E22 XD2 H25 G20 XD1 J24 G21 XD0 K23 G22 XCE3 F2 D2 XCE2 E1 B1 XCE1 F3 D3 I/O/Z Ex ansion bus data Expansion • Used for transfer of data,, address,, and control • Also controls initialization of DSP modes and expansion bus at reset via pullup/pulldown resistors i t – XCE[3:0] memory type ty e – XBLAST polarity y – XW/R polarity – Asynchronous A h or synchronous h h hostt operation ti – Arbitration mode (internal or external) – FIFO mode – Little endian/big endian – Boot mode O/Z Expansion bus I/O port memory space enables • Enabled by bits 28, 28 29, 29 and 30 of the word address • Only one asserted during any I/O port ort data access XCE0 E2 C2 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE† DESCRIPTION GJL GLS XBE3/XA5 C7 C5 XBE2/XA4 D8 A4 XBE1/XA3 A6 B5 XBE0/XA2 C8 C6 XOE A7 XRE C9 XWE/XWAIT D10 XCS A10 XAS D9 B6 I/O/Z XCNTL B10 B9 I XW/R D11 B8 I/O/Z Expansion bus host port write/read enable. XW/R polarity selected at reset XRDY A5 C4 I/O/Z Expansion bus host port ready (active low) and I/O port ready (active high) XBLAST B6 B4 I/O/Z Expansion bus host port burst last–polarity selected at reset XBOFF B11 A10 I XHOLD B5 A2 I/O/Z Expansion bus hold request XHOLDA D7 B3 I/O/Z Expansion bus hold acknowledge CE3 AB25 Y21 CE2 AA24 W20 CE1 AB26 AA22 CE0 AA25 W21 BE3 Y24 V20 BE2 W23 V21 BE1 AA26 W22 BE0 Y25 U20 EA21 J25 H20 EA20 J26 H21 EA19 L23 H22 EA18 K25 J20 EA17 L24 J21 EA16 L25 K21 EA15 M23 K20 EA14 M24 K22 EA13 M25 L21 EA12 N23 L20 EXPANSION BUS (CONTINUED) I/O/Z Expansion bus multiplexed byte-enable control/address signals • Act as byte enable for host port operation • Act as address for I/O port operation ort o eration A6 O/Z Expansion bus I/O port output enable C7 O/Z Expansion bus I/O port read enable B7 O/Z Expansion bus I/O port write enable and host port wait signals C9 I Expansion bus host port chip-select input Expansion bus host port address strobe ADVANCE INFORMATION Expansion bus host control. XCNTL selects between expansion bus address or data register Expansion bus back off EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY O/Z Memory space enables • Enabled by bits 24 and 25 of the word address • Only one asserted during any external data access O/Z Byte-enable control • Decoded from the two lowest bits of the internal address • Byte-write enables for most types of memory • C Can b be di directly tl connected t d tto SDRAM read d and d write it mask k signal i l (SDQM) EMIF – ADDRESS O/Z External address (word address) EA11 P24 L22 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 13 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS EA10 P23 M20 EA9 R25 M21 EA8 R24 N22 EA7 R23 N20 EA6 T25 N21 EA5 T24 P21 EA4 U25 P20 EA3 T23 R22 EA2 V26 R21 ED31 AD8 Y6 ED30 AC9 AA6 ED29 AF7 AB6 ED28 AD9 Y7 ED27 AC10 AA7 ED26 AE9 AB8 ED25 AF9 Y8 ED24 AC11 AA8 ED23 AE10 AA9 ED22 AD11 Y9 ED21 AE11 AB10 ED20 AC12 Y10 ED19 AD12 AA10 ED18 AE12 AA11 ED17 AC13 Y11 ED16 AD14 AB12 ED15 AC14 Y12 ED14 AE15 AA12 ED13 AD15 AA13 ED12 AC15 Y13 ED11 AE16 AB13 ED10 AD16 Y14 ED9 AE17 AA14 ED8 AC16 AA15 TYPE† DESCRIPTION EMIF – ADDRESS (CONTINUED) O/Z External address (word address) ADVANCE INFORMATION EMIF – DATA ED7 AF18 Y15 ED6 AE18 AB15 ED5 AC17 AA16 ED4 AD18 Y16 ED3 AF20 AB17 ED2 AC18 AA17 ED1 AD19 Y17 I/O/Z External data ED0 AF21 AA18 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE† DESCRIPTION GJL GLS V24 T21 O/Z Asynchronous memory read enable AOE V25 R20 O/Z Asynchronous memory output enable AWE U23 T22 O/Z Asynchronous memory write enable W25 T20 I Asynchronous memory ready input EMIF – ASYNCHRONOUS MEMORY CONTROL ARE ARDY EMIF – SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL SDA10 AE21 AA19 O/Z SDRAM address 10 (separate for deactivate command) SDCAS/SSADS AE22 AB21 O/Z SDRAM column-address strobe/SBSRAM address strobe SDRAS/SSOE AF22 Y19 O/Z SDRAM row-address strobe/SBSRAM output enable SDWE/SSWE AC20 AA20 O/Z SDRAM write enable/SBSRAM write enable HOLD Y26 V22 I Hold request from the host HOLDA V23 U21 O Hold-request-acknowledge to the host TOUT1 J4 F2 O Timer 1 or general-purpose output TINP1 G2 F3 I Timer 1 or general-purpose input TOUT0 F1 D1 O Timer 0 or general-purpose output TINP0 H4 E2 I Timer 0 or general-purpose input DMAC3 Y3 V3 DMAC2 AA2 W2 DMAC1 AB1 AA1 DMAC0 AA3 W3 CLKS0 M4 K3 I CLKR0 M2 L2 I/O/Z Receive clock CLKX0 M3 K1 I/O/Z Transmit clock DR0 R2 M2 I Receive data DX0 P4 M3 O/Z Transmit data FSR0 N3 M1 I/O/Z Receive frame sync FSX0 N4 L3 I/O/Z Transmit frame sync ADVANCE INFORMATION EMIF – BUS ARBITRATION TIMERS DMA ACTION COMPLETE STATUS O DMA action complete MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) External clock source (as opposed to internal) MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1 G1 E1 I External clock source (as opposed to internal) CLKR1 J3 G2 I/O/Z Receive clock CLKX1 H2 G3 I/O/Z Transmit clock DR1 L4 H1 I Receive data DX1 J1 H2 O/Z Transmit data FSR1 J2 H3 I/O/Z Receive frame sync FSX1 K4 G1 I/O/Z Transmit frame sync † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 15 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO. TYPE† DESCRIPTION GJL GLS R3 N1 I CLKR2 T2 N2 I/O/Z Receive clock CLKX2 R4 N3 I/O/Z Transmit clock DR2 V1 R2 I Receive data DX2 T4 R1 O/Z Transmit data FSR2 U2 P3 I/O/Z Receive frame sync FSX2 T3 P2 I/O/Z Transmit frame sync MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2) CLKS2 External clock source (as opposed to internal) ADVANCE INFORMATION RESERVED FOR TEST RSV0 L3 J2 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV1 G3 E3 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV2 A12 B11 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV3 C15 B13 O Reserved (leave unconnected, do not connect to power or ground) RSV4 D12 C10 O Reserved (leave unconnected, do not connect to power or ground) SUPPLY VOLTAGE PINS DVDD A11 A3 A16 A7 B7 A16 B8 A20 B19 D4 B20 D6 C6 D7 C10 D9 C14 D10 C17 D13 C21 D14 G4 D16 G23 D17 H3 D19 H24 F1 K3 F4 K24 F19 L1 F22 L26 G4 N24 G19 S 3.3-V supply voltage P3 J4 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS T1 J19 TYPE† DESCRIPTION DVDD CVDD T26 K4 U3 K19 U24 L1 W3 M22 W24 N4 Y4 N19 Y23 P4 AD6 P19 AD10 T4 AD13 T19 AD17 U1 AD21 U4 AE7 U19 AE8 U22 AE19 W4 AE20 W6 AF11 W7 AF16 W9 – W10 – W13 – W14 – W16 – W17 – W19 – AB5 – AB9 – AB14 – AB18 A1 E7 A2 E8 A3 E10 A24 E11 A25 E12 A26 E13 B1 E15 B2 E16 B3 F7 B24 F8 B25 F9 B26 F11 S 3.3-V supply voltage S 1.8-V supply voltage ADVANCE INFORMATION SUPPLY VOLTAGE PINS (CONTINUED) C1 F12 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 17 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS C2 F14 C3 F15 C4 F16 C23 G5 TYPE† DESCRIPTION ADVANCE INFORMATION SUPPLY VOLTAGE PINS (CONTINUED) CVDD C24 G6 C25 G17 C26 G18 D3 H5 D4 H6 D5 H17 D22 H18 D23 J6 D24 J17 E4 K5 E23 K18 AB4 L5 AB23 L6 AC3 L17 AC4 L18 AC5 M5 AC22 M6 AC23 M17 AC24 M18 AD1 N5 AD2 N18 AD3 P6 AD4 P17 AD23 R5 AD24 R6 AD25 R17 AD26 R18 AE1 T5 AE2 T6 AE3 T17 AE24 T18 AE25 U7 AE26 U8 AF1 U9 AF2 U11 AF3 U12 AF24 U14 S 1 8 V supply voltage 1.8-V AF25 U15 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS AF26 U16 – V7 – V8 – V10 TYPE† DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) CVDD – V11 – V12 – V13 – V15 – V16 A4 A1 A8 A5 A13 A12 A14 A18 A15 A22 S 1.8-V supply voltage VSS A19 B2 A23 B21 B4 C1 B12 C3 B13 C20 B14 C22 B23 D5 C5 D8 C11 D11 C16 D12 C22 D15 D1 D18 D2 E4 D6 E5 D21 E6 D25 E9 D26 E14 E3 E17 E24 E18 F4 E19 F23 F5 H1 F6 GND ADVANCE INFORMATION GROUND PINS Ground pins H26 F10 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 19 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS K1 F13 K26 F17 M1 F18 TYPE† DESCRIPTION ADVANCE INFORMATION GROUND PINS (CONTINUED) VSS M26 H4 N1 H19 N2 J1 N25 J5 N26 J18 P1 J22 P2 K6 P25 K17 P26 L4 R1 L19 R26 M4 U1 M19 U26 N6 W1 N17 W26 P1 AA4 P5 AA23 P18 AB3 P22 AB24 R4 AC1 R19 AC2 U5 AC6 U6 AC21 U10 AC25 U13 AC26 U17 AD5 U18 AD22 V4 AE4 V5 AE13 V6 AE14 V9 AE23 V14 AF4 V17 GND Ground pins AF8 V18 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) SIGNAL NAME PIN NO. GJL GLS AF10 V19 AF12 W5 AF13 W8 TYPE† DESCRIPTION GROUND PINS (CONTINUED) W11 AF15 W12 AF17 W15 AF19 W18 AF23 Y1 – Y3 – Y20 – Y22 – AA2 – AA21 – AB1 – AB3 – AB7 – AB11 – AB16 – AB20 GND Ground pins ADVANCE INFORMATION VSS AF14 – AB22 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 21 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 development support Texas Instruments offers an extensive line of development tools for the ’C6200 generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of ’C6200-based applications: Software Development Tools: Assembly optimizer Assembler/Linker Simulator Optimizing ANSI C compiler Application algorithms C/Assembly debugger and code profiler ADVANCE INFORMATION Hardware Development Tools: Extended development system (XDS) emulator (supports ’C6200 multiprocessor system debug) EVM (Evaluation Module) The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320 family member devices, including documentation. See this document for further information on TMS320 documentation or any TMS320 support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320-related products from other companies in the industry. To receive TMS320 literature, contact the Literature Response Center at 800/477-8924. See Table 2 for a complete listing of development-support tools for the ’C6200. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Table 2. TMS320C6xx Development-Support Tools DEVELOPMENT TOOL PLATFORM PART NUMBER Software C Compiler/Assembler/Linker/Assembly Optimizer Win32 TMDX3246855-07 C Compiler/Assembler/Linker/Assembly Optimizer SPARC Solaris TMDX3246555-07 Win32 TMDS3246851-07 SPARC Solaris TMDS3246551-07 Win32, Windows NT TMDX324016X-07 Simulator Simulator XDS510 Debugger/Emulation Software Hardware XDS510 Emulator† PC XDS510WS Emulator‡ SCSI TMDS00510 TMDS00510WS Software/Hardware EVM Evaluation Kit PC/Win95/Windows NT TMDX3260A6201 EVM Evaluation Kit (including TMDX3246855–07) PC/Win95/Windows NT TMDX326006201 † Includes XDS510 board and JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software is not included. ‡ Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable. XDS, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated. Win32 and Windows NT are trademarks of Microsoft Corporation. SPARC is a trademark of SPARC International, Inc. Solaris is a trademark of Sun Microsystems, Inc. 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). TMX Experimental device that is not necessarily representative of the final device’s electrical specifications TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GJL), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -250 is 250 MHz). Figure 5 provides a legend for reading the complete device name for any TMS320 family member. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 23 ADVANCE INFORMATION Device development evolutionary flow: TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 device and development-support tool nomenclature (continued) TMS 320 PREFIX TMX = TMP = TMS = SMJ = SM = C 6202 GJL (A) –250 DEVICE SPEED RANGE –100 MHz –150 MHz –167 MHz –200 MHz –233 MHz –250 MHz –300 MHz Experimental device Prototype device Qualified device MIL-STD-883C High Rel (non-883C) DEVICE FAMILY 320 = TMS320 family TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C) Blank = 0°C to 90°C, commercial temperature A = –40°C to 105°C, extended temperature PACKAGE TYPE† N = Plastic DIP J = Ceramic DIP JD = Ceramic DIP side-brazed GB = Ceramic PGA FZ = Ceramic CC FN = Plastic leaded CC FD = Ceramic leadless CC PJ = 100-pin plastic EIAJ QFP PQ = 132-pin plastic bumpered QFP PZ = 100-pin plastic TQFP PBK = 128-pin plastic TQFP PGE = 144-pin plastic TQFP GFN = 256-pin plastic BGA GGU = 144-pin plastic BGA GGP = 352-pin plastic BGA GJC = 352-pin plastic BGA GJL = 352-pin plastic BGA GLS = 384-pin plastic BGA ADVANCE INFORMATION TECHNOLOGY C = CMOS E = CMOS EPROM F = CMOS Flash EEPROM DEVICE ’1x DSP: 10 14 15 16 17 ’2x DSP: 25 26 ’2xx DSP: 203 204 206 209 240 ’3x DSP: 30 31 32 ’4x DSP: 40 44 ’5x DSP: 50 51 52 53 56 57 541 542 543 545 546 548 ’54x DSP: † DIP PGA CC QFP TQFP BGA = = = = = = ’6x DSP: Dual-In-Line Package Pin Grid Array Chip Carrier Quad Flat Package Thin Quad Flat Package Ball Grid Array 6201 6201B 6202 6203 6211 6701 6711 Figure 5. TMS320 Device Nomenclature (Including TMS320C6202) 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 documentation support Extensive documentation supports all TMS320 family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices; technical briefs; development-support tools; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the ’C6x devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the ’C6000 CPU architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface (HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and power-down modes. This guide also includes information on internal data and program memories. The TMS320C6x C Source Debugger User’s Guide (literature number SPRU188) describes how to invoke the ’C6x simulator and emulator versions of the C source debugger interface and discusses various aspects of the debugger, including: command entry, code execution, data management, breakpoints, profiling, and analysis. The TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes the contents of the ’C6x peripheral support library of functions and macros. It lists functions and macros both by header file and alphabetically, provides a complete description of each, and gives code examples to show how they are used. TMS320C6000 Assembly Language Tools User’s Guide (literature number SPRU186) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the ’C6000 generation of devices. The TMS320C6x Evaluation Module Reference Guide (literature number SPRU269) provides instructions for installing and operating the ’C6x evaluation module. It also includes support software documentation, application programming interfaces, and technical reference material. TMS320C62x Multichannel Evaluation Module User’s Guide (literature number SPRU285) provides instructions for installing and operating the ’C62x multichannel evaluation module. It also includes support software documentation, application programming interfaces, and technical reference material. TMS320C62x Multichannel Evaluation Module Technical Reference (SPRU308) provides provides technical reference information for the ’C62x multichannel evaluation module (McEVM). It includes support software documentation, application programming interface references, and hardware descriptions for the ’C62x McEVM. TMS320C6000 DSP/BIOS User’s Guide (literature number SPRU303) describes how to use DSP/BIOS tools and APIs to analyze embedded real-time DSP applications. Code Composer User’s Guide (literature number SPRU296) explains how to use the Code Composer development environment to build and debug embedded real-time DSP applications. Code Composer Studio Tutorial (literature number SPRU301) introduces the Code Composer Studio integrated development environment and software tools. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 25 ADVANCE INFORMATION The TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and assembly code for ’C6x devices and includes application program examples. TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 documentation support (continued) The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x devices, associated development tools, and third-party support. A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides access to information pertaining to the TMS320 family, including documentation, source code, and object code for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323. ADVANCE INFORMATION Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform resource locator (URL). 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 clock PLL All of the internal ’C6202 clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock. To use the PLL to generate the CPU clock, the filter circuit shown in Figure 6 must be properly designed. To configure the ’C6202 PLL clock for proper operation, see Figure 6 and Table 3. To minimize the clock jitter, a single clean power supply should power both the ’C6202 device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. See the input and output clocks section for input clock timing requirements. 3 OUT ’320C6202 EMI Filter PLLV GND 10 µF 0.1 µF (Bypass) PLLG C1 C2 CLKIN CLKOUT1 ÷2 CLKOUT2 CLKMODE0 2 ÷1 CLKMODE1 CPU Clock CLKMODE2 1 IN PLLF R1 0 0 0 – MULT × 1 f(CPU Clock) = f(CLKIN) 0 0 1 – MULT × 4 f(CPU Clock) = f(CLKIN) × 4 All Other Modes – Reserved NOTES: A. The ’C6202 PLL can generate CPU clock frequencies in the range of 130 MHz to 250 MHz. For frequencies below 130 MHz, the PLL should be configured to operate in bypass mode. B. For the ’C6202, values for C1, C2, and R1 are fixed and apply to all valid frequency ranges of CLKIN and CPU clock frequency. C. For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal has to be connected to a clean 3.3-V supply and the PLLG and PLLF terminals should be tied together. D. The 3.3-V supply for the EMI filter (and PLLV) must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. E. EMI filter manufacturer TDK part number ACF451832-153-T F. CLKMODE2 and CLKMODE1 exist only on the GLS device. There are no equivalent connections on the GJL device. G. The reserved PLL clock modes (GLS devices only) may or may not be supported on future devices as additional PLL multiply factors. For future flexibility, a board can be designed so that these inputs are configurable (either through jumpers, switches, or 0-Ω resistors). Figure 6. PLL Block Diagram Table 3. TMS320C6202 PLL Component Selection Table† CLKMODE CLKIN RANGE (MHz) CPU CLOCK FREQUENCY (CLKOUT1) RANGE (MHz) CLKOUT2 RANGE (MHz) R1 (Ω) C1 (nF) C2 (pF) TYPICAL LOCK TIME (µs) x4 32.5–62.5 130–250 65–125 60.4 27 560 75 † Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs. power-supply sequencing The 1.8-V supply powers the core and the 3.3-V supply powers the I/O buffers. The core supply should be powered up first, or at the same time as the I/O buffers supply. This is to ensure that the I/O buffers have valid inputs from the core before the output buffers are powered up, thus preventing bus contention with other chips on the board. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 27 ADVANCE INFORMATION 3.3 V TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 absolute maximum ratings over operating case temperature range (unless otherwise noted)† Supply voltage range, CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 2.3 V Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55_C to 150_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions ADVANCE INFORMATION MIN NOM MAX UNIT CVDD Supply voltage 1.71 1.8 1.89 V DVDD Supply voltage 3.14 3.30 3.46 V VSS VIH Supply ground 0 0 0 V VIL IOH Low-level input voltage 0.8 V High-level output current –8 mA IOL TC Low-level output current 8 mA 90 _C High-level input voltage 2.0 Operating case temperature V 0 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER VOH VOL II IOZ TEST CONDITIONS High-level output voltage DVDD = MIN, Low-level output voltage Input current‡ DVDD = MIN, IOH = MAX IOL = MAX MIN TYP 2.4 UNIT V VI = VSS to DVDD VO = DVDD or 0 V Off-state output current MAX 0.6 V ±10 uA ±10 uA IDD2V IDD2V Supply current, CPU + CPU memory access§ Supply current, peripherals¶ CVDD = NOM, CPU clock = 200 MHz TBD mA CVDD = NOM, CPU clock = 200 MHz TBD mA IDD3V Ci Supply current, I/O pins# DVDD = NOM, CPU clock = 200 MHz TBD mA Input capacitance Co Output capacitance ‡ TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown. § Measured with average CPU activity: 50% of time: 8 instructions per cycle, 32-bit DMEM access per cycle 50% of time: 2 instructions per cycle, 16-bit DMEM access per cycle ¶ Measured with average peripheral activity: 50% of time: Timers at max rate McBSPs at E1 rate DMA burst transfer between DMEM and SDRAM 50% of time: Timers at max rate McBSPs at E1 rate DMA servicing McBSPs # Measured with average I/O activity (30-pF load, SDCLK on): 25% of time: Reads from external SDRAM 25% of time: Writes to external SDRAM 50% of time: No activity 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 10 pF 10 pF TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics 50 Ω Vref Output Under Test CT = 30 pF† IOH † Typical distributed load circuit capacitance ADVANCE INFORMATION signal transition levels All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels. Vref = 1.5 V Figure 7. Input and Output Voltage Reference Levels for ac Timing Measurements POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 29 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN† (see Figure 8) ’C6202-200 NO. 1 tc(CLKIN) Cycle time, CLKIN 2 tw(CLKINH) 3 4 ’C6202-233 ’C6202-250 CLKMODE = x4 CLKMODE = x1 CLKMODE = x4 CLKMODE = x1 CLKMODE = x4 CLKMODE = x1 MIN MIN MIN MIN MIN MIN MAX MAX MAX MAX MAX UNIT MAX 20 5 17.2 4.3 16 4 ns Pulse duration, CLKIN high 8 2.25 6.9 1.9 6.4 1.8 ns tw(CLKINL) Pulse duration, CLKIN low 8 2.25 6.9 1.9 6.4 1.8 ns tt(CLKIN) Transition time, CLKIN 5 0.6 5 0.6 5 0.6 ns ADVANCE INFORMATION † The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. 1 4 2 CLKIN 3 4 Figure 8. CLKIN Timings timing requirements for XCLKIN†‡ (see Figure 9) ’C6202-200 ’C6202-233 ’C6202-250 NO. MIN 1 2 3 4 tc(XCLKIN) tw(XCLKINH) Cycle time, XCLKIN tw(XCLKINL) tt(XCLKIN) MAX 4P ns Pulse duration, XCLKIN high 1.8P ns Pulse duration, XCLKIN low 1.8P Transition time, XCLKIN ns 0.6 † The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. ‡ P = 1/CPU clock frequency in nanoseconds (ns). 1 4 2 XCLKIN 3 4 Figure 9. XCLKIN Timings 30 UNIT POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ns TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for CLKOUT1†‡ (see Figure 10) PARAMETER CLKMODE = x4 MIN 1 2 3 tc(CKO1) tw(CKO1H) Cycle time, CLKOUT1 tw(CKO1L) tt(CKO1) UNIT CLKMODE = x1 MAX MIN MAX P – 0.7 P + 0.7 P – 0.7 P + 0.7 ns Pulse duration, CLKOUT1 high (P/2) – 0.5 (P/2 ) + 0.5 PH – 0.5 PH + 0.5 ns Pulse duration, CLKOUT1 low (P/2) – 0.5 (P/2 ) + 0.5 PL – 0.5 PL + 0.5 ns 0.6 ns 4 Transition time, CLKOUT1 † PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. ‡ P = 1/CPU clock frequency in nanoseconds (ns). 0.6 1 ADVANCE INFORMATION NO. ’C6202-200 ’C6202-233 ’C6202-250 4 2 CLKOUT1 3 4 Figure 10. CLKOUT1 Timings switching characteristics for CLKOUT2‡ (see Figure 11) NO. 1 2 3 4 ’C6202-200 ’C6202-233 ’C6202-250 PARAMETER UNIT MIN MAX tc(CKO2) tw(CKO2H) Cycle time, CLKOUT2 2P – 0.7 2P + 0.7 ns Pulse duration, CLKOUT2 high P – 0.7 P + 0.7 ns tw(CKO2L) tt(CKO2) Pulse duration, CLKOUT2 low P – 0.7 P + 0.7 ns 0.6 ns Transition time, CLKOUT2 ‡ P = 1/CPU clock frequency in nanoseconds (ns). 1 4 2 CLKOUT2 3 4 Figure 11. CLKOUT2 Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 31 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for XFCLK†‡ (see Figure 12) NO. ’C6202-200 ’C6202-233 ’C6202-250 PARAMETER MIN 1 2 3 4 tc(XFCK) tw(XFCKH) Cycle time, XFCLK tw(XFCKL) tt(XFCK) MAX D * P – 0.7 D * P + 0.7 ns Pulse duration, XFCLK high (D/2) * P – 0.7 (D/2) * P + 0.7 ns Pulse duration, XFCLK low (D/2) * P – 0.7 (D/2) * P + 0.7 ns 0.6 ns Transition time, XFCLK † P = 1/CPU clock frequency in ns. ‡ D = 8, 6, 4, or 2; FIFO clock divide ratio, user-programmable 1 4 ADVANCE INFORMATION 2 XFCLK 3 4 Figure 12. XFCLK Timings 32 UNIT POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles† (see Figure 13 – Figure 14) ’C6202-200 ’C6202-233 ’C6202-250 NO. MIN 6 7 10 11 tsu(EDV-CKO1H) th(CKO1H-EDV) Setup time, read EDx valid before CLKOUT1 high tsu(ARDY-CKO1H) th(CKO1H-ARDY) UNIT MAX 4.0 ns Hold time, read EDx valid after CLKOUT1 high 0 ns Setup time, ARDY valid before CLKOUT1 high 4.0 ns Hold time, ARDY valid after CLKOUT1 high 0 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input. NO. 1 2 3 4 5 8 9 12 13 PARAMETER ’C6202-200 ’C6202-233 ’C6202-250 UNIT MIN MAX td(CKO1H-CEV) td(CKO1H-BEV) Delay time, CLKOUT1 high to CEx valid 0 4.0 ns Delay time, CLKOUT1 high to BEx valid 0 4.0 ns td(CKO1H-BEIV) td(CKO1H-EAV) Delay time, CLKOUT1 high to BEx invalid 0 4.0 ns Delay time, CLKOUT1 high to EAx valid 0 4.0 ns td(CKO1H-EAIV) td(CKO1H-AOEV) Delay time, CLKOUT1 high to EAx invalid 0 4.0 ns Delay time, CLKOUT1 high to AOE valid 0 4.0 ns td(CKO1H-AREV) td(CKO1H-EDV) Delay time, CLKOUT1 high to ARE valid 0 4.0 ns 4.0 ns td(CKO1H-EDIV) td(CKO1H-AWEV) Delay time, CLKOUT1 high to EDx invalid Delay time, CLKOUT1 high to EDx valid 14 Delay time, CLKOUT1 high to AWE valid ‡ The minimum delay is also the minimum output hold after CLKOUT1 high. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 0 0 ADVANCE INFORMATION switching characteristics for asynchronous memory cycles‡ (see Figure 13 – Figure 14) ns 4.0 ns 33 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Not ready = 2 Strobe = 5 HOLD = 1 CLKOUT1 1 1 2 3 4 5 CEx BE[3:0] EA[21:2] 7 6 ED[31:0] 8 8 ADVANCE INFORMATION AOE 9 9 ARE AWE 11 11 10 10 ARDY Figure 13. Asynchronous Memory Read Timing Setup = 2 Not ready = 2 Strobe = 5 HOLD = 1 CLKOUT1 1 1 2 3 4 5 CEx BE[3:0] EA[21:2] 12 13 ED[31:0] AOE ARE 14 14 AWE 11 10 11 10 ARDY Figure 14. Asynchronous Memory Write Timing 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (see Figure 15) NO NO. ’C6202-200 ’C6202-233 ’C6202-250 MIN MIN MIN MAX MAX MAX UNIT 7 tsu(EDV-CKO2H) Setup time, read EDx valid before CLKOUT2 high 2.5 2.1 2 ns 8 th(CKO2H-EDV) Hold time, read EDx valid after CLKOUT2 high 1.5 1.5 1.5 ns switching characteristics for synchronous-burst SRAM cycles†‡ (see Figure 15 and Figure 16) PARAMETER 1 tosu(CEV-CKO2H) Output setup time, CEx valid before CLKOUT2 high 2 toh(CKO2H-CEV) Output hold time, CEx valid after CLKOUT2 high 3 tosu(BEV-CKO2H) 4 ’C6202-200 ’C6202-233 ’C6202-250 MIN MIN MIN MAX MAX MAX UNIT 2P – 5.5 2P – 4.4 2P – 3.8 ns 1 1 1 ns Output setup time, BEx valid before CLKOUT2 high 2P – 5.5 2P – 4.4 2P – 3.8 ns toh(CKO2H-BEIV) Output hold time, BEx invalid after CLKOUT2 high 1 1 1 ns 5 tosu(EAV-CKO2H) Output setup time, EAx valid before CLKOUT2 high 2P – 5.5 2P – 4.4 2P – 3.8 ns 6 toh(CKO2H-EAIV) Output hold time, EAx invalid after CLKOUT2 high 1 1 1 ns 9 tosu(ADSV-CKO2H) Output setup time, SDCAS/SSADS valid before CLKOUT2 high 2P – 5.5 2P – 4.4 2P – 3.8 ns 10 toh(CKO2H-ADSV) Output hold time, SDCAS/SSADS valid after CLKOUT2 high 1 1 1 ns 11 tosu(OEV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2 high 2P – 5.5 2P – 4.4 2P – 3.8 ns 12 toh(CKO2H-OEV) Output hold time, SDRAS/SSOE valid after CLKOUT2 high 1 1 1 ns 13 tosu(EDV-CKO2H) Output setup time, EDx valid before CLKOUT2 high§ 2P – 5.5 2P – 4.4 2P – 3.8 ns 14 toh(CKO2H-EDIV) Output hold time, EDx invalid after CLKOUT2 high 1 1 1 ns 15 tosu(WEV-CKO2H) Output setup time, SDWE/SSWE valid before CLKOUT2 high 2P – 5.5 2P – 4.4 2P – 3.8 ns 16 toh(CKO2H-WEV) Output hold time, SDWE/SSWE valid after CLKOUT2 high 1 1 1 ns ADVANCE INFORMATION NO NO. † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ‡ SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. § For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 35 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) CLKOUT2 1 2 CEx BE[3:0] 3 BE1 BE2 BE3 BE4 4 EA[21:2] 5 A1 A2 A3 A4 6 7 Q1 ED[31:0] 8 Q2 Q3 9 Q4 10 SDCAS/SSADS† ADVANCE INFORMATION 11 12 SDRAS/SSOE† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. Figure 15. SBSRAM Read Timing CLKOUT2 1 2 CEx BE[3:0] 3 BE1 BE2 BE3 BE4 4 EA[21:2] 5 A1 A2 A3 A4 Q1 Q2 Q3 Q4 6 13 14 ED[31:0] 9 10 15 16 SDCAS/SSADS† SDRAS/SSOE† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. Figure 16. SBSRAM Write Timing 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 17) NO NO. 7 8 tsu(EDV-CKO2H) th(CKO2H-EDV) ’C6202-200 ’C6202-233 ’C6202-250 MIN MIN MIN MAX MAX MAX UNIT Setup time, read EDx valid before CLKOUT2 high 1 1 0.5 ns Hold time, read EDx valid after CLKOUT2 high 3 3 3 ns switching characteristics for synchronous DRAM cycles†‡ (see Figure 17–Figure 22) PARAMETER 1 tosu(CEV-CKO2H) Output setup time, CEx valid before CLKOUT2 high 2 toh(CKO2H-CEV) Output hold time, CEx valid after CLKOUT2 high 3 tosu(BEV-CKO2H) Output setup time, BEx valid before CLKOUT2 high 4 toh(CKO2H-BEIV) Output hold time, BEx invalid after CLKOUT2 high 5 tosu(EAV-CKO2H) Output setup time, EAx valid before CLKOUT2 high 6 toh(CKO2H-EAIV) Output hold time, EAx invalid after CLKOUT2 high 9 tosu(CASV-CKO2H) Output setup time, SDCAS/SSADS valid before CLKOUT2 high 10 toh(CKO2H-CASV) Output hold time, SDCAS/SSADS valid after CLKOUT2 high 11 tosu(EDV-CKO2H) Output setup time, EDx valid before CLKOUT2 high§ 12 toh(CKO2H-EDIV) Output hold time, EDx invalid after CLKOUT2 high 13 tosu(WEV-CKO2H) Output setup time, SDWE/SSWE valid before CLKOUT2 high 14 toh(CKO2H-WEV) 15 ’C6202-200 ’C6202-233 ’C6202-250 MIN MIN MIN MAX MAX MAX UNIT 2P – 6 2P – 4.6 2P – 4 ns 1.5 1.5 1.5 ns 2P – 6 2P – 4.6 2P – 4 ns 1.5 1.5 1.5 ns 2P – 6 2P – 4.6 2P – 4 ns 1.5 1.5 1.5 ns 2P – 6 2P – 4.6 2P – 4 ns 1.5 1.5 1.5 ns 2P – 6 2P – 4.6 2P – 4 ns 1.5 1.5 1.5 ns 2P – 6 2P – 4.6 2P – 4 ns Output hold time, SDWE/SSWE valid after CLKOUT2 high 1.5 1.5 1.5 ns tosu(SDA10V-CKO2H) Output setup time, SDA10 valid before CLKOUT2 high 2P – 6 2P – 4.6 2P – 4 ns 16 toh(CKO2H-SDA10IV) Output hold time, SDA10 invalid after CLKOUT2 high 1.5 1.5 1.5 ns 17 tosu(RASV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2 high 2P – 6 2P – 4.6 2P – 4 ns 18 toh(CKO2H-RASV) Output hold time, SDRAS/SSOE valid after CLKOUT2 high 1.5 1.5 1.5 ns ADVANCE INFORMATION NO NO. † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ‡ SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. § For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 37 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING (CONTINUED) READ READ READ CLKOUT2 1 2 CEx 3 BE[3:0] 5 EA[15:2] 4 BE1 BE2 CA2 CA3 BE3 6 CA1 7 8 D1 ED[31:0] 15 16 9 10 D2 D3 ADVANCE INFORMATION SDA10 SDRAS/SSOE† SDCAS/SSADS† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 17. Three SDRAM READ Commands WRITE WRITE WRITE CLKOUT2 1 2 CEx 3 BE[3:0] 4 BE1 5 EA[15:2] BE3 CA2 CA3 D2 D3 6 CA1 11 D1 ED[31:0] BE2 12 15 16 9 10 13 14 SDA10 SDRAS/SSOE† SDCAS/SSADS† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 18. Three SDRAM WRT Commands 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING (CONTINUED) ACTV CLKOUT2 1 2 CEx BE[3:0] 5 Bank Activate/Row Address EA[15:2] ED[31:0] 15 Row Address SDA10 17 ADVANCE INFORMATION 18 SDRAS/SSOE† SDCAS/SSADS† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 19. SDRAM ACTV Command DCAB CLKOUT2 1 2 15 16 17 18 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS/SSOE† SDCAS/SSADS† 13 14 SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 20. SDRAM DCAB Command POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 39 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING (CONTINUED) REFR CLKOUT2 1 2 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 17 18 SDRAS/SSOE† ADVANCE INFORMATION 9 10 SDCAS/SSADS† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 21. SDRAM REFR Command MRS CLKOUT2 1 2 5 6 CEx BE[3:0] EA[15:2] MRS Value ED[31:0] SDA10 17 18 9 10 13 14 SDRAS/SSOE† SDCAS/SSADS† SDWE/SSWE† † SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses. Figure 22. SDRAM MRS Command 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles† (see Figure 23) ’C6202-200 ’C6202-233 ’C6202-250 NO. MIN 3 toh(HOLDAL-HOLDL)Hold time, HOLD low after HOLDA low † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. UNIT MAX P ns switching characteristics for the HOLD/HOLDA cycles†‡ (see Figure 23) PARAMETER MIN 1 2 4 tR(HOLDL-EMHZ) td(EMHZ-HOLDAL) Response time, HOLD low to EMIF Bus high impedance tR(HOLDH-EMLZ) td(EMLZ-HOLDAH) Response time, HOLD high to EMIF Bus low impedance Delay time, EMIF Bus high impedance to HOLDA low UNIT 4P MAX § ns 0 2P ns 3P 7P ns 5 Delay time, EMIF Bus low impedance to HOLDA high 0 2P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ‡ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10. § All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. External Requestor Owns Bus DSP Owns Bus DSP Owns Bus 3 HOLD 2 5 HOLDA EMIF Bus† 1 4 C6202 C6202 † EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10. Figure 23. HOLD/HOLDA Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 41 ADVANCE INFORMATION NO. ’C6202-200 ’C6202-233 ’C6202-250 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 RESET TIMING timing requirements for reset (see Figure 24) ’C6202-200 ’C6202-233 ’C6202-250 NO. MIN 1 tw(RST) Width of the RESET pulse (PLL stable)† ADVANCE INFORMATION Width of the RESET pulse (PLL needs to sync up)‡ UNIT MAX CLKOUT1 cycles 10 µs 250 11 tsu(XD) Setup time, XD configuration bits valid before RESET high§ 5 CLKOUT1 cycles 12 th(XD) Hold time, XD configuration bits valid after RESET high§ 5 CLKOUT1 cycles † This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable. ‡ This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. § XD[31:0] are the boot configuration pins during device reset. switching characteristics during reset¶ (see Figure 24) NO. PARAMETER ’C6202-200 ’C6202-233 ’C6202-250 MIN MAX CLKOUT1 cycles 2 tR(RST) Response time to change of value in RESET signal 3 td(CKO1H-CKO2IV) td(CKO1H-CKO2V) Delay time, CLKOUT1 high to CLKOUT2 invalid –1 10 ns Delay time, CLKOUT1 high to CLKOUT2 valid –1 10 ns td(CKO1H-XFCKIV) td(CKO1H-XFCKV) Delay time, CLKOUT1 high to high group invalid –1 10 ns Delay time, CLKOUT1 high to high group valid –1 10 ns td(CKO1H-LOWIV) td(CKO1H-LOWV) Delay time, CLKOUT1 high to low group invalid –1 10 ns Delay time, CLKOUT1 high to low group valid –1 10 ns td(CKO1H-ZHZ) td(CKO1H-ZV) Delay time, CLKOUT1 high to Z group high impedance –1 10 ns Delay time, CLKOUT1 high to Z group valid –1 10 ns 4 5 6 7 8 9 10 ¶ High group consists of: Low group consists of: Z group consists of: 42 UNIT 2 XFCLK IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1 EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1, FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD, and XHOLDA POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 RESET TIMING (CONTINUED) CLKOUT1 1 2 2 RESET 3 4 5 6 7 8 9 10 CLKOUT2 HIGH GROUP† LOW GROUP† 11 12 XD[31:0]‡ † High group consists of: Low group consists of: Z group consists of: XFCLK IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1, FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD, and XHOLDA. ‡ XD[31:0] are the boot configuration pins during device reset. Figure 24. Reset Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 43 ADVANCE INFORMATION Z GROUP† TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXTERNAL INTERRUPT TIMING timing requirements for interrupt response cycles† (see Figure 25) ’C6202-200 ’C6202-233 ’C6202-250 NO. MIN 2 3 tw(ILOW) tw(IHIGH) UNIT MAX Width of the interrupt pulse low 2P ns Width of the interrupt pulse high 2P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. switching characteristics during interrupt response cycles† (see Figure 25) NO. ’C6202-200 ’C6202-233 ’C6202-250 PARAMETER ADVANCE INFORMATION MIN 1 4 5 6 UNIT MAX tR(EINTH – IACKH) td(CKO2L-IACKV) Response time, EXT_INTx high to IACK high Delay time, CLKOUT2 low to IACK valid 9P 0 10 ns ns td(CKO2L-INUMV) td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx valid 0 10 ns Delay time, CLKOUT2 low to INUMx invalid 0 10 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. 1 CLKOUT2 2 3 EXT_INTx, NMI Intr Flag 4 4 IACK 6 5 Interrupt Number INUMx Figure 25. Interrupt Timing 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS FIFO TIMING timing requirements for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28) NO. 5 6 MIN tsu(XDV-XFCKH) th(XFCKH-XDV) Setup time, read XDx valid before XFCLK high Hold time, read XDx valid after XFCLK high MAX UNIT 2.5 ns 2 ns switching characteristics for synchronous FIFO interface (see Figure 26, Figure 27, and Figure 28) 1 2 3 4 7 8 PARAMETER MIN MAX UNIT td(XFCKH-XCEV) td(XFCKH-XAV) Delay time, XFCLK high to XCEx valid 1.5 5.2 ns Delay time, XFCLK high to XBE[3:0]/XA[5:2] valid† 1.5 5.2 ns td(XFCKH-XOEV) td(XFCKH-XREV) Delay time, XFCLK high to XOE valid 1.5 5.2 ns Delay time, XFCLK high to XRE valid 1.5 5.2 ns td(XFCKH-XWEV) td(XFCKH-XDV) Delay time, XFCLK high to XWE/XWAIT‡ valid 1.5 5.2 ns 5.2 ns Delay time, XFCLK high to XDx valid 9 td(XFCKH-XDIV) Delay time, XFCLK high to XDx invalid † XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses. ‡ XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses. 1.5 ADVANCE INFORMATION NO. ns XFCLK 1 1 XCE3† 2 XBE[3:0]/XA[5:2]‡ 2 XA1 XA2 XA3 XA4 3 3 XOE 4 4 XRE XWE/XWAIT§ 6 5 XD[31:0] D1 D2 D3 D4 † FIFO read (glueless) mode only available in XCE3. ‡ XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses. § XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses. Figure 26. FIFO Read Timing (Glueless Read Mode) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 45 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED) XFCLK 1 1 XCEx 2 XBE[3:0]/XA[5:2]† 2 XA1 XA2 XA3 XA4 3 3 XOE 4 4 XRE XWE/XWAIT‡ 6 5 ADVANCE INFORMATION XD[31:0] D1 D2 D3 D4 † XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses. ‡ XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses. Figure 27. FIFO Read Timing XFCLK 1 1 XCEx 2 XBE[3:0]/XA[5:2]† 2 XA1 XA2 XA3 XA4 XOE XRE 7 7 XWE/XWAIT‡ 9 8 XD[31:0] D1 D2 † XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses. ‡ XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses. Figure 28. FIFO Write Timing 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 D3 D4 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING timing requirements for asynchronous peripheral cycles† (see Figure 29–Figure 30) ’C6202-200 ’C6202-233 ’C6202-250 NO. MIN 4 5 8 9 tsu(XDV-CKO1H) th(CKO1H-XDV) Setup time, read XDx valid before CLKOUT1 high tsu(XRY-CKO1H) th(CKO1H-XRY) UNIT MAX 4.0 ns Hold time, read XDx valid after CLKOUT1 high 0 ns Setup time, XRDY valid before CLKOUT1 high 4.0 ns Hold time, XRDY valid after CLKOUT1 high 0 ns † To ensure data setup time, simply program the strobe width wide enough. XRDY is internally synchronized. If XRDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, XRDY can be an asynchronous input. NO. 1 2 3 6 7 10 11 PARAMETER ’C6202-200 ’C6202-233 ’C6202-250 UNIT MIN MAX td(CKO1H-XCEV) td(CKO1H-XAV) Delay time, CLKOUT1 high to XCEx valid 0 4.0 ns Delay time, CLKOUT1 high to XBE[3:0]/XA[5:2] valid 0 4.0 ns td(CKO1H-XAIV) td(CKO1H-XOEV) Delay time, CLKOUT1 high to XBE[3:0]/XA[5:2] invalid 0 4.0 ns Delay time, CLKOUT1 high to XOE valid 0 4.0 ns td(CKO1H-XREV) td(CKO1H-XDV) Delay time, CLKOUT1 high to XRE valid 0 4.0 ns 4.0 ns td(CKO1H-XDIV) td(CKO1H-XWEV) Delay time, CLKOUT1 high to XDx invalid Delay time, CLKOUT1 high to XDx valid 12 Delay time, CLKOUT1 high to XWE/XWAIT valid ‡ The minimum delay is also the minimum output hold after CLKOUT1 high. § XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during asynchronous peripheral accesses. ¶ XWE/XWAIT operates as the write enable signal XWE during asynchronous peripheral accesses. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 0 0 ADVANCE INFORMATION switching characteristics for asynchronous peripheral cycles‡§¶ (see Figure 29–Figure 30) ns 4.0 ns 47 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED) Setup = 2 Not ready = 2 Strobe = 5 HOLD = 2 CLKOUT1 1 1 2 3 XCEx XBE[3:0]/XA[5:2]† 5 4 XD[31:0] 6 6 XOE ADVANCE INFORMATION 7 7 XRE XWE/XWAIT‡ 9 9 8 8 XRDY§ † XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during asynchronous peripheral accesses. ‡ XWE/XWAIT operates as the write enable signal XWE during asynchronous peripheral accesses. § XRDY operates as active-high ready input during asynchronous peripheral accesses. Figure 29. Expansion Bus Asynchronous Peripheral Read Timing Setup = 2 Not ready = 2 Strobe = 5 HOLD = 2 CLKOUT1 1 1 2 3 XCEx XBE[3:0]/XA[5:2]† 10 11 XD[31:0] XOE XRE 12 12 XWE/XWAIT‡ 9 8 9 8 XRDY§ † XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during asynchronous peripheral accesses. ‡ XWE/XWAIT operates as the write enable signal XWE during asynchronous peripheral accesses. § XRDY operates as active-high ready input during asynchronous peripheral accesses. Figure 30. Expansion Bus Asynchronous Peripheral Write Timing 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING timing requirements with external device as bus master (see Figure 31 and Figure 32) 1 2 3 4 5 6 7 8 9 10 16 17 18 MIN MAX UNIT tsu(XCSV-XCKIH) th(XCKIH-XCS) Setup time, XCS valid before XCLKIN high tsu(XAS-XCKIH) th(XCKIH-XAS) Setup time, XAS valid before XCLKIN high tsu(XCTL-XCKIH) th(XCKIH-XCTL) Setup time, XCNTL valid before XCLKIN high Hold time, XCNTL valid after XCLKIN high tsu(XWR-XCKIH) th(XCKIH-XWR) Setup time, XW/R valid before XCLKIN high† Hold time, XW/R valid after XCLKIN high† 4 ns 2.3 ns tsu(XBLTV-XCKIH) th(XCKIH-XBLTV) Setup time, XBLAST valid before XCLKIN high‡ Hold time, XBLAST valid after XCLKIN high‡ 4 ns 2.3 ns tsu(XBEV-XCKIH) th(XCKIH-XBEV) Setup time, XBE[3:0]/XA[5:2] valid before XCLKIN high§ Hold time, XBE[3:0]/XA[5:2] valid after XCLKIN high§ 4 ns 2.3 ns tsu(XD-XCKIH) th(XCKIH-XD) Setup time, XDx valid before XCLKIN high 4 ns 2.3 ns Hold time, XCS valid after XCLKIN high Hold time, XAS valid after XCLKIN high 19 Hold time, XDx valid after XCLKIN high † XW/R input/output polarity selected at boot. ‡ XBLAST input polarity selected at boot. § XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses. 4 ns 2.3 ns 4 ns 2.3 ns 4 ns 2.3 ns ADVANCE INFORMATION NO. switching characteristics with external device as bus master¶ (see Figure 31 and Figure 32) NO. 11 12 13 14 15 20 PARAMETER MIN td(XCKIH-XDLZ) td(XCKIH-XDV) Delay time, XCLKIN high to XDx low impedance td(XCKIH-XDIV) td(XCKIH-XDHZ) Delay time, XCLKIN high to XDx invalid td(XCKIH-XRY) td(XCKIH-XRYLZ) MAX 5 Delay time, XCLKIN high to XDx valid Delay time, XCLKIN high to XDx high impedance Delay time, XCLKIN high to XRDY valid# Delay time, XCLKIN high to XRDY low impedance td(XCKIH-XRYHZ) Delay time, XCLKIN high to XRDY high impedance# ¶ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. # XRDY operates as active-low ready input/output during host-port accesses. 21 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 UNIT ns 15.5 5 ns ns 18 ns 15.5 ns 5 15.5 ns 2P + 5 3P + 15.5 ns 5 49 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED) XCLKIN 2 1 XCS 4 3 XAS 6 5 XCNTL 8 7 XW/R† 8 7 XW/R† XBE[3:0]/XA[5:2]‡ 10 ADVANCE INFORMATION 9 XBLAST§ 10 9 XBLAST§ 11 D1 XD[31:0] 20 13 14 12 D2 D3 15 XRDY¶ † XW/R input/output polarity selected at boot ‡ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses. § XBLAST input polarity selected at boot ¶ XRDY operates as active-low ready input/output during host-port accesses. Figure 31. External Host as Bus Master—Read 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 D4 15 21 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED) XCLKIN 2 1 XCS 4 3 XAS 6 5 XCNTL 8 7 XW/R† 8 7 XW/R† 17 XBE[3:0]/XA[5:2]‡ XBE1 XBE2 XBE3 XBE4 10 9 ADVANCE INFORMATION 16 XBLAST§ 10 9 XBLAST§ 19 18 D1 XD[31:0] 20 D2 D3 15 D4 15 21 XRDY¶ † XW/R input/output polarity selected at boot ‡ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses. § XBLAST input polarity selected at boot ¶ XRDY operates as active-low ready input/output during host-port accesses. Figure 32. External Host as Bus Master—Write POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 51 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED) timing requirements with ’C6202 as bus master (see Figure 33, Figure 34, and Figure 35) NO. 9 10 11 12 14 15 MIN MAX UNIT tsu(XDV-XCKIH) th(XCKIH-XDV) Setup time, XDx valid before XCLKIN high 4 ns Hold time, XDx valid after XCLKIN high 2.3 ns tsu(XRY-XCKIH) th(XCKIH-XRY) Setup time, XRDY valid before XCLKIN high† Hold time, XRDY valid after XCLKIN high† 4 ns 2.3 ns tsu(XBFF-XCKIH) th(XCKIH-XBFF) Setup time, XBOFF valid before XCLKIN high 4 ns 2.3 ns Hold time, XBOFF valid after XCLKIN high † XRDY operates as active-low ready input/output during host-port accesses. switching characteristics with ’C6202 as bus master (see Figure 33, Figure 34, and Figure 35) NO. ADVANCE INFORMATION 1 2 3 4 5 6 7 8 PARAMETER MAX UNIT Delay time, XCLKIN high to XAS valid 5 15.5 ns Delay time, XCLKIN high to XW/R valid‡ 5 15.5 ns td(XCKIH-XBLTV) td(XCKIH-XBEV) Delay time, XCLKIN high to XBLAST valid§ 5 15.5 ns Delay time, XCLKIN high to XBE[3:0]/XA[5:2] valid¶ 5 15.5 ns td(XCKIH-XDLZ) td(XCKIH-XDV) Delay time, XCLKIN high to XDx low impedance 5 td(XCKIH-XDIV) td(XCKIH-XDHZ) Delay time, XCLKIN high to XDx invalid Delay time, XCLKIN high to XDx valid POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ns 15.5 5 Delay time, XCLKIN high to XDx high impedance td(XCKIH-XWTV) Delay time, XCLKIN high to XWE/XWAIT valid# ‡ XW/R input/output polarity selected at boot. § XBLAST output polarity is always active low. ¶ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses. # XWE/XWAIT operates as XWAIT output signal during host-port accesses. 13 52 MIN td(XCKIH-XASV) td(XCKIH-XWRV) 5 ns ns 18 ns 15.5 ns TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED) XCLKIN 1 1 XAS 2 2 XW/R† XW/R† 3 3 XBLAST‡ 4 4 XBE[3:0]/XA[5:2]§ 7 6 AD XD[31:0] 8 10 D2 D1 D3 D4 11 12 ADVANCE INFORMATION 5 BE 9 XRDY 13 13 XWE/XWAIT¶ † XW/R input/output polarity selected at boot ‡ XBLAST output polarity is always active low. § XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses. ¶ XWE/XWAIT operates as XWAIT output signal during host-port accesses. Figure 33. ’C6202 as Bus Master—Read XCLKIN 1 1 XAS XW/R† 2 2 XW/R† 3 3 XBLAST‡ 4 4 6 7 XBE[3:0]/XA[5:2]§ 5 XD[31:0] Addr 8 D1 D2 D3 D4 11 XRDY 12 13 13 XWE/XWAIT¶ † XW/R input/output polarity selected at boot ‡ XBLAST output polarity is always active low. § XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses. ¶ XWE/XWAIT operates as XWAIT output signal during host-port accesses. Figure 34. ’C6202 as Bus Master—Write POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 53 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED) XCLKIN 1 1 XAS XW/R† 2 2 4 4 XW/R† XBLAST‡ XBE[3:0]/XA[5:2]§ 6 7 5 ADVANCE INFORMATION XD[31:0] 8 Addr D1 11 D2 12 XRDY 15 14 XBOFF XHOLD¶ XHOLDA¶ XHOLD# XHOLDA# † XW/R input/output polarity selected at boot ‡ XBLAST output polarity is always active low. § XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses. ¶ Internal arbiter enabled # External arbiter enabled || This diagram illustrates XBOFF timing. Bus arbitration timing is shown in Figure 38 and Figure 39. Figure 35. ’C6202 as Bus Master—BOFF Operation|| 54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING timing requirements with external device as asynchronous bus master† (see Figure 36 and Figure 37) MIN MAX UNIT 1 tw(XCSL) Pulse duration, XCS low 4P ns 2 tw(XCSH) tsu(XSEL-XCSL) Pulse duration, XCS high 3 4 10 11 12 13 4P ns Setup time, expansion bus select signals‡ valid before XCS low Hold time, expansion bus select signals‡ valid after XCS low 2 ns 2 ns Hold time, XCS low after XRDY low P ns tsu(XBEV-XCSH) th(XCSH-XBEV) Setup time, XBE[3:0]/XA[5:2] valid before XCS high§ Hold time, XBE[3:0]/XA[5:2] valid after XCS high§ 2 ns 2 ns tsu(XDV-XCSH) th(XCSH-XDV) Setup time, XDx valid before XCS high 2 ns 2 ns th(XCSL-XSEL) th(XRYL-XCSL) 14 Hold time, XDx valid after XCS high † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ‡ Expansion bus select signals include XCNTL and XR/W. § XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses. switching characteristics with external device as asynchronous bus master (see Figure 36 and Figure 37) NO. 5 PARAMETER MIN td(XCSL-XDLZ) td(XCSH-XDIV) Delay time, XCS low to XDx low impedance 0 Delay time, XCS high to XDx invalid 0 td(XCSH-XDHZ) td(XRYL-XDV) Delay time, XCS high to XDx high impedance 8 Delay time, XRDY low to XDx valid 0 9 td(XCSH-XRYH) Delay time, XCS high to XRDY high 0 6 7 1 MAX UNIT ns 12 ns 12 ns 4 ns 12 ns 1 2 10 10 XCS 3 3 4 4 XCNTL XBE[3:0]/XA[5:2]† 3 3 4 4 XR/W‡ 3 3 4 4 XR/W‡ 5 XD[31:0] 7 6 8 5 7 6 8 Word 9 9 XRDY † XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses. ‡ XW/R input/output polarity selected at boot Figure 36. External Device as Asynchronous Master—Read POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 55 ADVANCE INFORMATION NO. TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING (CONTINUED) 1 10 2 10 1 XCS 3 3 4 4 XCNTL 11 11 12 12 XBE[3:0]/XA[5:2]† 3 3 4 4 XR/W‡ 3 3 4 4 XR/W‡ 13 XD[31:0] 14 13 ADVANCE INFORMATION 9 XRDY † XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses. ‡ XW/R input/output polarity selected at boot Figure 37. External Device as Asynchronous Master—Write 56 14 word Word POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 XHOLD/XHOLDA TIMING timing requirements for expansion bus arbitration (internal arbiter enabled)† (see Figure 38) NO. MIN 3 toh(XHDAH-XHDH) Output hold time, XHOLD high after XHOLDA high † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. MAX P UNIT ns switching characteristics for expansion bus arbitration (internal arbiter enabled)†‡ (see Figure 38) 1 2 4 PARAMETER MIN tR(XHDH-XBHZ) td(XBHZ-XHDAH) Response time, XHOLD high to XBus high impedance tR(XHDL-XHDAL) td(XHDAL-XBLZ) Response time, XHOLD low to XHOLDA low Delay time, XBus high impedance to XHOLDA high MAX § 0 2P 4P 5 Delay time, XHOLDA low to XBus low impedance † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ‡ XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST. § All pending XBus transactions are allowed to complete before XHOLDA is asserted. External Requestor Owns Bus DSP Owns Bus 4P 0 UNIT ns ns ns 2P ns ADVANCE INFORMATION NO. DSP Owns Bus 3 XHOLD (input) 2 4 XHOLDA (output) 1 XBus† 5 C6202 C6202 † XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST. Figure 38. Expansion Bus Arbitration—Internal Arbiter Enabled POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 57 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 XHOLD/XHOLDA TIMING (CONTINUED) switching characteristics for expansion bus arbitration (internal arbiter disabled)† (see Figure 39) NO. 1 PARAMETER td(XHDAH-XBLZ) td(XBHZ-XHDL) MIN Delay time, XHOLDA high to XBus low impedance‡ Delay time, XBus high impedance to XHOLD low‡ 2 † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ‡ XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST. 0 2 XHOLD (output) XHOLDA (input) 1 XBus† C6202 † XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST. ADVANCE INFORMATION Figure 39. Expansion Bus Arbitration—Internal Arbiter Disabled 58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MAX 2P 2P + 10 2P UNIT ns ns TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡ (see Figure 40) ’C6202-200 ’C6202-233 ’C6202-250 MIN 2 3 tc(CKRX) tw(CKRX) UNIT MAX Cycle time, CLKR/X CLKR/X ext 2P ns Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P–1 ns 5 tsu(FRH-CKRL) (FRH CKRL) Setup time, time external FSR high before CLKR low 6 th(CKRL-FRH) h(CKRL FRH) Hold time, time external FSR high after CLKR low 7 tsu(DRV-CKRL) (DRV CKRL) time DR valid before CLKR low Setup time, 8 th(CKRL-DRV) h(CKRL DRV) Hold time time, DR valid after CLKR low 10 tsu(FXH-CKXL) (FXH CKXL) Setup time, time external FSX high before CLKX low 11 th(CKXL-FXH) h(CKXL FXH) Hold time, time external FSX high after CLKX low CLKR int 9 CLKR ext 1 CLKR int 6 CLKR ext 3 CLKR int 8 CLKR ext 0 CLKR int 3 CLKR ext 3 CLKX int 9 CLKX ext 1 CLKX int 6 CLKX ext 3 ns ns ns ns ns ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 59 ADVANCE INFORMATION NO. TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) ADVANCE INFORMATION switching characteristics for McBSP†‡ (see Figure 40) ’C6202-200 ’C6202-233 ’C6202-250 NO. PARAMETER 1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 2 tc(CKRX) tw(CKRX) Cycle time, CLKR/X CLKR/X int 2P§ 3 Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C – 1¶ C + 1¶ ns 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int –2 3 ns CLKX int –2 3 CLKX ext 3 9 9 td(CKXH-FXV) d(CKXH FXV) Delay time, time CLKX high to internal FSX valid 12 tdis(CKXH-DXHZ) di (CKXH DXHZ) Disable time,, DX high g impedance following g last data bit from CLKX high 13 td(CKXH-DXV) d(CKXH DXV) Delay time, time CLKX high to DX valid 14 td(FXH-DXV) d(FXH DXV) UNIT MIN MAX 4 10 ns ns CLKX int –1 4 CLKX ext 3 9 CLKX int –1 4 CLKX ext 3 9 Delay time, FSX high to DX valid FSX int –1 3 ONLY applies when in data delay 0 (XDATDLY = 00b) mode. FSX ext 3 9 ns ns ns ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum delay times also represent minimum output hold times. § P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ¶ C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 DR 8 Bit(n-1) (n-2) (n-3) 2 3 ADVANCE INFORMATION 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) (n-3) Figure 40. McBSP Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 61 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 41) ’C6202-200 ’C6202-233 ’C6202-250 NO. MIN 1 2 tsu(FRH-CKSH) th(CKSH-FRH) 4 ns Hold time, FSR high after CLKS high 4 ns 1 2 FSR external CLKR/X (no need to resync) ADVANCE INFORMATION MAX Setup time, FSR high before CLKS high CLKS CLKR/X(needs resync) Figure 41. FSR Timing When GSYNC = 1 62 UNIT POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 42) ’C6202-200 ’C6202-233 ’C6202-250 NO. MASTER MIN 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX low 4 † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN MAX 2 – 3P ns 5 + 6P ns NO. ’C6202-200 ’C6202-233 ’C6202-250 MASTER§ SLAVE PARAMETER 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 MIN UNIT MIN MAX T–2 T+3 ns L–2 L+3 ns –2 4 L–2 L+3 3P + 4 MAX 5P + 17 ns ns P+3 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 63 ADVANCE INFORMATION switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 42) TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) ADVANCE INFORMATION Figure 42. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 64 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 43) ’C6202-200 ’C6202-233 ’C6202-250 NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX high 4 † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN MAX 2 – 3P ns 5 + 6P ns NO. ’C6202-200 ’C6202-233 ’C6202-250 MASTER§ SLAVE PARAMETER MIN 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# 3 td(CKXL-DXV) tdis(CKXL-DXHZ) 1 6 MAX MIN UNIT MAX L–2 L+3 ns T–2 T+3 ns Delay time, CLKX low to DX valid –2 4 3P + 4 5P + 17 ns Disable time, DX high impedance following last data bit from CLKX low –2 4 3P + 3 5P + 17 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid H–2 H+4 2P + 2 4P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). CLKX 1 2 6 Bit 0 7 FSX DX 3 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 43. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 65 ADVANCE INFORMATION switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 43) TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 44) ’C6202-200 ’C6202-233 ’C6202-250 NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX high 4 † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN MAX 2 – 3P ns 5 + 6P ns ADVANCE INFORMATION switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 44) NO. ’C6202-200 ’C6202-233 ’C6202-250 MASTER§ SLAVE PARAMETER MIN 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 MAX MIN UNIT MAX T–2 T+3 ns H–2 H+3 ns –2 4 H–2 H+3 3P + 4 5P + 17 ns ns P+3 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 2 4P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). 66 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 Bit 0 (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 44. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ADVANCE INFORMATION DR (n-2) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 67 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 45) ’C6202-200 ’C6202-233 ’C6202-250 NO. MASTER MIN 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX low 4 † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN MAX 2 – 3P ns 5 + 6P ns ADVANCE INFORMATION switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 45) NO. ’C6202-200 ’C6202-233 ’C6202-250 MASTER§ SLAVE PARAMETER MIN UNIT MIN MAX MAX H–2 H+3 ns T–2 T+1 ns 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid –2 4 3P + 4 5P + 17 ns tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high –2 4 3P + 3 5P + 17 ns 1 6 7 td(FXL-DXV) Delay time, FSX low to DX valid L–2 L+4 2P + 2 4P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). CLKX 1 2 FSX 7 6 DX 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 45. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 DMAC, TIMER, POWER-DOWN TIMING switching characteristics for DMAC outputs† (see Figure 46) NO. ’C6202-200 ’C6202-233 ’C6202-250 PARAMETER MIN 1 tw(DMACH) Pulse duration, DMAC high † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. UNIT MAX 2P – 3 ns 1 DMAC[3:0] Figure 46. DMAC Timing ’C6202-200 ’C6202-233 ’C6202-250 NO. MIN 1 2 tw(TINPH) tw(TINPL) ADVANCE INFORMATION timing requirements for timer inputs† (see Figure 47) UNIT MAX Pulse duration, TINP high 2P ns Pulse duration, TINP low 2P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. switching characteristics for timer outputs† (see Figure 47) NO. ’C6202-200 ’C6202-233 ’C6202-250 PARAMETER MIN 3 4 tw(TOUTH) tw(TOUTL) UNIT MAX Pulse duration, TOUT high 2P – 3 ns Pulse duration, TOUT low 2P – 3 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. 2 1 TINPx 4 3 TOUTx Figure 47. Timer Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 69 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 DMAC, TIMER, POWER-DOWN TIMING (CONTINUED) switching characteristics for power-down outputs† (see Figure 48) NO. ’C6202-200 ’C6202-233 ’C6202-250 PARAMETER MIN 1 tw(PDH) Pulse duration, PD high † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. 1 PD ADVANCE INFORMATION Figure 48. Power-Down Timing 70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 10P UNIT MAX ns TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 49) ’C6202-200 ’C6202-233 ’C6202-250 NO. MIN 1 Cycle time, TCK 3 tc(TCK) tsu(TDIV-TCKH) 4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high MAX 50 Setup time, TDI/TMS/TRST valid before TCK high UNIT ns 10 ns 5 ns switching characteristics for JTAG test port (see Figure 49) 2 PARAMETER td(TCKL-TDOV) Delay time, TCK low to TDO valid MIN MAX 0 15 UNIT ADVANCE INFORMATION NO. ’C6202-200 ’C6202-233 ’C6202-250 ns 1 TCK 2 2 TDO 4 3 TDI/TMS/TRST Figure 49. JTAG Test-Port Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 71 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MECHANICAL DATA GJL (S-PBGA-N352) PLASTIC BALL GRID ARRAY 27,20 SQ 26,80 25,20 SQ 24,80 25,00 TYP 1,00 16,30 NOM 0,50 AF AE AD AC AB AA Y 1,00 W U 16,30 NOM T R P N M L 0,50 ADVANCE INFORMATION V K J H G F E D C B A 1 3 2 Heat Slug 5 4 7 6 9 8 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 See Note E 3,50 MAX 1,00 NOM Seating Plane 0,70 0,50 NOTES: A. B. C. D. E. F. ∅ 0,10 M 0,60 0,40 0,15 4173516-2/C 07/99 All linear dimensions are in millimeters. This drawing is subject to change without notice. Thermally enhanced plastic package with heat slug (HSL). Flip chip application only Possible protrusion in this area, but within 3,50 max package height specification Falls within JEDEC MO-151/AAL-1 thermal resistance characteristics (S-PBGA package) NO 1 °C/W Air Flow LFPM† RΘJC RΘJA Junction-to-case 0.47 N/A Junction-to-free air 14.2 0 RΘJA RΘJA Junction-to-free air 12.3 100 Junction-to-free air 10.2 250 5 RΘJA Junction-to-free air † LFPM = Linear Feet Per Minute 8.6 500 2 3 4 72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 MECHANICAL DATA GLS (S-PBGA-N384) PLASTIC BALL GRID ARRAY 18,10 SQ 17,90 16,80 TYP 0,80 0,40 AB AA Y W V 0,80 U T R P N M L K G ADVANCE INFORMATION 0,40 J H F E D C B A 3 1 2 5 4 9 7 6 8 11 13 15 17 19 21 10 12 14 16 18 20 22 Heat Slug 2,80 MAX 1,00 NOM Seating Plane 0,55 0,45 0,10 M 0,15 0,45 0,35 4188959/B 12/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Thermally enhanced plastic package with heat slug (HSL) Flip chip application only thermal resistance characteristics (S-PBGA package) NO 1 °C/W Air Flow LFPM† N/A RΘJC RΘJA Junction-to-case 0.85 Junction-to-free air 21.6 0 RΘJA RΘJA Junction-to-free air 17.9 100 Junction-to-free air 14.2 250 RΘJA Junction-to-free air † LFPM = Linear Feet Per Minute 11.8 500 2 3 4 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 73 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. 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