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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors—General Hardware
Design Considerations
3.10.2
Device Connection
Figure 14 shows a typical interface between the IXP45X/IXP46X product line and a
SLIC CODEC, via the SSP and HSS ports, and a couple of GPIO signals.
Figure 14.
HSS Interface Example
Vccp (3.3 V)
Intel® IXP46X
Product Line of
Network Processors
External Oscillator
10 KΩ
GPIO_0
GPIO_1
Clock derived internally
from 3.6864 MHz
or external oscilator
SSP_EXTCLK
33 MHz
RESET_N INT_N
SSP_SCLK
SSP_SFRM
SSP_TXD
SSP_RXD
CLK
CS_N
DI
DO
Vccp (3.3 V)
SSP Interface
10 KΩ
HSS_TX_FRAME0
HSS_TXDATA0
HSS_TXCLK0
HSS_RXFRAME0
HSS_RXDATA0
HSS_RXCLK0
AFE
DTX
Vccp (3.3 V)
10 KΩ
HSS_TX_FRAME1
HSS_TXDATA1
Unused
HSS_TXCLK1
HSS
HSS_RXFRAME1
HSS_RXDATA1
RJ11
FSYNC
RXD
PCLK
Clock derived from
SLIC/CODEC
or external oscilator
SLIC CODEC
512 KHz to
8.192 MHz
10 KΩ
10 KΩ
10 KΩ
10 KΩ
10 KΩ
HSS_RXCLK1
HSS Interface
Vccp (3.3 V)
B4108-003
3.11
SSP Interface
The IXP45X/IXP46X network processors have a Synchronous Serial Peripheral Interface
(SSP) module. Its primary function is to provide connectivity between the Intel XScale
processor and an external SSP interface.
The SSP module supports National Microwire*, Texas Instruments* synchronous serial
protocol (SSP), and Motorola* serial peripheral interface (SPI).
The clock rate can be selected from an internal, 3.6864-MHz source or external source
fed at input pin SSP_EXTCLK. The clock can then be divided down anywhere from
7.2 KHz to 1.84 MHz by setting bits 15:08 in Control Register 0. For more information,
see the SSP configuration registers in the Intel® IXP45X and Intel® IXP46X Product
Line of Network Processors Developer’s Manual.
Intel® IXP45X and Intel® IXP46X Product Line of Network Processors
HDD
46
February 2007
Document Number: 305261; Revision: 004