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Download Cypress Perform STK12C68 User's Manual
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STK12C68 SRAM Write Cycle Parameter Cypress Parameter 25 ns Description Alt tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE [9,10] tLZWE [9] tAVAV tWLWH, tWLEH tELWH, tELEH tDVWH, tDVEH tWHDX, tEHDX tAVWH, tAVEH tAVWL, tAVEL tWHAX, tEHAX tWLQZ tWHQX Min Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active After End of Write 35 ns Max 25 20 20 10 0 20 0 0 Min Max 35 25 25 12 0 25 0 0 10 5 45 ns Min 45 30 30 15 0 30 0 0 13 5 Max 14 5 Unit ns ns ns ns ns ns ns ns ns ns Switching Waveforms Figure 9. SRAM Write Cycle 1: WE Controlled [11, 12] tWC ADDRESS tHA tSCE CE tAW tSA tPWE WE tSD tHD DATA VALID DATA IN tHZWE DATA OUT tLZWE HIGH IMPEDANCE PREVIOUS DATA Figure 10. SRAM Write Cycle 2: CE Controlled [11, 12] tWC ADDRESS CE WE tHA tSCE tSA tAW tPWE tSD DATA IN DATA OUT tHD DATA VALID HIGH IMPEDANCE Notes 10. If WE is Low when CE goes Low, the outputs remain in the high impedance state. 11. HSB must be high during SRAM Write cycles. 12. CE or WE must be greater than VIH during address transitions. Document Number: 001-51027 Rev. ** Page 10 of 20 [+] Feedback
