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Download Dataram DTM64370A memory module
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DTM64370A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 DIMM Identification DTM64370A 512MX72 4GB 2Rx8 PC3-12800R-11-11-B1 Performance range Clock / Module Speed / CL-tRCD -tRP 800 MHz / PC3-12800 / 11-11-11 667 MHz / PC3-10600 / 10-10-10 667 MHz / PC3-10600 / 9-9-9 533 MHz / PC3-8500 / 8-8-8 533 MHz / PC3-8500 / 7-7-7 400 MHz / PC3-6400 / 6-6-6 Description Features 240-pin JEDEC-compliant DIMM, 133.35 mm wide by 30 mm high DTM64370A is a registered 512Mx72 memory module, which conforms to JEDEC's DDR3, PC312800 standard. The assembly is Dual-Rank. Each Rank is comprised of nine 256Mx8 DDR3 Samsung SDRAMs. One 2K-bit EEPROM is used for Serial Presence Detect and a combination register/PLL, with Address and Command Parity, is also used. Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I/O signals in a Fly-by topology. A thermal sensor accurately monitors the DIMM module and can prevent exceeding the maximum operating temperature of 95C. Operating Voltage: 1.5V ± 0.075 I/O Type: SSTL_15 On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM Data Transfer Rate: 12.8 Gigabytes/sec Data Bursts: 8 and burst chop 4 mode ZQ Calibration for Output Driver and On-Die Termination (ODT) Programmable ODT / Dynamic ODT during Writes Programmable CAS Latency: 6, 7, 8, 9, 10 and 11 Bi-Directional Differential Data Strobe signals SDRAM Addressing (Row/Col/Bank): 15/10/3 Fully RoHS Compliant Pin Configuration Front Side Pin Description Back Side 1 VREFDQ 31 DQ25 61 A2 91 DQ41 121 VSS 2 VSS 62 VDD 92 VSS 63 CK1* 64 /CK1* 65 VDD 66 VDD 93 94 95 96 7 DQS0 37 DQ27 67 VREFCA 97 DQ43 127 VSS 8 VSS 9 DQ2 38 VSS 39 CB0 68 PAR_IN 69 VDD 98 VSS 128 DQ6 158 CB4 99 DQ48 129 DQ7 159 CB5 10 DQ3 40 CB1 70 A10/AP 100 DQ49 130 VSS 11 VSS 12 DQ8 41 VSS 42 /DQS8 71 BA0 72 VDD 101 VSS 131 DQ12 161 DM8 102 /DQS6 132 DQ13 162 NC 13 DQ9 43 DQS8 193 /S0 3 4 5 6 32 VSS DQ0 33 /DQS3 DQ1 34 DQS3 VSS 35 VSS /DQS0 36 DQ26 151 VSS Name 122 DQ4 152 DM3 /DQS5 123 DQ5 DQS5 124 VSS VSS 125 DM0 DQ42 126 NC 153 NC 154 VSS 155 DQ30 156 DQ31 157 VSS 160 VSS 73 /WE 103 DQS6 133 VSS 14 VSS 44 VSS 15 /DQS1 45 CB2 16 DQS1 46 CB3 17 VSS 47 VSS 74 /CAS 75 VDD 76 /S1 77 ODT1 104 VSS 105 DQ50 106 DQ51 107 VSS 163 VSS 18 DQ10 48 VTT 19 DQ11 49 VTT 20 VSS 50 CKE0 78 VDD 79 /S2, NC* 80 VSS 108 DQ56 138 DQ15 168 /RESET 109 DQ57 139 VSS 169 CKE1 110 VSS 140 DQ20 170 VDD 21 DQ16 51 VDD 81 DQ32 22 DQ17 52 BA2 23 VSS 53 /ERR_OUT 24 /DQS2 54 VDD 25 DQS2 55 A11 26 VSS 56 A7 82 DQ33 83 VSS 84 /DQS4 85 DQS4 86 VSS 27 DQ18 57 VDD 87 DQ34 28 DQ19 58 A5 29 VSS 59 A4 30 DQ24 60 VDD *Not used 88 DQ35 89 VSS 90 DQ40 Function 181 A1 211 VSS CB[7:0] Data Check Bits 182 VDD 212 DM5 DQ[63:0] Data Bits 183 VDD 184 CK0 185 /CK0 186 VDD 213 NC 214 VSS 215 DQ46 216 DQ47 DQS[8:0], /DQS[8:0] DM[8:0] /TDQS[17:9] CK[1:0], /CK[1:0] Differential Data Strobes Data Mask Termination strobes Differential Clock Inputs 187 /Event 217 VSS CKE[1:0] Clock Enables 188 A0 189 VDD 218 DQ52 219 DQ53 /CAS /RAS Column Address Strobe Row Address Strobe 190 BA1 220 VSS /S[3:0] Chip Selects 191 VDD 192 /RAS 221 DM6 222 NC /WE A[15:0] Write Enable Address Inputs 223 VSS BA[2:0] Bank Addresses 224 DQ54 225 DQ55 226 VSS 227 DQ60 ODT[1:0] SA[2:0] SCL SDA On Die Termination Inputs SPD Address SPD Clock Input SPD Data Input/Output 198 /S3, NC* 199 VSS 200 DQ36 228 DQ61 229 VSS 230 DM7 /EVENT /RESET PAR_IN Temperature Sensing Reset for register and DRAMs Parity bit for Addr/Ctrl 111 /DQS7 141 DQ21 171 A15 201 DQ37 231 NC /ERR_OUT Error bit for Parity Error 112 DQS7 113 VSS 114 DQ58 115 DQ59 116 VSS 142 VSS 172 A14 143 DM2 173 VDD 144 NC 174 A12/BC 145 VSS 175 A9 146 DQ22 176 VDD 202 VSS 203 DM4 204 NC 205 VSS 206 DQ38 232 VSS 233 DQ62 234 DQ63 235 VSS 236 VDDSPD A12/BC A10/AP VSS VDD VDDSPD Combination input: Addr12/Burst Chop Combination input: Addr10/Auto-precharge Ground Power SPD EEPROM Power 117 SA0 147 DQ23 177 A8 207 DQ39 237 SA1 VREFDQ Reference Voltage for DQ’s 118 SCL 119 SA2 120 VT 148 VSS 178 A6 149 DQ28 179 VDD 150 DQ29 180 A3 208 VSS 209 DQ44 210 DQ45 238 SDA 239 VSS 240 VTT VREFCA VTT NC Reference Voltage for CA Termination Voltage No Connection 134 DM1 164 CB6 194 VDD 135 NC 165 CB7 195 ODT0 136 VSS 166 VSS 196 A13 137 DQ14 167 NC (TEST) 197 VDD Document 06214, Revision A, 05-Jul-11, Dataram Corporation 2011 Page 1 DTM64370A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 DIMM Front view 133.35 [5.250] 9.50 [0.374] 30.00 [1.181] 17.30 [0.681] 5.00 [0.197] 5.175 [0.204] 47.00 [1.850] 71.00 [2.795] 2.50 [0.098] 123.00 [4.843] Back view Side view 4.00Max [0.157] Max 4.00 Min [0.157] Min 1.27 ±.10 [0.0500 ±0.0040] Notes Tolerances on all dimensions except where otherwise indicated are ±.13 (.005). All dimensions are expressed: millimeters [inches] Document 06214, Revision A, 05-Jul-11, Dataram Corporation 2011 Page 2 DTM64370A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 DIMM /RS1 /RS0 DQSR0 /DQSR0 DMR0 /TDQSR9 I/O[7:0] I/O[7:0] RANK 1 DQR[39:32] DQR[47:40] I/O[7:0] DM TDQS /CS /DQS DQS NU /TDQS I/O[7:0] RANK 1 DM TDQS /CS /DQS DQS NU /TDQS I/O[7:0] I/O[7:0] I/O[7:0] I/O[7:0] DQR[55:48] I/O[7:0] DM TDQS /CS /DQS DQS NU /TDQS DM TDQS /CS /DQS DQS NU /TDQS DM TDQS /CS /DQS DQS DM TDQS /CS /DQS DQS NU /TDQS DQSR6 /DQSR6 DMR6 /TDQSR15 NU /TDQS DQSR2 /DQSR2 DMR2 /TDQSR11 I/O[7:0] DQR[63:56] I/O[7:0] NU /TDQS NU /TDQS DM TDQS /CS /DQS DQS NU /TDQS DM TDQS /CS /DQS DQS NU /TDQS I/O[7:0] I/O[7:0] DM TDQS /CS /DQS DQS DQSR7 /DQSR7 DMR7 /TDQSR16 DQSR3 /DQSR3 DMR3 /TDQSR12 DQR[31:24] RANK 0 DM TDQS /CS /DQS DQS NU /TDQS DM TDQS /CS /DQS DQS NU /TDQS DM TDQS /CS /DQS DQS NU /TDQS I/O[7:0] DQR[23:16] I/O[7:0] DQSR5 /DQSR5 DMR5 /TDQSR14 DQSR1 /DQSR1 DMR1 /TDQSR10 DQR[15:8] DM TDQS /CS /DQS DQS NU /TDQS DM TDQS /CS /DQS DQS NU /TDQS RANK 0 DM TDQS /CS /DQS DQS DQR[7:0] DM TDQS /CS /DQS DQS NU /TDQS DQSR4 /DQSR4 DMR4 /TDQSR13 I/O[7:0] CBR[7:0] I/O[7:0] DM TDQS /CS /DQS DQS NU /TDQS DM TDQS /CS /DQS DQS NU /TDQS DQSR8 /DQSR8 DMR8 /TDQSR17 I/O[7:0] V DD TO SDRAMS All 15 OHMS DQR[63:0] DQ[63:0] CBR[7:0] CB[7:0] All 39 OHMS All 22 OHMS /RAS /RASR /DQS[8:0] /DQSR[8:0] /CAS /WE CKE0 /CASR /WER DMR[8:0] /TDQSR[17:9] REG / PLL DQSR[8:0] DM[8:0] CKE1 ODT0 ODT1 All 39 OHMS BA[2:0]R CKE1R ODT0R CK0 120 OHMS /CK0 L,R(CLK)[1:0] /L,R(CLK)[1:0] RCLK[1:0] DECOUPLING VDDSPD VDD V REF_DQ V SS VREF_CA V TT ODT1R VDD All 39 OHMS 100 nF /RCLK[1:0] CKE0R /ERR_OUT PAR_IN GLOBAL SDRAM CONNECTS /LCLK[1:0] BA[2:0]R A[14:0]R A[15:0] DQS[8:0] /TDQS[17:9] LCLK[1:0] /RS0 /RS1 /S0 /S1 BA[2:0] 100 nF Serial PD All Devices All SDRAMs All Devices All SDRAMs All SDRAMs /RESET A[15:0]R /RASR SDRAMS /CASR /WER CK1 VTT 120 OHMS /EVENT /CK1 All 240 OHMS All 39 OHMS CKE[1:0]R ODT[1:0]R /RS[1:0] ZQ VTT V SS Document 06214, Revision A, 05-Jul-11, Dataram Corporation 2011 SC L TEMPERATURE MONITOR/ SERIAL PD SA 0 SA 1 SD A SA 2 Page 3 DTM64370A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 DIMM Absolute Maximum Ratings (Note: Operation at or above Absolute Maximum Ratings can adversely affect module reliability.) PARAMETER Symbol Minimum Maximum Unit Temperature, non-Operating TSTORAGE -55 100 C TA 0 70 C Ambient Temperature, Operating DRAM Case Temperature, Operating TCASE 0 95 C VDD -0.4 1.975 V VIN,VOUT -0.4 1.975 V Voltage on VDD relative to VSS Voltage on Any Pin relative to VSS Notes: DRAM Operating Case Temperature above 85C requires 2X refresh. Recommended DC Operating Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Power Supply Voltage Symbol VDD Minimum 1.425 Typical 1.5 Maximum 1.575 Unit V Note I/O Reference Voltage VREFDQ 0.49 VDD 0.50 VDD 0.51 VDD V 1 I/O Reference Voltage VREFCA 0.49 VDD 0.50 VDD 0.51 VDD V 1 Notes: 1) The value of VREF is expected to equal one-half VDD and to track variations in the VDD DC level. Peak-to-peak noise on VREF may not exceed ±1% of its DC value. For Reference VDD/2 ± 15 mV. DC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Logical High (Logic 1) Symbol VIH(DC) Minimum VREF + 0.1 Maximum VDD Unit V Logical Low (Logic 0) VIL(DC) VSS VREF - 0.1 V AC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Logical High (Logic 1) Symbol VIH(AC) Minimum VREF + 0.175 Maximum - Unit V Logical Low (Logic 0) VIL(AC) - VREF - 0.175 V Document 06214, Revision A, 05-Jul-11, Dataram Corporation 2011 Page 4 DTM64370A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 DIMM Differential Input Logic Levels (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Differential Input Logic High Differential Input Logic Low Differential Input Cross Point Voltage relative to VDD/2 Symbol VIH.DIFF Minimum +0.200 Maximum DC:VDD AC:VDD+0.4 Unit V VIL.DIFF DC:VSS AC:VSS-0.4 -0.200 V VIX - 0.150 + 0.150 V Capacitance (TA = 25 C, f = 100 MHz) PARAMETER Pin Symbol Minimum Maximum Unit CCK 1.5 2.5 pF pF Input Capacitance, Clock CK0, /CK0 Input Capacitance, Address BA[2:0], A[15:0], /RAS, /CAS, /WE CI 1.5 2.5 Input Capacitance Control /S[1:0], CKE[1:0], ODT[1:0] CI 1.5 2.5 Input/Output Capacitance DQ[63:0], CB[7:0] DQS[8:0], /DQS[8:0], DM[8:0], TDQS[17:9] CIO 3 5 pF DC Characteristics (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Input Leakage Current Symbol Minimum Maximum Unit Note IIL -18 +18 µA 1,2 IOL -10 +10 µA 2,3 (Any input 0 V < VIN < VDD) Output Leakage Current (0V < VOUT < VDDQ) Notes: 1) All other pins not under test = 0 V 2) Values are shown per pin 3) DQ, DQS, DQS and ODT are disabled Document 06214, Revision A, 05-Jul-11, Dataram Corporation 2011 Page 5 DTM64370A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 DIMM IDD Specifications and Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Operating One Bank ActivePrecharge Current Operating One Bank Active-ReadPrecharge Current Precharge PowerDown Current Precharge PowerDown Current Precharge Quiet Standby Current Precharge Standby Current Active Power-Down Current Active Standby Current Operating Burst Write Current Operating Burst Read Current Burst Refresh Current Self Refresh Current Operating Bank Interleave Read Current Symbol IDD0* IDD1* IDD2P** IDD2P** IDD2Q** IDD2N** IDD3P** IDD3N** IDD4W* IDD4R* IDD5** IDD6** IDD7* Test Condition Operating current : One bank ACTIVATE-to-PRECHARGE Operating current : One bank ACTIVATE-to-READ-toPRECHARGE Precharge power down current: (Slow exit) Precharge power down current: (Fast exit) Precharge quiet standby current Precharge standby current Active power-down current Active standby current Burst write operating current Burst read operating current Refresh current Self-refresh temperature current: MAX TC = 85°C All bank interleaved read current Max Value Unit 1305 mA 1395 mA 846 mA 900 mA 1030 mA 1050 mA 990 mA 1310 mA 1765 mA 1710 mA 1940 mA 246 mA 2160 mA * One module rank in this operation the rest in IDD2P slow exit. ** All module ranks in this operation. Document 06214, Revision A, 05-Jul-11, Dataram Corporation 2011 Page 6 DTM64370A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data tAA 13.75(13.125) 20 ns CAS-to-CAS Command Delay tCCD 4 - tCK tCH(avg) 0.47 0.53 tCK tCK 1.5 1.875 ns tCL(avg) 0.47 0.53 tCK tDH 45 - ps Clock High Level Width Clock Cycle Time Clock Low Level Width Data Input Hold Time after DQS Strobe DQ Input Pulse Width tDIPW 360 - ps DQS Output Access Time from Clock tDQSCK -225 +225 ps Write DQS High Level Width tDQSH 0.45 0.55 tCK(avg) Write DQS Low Level Width tDQSL 0.45 0.55 tCK(avg) DQS-Out Edge to Data-Out Edge Skew tDQSQ - 100 ps Data Input Setup Time Before DQS Strobe tDS 10 - ps DQS Falling Edge from Clock, Hold Time tDSH 0.18 - tCK(avg) DQS Falling Edge to Clock, Setup Time tDSS 0.18 - tCK(avg) Clock Half Period tHP minimum of tCH or tCL - ns Address and Command Hold Time after Clock tIH 120 - ps Address and Command Setup Time before Clock tIS(AC150) 45 - ps Load Mode Command Cycle Time tMRD 4 - tCK DQ-to-DQS Hold tQH 0.38 - tCK(avg) Active-to-Precharge Time tRAS 35 9*tREFI ns Active-to-Active / Auto Refresh Time tRC 48.75(48.125) - ns RAS-to-CAS Delay tRCD 13.75(13.125) - ns - 7.8 µs o o tREFI o o Average Periodic Refresh Interval 0 C < TCASE < 95 C tREFI - 3.9 µs Auto Refresh Row Cycle Time tRFC 160 - ns Row Precharge Time tRP 13.75(13.125) - ns Read DQS Preamble Time tRPRE 0.9 Note-1 tCK(avg) Read DQS Postamble Time tRPST 0.3 Note-2 tCK(avg) Row Active to Row Active Delay tRRD Max(4nCK, 6ns) - ns Internal Read to Precharge Command Delay tRTP Max(4nCK, 7.5ns) - ns Write DQS Preamble Setup Time tWPRE 0.9 - tCK(avg) Write DQS Postamble Time tWPST 0.3 - tCK(avg) Write Recovery Time tWR 15 - ns Internal Write to Read Command Delay tWTR Max(4nCK, 7.5ns) - ns Average Periodic Refresh Interval 0 C < TCASE < 85 C Notes: 1. 2. The maximum preamble is bound by tLZDQS(min) The maximum postamble is bound by tHZDQS(max) Document 06214, Revision A, 05-Jul-11, Dataram Corporation 2011 Page 7 DTM64370A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 DIMM SERIAL PRESENCE DETECT MATRIX Byte# Function. Value 1 Number of Bytes Used / Number of Bytes in SPD Device / CRC Coverage. Bit 3 ~ Bit 0. SPD Bytes Used 176 Bit 6 ~ Bit 4. SPD Bytes Total 256 Bit 7. CRC Coverage Bytes 0-116 SPD Revision. Rev. 1.1 2 Key Byte / DRAM Device Type. 0 Hex 0x92 0x11 DDR3 SDRAM 0x0B Bit 3 ~ Bit 0. Module Type Bit 7 ~ Bit 4. Reserved - RDIMM 0 0x01 4 Bit 3 ~ Bit 0. Total SDRAM capacity, in megabits Bit 6 ~ Bit 4. Bank Address Bits Bit 7. Reserved SDRAM Addressing. 2Gb 8 banks 0 0x03 5 Bit 2 ~ Bit 0. Column Address Bits Bit 5 ~ Bit 3. Row Address Bits Bit 7, 6. Reserved 10 15 0 UNUSED 0x19 Key Byte / Module Type. 3 SDRAM Density and Banks. 6 Reserved. 0x00 Module Organization. Bit 2 ~ Bit 0. SDRAM Device Width Bit 5 ~ Bit 3. Number of Ranks Bit 7, 6. Reserved 7 8 9 Module Memory Bus Width. Bit 2 ~ Bit 0. Primary bus width, in bits Bit 4, Bit 3. Bus width extension, in bits Bit 7 ~ Bit 5. Reserved Fine Timebase (FTB) Dividend / Divisor. Bit 3 ~ Bit 0. Fine Timebase (FTB) Divisor Bit 7 ~ Bit 4. Fine Timebase (FTB) Dividend Medium Timebase (MTB) Dividend. 8-Bits 2-Rank 0 0x09 64-Bits 8-Bits 0 0x0B 0x11 0x0A 0x00 12 SDRAM Minimum Cycle Time (tCKmin). 1 1 1 (MTB = 0.125ns) 8 (MTB = 0.125ns) 1.25ns 13 Reserved. UNUSED 10 11 Medium Timebase (MTB) Divisor. 0x01 0x08 CAS Latencies Supported, Least Significant Byte. Bit 0. CL = 4 Bit 1. CL = 5 Bit 2. CL = 6 Bit 3. CL = 7 Bit 4. CL = 8 Bit 5. CL = 9 Bit 6. CL = 10 Bit 7. CL = 11 - 14 15 CAS Latencies Supported, Most Significant Byte. Document 06214, Revision A, 05-Jul-11, Dataram Corporation 2011 X X X X X X 0xFC 0x00 Page 8 DTM64370A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 DIMM Bit 0. CL = 12 Bit 1. CL = 13 Bit 2. CL =14 Bit 3. CL = 15 Bit 4. CL = 16 Bit 5. CL = 17 Bit 6. CL = 18 Bit 7. Reserved. 16 Minimum CAS Latency Time (tAAmin). 17 Minimum Write Recovery Time (tWRmin). 18 Minimum RAS# to CAS# Delay Time (tRCDmin). 19 Minimum Row Active to Row Active Delay Time (tRRDmin). 20 Minimum Row Precharge Delay Time (tRPmin). 13.125ns 0x69 15.0ns 0x78 13.125ns 0x69 6.0ns 0x30 13.125ns 0x69 1 1 35.0ns 0x11 Upper Nibbles for tRAS and tRC. 21 32 Bit 3 ~ Bit 0. tRAS Most Significant Nibble Bit 7 ~ Bit 4. tRC Most Significant Nibble Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte. Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte. Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte. Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte. Minimum Internal Write to Read Command Delay Time (tWTRmin). Minimum Internal Read to Precharge Command Delay Time (tRTPmin). Upper Nibble for tFAW. Bit 3 ~ Bit 0. tFAW Most Significant Nibble Bit 7 ~ Bit 4. Reserved Minimum Four Activate Window Delay Time (tFAWmin), Least Significant Byte. SDRAM Optional Features. Bit 0. RZQ / 6 Bit 1. RZQ / 7 Bit 6 ~ Bit 2. Reserved Bit 7. DLL-Off Mode Support SDRAM Drivers Supported. Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh (ASR) On-die Thermal Sensor (ODTS) Readout Reserved Reserved Reserved Reserved Module Thermal Sensor 33 SDRAM Device Type 22 23 24 25 26 27 28 29 30 31 Document 06214, Revision A, 05-Jul-11, Dataram Corporation 2011 48.125ns 160.0ns 160.0ns 7.5ns 7.5ns 0 0 30.0ns X X 0x18 0x81 0x00 0x05 0x3C 0x3C 0x00 0xF0 0x83 X X 0x01 With TS 0x80 Monolithic 0x00 Page 9 DTM64370A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 DIMM 34 Fine Offset for SDRAM Minimum Cycle Time(tCKmin) 1.25ns 0x00 35 Fine Offset for Minimum CAS Latency Time(tAAmin) 13.125ns 0x00 36 Fine Offset for Minimum RAS# to CAS# Delay Time(tRCDmin) 13.125ns 0x00 37 Fine Offset for Minimum Row Precharge Delay Time(tRPmin) 13.125ns 0x00 48.125ns 0x00 UNUSED 0x00 29<h<=30 0 0x0F 38 39-59 60 Fine Offset for Minimum Active to Active/Refresh Delay Time(tRCmin) Reserved Module Nominal Height. Bit 4 ~ Bit 0. Module Nominal Height max, in mm Bit 7 ~ Bit5. Reserved Module Maximum Thickness. 61 Bit 3 ~ Bit 0. Front, in mm (baseline thickness = 1 mm) Bit 7 ~ Bit 4. Back, in mm (baseline thickness = 1 mm) Reference Raw Card Used. 1<th<=2 1<th<=2 0x11 62 Bit 4 ~ Bit 0. Reference Raw Card Bit 6, Bit 5. Reference Raw Card Revision Bit 7. Reserved Address Mapping from Edge Connector to DRAM. Bit 0. Rank 1 Mapping (Registered DIMM - Reserved) Bit 7 ~ Bit 1. Reserved Module-Specific Section R/C B Rev.1 0 0x21 63 64-66 67 0x05 UNUSED Register Revision Number 0x00 FF 68, 69 Module-Specific Section UNUSED 70 Module-Specific Section P 0x50 71-112 113 114-116 117 118 119 120,121 122-125 126 127 128 129 130 131 132 133 134 135 136 137 138 Module-Specific Section UNUSED Module-Specific Section. Module-Specific Section Module Manufacturer ID Code, Least Significant Byte Module Manufacturer ID Code, Most Significant Byte Module Manufacturing Location Module Manufacturing Date Module Serial Number Cyclical Redundancy Code (CRC). Cyclical Redundancy Code (CRC). Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number UNUSED UNUSED 0x00 0x00 0x00 0x01 0x91 0x00 0x20 0x20 0x20 0xFE 0x4D 0X33 0X39 0X33 0x42 0x35 0x32 0x37 0x33 0x44 0x48 Document 06214, Revision A, 05-Jul-11, Dataram Corporation 2011 UNUSED CRC CRC M 3 9 3 B 5 2 7 3 D H Page 10 DTM64370A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 DIMM 139 140 141 142 143 144 145 146,147 148 149 150-175 176-255 Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Revision Code DRAM Manufacturer ID Code, Least Significant Byte DRAM Manufacturer ID Code, Most Significant Byte Manufacturer’s Specific Data Open for customer use Document 06214, Revision A, 05-Jul-11, Dataram Corporation 2011 0 C K 0 Space Space UNUSED UNUSED UNUSED UNUSED 0x30 0x2D 0x43 0x4B 0x30 0x20 0x20 0x20 0x00 0x00 0x00 0x00 Page 11 DTM64370A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 DIMM DATARAM CORPORATION, USA Corporate Headquarters, P.O. Box 7528, Princeton, NJ 08543-7528; Voice: 609-799-0071, Fax: 609-799-6734; www.dataram.com All rights reserved. The information contained in this document has been carefully checked and is believed to be reliable. However, Dataram assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Dataram. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Dataram. Document 06214, Revision A, 05-Jul-11, Dataram Corporation 2011 Page 12
