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Download Dataram DTM64343A memory module
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DTM64343A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 VLP DIMM Identification DTM64343A 512Mx72 4GB 2Rx8 PC3-10600R-9-10-L0 Performance range Clock / Module Speed / CL-tRCD -tRP 667 MHz / PC3-10600 / 9-9-9 533 MHz / PC3-8500 / 8-8-8 533 MHz / PC3-8500 / 7-7-7 400 MHz / PC3-6400 / 6-6-6 Features Description 240-pin JEDEC-compliant DIMM, 133.35 mm wide by 18.75 mm high DTM64343A is a registered 512Mx72 memory module, which conforms to JEDEC's DDR3, PC310600 standard. The assembly consists of two Ranks. Each Rank is comprised of nine 256Mx8 DDR3 Hynix SDRAMs. One 2K-bit EEPROM is used for Serial Presence Detect and a combination register/PLL, with Address and Command Parity, is also used. Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I/O signals in a fly-by topology. A thermal sensor can monitor the DIMM module and will signal the memory controller if a temperature limit is exceeded. Operating Voltage: 1.5V ±0.075 I/O Type: SSTL_15 2 On-board I C temperature sensor with integrated serial presence-detect (SPD) EEPROM Data Transfer Rate: 10.6 Gigabytes/sec Data Bursts: 8 and burst chop 4 mode ZQ Calibration for Output Driver and On-Die Termination (ODT) Programmable ODT / Dynamic ODT during Writes Programmable CAS Latency: 6, 7, 8, and 9 Bi-Directional Differential Data Strobe signals SDRAM Addressing (Row/Col/Bank): 15/10/3 Fully RoHS Compliant Pin Configuration Front Side Pin Description Back Side Name Function 1 VREFDQ 31 DQ25 61 A2 91 DQ41 121 VSS 151 VSS 181 A1 211 VSS CB[7:0] Data Check Bits 2 VSS 32 VSS 62 VDD 92 VSS 152 DM3 182 VDD 212 DM5 DQ[63:0] Data Bits 3 4 5 6 33 /DQS3 34 DQS3 35 VSS 36 DQ26 63 CK1* 64 /CK1* 65 VDD 66 VDD 93 94 95 96 153 /TDQS12 154 VSS 155 DQ30 156 DQ31 183 184 185 186 213 214 215 216 DQS[8:0], /DQS[8:0] DM[8:0] /TDQS[17:9] CK[1:0], /CK[1:0] Differential Data Strobes Data Mask Termination Data Strobes Differential Clock Inputs 7 DQS0 37 DQ27 67 VREFCA 97 DQ43 127 VSS 157 VSS 187 /Event 217 VSS CKE[1:0] Clock Enables 8 VSS 9 DQ2 38 VSS 39 CB0 68 PAR_IN 69 VDD 98 VSS 128 DQ6 99 DQ48 129 DQ7 158 CB4 159 CB5 188 A0 189 VDD 218 DQ52 219 DQ53 /CAS /RAS Column Address Strobe Row Address Strobe 10 DQ3 40 CB1 70 A10/AP 100 DQ49 130 VSS 160 VSS 190 BA1 220 VSS /S[3:0] Chip Selects 11 VSS 12 DQ8 41 VSS 42 /DQS8 71 BA0 72 VDD 101 VSS 131 DQ12 102 /DQS6 132 DQ13 161 DM8 191 VDD 162 /TDQS17 192 /RAS 13 DQ9 43 DQS8 73 /WE 103 DQS6 133 VSS 163 VSS 14 VSS 15 /DQS1 16 DQS1 17 VSS 44 VSS 45 CB2 46 CB3 47 VSS 74 /CAS 75 VDD 76 /S1 77 ODT1 104 VSS 105 DQ50 106 DQ51 107 VSS 18 DQ10 48 VTT 78 VDD 108 DQ56 138 DQ15 168 /RESET 198 /S3, NC* 19 DQ11 49 VTT 20 VSS 50 CKE0 79 /S2, NC* 80 VSS 109 DQ57 139 VSS 110 VSS 140 DQ20 169 CKE1 170 VDD 199 VSS 200 DQ36 21 DQ16 51 VDD 81 DQ32 111 /DQS7 141 DQ21 171 A15 201 DQ37 231 /TDQS16 VREFDQ Reference Voltage for DQ 22 DQ17 23 VSS 24 /DQS2 25 DQS2 26 VSS 27 DQ18 82 DQ33 83 VSS 84 /DQS4 85 DQS4 86 VSS 87 DQ34 112 DQS7 113 VSS 114 DQ58 115 DQ59 116 VSS 117 SA0 142 VSS 172 A14 143 DM2 173 VDD 144 /TDQS11 174 A12/ /BC 145 VSS 175 A9 146 DQ22 176 VDD 147 DQ23 177 A8 202 203 204 205 206 207 232 233 234 235 236 237 Reference Voltage for CA Termination Voltage Temperature Sensing No Connection 88 DQ35 89 VSS 90 DQ40 118 SCL 119 SA2 120 VTT 148 VSS 149 DQ28 150 DQ29 208 VSS 209 DQ44 210 DQ45 DQ0 DQ1 VSS /DQS0 52 BA2 53 /ERR_OUT 54 VDD 55 A11 56 A7 57 VDD 28 DQ19 58 A5 29 VSS 59 A4 30 DQ24 60 VDD 122 DQ4 /DQS5 123 DQ5 DQS5 124 VSS VSS 125 DM0 DQ42 126 /TDQS9 193 /S0 134 DM1 164 CB6 194 135 /TDQS10 165 CB7 195 136 VSS 166 VSS 196 137 DQ14 167 NC (TEST) 197 178 A6 179 VDD 180 A3 VDD CK0 /CK0 VDD VDD ODT0 A13 VDD VSS DM4 NC VSS DQ38 DQ39 /TDQS14 VSS DQ46 DQ47 221 DM6 /WE 222 /TDQS15 A[15:0] Write Enable Address Inputs 223 VSS BA[2:0] Bank Addresses 224 225 226 227 ODT[1:0] SA[2:0] SCL SDA On Die Termination Inputs SPD Address SPD Clock Input SPD Data Input/Output 228 DQ61 VSS Ground 229 VSS 230 DM7 VDD VDDSPD Power SPD EEPROM Power DQ54 DQ55 VSS DQ60 VSS DQ62 DQ63 VSS VDDSPD SA1 VREFCA VTT /Event NC 238 SDA 239 VSS 240 VTT * Not used Document 06591, Revision A, 6-Jul-2010, Dataram Corporation © 2010 Page 1 DTM64343A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 VLP DIMM Front view 133.35 [5.250] 9.50 [0.374] 18.75 [0.738] 5.00 [0.197] 5.175 [0.204] 47.00 [1.850] 71.00 [2.795] 2.50 [0.098] 123.00 [4.843] Back view Side view 3.94 Max [0.155] Max 4.00 Min [0.157] Min 1.27 ±.10 [0.0500 ±0.0040] Notes Tolerances on all dimensions except where otherwise indicated are ±.13 (.005). All dimensions are expressed: millimeters [inches] Document 06591, Revision A, 6-Jul-2010, Dataram Corporation © 2010 Page 2 DTM64343A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 VLP DIMM /RS1 /RS0 DQSR0 /DQSR0 DMR0 /TDQSR9 I/O[7:0] I/O[7:0] RANK 0 DQR[39:32] I/O[7:0] DQR[47:40] /DQS DQS DM TDQS /CS NU /TDQS /DQS DQS I/O[7:0] RANK 0 /DQS DQS DM TDQS /CS NU /TDQS /DQS DQS I/O[7:0] I/O[7:0] I/O[7:0] DQR[55:48] I/O[7:0] /DQS DQS DM TDQS /CS NU /TDQS /DQS DQS NU /TDQS /DQS DQS DM TDQS /CS NU /TDQS /DQS DQS DM TDQS /CS NU /TDQS I/O[7:0] DM TDQS /CS DQSR6 /DQSR6 DMR6 /TDQSR15 I/O[7:0] DQR[63:56] I/O[7:0] I/O[7:0] /DQS DQS DM TDQS /CS /DQS DQS NU /TDQS /DQS DQS DM TDQS /CS NU /TDQS /DQS DQS DM TDQS /CS NU /TDQS I/O[7:0] NU /TDQS DQSR7 /DQSR7 DMR7 /TDQSR16 DQSR3 /DQSR3 DMR3 /TDQSR12 DQR[31:24] RANK 0 DM TDQS /CS NU /TDQS /DQS DQS DM TDQS /CS NU /TDQS /DQS DQS DM TDQS /CS NU /TDQS I/O[7:0] DQSR2 /DQSR2 DMR2 /TDQSR11 DQR[23:16] I/O[7:0] DQSR5 /DQSR5 DMR5 /TDQSR14 DQSR1 /DQSR1 DMR1 /TDQSR10 DQR[15:8] DM TDQS /CS NU /TDQS /DQS DQS DM TDQS /CS NU /TDQS RANK 0 DM TDQS /CS DQR[7:0] /DQS DQS DM TDQS /CS NU /TDQS DQSR4 /DQSR4 DMR4 /TDQSR13 I/O[7:0] CBR[7:0] I/O[7:0] /DQS DQS DM TDQS /CS NU /TDQS /DQS DQS DM TDQS /CS NU /TDQS DQSR8 /DQSR8 DMR8 /TDQSR17 I/O[7:0] V DD TO SDRAMS All 22 OHMS All 15 OHMS DQR[63:0] DQ[63:0] CB[7:0] CBR[7:0] /RS0 /RS1 /S0 /S1 BA[2:0] BA[2:0]R A[15:0]R A[15:0] DQSR[17:0] /RAS /RASR /DQS[17:0] /DQSR[17:0] /CAS /WE /CASR /WER DM[8:0] DMR[8:0] CKE0 /TDQSR[17:9] CKE1 ODT0 REG / PLL DQS[17:0] /TDQS[17:9] ODT1 All 39 OHMS BA[2:0]R ODT1R CK0 120 OHMS /CK0 L,R(CLK)[1:0] /L,R(CLK)[1:0] LCLK[1:0] RCLK[1:0] /RCLK[1:0] DECOUPLING V DDSPD V DD V REF_DQ V SS VREF_CA V TT Serial PD All Devices All SDRAMs All Devices All SDRAMs All SDRAMs /RESET A[15:0]R /RASR SDRAMS /CASR /WER VTT /EVENT All 240 OHMS All 39 OHMS CKE[1:0]R ODT[1:0]R RS[1:0] All 39 OHMS 100 nF /LCLK[1:0] CKE0R CKE1R ODT0R /ERR_OUT PAR_IN GLOBAL SDRAM CONNECTS VDD All 39 OHMS 100 nF SCL ZQ VTT VSS Document 06591, Revision A, 6-Jul-2010, Dataram Corporation © 2010 TEMPERATURE MONITOR/ SERIAL PD SA0 SA1 SDA SA2 Page 3 DTM64343A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 VLP DIMM Absolute Maximum Ratings (Note: Operation at or above Absolute Maximum Ratings can adversely affect module reliability.) PARAMETER Symbol Minimum Maximum Unit Temperature, non-Operating TSTORAGE -55 100 C TA 0 70 C Ambient Temperature, Operating TCASE 0 95 C VDD -0.4 1.975 V VIN,VOUT -0.4 1.975 V DRAM Case Temperature, Operating Voltage on VDD relative to VSS Voltage on Any Pin relative to VSS Notes: DRAM Operating Case Temperature above 85 C requires 2X refresh. Recommended DC Operating Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Power Supply Voltage Symbol VDD Minimum 1.425 Typical 1.5 Maximum 1.575 Unit V Note I/O Reference Voltage VREFDQ 0.49 VDD 0.50 VDD 0.51 VDD V 1 I/O Reference Voltage VREFCA 0.49 VDD 0.50 VDD 0.51 VDD V 1 Notes: 1) The value of VREF is expected to equal one-half VDD and to track variations in the VDD DC level. Peak-to-peak noise on VREF may not exceed ±1% of its DC value. DC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Logical High (Logic 1) Symbol VIH(DC) Minimum VREF + 0.1 Maximum VDD Unit V Logical Low (Logic 0) VIL(DC) VSS VREF - 0.1 V AC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Logical High (Logic 1) Symbol VIH(AC) Minimum VREF + 0.175 Maximum - Unit V Logical Low (Logic 0) VIL(AC) - VREF - 0.175 V Document 06591, Revision A, 6-Jul-2010, Dataram Corporation © 2010 Page 4 DTM64343A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 VLP DIMM Differential Input Logic Levels (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Differential Input Logic High Differential Input Logic Low Differential Input Cross Point Voltage relative to VDD/2 Symbol VIH.DIFF Minimum +0.200 Maximum DC:VDD AC:VDD+0.4 Unit V VIL.DIFF DC:VSS AC:VSS-0.4 -0.200 V VIX - 0.150 + 0.150 V Capacitance (TA = 25 C, f = 100 MHz) PARAMETER Pin Symbol Minimum Maximum Unit CCK 1.5 2.5 pF pF Input Capacitance, Clock CK0, /CK0 Input Capacitance, Address BA[2:0], A[15:0], /RAS, /CAS, /WE CI 1.5 2.5 Input Capacitance Control /S[1:0], CKE[1:0], ODT[1:0] DQ[63:0], CB[7:0] DQS[8:0], /DQS[8:0], DM[8:0], /TDQS[17:9] CI 1.5 2.5 CIO 3 5 Input/Output Capacitance pF DC Characteristics (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Input Leakage Current Symbol Minimum Maximum Unit Note IIL -18 +18 μA 1,2 IOL -10 +10 μA 2,3 (Any input 0 V < VIN < VDD) Output Leakage Current (0V < VOUT < VDDQ) Notes: 1) All other pins not under test = 0 V 2) Values are shown per pin 3) DQ, DQS, DQS and ODT are disabled Document 06591, Revision A, 6-Jul-2010, Dataram Corporation © 2010 Page 5 DTM64343A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 VLP DIMM IDD Specifications and Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Operating One Bank ActivePrecharge Current Operating One Bank Active-ReadPrecharge Current Precharge PowerDown Current Precharge PowerDown Current Precharge Quiet Standby Current Precharge Standby Current Active Power-Down Current Active Standby Current Operating Burst Write Current Operating Burst Read Current Burst Refresh Current Self Refresh Current Operating Bank Interleave Read Current Symbol Test Condition Max Value Unit IDD0* Operating current : One bank ACTIVATE-to-PRECHARGE 1035 mA IDD1* Operating current : One bank ACTIVATE-to-READ-toPRECHARGE 1125 mA IDD2P** Precharge power down current: (Slow exit) 216 mA IDD2P** Precharge power down current: (Fast exit) 630 mA IDD2Q** Precharge quiet standby current 900 mA IDD2N** Precharge standby current 900 mA IDD3P** Active power-down current 630 mA IDD3N** Active standby current 1080 mA IDD4W* Burst write operating current 1755 mA IDD4R* Burst read operating current 1710 mA IDD5B** Refresh current 3780 mA IDD6** Self-refresh temperature current: MAX TC = 85°C 270 mA IDD7* All bank interleaved read current 2385 mA * One module rank in this operation the rest in IDD2P slow exit. ** All module ranks in this operation. Document 06591, Revision A, 6-Jul-2010, Dataram Corporation © 2010 Page 6 DTM64343A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 VLP DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit Internal read command to first data tAA 13.125 20 ns CAS-to-CAS Command Delay tCCD 4 - tCK tCH(avg) 0.47 0.53 tCK tCK 1.5 1.875 ns tCL(avg) 0.47 0.53 tCK tDH 65 - ps Clock High Level Width Clock Cycle Time Clock Low Level Width Data Input Hold Time after DQS Strobe tDIPW 400 - ps DQS Output Access Time from Clock tDQSCK -255 +255 ps Write DQS High Level Width tDQSH 0.45 0.55 tCK(avg) Write DQS Low Level Width tDQSL 0.45 0.55 tCK(avg) DQS-Out Edge to Data-Out Edge Skew tDQSQ - 125 ps Data Input Setup Time Before DQS Strobe tDS 30 - ps DQS Falling Edge from Clock, Hold Time tDSH 0.2 - tCK(avg) DQS Falling Edge to Clock, Setup Time tDSS 0.2 - tCK(avg) Clock Half Period tHP minimum of tCH or tCL - ns Address and Command Hold Time after Clock tIH 140 - ps DQ Input Pulse Width tIS 65 - ps Load Mode Command Cycle Time tMRD 4 - tCK DQ-to-DQS Hold tQH 0.38 - tCK(avg) Active-to-Precharge Time tRAS 36 9*tREFI ns Active-to-Active / Auto Refresh Time tRC 49.125 - ns RAS-to-CAS Delay tRCD 13.125 - ns - 7.8 μs Address and Command Setup Time before Clock o o tREFI o o Average Periodic Refresh Interval 0 C < TCASE < 95 C tREFI - 3.9 μs Auto Refresh Row Cycle Time tRFC 160 - ns Row Precharge Time tRP 13.125 - ns Read DQS Preamble Time tRPRE 0.9 Note-1 tCK(avg) Read DQS Postamble Time tRPST 0.3 Note-2 tCK(avg) Row Active to Row Active Delay tRRD Max(4nCK, 6ns) - ns Internal Read to Precharge Command Delay tRTP Max(4nCK, 7.5ns) - ns Average Periodic Refresh Interval 0 C < TCASE < 85 C Write DQS Preamble Setup Time tWPRE 0.9 - tCK(avg) Write DQS Postamble Time tWPST 0.3 - tCK(avg) Write Recovery Time tWR 15 - ns Internal Write to Read Command Delay tWTR Max(4nCK, 7.5ns) - ns Notes: 1. 2. The maximum preamble is bound by tLZDQS(min) The maximum postamble is bound by tHZDQS(max) Document 06591, Revision A, 6-Jul-2010, Dataram Corporation © 2010 Page 7 DTM64343A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 VLP DIMM SERIAL PRESENCE DETECT MATRIX Byte# Function Value 1 Number of Bytes Used / Number of Bytes in SPD Device / CRC Coverage. Bit 3 ~ Bit 0. SPD Bytes Used 176 Bit 6 ~ Bit 4. SPD Bytes Total 256 Bit 7. CRC Coverage Bytes 0-116 SPD Revision Rev. 1.0 2 Key Byte / DRAM Device Type 0 3 4 5 6 7 8 9 Key Byte / Module Type Bit 3 ~ Bit 0. Module Type Bit 7 ~ Bit 4. Reserved SDRAM Density and Banks Bit 3 ~ Bit 0. Total SDRAM capacity, in megabits Bit 6 ~ Bit 4. Bank Address Bits Bit 7. Reserved SDRAM Addressing Bit 2 ~ Bit 0. Column Address Bits Bit 5 ~ Bit 3. Row Address Bits Bit 7, 6. Reserved Reserved. Module Organization Bit 2 ~ Bit 0. SDRAM Device Width Bit 5 ~ Bit 3. Number of Ranks Bit 7, 6. Reserved Module Memory Bus Width Bit 2 ~ Bit 0. Primary bus width, in bits Bit 4, Bit 3. Bus width extension, in bits Bit 7 ~ Bit 5. Reserved Fine Timebase (FTB) Dividend / Divisor Bit 3 ~ Bit 0. Fine Timebase (FTB) Divisor Bit 7 ~ Bit 4. Fine Timebase (FTB) Dividend Hex 92 10 DDR3 SDRAM 0B RDIMM 0 01 2Gb 8 banks 0 03 10 15 0 UNUSED 19 00 8-Bits 2-Rank 0 09 64-Bits 8-Bits 0 0B 52 0C 00 10 Medium Timebase (MTB) Dividend 11 Medium Timebase (MTB) Divisor 12 SDRAM Minimum Cycle Time (tCKmin) 2 5 1 (MTB = 0.125ns) 8 (MTB = 0.125ns) 1.5ns 13 Reserved UNUSED 01 08 CAS Latencies Supported, Least Significant Byte 14 Document 06591, Revision A, 6-Jul-2010, Dataram Corporation © 2010 Bit 0. CL = 4 Bit 1. CL = 5 Bit 2. CL = 6 Bit 3. CL = 7 Bit 4. CL = 8 Bit 5. CL = 9 Bit 6. CL = 10 Bit 7. CL = 11 - X X X X 3C Page 8 DTM64343A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 VLP DIMM CAS Latencies Supported, Most Significant Byte Bit 0. CL = 12 Bit 1. CL = 13 Bit 2. CL =14 Bit 3. CL = 15 Bit 4. CL = 16 Bit 5. CL = 17 Bit 6. CL = 18 Bit 7. Reserved. 15 16 Minimum CAS Latency Time (tAAmin) 17 Minimum Write Recovery Time (tWRmin) 00 13.125ns 69 15.0ns 78 13.125ns 69 6.0ns 30 13.125ns 69 Bit 3 ~ Bit 0. tRAS Most Significant Nibble - 1 11 Bit 7 ~ Bit 4. tRC Most Significant Nibble Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte. Minimum Internal Write to Read Command Delay Time (tWTRmin) Minimum Internal Read to Precharge Command Delay Time (tRTPmin) Upper Nibble for tFAW 1 18 Minimum RAS# to CAS# Delay Time (tRCDmin) 19 Minimum Row Active to Row Active Delay Time (tRRDmin) 20 Minimum Row Precharge Delay Time (tRPmin) Upper Nibbles for tRAS and tRC 21 22 23 24 25 26 27 28 29 30 31 36.0ns 20 49.125ns 89 160.0ns 00 160.0ns 05 7.5ns 3C 7.5ns 3C Bit 3 ~ Bit 0. tFAW Most Significant Nibble - 0 00 Bit 7 ~ Bit 4. Reserved Minimum Four Activate Window Delay Time (tFAWmin), Least Significant Byte SDRAM Optional Features Bit 0. RZQ / 6 Bit 1. RZQ / 7 Bit 6 ~ Bit 2. Reserved Bit 7. DLL-Off Mode Support SDRAM Drivers Supported Extended Temperature Range Extended Temperature Refresh Rate Auto Self Refresh (ASR) On-die Thermal Sensor (ODTS) Readout Reserved Reserved Reserved Reserved - 0 Document 06591, Revision A, 6-Jul-2010, Dataram Corporation © 2010 30ns F0 X X 83 X 01 Page 9 DTM64343A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 VLP DIMM Module Thermal Sensor 32 Bit 7. Thermal sensor incorporated onto this assembly Bit 6 ~ Bit 0. Undefined 33-59 60 61 62 63 64 65-66 67 68, 69 70 71-116 117 118 119 120,121 122-125 126 127 128-131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 Reserved X 80 UNUSED UNUSED 00 17 < h ≤ 18 0 03 1 < th ≤ 2 1 < th ≤ 2 11 R/C L Rev.0 0 0A 1 1 not installed 05 00 Module-Specific Section UNUSED 00 Register Revision Number UNUSED 00 Module-Specific Section UNUSED 00 Drive Strength, Command/Address moderate 50 Module-Specific Section Module Manufacturer ID Code, Least Significant Byte Module Manufacturer ID Code, Most Significant Byte Module Manufacturing Location Module Manufacturing Date Module Serial Number Cyclical Redundancy Code (CRC) Cyclical Redundancy Code (CRC) Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number Module Part Number UNUSED 00 01 91 00 ## ## B7 2B 20 44 41 54 41 52 41 4D 20 36 34 33 34 33 20 Module Nominal Height Bit 4 ~ Bit 0. Module Nominal Height max, in mm Bit 7 ~ Bit5. Reserved Module Maximum Thickness Bit 3 ~ Bit 0. Front, in mm (baseline thickness = 1 mm) Bit 7 ~ Bit 4. Back, in mm (baseline thickness = 1 mm) Reference Raw Card Used Bit 4 ~ Bit 0. Reference Raw Card Bit 6, Bit 5. Reference Raw Card Revision Bit 7. Reserved Registered DIMM Module Attributes Bits [3:2]. # of rows of DRAMs on RDIMM Bits [1:0]. # of registers on RDIMM RDIMM Thermal Heat Spreader Solution Document 06591, Revision A, 6-Jul-2010, Dataram Corporation © 2010 Dataram UNUSED [date code] [serial number] CRC [space] D A T A R A M [space] 6 4 3 4 3 [space] Page 10 DTM64343A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 VLP DIMM 146,147 148 149 150-175 176-255 Module Revision Code DRAM Manufacturer ID Code, Least Significant Byte DRAM Manufacturer ID Code, Most Significant Byte Manufacturer’s Specific Data Open for customer use Document 06591, Revision A, 6-Jul-2010, Dataram Corporation © 2010 [unused] UNUSED UNUSED UNUSED UNUSED 20 00 00 00 00 Page 11 DTM64343A 4GB - 240-Pin 2Rx8 Registered ECC DDR3 VLP DIMM DATARAM CORPORATION, USA Corporate Headquarters, P.O.Box 7528, Princeton, NJ 08543-7528; Voice: 609-799-0071, Fax: 609-799-6734; www.dataram.com All rights reserved. The information contained in this document has been carefully checked and is believed to be reliable. However, Dataram assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Dataram. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Dataram. Document 06591, Revision A, 6-Jul-2010, Dataram Corporation © 2010 Page 12
