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Download Dataram DTM63372A memory module
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DTM63372 1GB - 128Mx64, 240-Pin Unbuffered non-ECC DDR2 DIMM Identification DTM63372 128Mx64 Performance range Clock/ Module Speed/ CL-tRCD -tRP 333MHz/ DDR2-667/ 5-5-5 267MHz/ DDR2-533/ 4-4-4 Features Description 240-pin JEDEC-compliant DIMM, 133.35 mm wide by 30 mm high Operating Voltage: 1.8 V ±0.1 DTM63372 is an Unbuffered non-ECC 128Mx64 memory module, which conforms to JEDEC's DDR2, PC2-5300 standard. The assembly is comprised of one Rank of eight 128Mx8 DDR2 SDRAMs. One 2K-bit EEPROM is used for Serial Presence Detect. Both output driver strength and input termination impedance are programmable to maintain signal integrity on the I/O signals. I/O Type: SSTL_18 Data Transfer Rate: 5.3 Gigabytes/sec Data Bursts: 4 or 8 bits, Sequential or Interleaved ordering Programmable I/O driver strength (OCD) Programmable On-Die Termination (ODT) Programmable CAS Latency: 4 or 5 Differential/Redundant Data Strobe signals SDRAM Addressing (Row/Col/Bank): 14/10/3 Fully ROHS Compliant Pin Configuration Front Side Pin Description Back Side 1 VREF 31 DQ19 61 A4 91 VSS 2 VSS 32 VSS 62 VDD 3 4 5 6 DQ0 DQ1 VSS /DQS0 33 DQ24 34 DQ25 35 VSS 36 /DQS3 7 DQS0 8 VSS 9 DQ2 121 VSS Name Function Data Check Bits 151 VSS 181 VDD 211 DM5 CB[7:0] 92 /DQS5 122 DQ4 152 DQ28 182 A3 212 NC DQ[63:0] Data Bits 63 A2 64 VDD 65 VSS 66 VSS 93 94 95 96 153 154 155 156 183 184 185 186 213 214 215 216 DQS[8:0], /DQS[8:0] DM[8:0} CK[2:0], /CK[2:0] CKE[1:0] Differential Data Strobes Data Mask Differential Clock Inputs Clock Enables 37 DQS3 38 VSS 39 DQ26 67 VDD 68 NC 69 VDD 97 VSS 98 DQ48 99 DQ49 127 VSS 128 DQ6 129 DQ7 157 VSS 158 DQ30 159 DQ31 217 DQ52 218 DQ53 219 VSS /CAS /RAS /S[1:0] Column Address Strobe Row Address Strobe Chip Selects 10 DQ3 11 VSS 12 DQ8 40 DQ27 41 VSS 42 CB0/NC 70 A10 71 BA0 72 VDD 100 VSS 101 SA2 102 NC 130 VSS 131 DQ12 132 DQ13 160 VSS 190 BA1 161 CB4/NC 191 VDD 162 CB5/NC 192 /RAS 220 CK2 221 /CK2 222 VSS /WE A[15:0] BA[2:0] Write Enable Address Inputs Bank Addresses 13 DQ9 43 CB1/NC 73 /WE 103 VSS 133 VSS 163 VSS 193 /S0 223 DM6 ODT[1:0] On Die Termination Inputs 14 VSS 15 /DQS1 16 DQS1 17 VSS 44 VSS 74 /CAS 104 45 /DQS8/NC 75 VDD 105 46 DQS8/NC 76 /S1 106 47 VSS 77 ODT1/NC 107 134 135 136 137 164 165 166 167 194 195 196 197 224 225 226 227 SA[2:0] SCL SDA VSS SPD Address SPD Clock Input SPD Data Input/Output Ground 18 NC 19 NC 20 VSS 48 CB2/NC 49 CB3/NC 50 VSS DQS5 123 DQ5 VSS 124 VSS DQ42 125 DM0 DQ43 126 NC /DQS6 DQS6 VSS DQ50 DM1 NC VSS CK1 DQ29 VSS DM3 NC DM8/NC NC VSS CB6/NC A1 VDD CK0 /CK0 187 VDD 188 A0 189 VDD VDD ODT0 A13 VDD VSS DQ46 DQ47 VSS NC VSS DQ54 DQ55 78 VDD 79 VSS 80 DQ32 108 DQ51 109 VSS 110 DQ56 138 /CK1 139 VSS 140 DQ14 168 CB7/NC 198 VSS 169 VSS 199 DQ36 170 VDD 200 DQ37 228 VSS 229 DQ60 230 DQ61 VDD VDDSPD VREF Power SPD EEPROM Power Reference Voltage NC No Connection 21 DQ10 51 VDD 81 DQ33 111 DQ57 141 DQ15 171 CKE1/NC 201 VSS 231 VSS 22 DQ11 23 VSS 24 DQ16 25 DQ17 26 VSS 27 /DQS2 52 CKE0 53 VDD 54 BA2 55 NC 56 VDD 57 A11 82 VSS 83 /DQS4 84 DQS4 85 VSS 86 DQ34 87 DQ35 112 113 114 115 116 117 142 143 144 145 146 147 172 173 174 175 176 177 232 233 234 235 236 237 28 DQS2 58 A7 88 VSS 29 VSS 59 VDD 89 DQ40 30 DQ18 60 A5 90 DQ41 * Connected but not used VSS /DQS7 DQS7 VSS DQ58 DQ59 VSS DQ20 DQ21 VSS DM2 NC VDD A15 * A14 * VDD A12 A9 202 203 204 205 206 207 DM4 NC VSS DQ38 DQ39 VSS DM7 NC VSS DQ62 DQ63 VSS 118 VSS 148 VSS 178 VDD 208 DQ44 238 VDDSPD 119 SDA 120 SCL 149 DQ22 150 DQ23 179 A8 180 A6 209 DQ45 210 VSS 239 SA0 240 SA1 Document 06504, Revision A, 10-Feb-09, Dataram Corporation © 2009 Page 1 DTM63372 1GB - 128Mx64, 240-Pin Unbuffered non-ECC DDR2 DIMM Front view 133.35 [5.250] 30.00 [1.181] 10.00 [0.394] 4.00 [0.157] 17.80 [0.700] 5.00 [0.197] 5.18 [0.204] 63.00 [2.480] 55.00 [2.165] 2.54 Min [0.100 Min] 123.00 [4.843] Back view Side view 2.67Max [0.105] Max 4.00 Min [0.157] Min 1.27 ±.10 [0.0500 ±0.0040] Notes Tolerances on all dimensions except where otherwise indicated are ± .13 (.005). All dimensions are expressed: millimeters [inches] Document 06504, Revision A, 10-Feb-09, Dataram Corporation © 2009 Page 2 DTM63372 1GB - 128Mx64, 240-Pin Unbuffered non-ECC DDR2 DIMM /S0 DMR0 DQSR0 /DQSR0 DMR4 DQSR4 /DQSR4 /DQS DQS CS /CS DM /DQS I/O[7:0] DQR[7:0] DQR[39:32] DMR1 DQSR1 /DQSR1 DQS CS /CS DM DQS CS /CS DM DQS CS /CS DM DQS CS /CS DM I/O[7:0] DMR5 DQSR5 /DQSR5 /DQS DQR[15:8] DQS CS /CS DM /DQS DQR[47:40] I/O[7:0] DMR2 DQSR2 /DQSR2 I/O[7:0] DMR6 DQSR6 /DQSR6 /DQS DQR[23:16] DQS CS /CS DM /DQS DQR[55:48] I/O[7:0] DMR3 DQSR3 /DQSR3 I/O[7:0] DMR7 DQSR7 /DQSR7 /DQS DQS CS /CS DM /DQS I/O[7:0] DQR[31:24] DQR[63:56] I/O[7:0] 67 OHMS DQ(63:0) DQR(63:0) CK0 DQS(7:0) DQSR(7:0) /CK0 /DQS(7:0) /DQRS(7:0) DM(7:0) SDRAM X 2 67 OHMS DMR(7:0) CK1 SDRAM X 3 /CK1 67 OHMS GLOBAL SDRAM CONNECTS BA(2:0) BA(2:0)R A(13:0) A(13:0)R /RAS /CAS /RASR /CASR /WE /WER CKE0 CKE0 22 pF CK2 /CK2 SDRAM X 3 DECOUPLING V DDSPD V DD VREF V SS Serial PD All Devices All SDRAMs All Devices ODT0 ODT0 22 pF SCL /S0 /S0 22 pF Document 06504, Revision A, 10-Feb-09, Dataram Corporation © 2009 WP SERIAL PD SDA SA0 SA1 SA2 Page 3 DTM63372 1GB - 128Mx64, 240-Pin Unbuffered non-ECC DDR2 DIMM Absolute Maximum Ratings (Note: Operation at or above Absolute Maximum Ratings can adversely affect module reliability.) PARAMETER Symbol Minimum Maximum Unit Temperature, non-Operating TSTORAGE -55 100 C TA 0 70 C TCASE 0 95* C VDD -0.5 2.3 V VIN,VOUT -0.5 2.3 V Ambient Temperature, Operating DRAM Case Temperature, Operating Voltage on VDD relative to VSS Voltage on Any Pin relative to VSS * DRAM Operating Case Temperature above 85C requires 2X refresh. Recommended DC Operating Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Power Supply Voltage Symbol VDD Minimum 1.7 Typical 1.8 Maximum 1.9 Unit V Note I/O Reference Voltage VREF 0.49 VDD 0.50 VDD 0.51 VDD V 1 Bus Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V Notes: 1. The value of VREF is expected to equal one-half VDD and to track variations in the VDD DC level. Peak-to-peak noise on VREF may not exceed ±1% of its DC value. DC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Logical High (Logic 1) Symbol VIH(DC) Minimum VREF + 0.125 Maximum VDD + 0.300 Unit V Logical Low (Logic 0) VIL(DC) -0.300 VREF - 0.125 V AC Input Logic Levels, Single-Ended (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Logical High (Logic 1) Symbol VIH(AC) Minimum VREF + 0.250 Maximum - Unit V Logical Low (Logic 0) VIL(AC) - VREF - 0.250 V Document 06504, Revision A, 10-Feb-09, Dataram Corporation © 2009 Page 4 DTM63372 1GB - 128Mx64, 240-Pin Unbuffered non-ECC DDR2 DIMM Differential Input Logic Levels (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER DC Input Signal Voltage Symbol VIN(DC) Minimum -0.300 Maximum VDD + 0.300 Unit V Note 1 DC Differential Input Voltage VID(DC) -0.250 VDD + 0.600 V 2 AC Differential Input Voltage VID(AC) -0.500 VDD + 0.600 V 3 AC Differential Cross-Point Voltage VIX(AC) 0.50 VDD - 0.175 0.50 VDD + 0.175 V 4 Notes: 1. VIN(DC) specifies the allowable DC excursion of each input of a differential pair. 2. VID(DC) specifies the input differential voltage, i.e. the absolute value of the difference between the two voltages of a differential pair. 3. VID(AC) specifies the input differential voltage required for switching. 4. The typical value of VIX(AC) is expected to be 0.5 VDD and is expected to track variations in VDD. Capacitance (TA = 25 C, f = 100 MHz) PARAMETER Pin Symbol Min. Max. Unit Input Capacitance, Clock CK0, /CK0, CK1, /CK1, CK2, /CK2 CIN1 6 12 pF Input Capacitance, Address and Control BA[2:0], A[13:0], /S0, /RAS, /CAS, /WE, CKE0, ODT0 CIN2 18 36 pF Input/Output Capacitance DQ[63:0], DQS[7:0], /DQS[7:0], DM[7:0] CIO 6 8 pF DC Characteristics (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Symbol Minimum Maximum Unit Note Input Leakage Current Command and Address ILI -80 80 μA 1 Input Leakage Current S[1:0],CKE[1:0], ODT[1:0] ILI -40 40 μA 1 Input Leakage Current CK[2:0], /CK[2:0] ILI -30 30 μA 1 Input Leakage Current DM ILI -10 10 μA 1 Output Leakage Current DQS, DQ IOZ -10 10 μA 2 Output Minimum Source DC Current IOH -13.4 - mA 3 Output Minimum Sink DC Current IOL +13.4 - mA 4 Notes: 1. 2. 3. 4. These values are guaranteed by design and are tested on a sample basis only DQx and ODT are disabled, and 0 V ≤ VOUT ≤ VDD. VDD = 1.7 V, VOUT = 1420 mV. (VOUT - VDD)/IOH must be less than 21 Ohms for values of VOUT between VDD and (VDD - 280 mV). VDD = 1.7 V, VOUT = 280 mV. VOUT/IOL must be less than 21 Ohms for values of VOUT between 0 V and 280 mV. Document 06504, Revision A, 10-Feb-09, Dataram Corporation © 2009 Page 5 DTM63372 1GB - 128Mx64, 240-Pin Unbuffered non-ECC DDR2 DIMM IDD Specifications and Conditions (TA = 0 to 70 C, Voltage referenced to Vss = 0 V) PARAMETER Operating One Bank ActivePrecharge Current Operating One Bank Active-ReadPrecharge Current Precharge PowerDown Current Precharge Quiet Standby Current Precharge Standby Current Symbol Test Condition Max Value Unit IDD0 CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching. 560 mA IDD1 IOUT = 0 mA; BL = 4, CL = 5, AL = 0; CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are switching. 640 mA 80 mA 240 mA 320 mA 200 mA 96 mA 400 mA 1200 mA 1200 mA 1400 mA 80 mA 1440 mA IDD2P IDD2Q IDD2N Active Power-Down Current IDD3P Active Power-Down Current IDD3P Active Standby Current IDD3N Operating Burst Write Current IDD4W Operating Burst Read Current IDD4R Burst Refresh Current IDD5 Self Refresh Current IDD6 Operating Bank Interleave Read Current IDD7 All banks idle; CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating. All banks idle; CKE is HIGH, /CS is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating. All banks idle; CKE is HIGH, /CS is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching. All banks open; CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating. Fast Power-down exit (Mode Register bit 12 = 0) All banks open; CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating. Slow Power-down exit (Mode Register bit 12 = 1) All banks open; tRAS = 70 ms; CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching. All banks open, Continuous burst writes; BL = 4, CL = 5 tCK, AL = 0; tRAS = 70 ms, CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching. All banks open, Continuous burst reads, IOUT = 0 mA; BL = 4, CL = 5 tCK, AL = 0, tRAS = 70 ms; CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching. Refresh command at every 75 ns; CKE is HIGH, /CS is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching. CK and /CK at 0 V; CKE ≤ 0.2 V; Other control and address bus inputs are floating; Data bus inputs are floating. All bank interleaving reads, IOUT= 0 mA; BL = 4, CL = 5 tCK; AL = 70 ns; tRRD = 7.5 ns; CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching. Notes: For all IDDX measurements, tCK = 3 ns, tRC = 60 ns, tRCD = 15 ns, tRAS = 45 ns, and tRP = 15 ns unless otherwise specified. All currents are based on DRAM absolute maximum values. . Document 06504, Revision A, 10-Feb-09, Dataram Corporation © 2009 Page 6 DTM63372 1GB - 128Mx64, 240-Pin Unbuffered non-ECC DDR2 DIMM AC Operating Conditions PARAMETER Symbol Min Max Unit DQ Output Access Time from Clock tAC -450 +450 ps CAS-to-CAS Command Delay tCCD 2 - tCK Clock High Level Width tCH 0.45 0.55 tCK Clock Cycle Time tCK 3000 8000 ps Clock Low Level Width tCL 0.45 0.55 tCK Data Input Hold Time after DQS Strobe tDH 175 - ps tDIPW 0.35 - tCK DQS Output Access Time from Clock tDQSCK -400 +400 ps Write DQS High Level Width tDQSH 0.35 - tCK Write DQS Low Level Width tDQSL 0.35 - tCK DQS-Out Edge to Data-Out Edge Skew tDQSQ 240 - ps Data Input Setup Time Before DQS Strobe tDS 100 - ps DQS Falling Edge from Clock, Hold Time tDSH 0.2 - tCK DQS Falling Edge to Clock, Setup Time tDSS 0.2 - tCK Clock Half Period tHP minimum of tCH or tCL - ns Address and Command Hold Time after Clock tIH 275 - ps DQ Input Pulse Width tIS 200 - ps Load Mode Command Cycle Time tMRD 2 - tCK DQ-to-DQS Hold tQH tHP - tQHS - - Data Hold Skew Factor tQHS - 400 ps Active-to-Precharge Time tRAS 45 70K ns Active-to-Active / Auto Refresh Time tRC 60 - ns RAS-to-CAS Delay tRCD 15 - ns Average Periodic Refresh Interval tREFI - 7.8 μs Auto Refresh Row Cycle Time tRFC 127.5 - ns Row Precharge Time tRP 15 - ns Read DQS Preamble Time tRPRE 0.9 1.1 tCK Read DQS Postamble Time tRPST 0.4 0.6 tCK Row Active to Row Active Delay tRRD 7.5 - ns Internal Read to Precharge Command Delay tRTP 7.5 - ns Write DQS Preamble Setup Time tWPRE 0.35 - ps Write DQS Postamble Time tWPST 0.4 0.6 tCK Write Recovery Time tWR 15 - ns Internal Write to Read Command Delay tWTR 7.5 - ns Exit Self Refresh to Non-Read Command tXSNR tRFC(min) + 10 - ns Exit Self Refresh to Read Command tXSRD 200 - tCK Address and Command Setup Time before Clock Document 06504, Revision A, 10-Feb-09, Dataram Corporation © 2009 Page 7 DTM63372 1GB - 128Mx64, 240-Pin Unbuffered non-ECC DDR2 DIMM SERIAL PRESENCE DETECT MATRIX Byte# Function. Value Hex 0 Number of Bytes Utilized by Module Manufacturer 128 bytes 0x80 1 Total number of Bytes in Serial PD device 256 bytes 0x08 2 Memory Type DDR2 SDRAM 0x08 3 Number of Row Addresses 14 0x0E 4 5 10 0x0A 0x60 6 Number of Column Addresses Module Attributes - Number of Ranks, Package and Height # of Ranks Card on Card DRAM Package Module Height Module Data Width. 7 Reserved 8 9 Voltage Interface Level of this assembly SDRAM Cycle time. (Max. Supported CAS Latency). CL=X (tCK) ns SDRAM Access from Clock. (Highest CAS latency). (tAC) ns 10 11 12 DIMM configuration type (Non-parity, Parity or ECC) Data Parity Data ECC Address/Command Parity TBD TBD TBD TBD TBD Refresh Rate/Type (us) 13 Primary SDRAM Width 14 1 No Planar 30mm 72 0x48 UNUSED 0x00 SSTL/1.8V 3.0 0x05 0x30 0.45 0x45 0x00 7.8 (SR) 0x82 8 0x08 Error Checking SDRAM Width UNUSED 0x00 15 Reserved UNUSED 0x00 16 SDRAM Device Attributes: Burst Lengths Supported 17 18 TBD TBD Burst Length = 4 Burst Length = 8 TBD TBD TBD TBD SDRAM Device Attributes - Number of Banks on SDRAM Device SDRAM Device Attributes: CAS Latency TBD TBD Latency = 2 Latency = 3 - Document 06504, Revision A, 10-Feb-09, Dataram Corporation © 2009 0x0C X X 8 0x08 0x30 Page 8 DTM63372 1GB - 128Mx64, 240-Pin Unbuffered non-ECC DDR2 DIMM 19 20 21 22 23 24 25 26 Latency = 4 X Latency = 5 X Latency = 6 TBD DIMM Mechanical Characteristics. Max. module thickness. x </= 4.10 (mm) DIMM type information Regular RDIMM (133.35mm) Regular UDIMM (133.35mm) X SODIMM (67.6mm) Micro-DIMM (45.5mm) Mini RDIMM (82.0mm) Mini UDIMM (82.0mm) TBD TBD SDRAM Module Attributes (Refer to Byte20 for DIMM type information). Number of active registers on the DIMM (N/A for UDIMM) 1 Number of PLL on the DIMM (N/A for UDIMM) 0 FET Switch External Enable No TBD Analysis probe installed No TBD SDRAM Device Attributes: General Includes Weak Driver X Supports 50 ohm ODT X Supports PASR (Partial Array Self Refresh) TBD TBD TBD TBD TBD Minimum Clock Cycle Time at Reduced CAS Latency, CL = X3.75 1 (ns) Maximum Data Access Time (tAC ) from Clock at CL = X- 1 0.40 (ns) Minimum Clock Cycle Time at CL = X-2 (ns) 0x01 0x02 0x00 0x03 0x3D 0x40 0x00 27 Maximum Data Access Time (tAC ) from Clock at CL = X-2 (ns) Minimum Row Precharge Time (tRP ) (ns) 0x00 15 0x3C 28 29 Minimum Row Active to Row Active Delay (tRRD ) (ns) Minimum RAS to CAS Delay (tRCD ) (ns) 7.5 15 0x1E 0x3C 30 Minimum Active to Precharge Time (tRAS ) (ns) 45 0x2D 31 Module Rank Density 1GB 0x01 32 33 34 35 36 37 38 Address and Command Setup Time Before Clock (tIS) (ns) Address and Command Hold Time After Clock (tIH) (ns) Data Input Setup Time Before Strobe (tDS) (ns) Data Input Hold Time After Strobe (tDH) (ns) Write Recovery Time (tWR ) (ns) Internal write to read command delay (tWTR ) (ns) Internal read to precharge command delay (tRTP ) (ns) 0.2 0.28 0.1 0.18 15 7.5 7.5 0x20 0x28 0x10 0x18 0x3C 0x1E 0x1E Document 06504, Revision A, 10-Feb-09, Dataram Corporation © 2009 Page 9 DTM63372 1GB - 128Mx64, 240-Pin Unbuffered non-ECC DDR2 DIMM 39 40 41 42 43 44 45 46 47 48 49 Memory Analysis Probe Characteristics. Extension of Byte 41(tRC) and Byte 42 (tRFC) (ns) Add this value to byte 41 Add this value to byte 42 SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) (ns) SDRAM Device Minimum Auto-Refresh to Active/AutoRefresh Command Period (tRFC). (ns) SDRAM Device Maximum Cycle Time (tCK max). (ns) UNUSED 0 .5 60 0x3C 127.5 0x7F 8 0x80 SDRAM Dev DQS-DQ Skew for DQS & DQ signals (tDQSQ) 0.24 (ns) DDR SDRAM Device Read Data Hold Skew Factor (tQHS) 0.34 (ns) PLL Relock Time (us) UNUSED DRAM maximun Case Temperature Delta. (Degree C). DT4R4W Delta (Bits 0:3) 0.4 Tcasemax delta (Bits 7:4) 10 Thermal Resistance of DRAM Package from Top (Case) to 58 Ambient ( Psi T-A DRAM ). (C/Watt) DRAM Case Temperature Rise from Ambient due to Activate-Precharge/ Mode Bits (DT0/Mode Bits). (Degree C). Bit 0. If "0" DRAM does not support high temperature selfrefresh entry Bit 1. If "0" Do not need double refresh rate for the proper operation DT0, (Bits 2:7) - 0x00 0x06 0x18 0x22 0x00 0x51 0x74 0x57 1 1 6.3 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q). (Degree C). 6 0x3C 51 DRAM Case Temperature Rise from Ambient due to Precharge Power-Down (DT2P). (Degree C). 1.44 0x60 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N). (Degree C). 6.9 0x2E 53 DRAM Case temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3Pfast). (Degree C). 4.4 0x58 54 DRAM Case temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3Pslow). (Degree C). 2.2 0x58 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit). (Degree C). Bit 0. "0" if DT4W is greater than DT4R DT4R, ( Bits 1:7 ) - 0x4A 0 14.8 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B). (Degree C). 24.5 0x31 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7). (Degree C). 26.5 0x35 58 Thermal Resistance of PLL Package from Top to Ambient (Psi T-A PLL). (C/Watt). UNUSED 0x00 Document 06504, Revision A, 10-Feb-09, Dataram Corporation © 2009 Page 10 DTM63372 1GB - 128Mx64, 240-Pin Unbuffered non-ECC DDR2 DIMM 59 Thermal Resistance of Register Package from Top to Ambient ( Psi T-A Register). (C/Watt). UNUSED 0x00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active). (Degree C). UNUSED 0x00 61 Register Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit). Bit 0.If "0"Unit for Bits 2:7 is 0.75C Bit 1. RFU. Default: 0 Register Active,( Bits 2:7 ) - 62 63 64 65 66-71 72 73-90 91,92 93,94 95 96 97 98 99127 SPD Revision Checksum for Bytes 0-62 Module Manufacturer’s JEDEC ID Code Module Manufacturer’s JEDEC ID Code Module Manufacturer’s JEDEC ID Code Module Manufacturing Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number Module Serial Number Module Serial Number Module Serial Number Manufacturer’s Specific Data Document 06504, Revision A, 10-Feb-09, Dataram Corporation © 2009 0.75 0 0 Revision 1.2 Dataram ID Dataram ID UNUSED UNUSED UNUSED UNUSED S E R # UNUSED 0x00 0x12 0x9D 0x7F 0x91 0x00 0x00 0x20 0x00 0x00 0x53 0x45 0x52 0x23 0x00 Page 11 DTM63372 1GB - 128Mx64, 240-Pin Unbuffered non-ECC DDR2 DIMM DATARAM CORPORATION, USA Corporate Headquarters, P.O.Box 7528, Princeton, NJ 08543-7528; Voice: 609-799-0071, Fax: 609-799-6734; www.dataram.com All rights reserved. The information contained in this document has been carefully checked and is believed to be reliable. However, Dataram assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Dataram. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Dataram. Document 06504, Revision A, 10-Feb-09, Dataram Corporation © 2009 Page 12
