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Electrical Specifications
Table 2-8. Voltage and Current Specifications
Symbol
VID range
Parameter
Min
Typ
Max
Unit
Notes1
VID
1.200
—
1.425
V
2
Refer to Table 2-10 and
Figure 2-3
V
3, 4, 5, 6
Refer to Table 2-9 and
Figure 2-2
V
3, 4, 6, 7,
8
A
9
A
10, 11, 15
VCC for
775_VR_CONFIG_04B
processors
VCC
3.80F GHz (PRB = 1)
3.60F GHz (PRB = 1)
3.40F GHz (PRB = 1)
VCC
VCC for
775_VR_CONFIG_04A
processors
3.20F GHz (PRB = 0)
ICC for processor with
multiple VID
3.80F GHz (PRB = 1)
ICC
3.60F GHz (PRB = 1)
—
—
119
119
3.40F GHz (PRB = 1)
119
3.20F GHz (PRB = 0)
78
ICC Stop-Grant
ISGNT
3.80F GHz (PRB = 1)
3.60F GHz (PRB = 1)
—
—
3.40F GHz (PRB = 1)
56
56
56
3.20F GHz (PRB = 0)
40
—
—
ICC
A
12
1.14
1.20
1.26
V
13, 14
DC Current that may be
drawn from VTT_OUT per
pin
—
—
580
mA
ITT
FSB termination current
—
—
3.5
A
15, 16
ICC_VCCA
ICC FOR PLL LANDS
—
—
120
mA
15
ICC_VCCIOPLL
ICC FOR I/O PLL LAND
—
—
100
mA
15
ICC_GTLREF
ICC for GTLREF
—
—
200
µA
15
ITCC
ICC TCC active
VTT
FSB termination voltage
(DC+AC specifications)
VTT_OUT ICC
NOTES:
1.
2.
3.
4.
5.
Datasheet
Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical
data. These specifications will be updated with characterized data from silicon measurements at a later date.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such
that two processors at the same frequency may have different settings within the VID range. Please note this
differs from the VID employed by the processor during a power management event (Thermal Monitor 2 or
Enhanced HALT State).
These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.4 and Table 2-2 for more information.
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the
socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external
noise from the system is not coupled into the oscilloscope probe.
Refer to Table 2-10 and Figure 2-3 for the minimum, typical, and maximum VCC allowed for a given current.
The processor should not be subjected to any Vcc and Icc combination wherein VCC exceeds Vcc_max for a
given current.
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