1
Download Supermicro SuperServer 6015V-TB
Transcript
Appendix B: BIOS POST Codes Appendix B BIOS POST Codes This section lists the POST (Power On Self Test) codes for the PhoenixBIOS. POST codes are divided into two categories: recoverable and terminal. Recoverable POST Errors When a recoverable type of error occurs during POST, the BIOS will display an POST code that describes the problem. BIOS may also issue one of the follow- ing beep codes: 1 long and two short beeps - video configuration error 1 repetitive long beep - no memory detected Terminal POST Errors If a terminal type of error occurs, BIOS will shut down the system. Before doing so, BIOS will write the error to port 80h, attempt to initialize video and write the error in the top left corner of the screen. The following is a list of codes that may be written to port 80h. POST Code Description 01h 02h 03h 04h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Eh 0Fh 10h 11h 12h 13h 14h 16h 17h IPMI Initialization Verify Real Mode Disable Non-Maskable Interrupt (NMI) Get CPU type Initialize system hardware Disable shadow and execute code from the ROM. Initialize chipset with initial POST values Set IN POST flag Initialize CPU registers Enable CPU cache Initialize caches to initial POST values Initialize I/O component Initialize the local bus IDE Initialize Power Management Load alternate registers with initial POST values Restore CPU control word during warm boot Reset PCI Bus Mastering devices Initialize keyboard controller 1-2-2-3 BIOS ROM checksum Initialize cache before memory Auto size B-1
