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Download VisualDSP++ 5.0 User`s Guide
Transcript
Simulation of Blackfin Processors Multicycle Instructions Multicycle instructions are a category of instructions that cannot complete in fewer than two cycles. Consequently, the extra cycles generated by such an instruction cannot be removed without removing the multicycle instruction itself. In Figure D-3, multicycle instruction “[--SP] = (R7:6, P5:3)” enters the pipeline Decode stage at cycle 16 and takes five cycles to complete (1 cycle per register to push on the stack SP). The next instruction “R7 = 0” takes only one cycle. Figure D-3. Example of a Multicycle Instruction in the Pipeline Viewer For details about multicycle instructions, see “Multicycle Instructions and Latencies” on page D-22. Abbreviations in Pipeline Viewer Messages Table D-9 shows abbreviations that may appear in the Pipeline Viewer window. VisualDSP++ 5.0 User’s Guide D-17
