Download Data Sheet Final - ADSP-BF50x Blackfin

ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Serial Peripheral Interface (SPI) Port—Master Timing
Table 34 and Figure 23 describe SPI port master operations.
Table 34. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
tSSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
tHSPIDM
Switching Characteristics
tSDSCIM
SPISELx low to First SCK Edge
tSPICHM
Serial Clock High Period
tSPICLM
Serial Clock Low Period
tSPICLK
Serial Clock Period
Last SCK Edge to SPISELx High
tHDSM
tSPITDM
Sequential Transfer Delay
tDDSPIDM
SCK Edge to Data Out Valid (Data Out Delay)
tHDSPIDM
SCK Edge to Data Out Invalid (Data Out Hold)
Min
VDDEXT = 1.8 V
Max
Min
VDDEXT = 2.5 V/3.3 V
Max
11.6
–1.5
9.6
–1.5
ns
ns
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK –1.5
2 × tSCLK –2.0
2 × tSCLK –1.5
0
6
–1.0
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
0
6
–1.0
ns
ns
ns
ns
ns
ns
ns
ns
SPIxSELy
(OUTPUT)
tSDSCIM
tSPICLM
tSPICHM
tSPICLK
tHDSM
SPIxSCK
(OUTPUT)
tDDSPIDM
tHDSPIDM
SPIxMOSI
(OUTPUT)
tSSPIDM
CPHA = 1
tHSPIDM
SPIxMISO
(INPUT)
tDDSPIDM
tHDSPIDM
SPIxMOSI
(OUTPUT)
CPHA = 0
tSSPIDM
tHSPIDM
SPIxMISO
(INPUT)
Figure 23. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. B
|
Unit
Page 42 of 84 |
April 2014
tSPITDM