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Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
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REV: 070505
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MEMORY RESOURCES
Like the 8051, the DS87C530/DS83C530 use three memory areas. The total memory configuration of the
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12 of 47
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13 of 47
.
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DS87C530/DS83C530
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Unlike many 8051 derivatives, the DS87C530/DS83C530
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T
.
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WW 0always
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not have fast RAM in place. Internal SRAMWaccess .is
W1
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WW
slow RAM or peripherals, select a larger Stretch value. Note that this affects data memory only and the
only way to slow program memory (ROM) access is to use a slower crystal.
15 of 47
.
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .TW
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W
W
W
W
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M
OReal-Time
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.
O
W
W
DS87C530/DS83C530
Microcontrollers
W Clock
W
C
W
.
W
W
.T
WW .100Y
M.T
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100
M
.
O
W
M
O
W
W
.C
Y.C
W
.CO .TW 1 and 7Wcauses
WW
.TW
.TW to stretch
100
00Y
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Using
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the
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and all
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.
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00Yvalue between
M
.
O
1
W
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O
W
C
.
O
W
W
C
W
.
Y
W
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.
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W are increased
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WW
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.
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O read/write strobe
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This results
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Ymore
WW
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WW and.10relaxed
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100
WW .100Y.C M.TW
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.
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O
W
O
memory/peripherals
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WWof 0the
WW .100Y.C M.TW
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Y.C Table.T3Wshows theWresulting
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WW section.
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WW 00Y.CO .TW
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CO
.
W
W
Y
W
W
0
W
T
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uses the 1Clock
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SFR
value
. location 8Eh. The
M is
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.10
O
W.1Stretch
. 00
Oreferred to as M2 through
.CThe
OM
W
Wbits
C
.
Y
W
C
selected using
CKCON.2–0.
In
the
table,
these
bits
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M0.
W
.
0
Y
W
W
.TW
W
.T
W
Mfirst
.10
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100
00Y
M
.
O
1
W
M
.
O
W
C
.
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memory
WW .100Y
WW 00Y.CO .TW
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WW .100Y.C M.TW
M
O
1
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W
M
.
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O Stretch Values WW
WW 00Y.CO .TW
W
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C
.
Y
W
W
Table 3. Data
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W
0
Y
W
0
W
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00
W.1 Y.COM W
W.1 Y.COM W
W
W.1 Y.COM W
W
W
W
CKCON.2–0
STROBE WIDTH
W RD.1OR
00 WR STROBE
W
M.T
.100 TIME
M.T
O
W
M.TCYCLES
.100MEMORY
O
W
C
.
O
W
W
W
Y
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Y.C
W AT 33MHz
W
WWWIDTH
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M.T
M2
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M0
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WW .100Y.
WW 00Y.CO .TW
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WW .1002Y.C M.TW
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WW .100Y.C M.TW
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WW .1040Y.C M.TW
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WW 00Y.CO .TW
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WW .100Y.C M.TW
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WW 20 .100Y
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WW .1007Y.C M.TW
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WW24 .100Y.C M.TW
WW .1080Y.C M.TW
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WW 00Y.CO
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W
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DUAL DATA POINTER W W.100
W
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W
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W the Dual
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WW RAM
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WW .100Y.
WWis used
W off-chipWdata
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.
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WW 00Y
W.1 Y.Cis
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W
Y
DS87C530/DS83C530, the standard
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W
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WWdata .pointer
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W.1 Ycode.
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W
These are the standard locations. Using
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.
W
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W
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W
00
Y
W
00 pointer.
WWThe DPTR
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.1active
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O
W
O
W
W
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Y are 0.
W
W other0bits
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W
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M.T The user
.100 and O
W.1
M.T 86h have any
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W
W
W
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.
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W
.
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WW the.1lsb
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M.T is the
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M.T use the currently
O
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O
WW
W
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.
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W
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W
.
Y
W
W
W
0
Y
W
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10switch
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WW
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W
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W
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W 1 Y.COM
W.1 Y.COM W
W
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W
W
W
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W
W
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W
W
Y.
W
M.T DPTR
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W
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WW
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16 of 47
.
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
W
M
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W.1 Y.COM W
WW 00Y.CO .TW
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W
W
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W
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W
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OReal-Time
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.
O
W
W
DS87C530/DS83C530
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W Clock
W
C
W
.
W
W
.T
WW .100Y
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.100
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100
M
.
O
W
M
O
W
W
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WW .100Y.C M.TW
WW .100Y.C M.TW
WW MANAGEMENT
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.
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WW 00Y.CO .TW
W
WW 00Y.CO .TW
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W
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W
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Wstandard
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W
W
Y
W
C
W
.
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W
T
W
.
DS87C530/DS83C530
provide
a
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mode
the
to
W
0
0
Y
W
W
.1
.T
M.T
.10
OM
100
W
M
.
O
W
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.
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W
W
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W
. full operation.
continue W
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DS87C530/DS83C530
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Y
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WW .1with
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W
TW
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O
1
W
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O
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W
C
O
W
WW .100Y.
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WW .100Y.C M.TW
WW .100Y.C M.TW
M
O
W
O
W
WW .100Y.C M.TW
WW 00Y.CO MODE
W (PMM)
WW .100Y.C M.TW
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WW 00Y.CO .TW
W.
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W
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W
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T
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a complete scheme of.1reduced
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theOCPU
.
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W
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00 offers
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W
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OM
W
W.1to use
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.
Y
W
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to run software
but
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DS87C530/DS83C530
W
.
0
Y
W
W
.TW
W
0
0
Y
W
T
.
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0
0
W
T
M
.
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.
O
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.
W cycle rateOis (Clock/4). At 33MHz
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WW crystal
W
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WW .100Y.C M.TW
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T
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W
the instruction cycleWspeed
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WW
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WW .100Y.
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WW .100Y.C M.TW
W
M
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O
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W
M
.
O
W
WW .100Y.C M.TW
WW 00Y.CO .TW
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WW 4 illustrates
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.
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Wmechanism
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W
W.1 Y.COM W
CO
.
Y
W
W
Y
W
W
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0
W
T
for several commonW
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function
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.
100
0is a direct
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.
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00
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.
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1
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.
O
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O
W
W
WW
PMM 1 eliminates most
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W whileWstill
00Y
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1
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WW
T
M.T
.
.
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.
O
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W
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.
O
W
C
.
O
PMM 2 runs very slowlyW
and
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the
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W
.C
WW .100Y
.T
WW .100Y.C M.TW
.TW
00Y
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1
illustrated in Table 5. W
W
M
.
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W
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.
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W
W
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.
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W
WW .100Y
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WW .100Y.C M.TW
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W This
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aW
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W
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.
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W
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O divided by 4. Since
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C
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at W
a rate ofY.crystal
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W
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W
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Y
W
W
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W
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00
W
.T
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W.1 Y.COM
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faster than from Idle and PMM allows
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there is little reasonWto
W.1 NOPs),
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W.1 the
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.
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W
.
Y
W
W
W
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W
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100
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use Idle mode in new designs.
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.
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W
M
.
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W
O
W
WW .100Y.C
WW .100Y.C M.TW
WW .100Y.C M.TW
W
O
W
O
W
Table 4. Machine Cycle Rate
WW .100Y.C
WW .100Y.C M.TW
WW .100Y.C M.TW
W
O
W
O
W
WW .100Y.
FULL
W PMM1
Y.C
WW .100Y.C MPMM2
TW
.
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WWOPERATION
T
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O CLOCKS)
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WW 00Y
W.1 Y.COM W
WW 00Y.C
W
W
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W
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W 172.8 W
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W2.765
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O
W
W
C
.
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W
W
W
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WW .100Y 15.6
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W
.
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W
W
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Y
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W
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6.25
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WW
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WW
W.1 Y.COM W
W
W
W
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Table 5. Typical Operating Current in W
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WW 00Y.CO .TW
W
W
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M
W.1 PMM2
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T
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W
W
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W
(mA)
(mA)
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W.1 Y.COM W
W
11.0592
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5.3
4.8
W
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W
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17.2
5.6
WW .100Y 6.4
W
W
25
25.7
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W
33
32.8
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8.2
.
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
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M
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DS87C530/DS83C530
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W Clock
W
C
W
.
W
W
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WW .100Y
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100
M
.
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W
M
O
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O
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WW .100Y.C M.TW
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WW 00Y.CO .TW
W
WW 00Y.CO .TW
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.
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W
W
Y
W
W
M
.1
A major
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W.1 inY.C
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W
Y
W
W
0
W
T
W
.
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the
user
to
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operation
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an
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ring
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and
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W
0
0
W
W
.1
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.10
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100
W
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.
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W
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.
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W
W
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W
.
the crystalWamplifier.
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have
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Y.The
. W
W
M.T
.ring is not accurate,
10software
001024.
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.
O
1
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M
.
O
by either 4, 64,
or
The
so
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W
C
W
.C
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WW .100Y.
.TW
WW .0.5mA
.TW depending
00Y andM6.0mA,
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WW
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this mode
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WWrunning
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WW cycle,
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00Yit makes
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Ysaving
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.
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.
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.
O
W
C
.
W
.C
W
CO
major contribution
in PMM1 or W
PMM2.
.running
WW .100Y
.TW
.TW
00Y
WW .when
M
.TW
1
00Y
M
.
O
1
W
M
O
W
WW .100Y.C M.TW
WW 00Y.CO .TW
WW .100Y.C M.TW
W
1
PMM OPERATION
OM
WW 00Y.CO .TW
W.
WW 00Y.CO .TW
C
.
W
W
W
Y
W
W the .PMM
M
.1 divider
00
Software invokes
setting
bits
SFR
M.T the appropriate
OMarea. The basic choices
W.1in the
.CO .TW
O
WW are
W 1 Yby
C
.
Y
W
C
W
.
0
Y
W
W
W
0 ring). M
W64, and
.T
00
0
W source..10There
speed and clock
areMthree
and
.T speeds (4,
W.1 Y
OMtwo clock sourcesW(crystal,
W.1 1024)
.CO .TW
O
W
C
.
W
C
W
.
0
Y
W
W
Both the decisions
and
the
controls
are
separate.
Software
will
typically
select
the
clock
speed
first.
Then,
W
0
0
Y
W
T
.
W
.1
.T
00
M
.10
OM
OM
WW
W.1to ring
.COcan .disable
it will perform the switch
operation
if desired.WLastly,
the crystal
amplifier
Y.Cif
WW software
C
W
.
0
Y
W
W
.TW
W
0
0
Y
T
1
0
0
W
T
M
.
.
1
0
M
.
O
1
W
M
.
O
desired.
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
W
O
WW 00Y.CO .TW
W
CO
.
W
C
W
.
Y
W
W
W
0
Y
W
T
There are two ways W
of exiting
Software
condition
by reversing
the procedure
.
0
0
.T can remove the
10PMM.
W.1 thatY.COM W
OM at a divide-by-4 W
W.1 operation
OM remove it. To W
W.can
C
.
C
invoked PMM or hardware
(optionally)
resume
rate
under
W
.
Y
W
W
W
.T
W
M.T
.100
.TW
100
00Y
M
.
O
1
W
M
.
O
W
C
.
O
software control, simply W
select
4
clocks
per
cycle,
and
then
crystal-based
operation
if
relevant.
When
W
.C
WW .100Y
.T
W
WW .100Y.C M.TW
.T
00Yin favor
OM
1
disabling the crystal asW
the time
base
of
the
ring
oscillator,
there
are
timing
restrictions
associated
W
M
.
O
W
C
.
O
W
W
C
.
Y
W
W
W
Y.C are.Tdescribed
WW .100Y
.TW
Woperation.
with restarting the crystal
below.
M.
.100
00Details
M
O
1
W
M
.
O
W
C
.
O
W
W
Y
W
WW .100Y.C M.TW
WW .100Y.C M.TW
M
.100
W
O
W
.CO
O
W
W
C
There are three registers containing
bits
that
are
concerned
with
PMM
functions.
They
are
Power
.
Y
W
C
W
.
0
Y
W
W
W
0
W
.T
1
00
W
M
.T C5h), and
00Y (STATUS;
OM
Management Register (PMR; C4h),
External
Flag (EXIF; 91h) WW.
W.1 Interrupt
.CO
OM
W.1Status
C
.
Y
W
C
W
.
0
Y
W
W
W
0
Y
W
.T
W
.100
W.1 Y.CO
M.T
.100
OM
W
O
W
W
C
.
W
C
W
Y
W
W
W
Clock Divider
WW .100Y.
.100
M.T
.100
W
M.T
O
W
.C
O
W
W
C
W (PMR.7)
.C by selecting
W
00Y
0Y. andMCD0
Y
TW (PMR.6)Was
Software can select the instruction
rate
bits W
CD1
.
1
0
0
WW cycle
T
.
.
1
0
.
1
W
O
W
OM
W.
follows:
WW .100Y.
WW .100Y.C M.TW
WW .100Y.C M.TW
W
O
O CYCLE RATE WW
W
CD1
CD0
W
Y.C
WW .100Y
0
W
T
.
0
WW .100Y.C M.TW
M
.1
O
WW 00
W
WW 00Y.CO .TW
C
0
0
Reserved
.
W
W
W
Y
W
W
.1
.T
00
W.1 Y.COM W
WW 0
W.1 Y.CO4M
W
0
1
clocks
(default)
W
W
W
W
.T
00
W
W.1
M.T
.100
W.1 Y.COM W
O
W
W
W
C
.
1
0
64
clocks
W
W
W
WW .100Y
.1
M.T
.100
M.T
O
W
O
WW
W
C
.
W
C
W
.
Y
W
W
1
1
1024
clocks
W
0
Y
W
.T
0
W
.T
00
W.1 Y.COM W
WW
W.1 Y.COM W
W
W
W
0
W
T
.
0
0
W
.T
.1
.10 afterOaMdelay
OM that the
The selection of instruction cycle rate will take
of one instruction
Weffect
.CNote
WW cycle.
C
.
Y
W
W
0
Y
W
.TWbe
W including
Mwill
clock divider choice applies to all functions
are.10altered,
it
M.TSince baud rates
.100 timers.
O
W
O
W
C
.
.C
W in PMM.
W minor restrictions
0Yaccessing
WW .10on
difficult to conduct serial communication W
while
the
.Tare
00Y There
1
M
.
W
O state to select either
W in a 4-clock
W 64 (PMM1) or 1024
C
.
W
clock selection bits. The processor must be running
W
Y
W
W
.T
.100 from
OM
W
(PMM2) clocks. This means software cannot go
directly
PMM1
to PMM2 or visa versa. It must
C
.
W
W
.TW
00Y
1
M
.
return to a 4-clock rate first.
O
W
WW .100Y.C
W
WW
18 of 47
.
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .TW
W.1 Y.COM W
W
W
W
W
.T
00
W
M
OReal-Time
W.1 Ywith
M.T
.100
W.1 Y.COMEPROM/ROM
C
.
O
W
W
DS87C530/DS83C530
Microcontrollers
W Clock
W
C
W
.
W
W
.T
WW .100Y
M.T
.100
.TW
100
M
.
O
W
M
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
Switchback
O
WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
0
W to .a104-clock
M bits to
.1 clock control
To return
rate.T
from PMM, software.1can simply
select the CD1 and CD0
OM
W
.COalternatives
OM
WW hardware
C
.
Y
W
W
0
Y
W
WW per00cycle
.TW
the 4 W
clocks
the
DS87C530/DS83C530
provide
several
W
0
0
Y.C state..THowever,
W
.T
1
0
M
.
1
M
.
O
1
W
M
.
O
W
.C 4-clock
O If Switchback is enabled,
WSwitchback.
for automatic
WW .1return
.TW
00Y to a M
0Y.Cthe device
WW .10then
.TWwill automatically
WW .100Y.C M.TW
M
O
W
O
per cycle speed
when
an
interrupt
occurs
from
an
enabled,
valid
external
interrupt
source.
A
Switchback
W
C
W
Y.
WW 00Y.CO .TW
.TW
WW .10of0Ya.CserialMstart
.TWbit if theW
100 is Oenabled
M
.
will alsoWoccur when
a UART
detects
the
beginning
serial
receiver
1
W
M
.
O
O
W
W
WW
0Y.C Mof.TaW
0reception
0Y.C anMinterrupt;
Y.C
TW
(REN = 1).
Note the
beginning
ofWa start bit W
does
not.1generate
thisW
occursWon
.
1
0
0
WW
T
.
.
0
1
M
.
W detection
.CO
O
Whardware
W
.COof a.Tstart
Yto
Won
C
complete serial
word.
The
automatic
Switchback
bit
allows
correct
W
.
0
Y
W
W
.TW
W
0
0
Y
W
1
0
W
M
.
.T
1
00
M
.
O
1
W
M
.
O
W
O serial reception. A Switchback
baud rates in time
will also occur when W
a byte
W is written
Wfor a proper
Y.C to the.TW
WW .100Y.C M.TW
100
0Y.C M.TW
WW for.10transmission.
.
OM
SBUF0 or SBUF1
W
O
W
C
.
O
W
W
C
W
.
Y
W
C
W
.
Y
W
W
.T
WW .100Y
M.T
.100
.TW
100
M
.
O
W
M
O
W
W
.C
.CO the
0Y.C M.TW
WW by
Switchback is W
enabled
setting
SWB bit (PMR.5)
WW .to
.TW For anWexternal
10interrupt,
00aY1 in software.
.
.TW
1
00Y
M
O
1
W
M
.
O interrupt source could
W example,
W only Yif.Cthe
CO
Switchback will occur
the
interrupt.
For
.generate
Y.C if .TW
WW really
W
0
Y
W
W
W
0
0
W
T
.
W
.1
.T
00 priority
M
.10
OM
INT0 is enabled but has
on INT0
if W
the CPU
OM setting, then Switchback
W
W.1a low
.CO not .occur
Y.Cis
WW 00Ywill
C
W
.
0
W
W
.TW
W
0
Y
W
T
1
W
M
.
.T
1
00
M
.
servicing a high priority
interrupt.
O
1
W
M
.
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
Status
W
Y
W
W
.T
W.1 Y.COM W
.100
W.1 Y.COM W
OM decisions about W
W
W
C
.
W
W
Information in the Status
register
assists
switching
into
PMM.
This
register
contains
W
.T
W
M.T
.100
.TW
100
00Y
M
.
O
1
W
M
.
O
W
C
.
O
W
information about the level
of active interrupts and the activity
serial
.C ports..TW
WW .100Y
.T
WWon the
00Y
WW .100Y.C M.TW
1
M
.
OM
W
O
W
C
.
O
W
W
C
.
Y
W
W
W
0Y levels
Y.C levels
.Tare
WWsupport
M.
.100
.TW
The DS87C530/DS83C530
of interruptWpriority.
Power-fail, High,
10These
00three
M
.
O
1
W
M
.
O
W
C
.
O
W
W
W If 0PIP
Y.C
W of each
Y.Cservice.Tstatus
Wlevel.
and Low. Bits STATUS.7–5
Priority;.100Y
.TWInterruptW
WWindicate
M
1 0 (Power-fail
00the
M
.
1
M
.
O
W
O
WW 00Y.CO
W
C
.
W
C
STATUS. 7) is 1, then the W
processor
is
servicing
this
level.
If
either
HIP
(High
Interrupt
Priority;
W
.
Y
W
W
W
.T
W
.T
00Y
.100 the corresponding
W.1 Y.COM
OM
W
STATUS.6) or LIP (Low Interrupt
STATUS.5) is high,
then
levelWisWin
OM
W.1 Priority;
C
.
W
C
W
.
Y
W
W
.T
W
.100
.TW
100
00Y
M
.
service.
O
1
W
M
.
O
W
O
W
WW .100Y.C
WW .100Y.C M.TW
WW .100Y.C M.TW
W
W
.C
W
W
.CO(Switchback)
W
CO interrupt
W
.level
Y
W
Software should not rely on a lower
source
to
remove
PMM
when
a
W
00Y
0
Y
W
T
.
1
0
0
WW priority
T
.
.
1
0
M
.
1
W
M
.
O
higher level is in service. Check the
before
WW entering
Wthe current
.CO .service
Y.C PMM..TIf
WW .100Y.
WWcurrent
W level W
0
Ypriority
0
0
W
T
1
0
M this condition WW
.
M
service level locks out a desired Switchback
then it would be advisable
wait
W.1 source,
.COuntil.T
Y
WW to
W
.CO .TW
Y
W
W
0
Y
W
0
0
W
.100
clears before entering PMM.
1
0
M
.
1
W
M
.
O
W
O
W
WW .100
WW .100Y.C M.TW
WW .100Y.C M.TW
W
O
W
O PMM by enteringW
W
Alternately, software can prevent an undesired
from
Wservice WW .10
W
0Y.C interrupt
W a low.1priority
T
.
0
0Y.C
WW .10exit
T
.
M
OM
level before entering PMM. This will prevent
interrupts from
Opriority
WW
W otherYlow
.aCSwitchback.
WWcausing
C
W
.
Y
W
W
W
0
W
T
.
0
W
.1
.T
00
W.1 Y.COM W
WW
W.1 Y.COM W
W
W
W
0
W
Status also contains information aboutWthe state
Zero
Activity
0 Receive .T
M.T ports. Serial Port
.100of the Oserial
W.1 Y.COM W
WW
W
W
C
.
W
W
(SPRA0; STATUS.0) indicates a serial word
is
being
received
on
Serial
Port
0
when
this
bit
is
set
to
a
1.
W
0
Y
W
T
.
0
0
W
.T
0
OM out a
W.1is still
OM that the serial W
W.1 Yindicates
Serial Port 0 Transmit Activity (SPTA0; STATUS.1)
port
shifting
.C
C
.
Y
W
W
0
W
.TW
0 Serial MPort
0
W
.1for
M
.10provide
serial transmission. STATUS.2 and STATUS.3
the.T same information
1,
O
W
O
W
C
.
W
.C
Y
W
W
0
Y
W
0
0
W
T
.
respectively. These bits should be interrogated before
or PMM2 to W
ensure
0 enteringMPMM1
.1 that no serial
O
W.1divisor
W
C
.
W
W
port operations are in progress. Changing the
clock
rate
during
a
serial
transmission
or reception
Y
W
W
.T
100
M
.
O
W
will corrupt the operation.
WW .100Y.C M.TW
O
W
WW .100Y.C
W
WW
19 of 47
.
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .TW
W.1 Y.COM W
W
W
W
W
.T
00
W
M
OReal-Time
W.1 Ywith
M.T
.100
W.1 Y.COMEPROM/ROM
C
.
O
W
W
DS87C530/DS83C530
Microcontrollers
W Clock
W
C
W
.
W
W
.T
WW .100Y
M.T
.100
.TW
100
M
.
O
W
M
O
W
W
.CO .TW
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100YOperation
Crystal/Ring
M
O
WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
M from
.1
The W
DS87C530/DS83C530
to choose
selection
00
M source as an independent
M.Tallow software W
Oclock
W.1 Ythe
.CO .Tunder
O
WW 00Y
W.1 cycle
C
W
.
C
W
.
W
W
the instruction
rate.
The
user
can
select
crystal-based
or
ring
oscillator-based
operation
W
0
Y
W
.T
1
0
W
M
.
.T
1
00
M
.
O
1
W
M
.
O external clock) source.
W
.C may.Tsave
O reset default is W
W
W
software W
control.
Power-on
(or
ring
WW The
W
00Y
0Y.C
Y.C
W the crystal
TW
.
1
0
0
W
T
M the
.
.
1
0
M
.
O
1
W
M
.
O
power depending
on
the
actual
crystal
speed.
To
save
still
more
power,
software
can
then
disable
W
C
W
.C
W
.CO .TW
WW .100Y.
.TW
W
.TW also requires
00Y theM
WW .1This
M
1
00Y process
crystal amplifier.
requires
two
steps.
Reversing
process
two
steps.
.
O
W
M
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
W
.CO the
O
WRG
W(EXIF.3)
.CO source.
Y
WWas the
C
W
.
0
Y
W
W
The XT/ RG
bit
selects
the
crystal
or
ring
clock
Setting
XT/
=
1
selects
.TW
W
0
0
Y
W
T
.
1
0
W
M
.
.T
1
00
M
.
O
1
W
M
.
O
O
W RG =Y.0Cselects
crystal. SettingWXT/
the
bit.Tserves
Y.C
WW (EXIF.2)
W as a status
WW bit.1by
.TW
W ring. TheWRGMD
00indicating
0Y.C M
0
0
W
T
M
.
1
0
.
O
1
W
M indicates the CPU
O
the active clock source.
is running
= 1 indicates it
W. RGMD
WW
Wcrystal. RGMD
.CO = 0.T
Y.Cfrom the
WW .100Y.C M.TW
W
0disable
YWhen
Wthe
Tcrystal
.
0
0
WWthe ring.
1
0
M
.
is running from
operating
from
ring,
the
amplifier
by setting
the
O
W
.CO
WW
W.1 Y.COM W
C
.
Y
W
W
0
Y
W
W
.TW
0 = 0. M.T
10
0RG
W
T be done W
XTOFF bit (PMR.3)
to .a101.0 This can
when XT/
M
.
.only
1
.
O
W
M
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
O
W source,
When changing theW
clock
will W
take
effect 0after
Y.C
WW
W
.COthe selection
0This
Y.C a one-instruction-cycle
WW delay.
.TW
W
0
Y
T
.
1
0
0
W
T
M
.
.
1
0
M
.
O
1
W
M
.
applies to changes fromW
crystal toCring
assumes
that the crystalWamplifierYis
O
W this
.C
O and vise versa. However,
C
W
W
W
W software
00 If
0Y.disabled
Y. ring is active,
WW
Tthe
.
1
0
0
WW when
T
M.T
.
.
1
0
running. In most cases,
the
previously
crystal
to
save
power.
M
.
O
1
W
M
.
O
W
C
W
W
W
.C
Y.
.CO .TWmust switch
WWto crystal
ring operation is being
the crystalWmust first
.TW
100be OM.T
00Yoperation,
WWused.1and
.
1
00Ythe system
M
.
W
M
O
W
.C
W
W
W
enabled. Set the XTOFF
begin.
The
.CO0. .At
Wthis time,
00Y
0Y.C oscillation
WWthe .1crystal
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20 of 47
.
WW 00Y.CO .TW
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WW 00Y.CO .TW
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DS87C530/DS83C530
Microcontrollers
W Clock
W
C
W
.
W
W
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21 of 47
.
WW 00Y.CO .TW
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WW 00Y.CO .TW
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DS87C530/DS83C530
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W Clock
W
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W
.
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W
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WW .100Y
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22 of 47
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DS87C530/DS83C530
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W
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Y
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T
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.
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O
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W.1
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W.1
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
W
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WW
The DS87C530/DS83C530
the Stop
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the
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W
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W
W
W
0
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W
T
.
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M
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W
device provides a bandgap
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W
Wreference
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O
W
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W
W
C
.
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W
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W can optionally
M
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W.the
W.1 Y.COM W
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W
W.1 andYPower-fail
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W
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W
W
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M
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O
Wbrownout
O
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W
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and
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.
W
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W
.
Y
W
W
00
W
WW .100Y
M.T
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W
O
W
W
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W
Y
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W
WW .100Y.C M.TW
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.
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W
YI will beWapproximately
W 50mA
In Stop mode with the bandgap
with 1mA with the .10
W enabled,
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O
W
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O
W
W
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.
W
C
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W the bandgap
Yin Stop mode,
WW .100Y.C
W or Interrupt
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W
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thisWW
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W
00Y
0
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W
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.
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results in an uncontrolled power-down
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W
O
W
OM
W.
WW .100Y.
WW .100Y.C M.TW
WW .100Y.C M.TW
WW 00Y
W
CO
.register
WW Flag
W
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Y
W
The control of the bandgap reference
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W
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W
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.
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WW is .1located
T
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OMThe default or WW.
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Setting BGS (EXIF.0) to a 1 will keep
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.
W
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W
.
W
W
00
0
Y
W
WW This
.Tthe
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W.1
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reset condition is with the bit at a logic 0.
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O
W
O
W
W
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W
Y
W
W
0
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WWmodes.
WW during
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W.1
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O
W
O
W
W
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W
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W
W
W
WW .100Y
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O
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WW
W
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The second feature allows an additionalWpower
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W
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Y
W
W saving
W
0
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W
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00 It isMthe
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O
W.1 that
the ability to start instantly when exiting W
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internal ring oscillator
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WW
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W
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W
.
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W
W
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when W
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The
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.10 StopOmode
W.interrupt.
.CO .TW
C
.
Y
W
W
0
Y
W
0
W
of the ring oscillator is as follows.
.T
00
W.1 Y.COM
W.1 Y.COM W
W
W
W
0
W
T
.100
M.clocks
.10all
W
O
W
Using Stop mode turns off the crystal oscillator
and
internal
to
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power.
This requires that
W
C
Y.
WW .100Actual
.TW time is W
M
the oscillator be restarted when exiting Stop mode.
startup
crystal-dependent,
but is
WW 00Y.CO .TW
W
normally at least 4ms. A common recommendation is.110ms. In anMapplication that will wake up, perform
W
.CO
Ybe
a short operation, then return to sleep, the crystal
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0
WW
0
.1
W
the ring oscillator will start instantly. Running from
WWthe ring, the user can perform a simple operation and
return to sleep before the crystal has even started. If a user selects the ring to provide the startup clock and
the processor remains running, hardware will automatically switch to the crystal once a power-on reset
interval (65,536 clocks) has expired. Hardware uses this value to assure proper crystal start even though
power is not being cycled.
23 of 47
.
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
W
M
.1
.T
00
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M
OReal-Time
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O
W
W
DS87C530/DS83C530
Microcontrollers
W Clock
W
C
W
.
W
W
.T
WW .100Y
M.T
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100
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.
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real-time
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WW
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M6.Tshows
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how theW
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WW the.10ring,
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WW .100Y.C M.TW
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WW .100Y.C M.TW
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WW 00Y.CO .TW
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WWcontrols
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W
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W
use the ring
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will
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W
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W
M
.100 crystal
W.1 crystal,
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.100to theOcrystal
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W
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W
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W
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. Mode, located at EXIF.2,
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Figure 6. Ring
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WW 00Y.CO .TW
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WW 00Y.CO .TW
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C
EMI REDUCTION
W
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WW .100Y.
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One of the major contributors to radiated noise
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DS87C530/DS83C530 allow software to disable ALE
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24 of 47
.
WW 00Y.CO .TW
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DS87C530/DS83C530
Microcontrollers
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.
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The WDS87C530/DS83C530
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M
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Y
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There is one important
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WW
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1
and
CKCON.3
.
C
W
0Y.
Y
W
W
W
0
0
Y.
W
T
.
1
0
0
W
T
.
.
1
0
M
. that the
1 unnecessary
M to alter these bits.
Unless a user desires very fast timing, W
it .is
Note
controls are WW
.CO timer
Y
WW
W
.CO .TW
Y
W
W
0
Y
W
T
.
0
0
W
.100
independent.
1
0
M
.
1
W
M
.
O
W
O
W
WW .100
WW .100Y.C M.TW
WW .100Y.C M.TW
W
O
W
O
W
POWER-FAIL RESET
WW .10
WW .100Y.C M.TW
WW .100Y.C M.TW
O of tolerance.
O
The DS87C530/DS83C530 use a precision
voltage
reference to decide
is
WW
Wbandgap
.Cout
WWif V0CC
C
W
.
Y
W
W
W
0
Y
W
T
.
W circuit
.1
.T
00
.1 rises above
While powering up, the internal monitor
VCC
OM the VRST
W
OM a reset state until
WW
W.1 maintains
C
.
W
C
W
.
Y
W
W
W
0
Y
.T
0
W enables
level. Once above this level, the monitor
oscillator andWcounts .165,536
clocks.
M.T
.100the crystal
OM It then
W
O
WW
W
C
.
W
C
W
.
Y
W
W
exits the reset state. This power-on reset W
(POR) interval
allows
time
for
the
oscillator
to
stabilize.
W
0
Y
W
T
.
0
0
.T
0
M
.1
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
.T
00
M
A system needs no external components to generate
reset. Anytime
W.1 VCCY.drops
OM
W.1 aY.power-related
CO below
W
C
W
W
0
W
0
0
W
T
0
VRST, as in power failure or a power drop, the.1monitor
M. generate and hold
W.a1 reset. It occurs
Owill
W
W
C
.
W
W
Y
W
automatically, needing no action from the software.
Refer
Specifications section for the
W
.T
00 to the Electrical
W.1 Y.COM W
exact value of VRST.
W
W
M.T
.100
O
W
C
.
WW .100Y
POWER-FAIL INTERRUPT
W
WW
The voltage reference that sets a precise reset threshold
also generates an optional early warning powerfail interrupt (PFI). When enabled by software, the processor will vector to program memory address
0033h if VCC drops below VPFW. PFI has the highest priority. The PFI enable is in the Watchdog Control
SFR (WDCON–D8h). Setting WDCON.5 to logic 1 will enable the PFI. Application software can also
25 of 47
.
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .TW
W.1 Y.COM W
W
W
W
W
.T
00
W
M
OReal-Time
W.1 Ywith
M.T
.100
W.1 Y.COMEPROM/ROM
C
.
O
W
W
DS87C530/DS83C530
Microcontrollers
W Clock
W
C
W
.
W
W
.T
WW .100Y
M.T
.100
.TW
100
M
.
O
W
M
O
W
O
W
.C
Y.C
W to a 1. The
WWflag.1is00independent
.TW
WWcondition
.Tbit
00Ysets this
0Y.Cat WDCON.4.
WW
read
the PFI
A PFI
of the
M
.TW
1
0flag
M
.
O
1
W
M
.
O
W
C
.
O
W
W
C
.
Y
W
C
W
.
0
Y
W and the
interrupt
and software
clear
PFI is enabled
.TW bit
W
.T
WW enable
Mselect
.10 bandgap
.TW must manually
100 it. IfOthe
00Y
M
.
O
1
W
M
.
W
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W a PFIYwill
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the device out
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.C
.CObring
WW .100Y.
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WW
.TW
00Y
W
M
.TW
1
00
M
.
O
1
W
M
.
O
W
W
.CO .TW
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .1TIMER
00Y
WATCHDOG
M
O
W
WW 00Y.CO .TW
W
Winclude aWprogrammable
.CO losing
Y.C
Wcontrol, the
0
Yfrom
WW
T
.
To prevent
DS87C530/DS83C530
watchdog
0
0
WWsoftware
T
.
1
0
OM
W.1 Y.C
M
.1
OM
W.
W
C
W
.
W
W
0
Y
W
WW 00Y
timer. TheWWatchdog
is.C
aO
free-running
timer
that
sets
a
flag
if
allowed
to
reach
a
preselected
timeout.
W
.T
M.TIt
.10
.TW
100
M
.
O
1
W
M
.
O
W
C
.
O
Wby software.
can be (re)started
WW .100Y
.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
M
O
W
O
W
C
O
W
0Y.its
Y.C the .Watchdog
WWout it.10sets
.TW
Y.C
WWsource.
TW
00When
WW .1is00to
M
.TW
A typical application
selectMthe
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times
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1
M
.
O
W
O
.C
W
W
WW before
.CO must
Wrestart theWtimer
00Y
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it reaches
isM.TW
TWits timeoutWor the .processor
.
1
0
WWreset..1Software
T
.
1
00Y
M
.
O
W
M
O
W
O
W
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WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
W one .of
.T
00 timeout
M and enables the W
Software can select
timer
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OM
W.1function.
W.1 the
OM values. Then, itWrestarts
W 1 four
.CO .TW
Y.C
C
.
0
Y
W
W
.TW
W
0
0
Y
W
After enabling theWreset function,
software
the
its expiration orWhardware
1
0 timer before
M
.
.T must then restart
1
00
M
.
O
1
M
.
O
W
.C
O Reset Enable andWthe
W
WW
will reset the CPU.W
Both
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WWthe 0Watchdog
W
00Y
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Y.C
W
TWcontrol bits
.
1
0
0
T
M.T
.
.
1
M
.
O
1
W
M
.
O
W
C
O
W
by a “Timed Access”W
circuit.
This
accidentally
clearing the
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.C
0Y.
WW
.TW
Werrant software
Y.C prevents
WW from
.TW
10For
00Yfrequency
M
.
1
M
.
O
W
M.Ta function of theWcrystal
.100 theyOare
Timeout values are W
preciseWsince
as
shown
in
Table
7.
O
W
WW .100Y.C M.TW
W
0Y.C M.TW
Y.Calso are
W
0
0
WW at 33MHz
T
.
reference, the time periods
shown.
1
0
.
1
OM
WW 00Y.CO .T
W.
WW 00Y.CO .TW
C
.
W
W
W
Y
W
W
.T
.1
W.1 Y.COM
.100
OaMreset circuit. It willWset
Wnot
OM for systems that W
W
C
.
The Watchdog also provides
a usefulY.option
do
require
an00
C
W
Y
W
W
W
W
W
M.
.1
M.T this interrupt source.
.100
O
W
M.Tflag. Software can
.100 theOreset
O
W
C
interrupt flag 512 clocks beforeWsetting
optionally
enable
.
W
Y
W
.C
Y.C
W
.TW debug, W
WW of .the
M
.100
.TW
100
00Y
M
.
The interrupt is independent
reset.
A
common
use
of
the
interrupt
is
during
to
show
1
W
M
O
W
.CO
O
W
W
C
.
Y
W
C
W
.
0
Y
W
W
W
0
0
W the.10Watchdog
.T be restarted by
developers where the Watchdog
times
must
W
.T indicates where
00Yout. This
W.1 Y.COM
OM
W
OM
W
W.1 asYa.Cconvenient
C
.
W
W
software. The interrupt also W
can
time-base
generator
or
can
wake-up
the
processor
Y
W
Wserve
W
.T
.100
.TW
100
00
M
.
O
1
W
M
.
O
W
O
W
from power saving modes.
WW .100Y.C
WW .100Y.C M.TW
WW .100Y.C M.TW
WW 00Y.C
W
WW 00Y.CO .TW
CO
.
W
W
W
Y
W
0
W
T
.
The Watchdog function is controlled
Clock
Control (CKCON–8Eh),
Control W.1
M
.1
.10 by theOM
OWatchdog
W
W
C
.
W
C
W are WD1
Y CKCON.6
WW .100Y.
W
W SFRs.WCKCON.7
(WDCON–D8h), and Extended W
Interrupt
Enable
and
0
Y. (EIE–E8h)
T
.
0
0
T
.
1
0
M
W
.1 Watchdog
W.
OMtimeout period as W
W
.CO 7. .TW
and WD0, respectively, and they select
the
Table
WW .100Y
W shown.1in
00Y
WW .100Y.C M.TW
M
O
WW 00
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
W
.1
.T
00
Table 7. Watchdog Timeout Values
W.1 Y.COM W
WW 0
W.1 Y.COM W
W
W
W
W
.T
00
INTERRUPTW
W.1
M.T RESET TIMEOUT
.100 (33MHz)
OM(33MHz)
W.1 YTIME
O
W
W
C
WD1
WD0
TIME
.
W
C
W
.
W
W
Y
W
TIMEOUT WW
.1
M.T
.100
M.T
.100
O
W
O
WW
W
C
.
17
17
W
C
W
.
Y
W
W
W
0
Y
0
0
2 clocks
3.9718ms
clocks .10
3.9874ms
.T
W
.T 2 + 512 W
.100
OM
W
OM
WW
W
C
20
20
.
W
C
W
.
Y
W
W
W
0
1
2 clocks
31.77ms
2
+
512
clocks
31.79ms
0
Y
W
T
.
0
0
W
.T
1
M
.10
OM 223 + 512 clocksWW.
W
.CO .TW
C
.
Y
W
1
0
223 clocks
254.20ms
254.21ms
W
0
Y
W
W
.T
10
00
M
W.1 Y.COM 226W+ 512 clocks WW. 2033.62ms
.CO
Y
W
1
1
226 clocks
2033.60ms
0
W
0
0
W
T
.
0
.1
W.1 Y.COM W
WW
W
W
W
.T
00
As shown above, the Watchdog Timer uses theWcrystal
OM as a time base. A user selects one of
W.1 frequency
C
.
Y
.TW are 217 = 131,072 clocks; 220 =
four counter values to determine the timeout. W
TheseW
clock
Mlengths
.100 counter
O
C
23
26
.
0Y
WW .10clocks.
1,048,576; 2 = 8,388,608 clocks; and 2 = 67,108,864
The times shown in Table 7 are with a
W
W
33MHz crystal frequency. Once the counter chain
has
completed
a full interrupt count, hardware will set
W
an interrupt flag. Regardless of whether the user enables this interrupt, there are then 512 clocks left until
the reset flag is set. Software can enable the interrupt and reset individually. Note that the Watchdog is a
free-running timer and does not require an enable.
26 of 47
.
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .TW
W.1 Y.COM W
W
W
W
W
.T
00
W
M
OReal-Time
W.1 Ywith
M.T
.100
W.1 Y.COMEPROM/ROM
C
.
O
W
W
DS87C530/DS83C530
Microcontrollers
W Clock
W
C
W
.
W
W
.T
WW .100Y
M.T
.100
.TW
100
M
.
O
W
M
O
W
.C
W
.C
W
W the Watchdog
.CO bits
WW .1Timer
.TWstatus
00Y andMtwo
.Taffect
00Y
WWare five
There
control
in special W
function.1registers
that
.TW
00Y
M
O
1
W
M
.
O
W
.C
O user. WDIF (WDCON.3)
Wat timer
W
Y.Cinterrupt
WW
flagsWthat
report
to
the
flag that isW
set
termination
W
00Y
Y.C
WW .1is00the
TW
.
1
0
T
M.T when
.
.
0
M
O
1
W
M
.
O
W
C
. is set.Twhen
O
W clocks
there areW512
remaining
until the W
reset
set.
is the flag
W
.CWTRF
Ythat
W flag is
W
WW
.T(WDCON.2)
100
00Y
0Y.C M.TW
W
M
.
1
0
M
.
O
1
W
.
O
the timer has
is W
normally.C
associated
reset and allows software
Otimed out. This flagW
Wcompletely
Wwith a CPU
Y
WW .100Y.C M.TW
W
0the
Y.Csource.
W
T
.
0
0
WW the
T
.
1
0
to determine
reset
EWT
(WDCON.1)
is
enable
for
the
Watchdog
Timer reset function.
M
.
W
WW 00Y.CO .TW
W.1 Y.COM W
CO
.
W
W
Y
W
W
0
W
T
RWT (WDCON.0)
is the bit that
restart
Timer. Setting this
.
W
.T software uses toW
.10 the Watchdog
OM the
W.1 bitYrestarts
.100
OMbit before the timeout.
.Cthese
OM Application software
W
C
.
W
C
timer for W
another
interval.
must
set
this
Both
of
W
.
0
Y
W
WW full
.TW
Y
W
.T
Mbits
.10
.TW
100
M
.
O
W
M
.100 Access
O
W
C
.
are protectedW
byWTimed
discussed
below.
As
mentioned
previously,
WD1
and
0
(CKCON
.7
and
O
WW .100Y
.TW
WW .100Y.C M.TW
0Y.CReset
Wtimeout.
M
.TW
0The
O
1
6) select the
Watchdog
Timer
bit
(WDCON.0)
should
be
asserted
prior
to
modifying
W
M
.
O
W
.C
W
.CO .T
WW count.
.TW
W (WD1, WD0)
00Y Finally,
0Y.C
WW to .avoid
TWof the watchdog
.
1
0
WW
the Watchdog
Timer.1Mode
bits
corruption
M
.
1
00Y Select
M
O
W
M
O
W
WW (EIE.4).
.CO Interrupt
WW .100Y.C M.TW
the user can enable
EWDI
W using W
0Y.C M.TW
0
WW the.1Watchdog
T
.
1
00Y
.
O
W
O
W
OM
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
INTERRUPTS WW
O
WW 00Y.CO .TW
WW 00Y.CO .TW
C
.
W
W
Y
W
W
M
.1
.T
00
M
.1
The DS87C530/DS83C530
three
levels. The
Power-Fail
.CO .TW
OM14 interrupt sources
WW
W.1 provide
.CO priority
Y
WW with
C
W
.
0
Y
W
W
W
0
0
Y
W
T
0
W the highest
M
00 priority..TSoftware can assign
Interrupt (PFI) has
low
sources.
M. priority to otherW
W.1 All
O
W.1highYor
.CO .TW
W.1 Y.COM W
C
.
Y
W
W
0
W
W
W the PFI,
interrupts that are W
new to the
8051 family,
except for
.10 the OM
M.T natural priority
.100have aOlower
Wthan
M.T
.100
W
O
W
W
C
.
W
C
originals.
W
0Y.C M.TW
Y
W
W
0
0
W
T
.
1
0
WW .100Y.
T
.
.
1
O
W
M
OM
W.
WW .100Y.C M.TW
WW 00Y.CO .TW
WW .100Y.C M.TW
W
Table 8. Interrupt Sources
OM
WW 00Y.CO .T
W.1andYPriorities
WW 00Y.CO .TW
C
.
W
W
W
W
W
M
.1
.T
1
00
OM
WW 00Y.CO .
W.1 Y.COM W VECTORWW. NATURAL
C
.
NAME
FUNCTION
8051/DALLAS
W
Y
W
W
W
.T
00
W
PRIORITY
W.1 Y.COM
M.T
.100
W.1 Y.COM W
O
W
W
W
C
.
W
W
W 33h W
00
Y
PFI
Power-Fail W
Interrupt
DALLAS
.100 1 OM.T
W.1 Y.COM
M.T
.100
W
O
W
W
C
.
W
W 8051 W
Y
External Interrupt
WW 0 .100Y.C M.TW 03h W
M
INT0
.100
M.T
.1002
W
O
W
.CO
O
W
W
C
.
Y
W
C
W
.
0
Y
W
W
W
0
Y
W
.T
W
TF0
Timer 0
8051
.1030
W.1 Y.CO
M.T 0Bh
.100
OM
W
O
W
W
C
.
W
C
W
Y
W
W
Y.
W
WW
.100
External Interrupt
1
INT1
M.T 8051
.1400
W
M.T 13h
.100
O
W
.C
O
W
W
C
W
00Y
WW 5.100Y.
.TW8051
1
WW .100Y.C M.TW
.
TF1
Timer 1
1Bh
M
W
O
W
O
W
WW .100Y.
W
WW 6 .100Y.C M.TW
WWPort .0100Y.C M.T23h
SCON0
TI0 or RI0 from Serial
8051
W
O
W
O
W
W
WW .100Y
WW 7 .100Y.C M.T8051
WW .100Y.C M.2Bh
TW
TF2
Timer 2
W
O
WW 00
W
.CO .TW
W
C
.
Y
W
W
W
0
Y
W
SCON1
TI1 or RI1 from SerialWPort 1 100
3Bh
8 .10
DALLAS
.1
.T
OM
W
OM
WW 0
W.
C
.
W
C
W
.
Y
W
W
W
Y
W9
.T
INT2
External Interrupt 2 W
43h.T
DALLAS
00
W.1
M
.100
W.1 Y.COM W
O
W
W
W
C
.
W
W
W
External Interrupt 3
10
DALLAS
WW .100Y 4Bh
INT3
.1
M.T
.100
M.T
O
W
O
WW
W
C
.
W
C
W
.
Y
W
W
W
0
Y
W
.T
0
W
INT4
External Interrupt 4
53h .T
11
DALLAS
00
W.1 Y.COM W
WW
W.1 Y.COM W
W
W
W
0
W
T
.
0
0
W
External Interrupt 5
5Bh .T
12
DALLAS
INT5
0
M
.1
W.1 Y.COM W
WW 00Y.CO .TW
W
W
.T
WDTI
Watchdog Timeout Interrupt W
13
00 63h
M
W.1 DALLAS
W.1 Y.COM W
.CO
W
Y
W
0
W
0
0
W
T
RTCI
RTC Interrupt
14
.
0 6Bh
.1 DALLAS
W.1 Y.COM W
WW
W
W
W
.T
00
W.1 Y.COM W
W
W
M.T
.100
O
W
C
.
WW .100Y
W
WW
27 of 47
.
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .TW
W.1 Y.COM W
W
W
W
W
.T
00
W
M
OReal-Time
W.1 Ywith
M.T
.100
W.1 Y.COMEPROM/ROM
C
.
O
W
W
DS87C530/DS83C530
Microcontrollers
W Clock
W
C
W
.
W
W
.T
WW .100Y
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.
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WW .100Y.C M.TW
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W
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W
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WW 00Y.CO
W
ADDRESS
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WW
W
30h
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60h
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29 of 47
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W
W
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WW9. EPROM
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W
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W Code.1Data
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WW .100Y.C M.TW
WW .100Y.C M.TW
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WW 00Y.CO .TW
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Supply Current Stop Mode,W
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1
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.
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W
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1
150
6
.
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W
W
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W
(-40°C to +85°C)
WW .100Y.C M.TW
WW .100Y.C M.TW
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W
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.
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W
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W
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5000
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W
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W.1 Y.COM W
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W
W
0
W
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W
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W
W
C
50
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6
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.
W
C
W
Y
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W
(-40°C to +85°C)
W
WW .100Y.
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W
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W
Backup Supply Current, Data-Retention
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WW .100Y.
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WW .100Y.C M.TW
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Backup Supply Current, Data-Retention Mode
O mA
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WW .100Y
WW .1001Y.C M
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WW .100Y.C M.TW
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WW 00
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W
0
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Y
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W
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W.1
W.1 Y.COM W
W
W.1 VYIH.COM W
W
W
W
3
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W
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W
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W.1
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W
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W
W
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.
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C
3
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W
.
Y
W
CC
W
Y
W
WW .100IH2
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O
W
O
WW
W
C
3
Output Low Voltage at IOL = 1.6mA
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0.45
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.
W
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W
Y
W
W
W
0
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W
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0
W
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W
W
3
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.
0
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W
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0
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M
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W.1 Y.COM W
WW 00Y.CO .TW
W
W
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W
W
C
IOH = -50mA
.
W
W
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W
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W
Output High Voltage Ports 1, 2, 3
W
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W
V
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W
C
.
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W
Y
W
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V
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.
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W
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Input Low Current Ports 1, 2, 3 at 0.45V
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11
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W
Transition Current from 1 to 0 Ports 1, 2, 3 at 2V
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33 of 47
-800
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12
.
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
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M
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DS87C530/DS83C530
Microcontrollers
W Clock
W
C
W
.
W
W
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WW .100Y
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.100
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100
M
.
O
W
M
O
W
WW .100Y.C M.TW
WW 00Y.CO CHARACTERISTICS
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WW .10(continued)
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DCWELECTRICAL
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WW 00Y.CO .TW
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WWto 5.5V,
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W
0
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00
W.1 UNITS
W.1 Y.COM
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OM
W.1 PARAMETER
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MIN W TYP WW
MAX
Y
W
C
.
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W
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W
0
0
Y
W
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1
0
0
W
M
.
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0
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.
O
1
W
M
.
O-10
WI
Input Leakage
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13
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W
WPort 0, EA, O
W+10
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00Y
WW L.100Y.C M.TW
1
WW .100Y.C M.TW
M
.
O
W
O
W
Input LeakageW
Port 0, Bus C
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I
-300
+300
14
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O
L
WW .100Y.
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WW .100Y.C M.TW
WW .100Y.
M
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O
W
M
RST Pulldown Resistance
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50
200W
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W
O
W
W
W
00
WW .100Y.C M.TW
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WW .100Y.C M.TW
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.
O
W
O
W
C
.
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W
W
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the temperature
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WW temperature
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.
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Wnot battery
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W
.
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Y
W
W
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W
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W
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.
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0
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W
T
M
.
.
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All parameters.1apply
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M
.
O
W
O
W
OM
W
Note 3:
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WW .100Y.C M.TW
W
Y.C to ground.
WW .100Y.C M.TW
0
WW are.referenced
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.
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Wmeasured
Y.C
WW
CO33MHzTclock
W
.with
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Y
W
W
.TW
W
0
0
Y
W
T
.
1
0
0
W
M
.
.
Note 5:
at ground, other pins disconnected.
Idle mode current.1
measured
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33MHz clock source on XTAL1, .V1 = 5.5V, RSTM
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O
W
O
W
O
W
W
WW .100Y.C M.TW
W
Note 6:
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WWV =.5.5V,
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WW
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.
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O
W
M
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O
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WW between
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W
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Y
W
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.
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W
0
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Port
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reset and when at a logic highW
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W
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WW .100Y.C M.TW
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.
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WW .100Y.C M.TW
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W
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W.cycles.
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W a one-shot
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W
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W
W
W
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W
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.
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.
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W
M
W
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.
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W the00Y
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theW
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Walso have toW
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WW from.110to0Y
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M
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W.1 Y.COM
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W
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W
W
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W
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W
W
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WWholding.1latch
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.
O
W
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W
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W
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W
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W
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W
M
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W.1 Y.COM W
WW 00Y.CO
W.1 Y.COM W
W
W
W
W
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W
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W
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W
C
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C
W
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TYPICAL ICC vs. FREQUENCY
WW .100Y.
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C
W
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WW .100Y.
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WW .100Y.C M.TW
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M
W
O
W
O
W
WW .100Y.
WW .100Y.C M.TW
WW .100Y.C M.TW
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O
W
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WW .100Y
WW .100Y.C M.TW
WW .100Y.C M.TW
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WW 00
W
WW 00Y.CO .TW
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W
W
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W
W
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WW 0
W.1 Y.COM W
W
W
W
W
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W.1
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W
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W
C
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WW .100Y
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WW 00Y.CO .TW
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W
W
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W
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W
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WW .100Y.
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WW .100Y.C M.TW
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WW .100Y.C
W
WW
CC
CC
CC
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CC
BAT
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CC
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CC
34 of 47
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.
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W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
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M
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.
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W
W
DS87C530/DS83C530
Microcontrollers
W Clock
W
C
W
.
W
W
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WW .100Y
M.T
.100
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100
M
.
O
W
M
O
W
WW .100Y.C M.TW
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WW .10(Note
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ACWELECTRICAL
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.
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WW 00Y.CO .TW
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M
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W.1 Y.C
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WW CLOCK
W
W
Y
W
C
W
.
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W
W
W
0
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W
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W
.
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WW .100Y.C M.TW
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WW .1000Y.C M33
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WW 26.100Y.C M.TW tCLCL-5W
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W.1 andYindustrial
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W
.
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W
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W
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W
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W
M
.
WW 00Y.CO .TW
WW .100Y.
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W
W
1
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WW .100Y
WW .100Y.C M.TW
WW .100Y.C M.TW
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WW 00
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WW .100Y.
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WW .100Y.C M.TW
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WW .100Y.C
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35 of 47
.
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
W
M
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M
OReal-Time
W.1 Ywith
M.T
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C
.
O
W
W
DS87C530/DS83C530
Microcontrollers
W Clock
W
C
W
.
W
W
.T
WW .100Y
M.T
.100
.TW
100
M
.
O
W
M
O
W
W
.C
.CO .TW
WW .100Y.C M.TW
WW STRETCH
.TW
00Y
WW CHARACTERISTICS
MOVX
USING
MEMORY
CYCLES
1
00Y
M
.
1
M
.
O
WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
W
Y
W
W
M
.1
.T
VARIABLE
CLOCK
.100
OM
W.1 Y.C
.COSTRETCH
OM
WW UNITS
W
PARAMETER
SYMBOL
Y
W
C
W
.
0
W
W
.TW
W
0
0
Y
W
1
0 MIN M.T
MAX
W
M
.
.T
1
00
.
O
1
W
M
.
W
.CO
WW .100Y.C tMCS
WW 00Y.CO .TW
.TW
0YCLCL
WW .101.5t
TW
-5
.
W
M=0
M
O
1
W
M
.
Data Access ALE
Pulse
Width
t
ns
O
W
C
LHLL2
O
W
WW .100Y. tMCSM
-5
>0.TW
0Y.C
WW .12t0CLCL
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WW .100Y.C M.TW
M
O
W
O
W
O
W
WW .100Y.CtMCS=0M.TW
CLCL
0Y.-5C M.TW
Y.CLow .TW t
WW 0.5t
0
WWValid.1to00ALE
1
Port 0 Address
ns
.
AVLL2
CO>0 TW
OM
WW 00Yt.MCS
W
-5Y.CO
WW tCLCL
C
W
.
W
W
.
W
0
Y
W
T
W
M.
.10
OM
W.1 Y
M.T
.100
O
W
C
.
O
W
W
C
0.5t
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t
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.
Address Hold After
C
W ns .100 MCS M.TW
W ALE 0Low
W tLLAX2 WW CLCL
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Y.for
TW
.
0
0
W
T
.
1
M
.
1
MOVX Write
CO
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OM
WW 0t0MCS
W.
W
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Y.>0
WW
C
.
Y
W
W
W
0
Y
W
W
.1 t =0 OM.T
.T
1-50
00
M
.
1
W
M
.
O
W
2t
CLCL
MCS
W
W
Y.C
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W
.TW
tRLRH
ns
WW .100Y.C M.TW
RD Pulse WidthWW
100
M
.
00Y
O
1
W
M
.
tMCSW
-10
t >0
O
.C
O
W
W
WW .1MCS
00Y
WW .100Y.C M.TW
WW .100Y.C M.TW
M.T
O
W
2t
-5
t
=0
O
CLCL
MCS
W
C
.C
W
nsWW
.CO t.WLWH
0Y.
WR Pulse Width WWW
.TW
W
.TW
10>0
00Y
TW
M
.
1
00Y
M
.
t
t
O
1
W
M
MCS-10
MCS
.
O
W
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O
W
W
WW t .1=0
00Y
WW .100Y.C2tCLCLM-22
.TW
WW .100Y.C M.TW
M.T
MCS
O
W
O
W
C
ns WW
RD Low Valid Data In WW
Y.
.CO tRLDV
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WW .100Y.CtMCS-24
.TW
100
W
tMCS
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M
.
.TW
00Y
M
O
1
W
M
.
O
W
O
W
WW — .100Y.C M.TW
0Y.C M.TW ns
Y.C tRHDX.TW
Data Hold After Read WW
0WW
0
0
1
0
.
1
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OM
WW
W.
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Y
WW 00Y
C
W
.
0
W
W
t
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W
0
Y
W
T
CLCL
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.
W
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00
Data Float After Read
W.1 Y.COM
W.1 2tY.C-5OM W
OM
W
W.1 Y.CtRHDZ
W
t
>0
W
W
CLCL
MCS
W
.T
W
M.
.100
.TW
100
00
M
.
O
1
W
M
.
O
W
C
.
O
W
-31
tMCS
CLCL
Y.C
W =0 .100Y
WW 00Y.tC
W
WW 2.5t
.TWns
M
ALE Low to Valid Data In W
100
LLDV M.T
M
.
1
.
O
W
O
WW 00Y.CO
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-26
tMCS
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W
C
.
W
C
W
.
Y
W
W
W
Y
W
.T
00
W
M
.1
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.100
OM
W3t.1CLCL-29
tMCS=0 WW
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OM
W
C
.
Y
W
C
W
.
0
Y
W
W
W
Port 0 Address to Valid Data In W
tAVDV1
ns
Y
W
10
00 -29 M.T
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O
M.T
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+2
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O
W
O
W
C
.
W
C
W
0Y.C
W
W
0
0Y
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T
.
1
WW .100Y.
T
.
.
M
t =0
W
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W t Y.COM W
WWCLCL 00Y.CO ns.TW MCS WW
Port 2 Address to Valid Data In
00Y
W
1
0
WW .1AVDV2
T
.
.
1
t
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t
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0
M
.
MCS
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MCS
W
OM
W
WW 00Y.CO .TW
WW .100Y.
W
W0.5t
WW .100Y.C M
0.5t.T
t
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1
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M
O
WW 00Y
WtLLWL
ALE Low to RD or WR Low
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WW
Y
W
W
0
W
tCLCL
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t
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t
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0
WW .100Y.C M
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.
W.1
W.1 Y.COM WMCS
O
W
W
W
C
.
W
00
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-9W
W
WWt .100Y
.100 nsOM.T tMCS=0
W.1
M
Port 0 Address to RD or WR Low
AVWL1
W
O
W
W
C
.
W
-7 W
tW >0
0
WW .100Y
WW .100Y.C 2tCLCL
M.T MCS
W.1
M.T
O
W
O
W
W
C
.
W
C
1.5t
-17
t
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W
.
Y
W
W
MCS
Y CLCL .TW
W
WtAVWL2
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.100 ns OM.T
Port 2 Address to RD or WR Low
.100 2.5t OM-16
W
WW
W
C
t
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.
W
C
CLCL
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.
Y
W
W
W
0
Y
W
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0
W
.T
00
W.1 nsY.COM W
WW
W.1 Y.C-6OM W
tQVWX
W
Data Valid to WR Transition
W
W
0
W
T
.
0
0
W
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0
M
.1
OM
W.1 tY
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WW 00Y.CO tMCS.=0
C
CLCL
W
.
W
W
W
W
Data Hold After Write
tWHQX
MT
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.1002tCLCL-6OM.T
O
W
W
t
>0
C
WW .100Y. MCS
WW .100Y.C M.TW
W
O
tRLAZ WW
RD Low to Address Float
W(Note 1) WW ns
Y.C
0
W
T
.
0
tMCS=0
W.1 -4 Y.COM W 10
tWHLH WW
ns
RD or WR High to ALE High
0
T
.
0
1
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W.tCLCL-5 OM tCLCL+5
WW .100Y.C
W
Note 1:
is a time period related to the Stretch memory cycle
t
WWselection. The following table shows the value of t for each Stretch
selection.
MCS
MCS
36 of 47
.
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .TW
W.1 Y.COM W
W
W
W
W
.T
00
W
M
OReal-Time
W.1 Ywith
M.T
.100
W.1 Y.COMEPROM/ROM
C
.
O
W
W
DS87C530/DS83C530
Microcontrollers
W Clock
W
C
W
.
W
W
.T
WW .100Y
M.T
.100
.TW
100
M
.
O
W
M
O
W
W
.C
Y.C
.CO .TW
WW .(continued)
.TW
WW STRETCH
.TW
100
00Y
WW CHARACTERISTICS
M
MOVX
USING
MEMORY
CYCLES
1
00Y
M
.
O
1
W
M
.
WW 00Y.CO .TW
WW .100Y.C M.TW
WW 00Y.CO .TW
W
WM2
1
M
.
M1 M
M0
MOVX CYCLES
O
W tMCS
.1
WW 00Y.CO .TW
WW .100Y.C M.TW
WW 00Y.CO .TW
W
W
0
0
0
M
.12 machine cycles
WW 0 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
0
M
.1
0W
3 machine
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4WtCLCL
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.10 0 OM.T 1
OM
W
.CO .TW
W
W
C
.
Y
W
C
W
.
0
Y
W
W
W
0
0
Y
W
T
.
M
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0W
4 .machine
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8 tCLCL
10
001
OM
W
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WW
W.1 Y.COM W
C
.
Y
W
W
0
Y
W
W
0
W 5 machine
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0 W
12 tCLCL
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W.1 Y.COM W
M.T1
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OM
W
O
W
W
C
.
W
C
W
Y
W16 t .100
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Y.
W 6 machine
1 WW
0W
CLCL
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OM
W
M.T
.1000
O
W
C
.
O
W
W
C
.
W tCLCL .100Y
.TW
WW
00Y
1
7 machine
cycles M.TW
20
WW 0.100Y.C M1.TW
M
1
.
O
W
O
W
O
W
W
W
Y.C
0Y.C M.TW
W8W
1
0 .TW
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24WtCLCL W.100
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WW 1 .100Y.C M
M.T
1
.
O
O
W
O
W
W
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Y.C
W
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W
1
9 machine
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28 W
tCLCL
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100
00Y
WW 1 .100Y.C 1M.TW
M
.
1
M
.
O
W
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C M.TW
O
W
WW 00Y.CO .TW
WW .100Y.C M.TW
WW 00Y.CO .TW
W
W
M
.1
EXTERNAL CLOCKWCHARACTERISTICS
O
W
M
.1
WW 00Y.CO .TW
.CO .TW
WW .100Y.C M.TW
W
Y
W
0
W
0
O
PARAMETER
MIN.1
TYP M MAX
UNITS WW
W.1 Y.COM SYMBOL
Y.C
WW 00Y.CO .TW
0
W
W
.TW
W
0
W
1
M
.
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1
00
M
.
Clock High Time W
10
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O
1
W
M
.
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W
O
W
Y.C
WW .100Y.C M.TW
WW
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WW .100Y.C M.TWtCLCX
Clock Low Time
10 W.100
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M
O
WW 00Y.CO .T
W
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W
C
.
Y
W
W
W
0
Y
W
0
W
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00
Clock Rise Time
W.1 Y.COM
W.1 Y.COM5 W ns
W
W.1 Y.COM CLCL
W
W
W
W
W
W
M.
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.T
Clock Fall Time
tCHCL
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100
00
M
.
O
1
W
M
.
O
W
C
.
O
W
W
Y
W
WW .100Y.C M.TW
WW .100Y.C M.TW
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W
O
W
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O
W
W
C
.
Y
W
C
W
.
0
Y
W
W
W
0
W
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00
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00Y
W.1 Y.COM
SERIAL PORT MODEW
0 TIMING
W.1 Y.COM W
OM
W
W.1 CHARACTERISTICS
W
C
.
W
W
W
.T
W
.100
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100
00Y
M
.
O
1
W
M
.
O
W
O
W
C
PARAMETER
SYMBOL
CONDITIONS
MAX
UNITS
W
Y.TYP
WW .100Y.C
0
WW MIN
T
.
0
WW .100Y.C M.TW
1
M
.
WW 00Y.C
W
WW 00Y.CO .TW
.CO .TW
W
Y
W
0
WW .SM2
clocks per cycle
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W.1 Y.
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W
Serial Port Clock Cycle
O
W
W
C
.
W
C
W
Y
ns W
tXLXL
W
00
W
WW .100Y.
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M.T
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O
W
O
W
W
C
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.
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W
WW .100CLCL
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WW .100Y.C M.TW
.100
M
W
O
W
O
W
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WW .100
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WW 10t
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O
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W
WW 0
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W
W ns
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tQVXH WWW
Y
W
0
Y
W
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0
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0
W.1
M
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cycle
O
W
W
W
C
.
W
W
W
WW .100Y
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O
W
O
WW
W
C
.
W
C
W
.
Y
W
W
W
0
Y
W 2tCLCL
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0
W
T
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00clocks per
Output Data Hold from
W.1 Y.COM ns
OM
WW
W.
W
tXHQX
C
W
.
W
W
W
0
Y
W
T
.
0
0
W
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0
W.1 Y.COM W
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cycle
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W4.1clocks
W
C
.
W
W
Y
W
W
M.T
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M.T
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O
W
O
W
C
W
.C
Y.
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0, 12 clocks
WtCLCL
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100
00Y per cycle
.
Input Data Hold after
1
M
.
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O
W
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Y.C
WW
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WW .100per
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W
WW .100Y.C M.TW
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0
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W
W
Input Data Valid
SM2 = 1, W
4 clocks per cycle
3tCLCL
37 of 47
.
WW 00Y.CO .TW
W.1 Y.COM W
WW 00Y.CO .TW
W
W
W
W
M
.1
.T
00
W.1 Y.COM W
WW 00Y.CO .TW
W.1 Y.COM W
W
W
W
W
.T
00
W
M
OReal-Time
W.1 Ywith
M.T
.100
W.1 Y.COMEPROM/ROM
C
.
O
W
W
DS87C530/DS83C530
Microcontrollers
W Clock
W
C
W
.
W
W
.T
WW .100Y
M.T
.100
.TW
100
M
.
O
W
M
O
W
O
W
WW .100Y.C M.TW
WW .100Y.C M.TW
WW .100Y.C OFMAC
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EXPLANATION
W
O
WW 00Y.CO .TW
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W
C
W
.
Y
W
WW to 0remain
W
0
Y
In anWeffort
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with
the
original
8051
family,
this
device
specifies
the same parameters
W
T
.
M
.10
W.1 Y.COM W
M.T
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O
W
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W
W
C
.
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W
M
O
W
C
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.
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W
C
W
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W
WW .100Y.
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W
M.T
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M
O
1
W
M
.
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W
C
O
W
W
Y.
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WW .100Y.C M.TW
W WWR signal
Instruction
t Time
100
WW .100Y.C M.TW I
M
.
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W
O
W
Y.C logic .TW
NoWlonger a00valid
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WW 00Y.CO .TW P
WW .100Y.C M.TW X W
1
W
.
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1
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Q
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W
OM
W.
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C
.
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Y
W
W
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W
0
0
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W
M
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D Input W
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M
O
1
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.
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O
W
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WW .100Y.C M.TW
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.
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L Logic levelW
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WW 00Y.CO .TW
W
WW 00Y.CO .TW
C
.
W
W
Y
W
W
M
.1
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00
W.1 Y.COM W
WW 00Y.CO .TW
W.1 Y.COM W
W
W
W
W
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00
W
W.1 Y.COM W
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W.1 Y.COM W
O
W
W
W
C
.
W
POWER-CYCLE
W
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WWTIMING
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100
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M
.
O
1
W
M
.
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W
C
O
W
Y.
W
Y.C
WW NOTES
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W
WMIN
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PARAMETER
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100
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WW .100Y.C M.TSYMBOL
M
.
1
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.
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W
O
W
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W
W
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W
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Cycle Startup TimeWW
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T
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.
.
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1
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.
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Power-On Reset Delay
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WW .100Y.C 65,536
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1
WW .100Y.C M.TtW
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.
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WW .100Y.C M.TW
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.
0
WWvaries.1with
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.
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WW 00Y.CO .T
W
WW 00Y.CO .TW
Fox.
C
.
W
W
W
Y
W
W
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Note 2:
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this
Otime
W.At1 33MHz,
OM
W
Wcounter
C
.
W
C
W
.
Y
W
W
W
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W
M.
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100
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M
.
O
1
W
M
.
O
W
C
.
O
W
W
Y
W
WW .100Y.C M.TW
WW .100Y.C M.TW
M
.100
W
O
W
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O
W
W
C
EPROM PROGRAMMING
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.
Y
W
C
W
.
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W
W
W
0
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00
W to +27°C.)
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W.1 Y.COM W
WW 00Y.CO
W.1 Y.COM W
W
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47 of 47
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No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
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