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Table B–3 shows the IEEE standard charts. In the charts, the second column is the result when
the user signal handler is disabled; the third column is the result when that handler is enabled.
The OS completion handler supplies the IEEE default that is specified in the second column.
The contents of the Alpha registers contain sufficient information for an enabled user handler
to compute the value in the third column.
Table B–3: IEEE Standard Charts
Exception
User Signal Handler
Disabled (IEEE Default)
User Signal Handler
Enabled (Optional)
Invalid Operation
(1) Input signaling NaN
Quiet NaN
(2) Mag. subtract Inf.
Quiet NaN
(3) 0 * Inf.
Quiet NaN
(4) 0/0 or Inf/Inf
Quiet NaN
(5) x REM 0 or Inf REM y
Quiet NaN
(6) SQRT(negative non-zero)
Quiet NaN
(7) Cvt to int(ovfl)
Low-order bits
(8) Cvt to int(Inf, NaN)
0
(9) Compare unordered
Quiet NaN
Division by Zero
x/0, x finite <>0
+/–Inf
Overflow
Round nearest
+/–Inf.
Res/2**192 or 1536
Round to zero
+/–MAX
Res/2**192 or 1536
Round to –Inf
+MAX/–Inf
Res/2**192 or 1536
Round to +Inf
+Inf/–MAX
Res/2**192 or 1536
0/denorm
Res*2**192 or 1536
Rounded
Res
Underflow
Underflow
Inexact
Inexact
B–12 Alpha Architecture Handbook