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DPC31 HW
9.6.2.1
Clock Supply (XPLLEN = ‘1’)
No.
Parameters
1
2
3
4
Min
Clock High Time
Clock Low Time
Rise Time
Fall Time
Max
Unit
1
1
ns
ns
ns
ns
7.5
9.8
Table 9.6-3: Input Clock
TCLH
TCLL
1
2
2,4V
CLK
0,6V
3
4
Figure 9.6-1: Clock Timing
9.6.2.2
Clock Outputs
The clock outputs (CLKOUT1X2 and CLKOUT1X4) are active during the RESET also. They are derived from
the PLL (when XPLLEN = ‘0’). The clock outputs thus have the inaccuracy of the PLL (frequency stability:
±400ppm; phase jitter: 1.5ns). Refer also to Chapter 7.8.1.
9.6.2.3
Interrupt
After acknowledging an interrupt with EOI, there is at least a 1us or 1 ms wait in the DPC31 prior to a new
interrupt being read out.
No.
1
Parameters
Interrupt Inactive Time (if EOI_Timebase = 0)
Interrupt Inactive Time (if EOI_Timebase = 1)
Min
Max
Unit
1
1
2
2
µs
ms
Table 9.6-4: Interrupt Inactive Time after EOI
X/INT
1
EOI
Figure 9.6-2: Peripheral Mode, Interrupt EOI Timing
DPC31 HW Description
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