Download Clevo E4120 Service manual

E5120Q/E5120Q-C, E5125/E5125-C, E5128Q, E5128Q-C
Preface
Notebook Computer
E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C
Service Manual
Preface
I
Preface
Notice
The company reserves the right to revise this publication or to change its contents without notice. Information contained
herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent vendor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this publication nor are
they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication.
This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or
reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publication, except for copies kept by the user for backup purposes.
Preface
Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks of
their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement
of that product or its manufacturer.
Version 1.0
November 2010
Trademarks
Intel, Intel Core, Intel Pentium and Intel Celeron are trademarks of Intel Corporation.
Windows® is a registered trademark of Microsoft Corporation.
Other brand and product names are trademarks and /or registered trademarks of their respective companies.
II
Preface
About this Manual
This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and
inspection of personal computers.
It is organized to allow you to look up basic information for servicing and/or upgrading components of the E5120Q/
E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C series notebook PC.
The following information is included:
Chapter 1, Introduction, provides general information about the location of system elements and their specifications.
Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to upgrade
elements of the system.
Preface
Appendix A, Part Lists
Appendix B, Schematic Diagrams
Appendix C, Updating the FLASH ROM BIOS
III
Preface
IMPORTANT SAFETY INSTRUCTIONS
Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to persons when using any electrical equipment:
Preface
1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet
basement or near a swimming pool.
2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of electrical shock from lightning.
3. Do not use the telephone to report a gas leak in the vicinity of the leak.
4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may
explode. Check with local codes for possible special disposal instructions.
5. This product is intended to be supplied by a Listed Power Unit with an AC Input of 100 - 240V, 50 - 60Hz, DC Output
of 19V, 3.42A or 18.5V, 3.5A (65W) minimum AC/DC Adapter.
CAUTION
This Computer’s Optical Device is a Laser Class 1 Product
FCC Statement
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
This device may not cause harmful interference.
This device must accept any interference received, including interference that may cause undesired operation.
IV
Preface
Instructions for Care and Operation
The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions:
1.
Don’t drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.
Do not expose the computer
to any shock or vibration.
2.
Do not place anything heavy
on the computer.
Keep it dry, and don’t overheat it. Keep the computer and power supply away from any kind of heating element. This
is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.
Do not leave it in a place
where foreign matter or moisture may affect the system.
Don’t use or store the computer in a humid environment.
Do not place the computer on
any surface which will block
the vents.
Preface
Do not expose it to excessive
heat or direct sunlight.
3.
Do not place it on an unstable
surface.
Follow the proper working procedures for the computer. Shut the computer down properly and don’t forget to save
your work. Remember to periodically save your data as data may be lost if the battery is depleted.
Do not turn off the power
until you properly shut down
all programs.
Do not turn off any peripheral
devices when the computer is
on.
Do not disassemble the computer by yourself.
Perform routine maintenance
on your computer.
V
Preface
4.
5.
Avoid interference. Keep the computer away from high capacity transformers, electric motors, and other strong magnetic fields. These can hinder proper performance and damage your data.
Take care when using peripheral devices.
Use only approved brands of
peripherals.
Unplug the power cord before
attaching peripheral devices.
Preface
Power Safety
The computer has specific power requirements:

VI
•
•
Power Safety
Warning
•
Before you undertake
any upgrade procedures, make sure that
you have turned off the
power, and disconnected all peripherals
and cables (including
telephone lines). It is
advisable to also remove your battery in
order to prevent accidentally turning the
machine on.
•
•
•
Only use a power adapter approved for use with this computer.
Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are
unsure of your local power specifications, consult your service representative or local power company.
The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do
not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one.
When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire.
Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices.
Before cleaning the computer, make sure it is disconnected from any external power supplies.
Do not plug in the power
cord if you are wet.
Do not use the power cord if
it is broken.
Do not place heavy objects
on the power cord.
Preface
Battery Precautions
• Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer.
• Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the
computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire.
• Recharge the batteries using the notebook’s system. Incorrect recharging may make the battery explode.
• Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service
personnel.
• Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode
or leak if exposed to fire, or improperly handled or discarded.
• Keep the battery away from metal appliances.
• Affix tape to the battery contacts before disposing of the battery.
• Do not touch the battery contacts with your hands or metal objects.
Battery Guidelines
Preface
The following can also apply to any backup batteries you may have.
• If you do not use the battery for an extended period, then remove the battery from the computer for storage.
• Before removing the battery for storage charge it to 60% - 70%.
• Check stored batteries at least every 3 months and charge them to 60% - 70%.

Battery Disposal
The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under various state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste
officials for details in your area for recycling options or proper disposal.
Caution
Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer.
Discard used battery according to the manufacturer’s instructions.
Battery Level
Click the battery icon
in the taskbar to see the current battery level and charge status. A battery that drops below a level of 10%
will not allow the computer to boot up. Make sure that any battery that drops below 10% is recharged within one week.
VII
Preface
Related Documents
You may also need to consult the following manual for additional information:
User’s Manual on CD/DVD
This describes the notebook PC’s features and the procedures for operating the computer and its ROM-based setup program. It also describes the installation and operation of the utility programs provided with the notebook PC.
System Startup
Remove all packing materials.
Place the computer on a stable surface.
Insert the battery and make sure it is locked in position.
Securely attach any peripherals you want to use with the computer
(e.g. keyboard and mouse) to their ports.
5. Attach the AC/DC adapter to the DC-In jack on the left of the
computer, then plug the AC power cord into an outlet, and connect
the AC power cord to the AC/DC adapter.
6. Use one hand to raise the lid/LCD to a comfortable viewing angle (do
not exceed 135 degrees); use the other hand (as illustrated in Figure
1) to support the base of the computer (Note: Never lift the computer
by the lid/LCD).
7. Press the power button to turn the computer “on”.
Preface
1.
2.
3.
4.

Shut Down
135 ﾟ
Figure 1
Opening the Lid/LCD/Computer with AC/DC Adapter
Plugged-In
VIII
Note that you should always shut your computer
down
by
choosing Shut Down
from the Start Menu.
This will help prevent
hard disk or system
problems.
Preface
Contents
Introduction ..............................................1-1
Overview .........................................................................................1-1
Specifications ..................................................................................1-2
External Locator - Top View with LCD Panel Open ......................1-4
External Locator - Front & Right Side Views .................................1-5
External Locator - Left Side & Rear View .....................................1-6
External Locator - Bottom View .....................................................1-7
Mainboard Overview - Top (Key Parts) .........................................1-8
Mainboard Overview - Bottom (Key Parts) ....................................1-9
Mainboard Overview - Top (Connectors) .....................................1-10
Mainboard Overview - Bottom (Connectors) ...............................1-11
Overview .........................................................................................2-1
Maintenance Tools ..........................................................................2-2
Connections .....................................................................................2-2
Maintenance Precautions .................................................................2-3
Disassembly Steps ...........................................................................2-4
Removing the Battery ......................................................................2-5
Removing the Hard Disk Drive .......................................................2-6
Removing the Optical (CD/DVD) Device ......................................2-8
Removing the System Memory (RAM) ..........................................2-9
Removing and Installing a Processor ............................................2-11
Removing the 3G Module .............................................................2-14
Removing the Wireless LAN Module ...........................................2-15
Removing the Bluetooth Module ..................................................2-16
Removing the Keyboard ................................................................2-17
Part Lists ..................................................A-1
Part List Illustration Location ........................................................ A-2
Top (E5120Q) ................................................................................ A-3
Schematic Diagrams................................. B-1
System Block Diagram ...................................................................B-2
Clock Generator ..............................................................................B-3
CPU 1/7 (DMI, PEG, FDI) .............................................................B-4
CPU 2/7 (CLK, MISC, JTAG) .......................................................B-5
CPU 3/7 (DDR3) ............................................................................B-6
CPU 4/7 (Power) .............................................................................B-7
CPU 5/7 (Graphics Power) .............................................................B-8
CPU 6/7 (GND) ..............................................................................B-9
CPU 7/7 (RESERVED) ................................................................B-10
DDR3 SO-DIMM_0 .....................................................................B-11
DDR3 SO-DIMM_1 .....................................................................B-12
LVDS, Inverter .............................................................................B-13
HDMI, CRT ..................................................................................B-14
IBEXPEAK- M 1/9 .......................................................................B-15
IBEXPEAK - M 2/9 ......................................................................B-16
IBEXPEAK - M 3/9 ......................................................................B-17
IBEXPEAK - M 4/9 ......................................................................B-18
IBEXPEAK - M 5/9 ......................................................................B-19
IBEXPEAK - M 6/9 ......................................................................B-20
IBEXPEAK - M 7/9 ......................................................................B-21
IBEXPEAK - M 8/9 ......................................................................B-22
IBEXPEAK - M 9/9 ......................................................................B-23
New Card, Mini PCIE ...................................................................B-24
3G, CCD, TPM .............................................................................B-25
IX
Preface
Disassembly ...............................................2-1
Top (E5125) ................................................................................... A-4
Top (E5128Q) ................................................................................ A-5
Bottom ........................................................................................... A-6
DVD Dual Drive ............................................................................ A-7
LCD ............................................................................................... A-8
Preface
Preface
Card Reader/LAN JMB251C ....................................................... B-26
LAN (JMC251C), SATA HDD, ODD ......................................... B-27
Audio Codec VIA1812 ................................................................. B-28
KBC-ITE IT8502E ....................................................................... B-29
LED, MDC, BT ............................................................................ B-30
USB, Fan, TP, Multi-Conn ........................................................... B-31
5VS, 3VS, 1.5VS .......................................................................... B-32
Power 3.3V/5V ............................................................................. B-33
Power 1.5V/0.75V, 1.8VS ............................................................ B-34
Power 1.1VS_VTT ....................................................................... B-35
Power VGFX_Core ...................................................................... B-36
V-Core .......................................................................................... B-37
AC_IN, Charger ........................................................................... B-38
Click Board .................................................................................. B-39
Audio Board/USB ........................................................................ B-40
Power Switch & LED Board ........................................................ B-41
External ODD Board .................................................................... B-42
Sequence ....................................................................................... B-43
Updating the FLASH ROM BIOS......... C-1
To update the FLASH ROM BIOS you must: C-1
Download the BIOS ....................................................................... C-1
Unzip the downloaded files to a bootable CD/DVD/ or USB Flash
drive ................................................................................................ C-1
Set the computer to boot from the external drive ........................... C-1
Use the flash tools to update the BIOS .......................................... C-2
Restart the computer (booting from the HDD) .............................. C-2
X
Introduction
Chapter 1: Introduction
Overview
This manual covers the information you need to service or upgrade the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/
E5128Q-C series notebook computer. Information about operating the computer (e.g. getting started, and the Setup utility) is in the User’s Manual. Information about dri-vers (e.g. VGA & audio) is also found in the User’s Manual. The
manual is shipped with the computer.
Operating systems (e.g. Windows Vista/ Window 7, etc.) have their own manuals as do application softwares (e.g. word
processing and database programs). If you have questions about those programs, you should consult those manuals.
1.Introduction
The E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C series notebook is designed to be upgradeable. See Disassembly on page 2 - 1 for a detailed description of the upgrade procedures for each specific component. Please take note
of the warning and safety information indicated by the “” symbol.
The balance of this chapter reviews the computer’s technical specifications and features.
Overview 1 - 1
Introduction
Specifications

Latest Specification Information
The specifications listed here are correct at the
time of sending them to the press. Certain items
(particularly processor types/speeds) may be
changed, delayed or updated due to the manufacturer's release schedule. Check with your
service center for more details.
Processor Options
BIOS
Intel® Core™ i7 Processor
One 32Mb SPI Flash ROM
Phoenix™ BIOS
i7-640M (2.80GHz), i7-620M (2.66GHz)
4MB L3 Cache & 1066MHz FSB
i5-540M (2.53GHz), i5-520M (2.4GHz), 
i5-450M (2.4GHz), i5-430M (2.26GHz)
3MB L3 Cache & 1066MHz FSB
(Factory Option) One Changeable 12.7mm(h) Super Multi
Optical Device Drive
One Changeable 2.5" 9.5 mm (h) SATA HDD
Intel® Core™ i3 Processor
Audio
i3-370M (2.4GHz), i3-350M (2.26GHz), i3-330M (2.13GHz)
3MB L3 Cache & 1066MHz FSB
1.Introduction
Intel® Pentium® Processor
P6000 (1.86GHz)
3MB L3 Cache & 1066MHz FSB

CPU
The CPU is not a user serviceable part. Accessing the CPU in any way may violate your
warranty.
Intel® Celeron® Processor
High Definition Audio Compliant Interface
2 * Built-In Speakers
Built-In Microphone
Keyboard
Full-size “WinKey” keyboard (with numeric keypad)
P4500 (1.86GHz)
2MB L3 Cache & 1066MHz FSB
Pointing Device
LCD
Built-in Touchpad
15.6" (39.62) HD TFT LCD
Security
Memory
Security (Kensington® Type) Lock Slot
BIOS Password
Two 204 Pin SO-DIMM Sockets Supporting DDR3 1066/
1333 MHz Memory
Memory Expandable up to 8GB
Interface
Core Logic
Intel ® HM55 Chipset
Video Adapter
Intel ® HM55 Integrated Video
Shared Memory Architecture of up to 1748MB
MS DirectX® 10 compatible
1 - 2 Specifications
Storage
Intel® Core™ i5 Processor
Three USB 2.0 Ports
One HDMI-Out Port
One Headphone-Out Jack
One Microphone-In Jack
One RJ-45 LAN Jack
One DC-in Jack
One External Monitor Port
Introduction
Card Reader
Environmental Spec
Embedded Multi-In-1 Card Reader
MMC (MultiMedia Card) / RS MMC
SD (Secure Digital) / Mini SD / SDHC/ SDXC
Compatible
MS (Memory Stick) / MS Pro / MS Duo
Temperature
Operating: 5°C - 35°C
Non-Operating: -20°C - 60°C
Communication
Dimensions & Weight
374mm (w) * 250mm (d) * 14.3 - 34.1mm (h)
2.3 kg (with 48.84WH Battery and ODD)
1.Introduction
Built-In Gigabit Ethernet LAN
(Factory Option) 300K/ 1.3M Pixel USB PC Camera Module
(Factory Option) Bluetooth 2.1 + EDR Module
(Factory Option) 3.75G/HSPA Half Mini-Card Module
(Factory Option) Combo WLAN (802.11b/g/n) and Bluetooth 3.0 Module
(Factory Option) Intel® WiFi Link 1000 (802.11b/g/n) Wireless LAN Half Mini-Card Module
(Factory Option) Third-Party 802.11b/g/n Wireless LAN Half
Mini-Card Module
Relative Humidity
Operating: 20% - 80%
Non-Operating: 10% - 90%
Power
6 Cell Smart Lithium-Ion Battery Pack, 48.84WH
(Factory Option) 6 Cell Smart Lithium-Ion Battery Pack,
62.16WH
(Factory Option) 4 Cell Smart Lithium-Ion Battery Pack,
32.56WH
Full Range AC/DC Adapter
AC Input: 100 - 240V, 50 - 60Hz
DC Output: 19V, 3.42A or 18.5V, 3.5A (65W)
Energy Star 5.0 Compliant
Specifications 1 - 3
Introduction
Figure 1
External Locator - Top View with LCD Panel Open
1.Introduction
Top View
1
1. PC Camera
(Optional)
2. LCD
3. Power Button
4. LED Status
Indicators
5. Keyboard
6. Built-In
Microphone
7. Touchpad &
Buttons
2
4
3
5
6
7
1 - 4 External Locator - Top View with LCD Panel Open
Introduction
External Locator - Front & Right Side Views
Figure 2
Front View
1. LED Indicators
FRONT VIEW
1
Right Side View
RIGHT SIDE VIEW
1
2
3
4
5
1. Microphone-In
Jack
2. Headphone-Out
Jack
3. USB 2.0 Port
4. Optical Device
Drive Bay
5. Emergency Eject
Hole
External Locator - Front & Right Side Views 1 - 5
1.Introduction
Figure 3
Introduction
External Locator - Left Side & Rear View
Figure 4
Left Side View
/
LEFT SIDE VIEW
1
2
3
4
5
6
1.Introduction
1. DC-In Jack
2. External Monitor
Port
3. RJ-45 LAN Jack
4. HDMI-Out Port
5. 2 * USB 2.0 Ports
6. Vent
7. Multi-in-1 Card
Reader
Figure 5
REAR VIEW
Rear View
1. Security Lock Slot
2. Battery
1
1 - 6 External Locator - Left Side & Rear View
2
5
7
Introduction
External Locator - Bottom View
Figure 6
Bottom View
1
3
3
2
6
3
3
3

4
Overheating
5
5
To prevent your computer from overheating, make sure nothing blocks any vent
while the computer is
in use.
External Locator - Bottom View 1 - 7
1.Introduction
1. Battery
2. Component Bay
Cover
3. Vent
4. Hard Disk Bay
Cover
5. Speakers
6. USIM Card
Cover
Introduction
Figure 7
Mainboard Overview - Top (Key Parts)
Mainboard Top
Key Parts
1.Introduction
1. JMC251C
2. Clock Generator
3. KBC-ITE IT8502E
2
3
1
1 - 8 Mainboard Overview - Top (Key Parts)
Introduction
Mainboard Overview - Bottom (Key Parts)
Figure 8
Mainboard Bottom
Key Parts
8
7
6
4
2
5
3
Mainboard Overview - Bottom (Key Parts) 1 - 9
1.Introduction
1
1. Memory Slots
DDR3 SO-DIMM
2. Mini-Card
Connector (3.5G
Module)
3. Audio Codec
4. USIM Card
5. Mini-Card
Connector (WLAN
Module)
6. Multi-in-1 Card
Reader
7. Platform Controller
Hub
8. CPU Socket (CPU
installed)
Introduction
Figure 9
Mainboard Overview - Top (Connectors)
1.Introduction
Mainboard Top
Connectors
1. HDMI-Out Port
2. USB Ports
3. Speaker Cable
Connector
4. Microphone
Cable Connector
5. TouchPad Cable
Connector
6. Click Board
Connector
7. Audio Board
Connector
8. Keyboard Cable
Connector
9. Switch Board
Cable Connector
9
1
8
2
4
5
6
2
7
3
1 - 10 Mainboard Overview - Top (Connectors)
Introduction
Mainboard Overview - Bottom (Connectors)
Figure 10
8
10
9
7
1
6
2
1. Battery
Connector
2. ODD Connector
3. HDD Connector
4. Bluetooth Cable
Connector
5. CPU Fan Cable
Connector
6. RJ-45 LAN Jack
7. External Monitor
Port
8. DC-In Jack
9. CCD Cable
Connector
10. LCD Cable
Connector
11. CMOS Battery
Connector
5
4
3
Mainboard Overview - Bottom (Connectors) 1 - 11
1.Introduction
11
Mainboard Bottom
Connectors
1.Introduction
Introduction
1 - 12
Disassembly
Chapter 2: Disassembly
Overview
This chapter provides step-by-step instructions for disassembling the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/
E5128Q-C series notebook’s parts and subsystems. When it comes to reassembly, reverse the procedures (unless otherwise indicated).
We suggest you completely review any procedure before you take the computer apart.
To make the disassembly process easier each section may have a box in the page margin. Information contained under
the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a 
lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the disassembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previous disassembly procedure. The amount of screws you should be left with will be listed here also.

Information
A box with a  will also provide any possible helpful information. A box with a  contains warnings.
An example of these types of boxes are shown in the sidebar.

Warning
Overview 2 - 1
2.Disassembly
Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the User’s Manual but are
repeated here for your convenience.
Disassembly
NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the
battery is removed too).
Maintenance Tools
The following tools are recommended when working on the notebook PC:
2.Disassembly
•
•
•
•
•
•
M3 Philips-head screwdriver
M2.5 Philips-head screwdriver (magnetized)
M2 Philips-head screwdriver
Small flat-head screwdriver
Pair of needle-nose pliers
Anti-static wrist-strap
Connections
Connections within the computer are one of four types:
2 - 2 Overview
Locking collar sockets for ribbon connectors
To release these connectors, use a small flat-head screwdriver to
gently pry the locking collar away from its base. When replacing the connection, make sure the connector is oriented in the
same way. The pin1 side is usually not indicated.
Pressure sockets for multi-wire connectors
To release this connector type, grasp it at its head and gently
rock it from side to side as you pull it out. Do not pull on the
wires themselves. When replacing the connection, do not try to
force it. The socket only fits one way.
Pressure sockets for ribbon connectors
To release these connectors, use a small pair of needle-nose pliers to gently lift the connector away from its socket. When replacing the connection, make sure the connector is oriented in
the same way. The pin1 side is usually not indicated.
Board-to-board or multi-pin sockets
To separate the boards, gently rock them from side to side as
you pull them apart. If the connection is very tight, use a small
flat-head screwdriver - use just enough force to start.
Disassembly
Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a removal and/or replacement job, take the following precautions:
•Before removing or servicing any part from the computer, turn the computer off and detach any power supplies.
•When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire.
6. Peripherals – Turn off and detach any peripherals.
7. Beware of static discharge. ICs, such as the CPU and main support chips, are vulnerable to static electricity.
Before handling any part in the computer, discharge any static electricity inside the computer. When handling a
printed circuit board, do not use gloves or other materials which allow static electricity buildup. We suggest that
you use an anti-static wrist strap instead.
8. Beware of corrosion. As you perform your job, avoid touching any connector leads. Even the cleanest hands produce oils which can attract corrosive elements.
9. Keep your work environment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted
to charged surfaces, reducing performance.
10. Keep track of the components. When removing or replacing any part, be careful not to leave small parts, such as
screws, loose inside the computer.
Power Safety
Warning
Before you undertake
any upgrade procedures, make sure that
you have turned off the
power, and disconnected all peripherals
and cables (including
telephone lines). It is
advisable to also remove your battery in
order to prevent accidentally turning the
machine on.
Cleaning
Do not apply cleaner directly to the computer, use a soft clean cloth.
Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.
Overview 2 - 3
2.Disassembly
1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other
components could be damaged.
2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight.
3. Avoid interference. Note the proximity of any high capacity transformers, electric motors, and other strong magnetic fields. These can hinder proper performance and damage components and/or data. You should also monitor
the position of magnetized tools (i.e. screwdrivers).
4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly
damaged.
5. Be careful with power. Avoid accidental shocks, discharges or explosions.

Disassembly
Disassembly Steps
The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM
THE DISASSEMBLY STEPS IN THE ORDER INDICATED.
To remove the Battery:
1. Remove the battery
To remove the Bluetooth Module:
page 2 - 5
1. Remove the battery
2. Remove the Bluetooth Module
page 2 - 5
page 2 - 6
To remove the Keyboard:
To remove the HDD:
2.Disassembly
1. Remove the battery
2. Remove the HDD
To remove the Optical Device:
1. Remove the battery
2. Remove the Optical device
page 2 - 5
page 2 - 8
To remove the System Memory:
1. Remove the battery
2. Remove the system memory
page 2 - 5
page 2 - 9
To remove and install a Processor:
1. Remove the battery
2. Remove the processor
3. Install the processor
page 2 - 5
page 2 - 11
page 2 - 13
To remove the 3G Module:
1. Remove the battery
2. Remove the 3G module
page 2 - 5
page 2 - 14
To remove the Wireless LAN Module:
1. Remove the battery
2. Remove the WLAN module
2 - 4 Disassembly Steps
page 2 - 5
page 2 - 15
1. Remove the battery
2. Remove the keyboard
page 2 - 5
page 2 - 16
page 2 - 5
page 2 - 17
Disassembly
Removing the Battery
1.
2.
3.
4.
Figure 1
Battery Removal
Turn the computer off, and turn it over.
Slide the latch 1 in the direction of the arrow (Figure 1a).
Slide the latch 2 in the direction of the arrow, and hold it in place (Figure 1a).
Slide the battery 63 in the direction of the arrow 4 (Figure 1b).
a. Slide latch at point 1 towards the unlock symbol
and hold it in place.
b. Slide the battery in the direction of the arrow.
b.
a.
2
1
3
2.Disassembly
4

3. Battery
Removing the Battery 2 - 5
Disassembly
Removing the Hard Disk Drive
Figure 2
HDD Assembly
Removal
2.Disassembly
a. Locate the HDD bay cover
and remove the screws.
The hard disk drive can be taken out to accommodate other 2.5" serial (SATA) hard disk drives with a height of 9.5mm
(h). Follow your operating system’s installation instructions, and install all necessary drivers and utilities (as outlined in
Chapter 4 of the User’s Manual) when setting up a new hard disk.
Hard Disk Upgrade Process
1. Turn off the computer, and remove the battery (page 2 - 5).
2. Locate the hard disk bay cover and remove screws 1 & 2 (Figure 2a).

a.
HDD System Warning
New HDD’s are blank. Before you
begin make sure:
You have backed up any data
you want to keep from your old
HDD.
1

• 2 Screws
2 - 6 Removing the Hard Disk Drive
2
You have all the CD-ROMs and
FDDs required to install your operating system and programs.
If you have access to the internet,
download the latest application
and hardware driver updates for
the operating system you plan to
install. Copy these to a removable medium.
Disassembly
3.
4.
5.
6.
7.
Remove the hard disk bay cover 63 (Figure 3b).
Grip the tab and slide the hard disk in the direction of arrow 4 (Figure 3c).
Lift the hard disk 5 out of the bay 6 (Figure 3d).
Remove the screw 7 - 10 and the mylar cover 11 from the hard disk 12 (Figure 3e).
Reverse the process to install a new hard disk (do not forget to replace all the screws and covers).
b.
d.
6
5
Figure 3
HDD Assembly
Removal (cont’d.)
b. Remove the HDD bay
cover.
c. Grip the tab and slide the
HDD in the direction of
the arrow.
d. Lift the HDD assembly
out of the bay.
e. Remove the screws and
mylar cover.
2.Disassembly
e.
3
e.
c.

7
8
10
11
9
4
3. HDD Bay Cover
11. Adhesive Cover
12. HDD
• 4 Screws
12
Removing the Hard Disk Drive 2 - 7
Disassembly
Figure 4
Optical Device
Removal
a. Remove the screw at
point 1 .
b. Use a screwdriver to
carefully push out the
optical device at point
2 .
Removing the Optical (CD/DVD) Device
1.
2.
3.
4.
Turn off the computer, remove the battery (page 2 - 5) and hard disk (page 2 - 6).
Remove the screw at point 1 (Figure 4a).
Use a screwdriver to carefully push out the optical device 3 at point 2 (Figure 4b).
Insert the new device and carefully slide it into the computer (the device only fits one way. DO NOT FORCE IT; The
screw holes should line up).
5. Restart the computer to allow it to automatically detect the new device.
2.Disassembly
a.
b.
3
1
2

3. Optical Device
• 1 Screw
2 - 8 Removing the Optical (CD/DVD) Device
2
Disassembly
Removing the System Memory (RAM)
Figure 5
The computer has two memory sockets for 200 pin Small Outline Dual In-line Memory Modules (SO-DIMM) supporting
DDRIII (DDR3) Up to 1066/1333 MHz. The main memory can be expanded up to 8GB. The SO-DIMM modules supported are 1024MB and 2048MB DDRIII Modules. The total memory size is automatically detected by the POST routine once you turn on your computer.
Memory Upgrade Process
1.
2.
3.
4.
Turn off the computer, turn it over and remove the battery (page 2 - 5).
Remove screws 1 - 4 from the component bay cover (Figure 5a).
The RAM modules will be visible at point 5 on the mainboard (Figure 5b).
Gently pull the two release latches ( 6 & 7 ) on the sides of the memory socket in the direction indicated by the
arrows (Figure 5c). The RAM module 8 will pop-up (Figure 5d), and you can then remove it.
1
d.
c.

2
Contact Warning
6
3
8
4
7
b.
5
a. Remove the screws
from the component
bay cover.
b. The RAM modules will
be visible at point 5
on the mainboard.
c. Pull the release latches.
d. Remove the module.
Be careful not to touch
the metal pins on the
module’s
connecting
edge. Even the cleanest
hands have oils which
can attract particles, and
degrade the module’s
performance.

8. RAM Module
• 4 Screws
Removing the System Memory (RAM) 2 - 9
2.Disassembly
a.
RAM Module
Removal
Disassembly
2.Disassembly
5. Pull the latches to release the second module if necessary.
6. Insert a new module holding it at about a 30° angle and fit the connectors firmly into the memory slot.
7. The module will only fit one way as defined by its pin alignment. Make sure the module is seated as far into the slot
as it will go. DO NOT FORCE IT; it should fit without much pressure.
8. Press the module in and down towards the mainboard until the slot levers click into place to secure the module.
9. Replace the component bay cover and the screws (see page 2 - 8).
10. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.
2 - 10 Removing the System Memory (RAM)
Disassembly
Removing and Installing a Processor
Figure 6
Processor Removal Procedure
Processor Removal
1. Turn off the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 8).
2. Locate the heat sink.
3. Loosen the CPU heat sink screws in the order 3 , 2 & 1 (the reverse order as indicated on the label Figure
6b).
4. Carefully lift up the heat sink 4 (Figure 6c) off the computer.
a. Locate the heat sink.
b. Remove the screws from
the CPU heatsink.
c. Remove the CPU heat
sink.
a.
c.
2.Disassembly
4
A
b.
3
1

2
4. Heat Sink
• 3 Screws
Removing and Installing a Processor 2 - 11
Disassembly
Figure 7
Processor Removal
(cont’d)
d. Turn the release latch to
unlock the CPU.
e. Lift the CPU out of the
socket.
5.
6.
7.
8.
Turn the release latch 5 towards the unlock symbol
to release the CPU (Figure 7d).
Carefully (it may be hot) lift the CPU 6 up and out of the socket (Figure 7e).
Reverse the process to install a new CPU.
When re-inserting the CPU, pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!).
d.
5
2.Disassembly
5
Unlock
Lock
e.

Caution
6

6. CPU
2 - 12 Removing and Installing a Processor
The heat sink, and CPU area in
general, contains parts which are
subject to high temperatures. Allow
the area time to cool before removing these parts.
Disassembly
Processor Installation Procedure
Figure 8
1. Insert the CPU A (Figure 8a), pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE
IT!), and turn the release latch B towards the lock symbol
(Figure 8b).
2. Remove the sticker C (Figure 8c) from the heat sink.
3. Insert the heat sink D as indicated in Figure 8d.
4. Tighten the CPU heat sink screws in the order 1 , 2 & 3 (the order as indicated on the label and Figure 8d).
5. Replace the component bay cover (don’t forget to replace the fan cable) and tighten the screws (page 2 - 9).
a.
c.
Processor
Installation
a. Insert the CPU.
b. Turn the release latch towards the lock symbol.
c. Remove the sticker from
the heat sink and insert
the heat sink.
d. Tighten the screws.
A
2.Disassembly
C
d.
b.
B
D
3
1
2
Note:
Tighten the screws
in the order as indicated on the label.

A. CPU
D. Heat Sink
• 3 Screws
Removing and Installing a Processor 2 - 13
Disassembly
Figure 9
3G Module Removal
a. Locate the 3G module.
b. Disconnect the cable
and remove the screw.
c. Remove the 3G module.
Removing the 3G Module
1.
2.
3.
4.
Turn off the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
The 3G module will be visible at point 1 on the mainboard (Figure 9a).
Carefully disconnect the cable 2 , and then remove the screw 3 (Figure 9b).
The 3G module 4 (Figure 9c) will pop-up, and you can remove it from the computer (Figure 9d).
2.Disassembly
a.
d.
c.
Note: Make sure you
reconnect the antenna
cable to socket (Figure 9b).
4
1
no 3g
b.
4

2
4. 3G Module
• 1 Screw
3
2 - 14 Removing the 3G Module
Disassembly
Removing the Wireless LAN Module
1.
2.
3.
4.
Figure 10
Turn off the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 9).
The Wireless LAN module will be visible at point 1 on the mainboard (Figure 10a).
Carefully disconnect the cables 2 & 3 , and then remove the screw 4 (Figure 10b).
The Wireless LAN module 5 (Figure 10c) will pop-up, and you can remove it from the computer (Figure 10d).
c.
a.
Wireless LAN
Module Removal
a. Locate the WLAN.
b. Disconnect the cables
and remove the screw.
c. The WLAN module will
pop up.
d. Remove the Wireless
LAN module.
5
1
b.
d.
4
3
5

5.Wireless LAN Module
2
• 1 Screw
Removing the Wireless LAN Module 2 - 15
2.Disassembly
Note: Make sure you
reconnect the antenna
cable to the “1 + 2”
socket (Figure 10b).
Disassembly
Figure 11
Bluetooth Module
Removal
1.
2.
3.
4.
5.
Turn off the computer, turn it over, and remove the battery (page 2 - 5) and the component bay cover (page 2 - 8).
The Bluetooth module will be visible at point 1 on the mainboard (Figure 11a).
Remove screw 2 (Figure 11b) and turn the module over (Figure 11c).
Carefully disconnect the cable 3 and separate the connector 4 (Figure 11c) from the Bluetooth Module.
Lift the Bluetooth Module 5 (Figure 11d) up and off the computer.
a.
c.
d.
3
2.Disassembly
a. Locate the Bluetooth
module.
b. Remove the screw and
turn the module over.
c. Disconnect the cable
and the connector from
the Bluetooth module.
d. Lift the Bluetooth module
out.
Removing the Bluetooth Module
4
1
b.
5

5. Bluetooth Module
2
• 1 Screw
2 - 16 Removing the Bluetooth Module
Disassembly
Removing the Keyboard
Figure 12
1. Turn off the computer, and remove the battery (page 2 - 5).
2. Remove screws 1 - 2 from the bottom of the computer. Press at point 3 to unsnap the LED cover module (you
may need to use a small screwdriver to do this Figure 12a).
3. Turn the computer over, unsnap up the LED cover module 4 from point 5 on the left of the computer, towards the
right (Figure 12b).
4. Remove screws 6 - 10 from the keyboard (Figure 12c).
5. Carefully lift the keyboard up, being careful not to bend the keyboard ribbon cable 11 . Disconnect the keyboard
ribbon cable 11 from the locking collar socket 12 (Figure 12d)
6. Carefully lift up the keyboard 13 (Figure 12e) off the computer.
a.
d.
12
3
1
a. Remove screws from the
bottom of the computer.
b. Turn the computer over,
unsnap up the LED cover module from point 5
towards the right .
c. Remove screws from
the keyboard.
d. Carefully lift the keyboard up and disconnect
the keyboard ribbon cable from the locking collar socket.
e. Remove the keyboard.
2
b.

5
Re-Inserting the
Keyboard
4
e.
When re-inserting the
keyboard firstly align the
four keyboard tabs at the
bottom (Figure 12c) at
the bottom of the keyboard with the slots in the
case.
c.
6
7
8
9
10
13

4. LED Cover Module
13. Keyboard
• 7 Screws
Keyboard Tabs
Removing the Keyboard 2 - 17
2.Disassembly
11
Keyboard Removal
2.Disassembly
Disassembly
2 - 18
Appendix A:Part Lists
This appendix breaks down the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C series notebook’s construction into a series of illustrations. The component part numbers are indicated in the tables opposite the drawings.
Note: This section indicates the manufacturer’s part numbers. Your organization may use a different system, so be sure
to cross-check any relevant documentation.
Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the
total number of duplicated parts used.
A.Part Lists
Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the
time of publication. Over the product life, some parts may be improved or re-configured, resulting in new part numbers.
A - 1
Part List Illustration Location
The following table indicates where to find the appropriate part list illustration.
Table A - 1
A.Part Lists
Part List Illustration
Location
A - 2
Part
E5120Q/E5120Q-C/E5125/
E5125-C/E5128Q/E5128Q-C
Top (E5120Q)
page A - 3
Top (E5125)
page A - 4
Top (E5128Q)
page A - 5
Bottom
page A - 6
DVD Dual Drive
page A - 7
LCD
page A - 8
Top (E5120Q)
非耐落
灰色
Top (E5120Q) A - 3
A.Part Lists
Figure A - 1
Top (E5120Q)
Top (E5125)
A.Part Lists
Figure A - 2
Top (E5125)
非耐落
灰色
A - 4 Top (E5125)
Top (E5128Q)
非耐落
非耐落
非耐落
非耐落
非耐落
灰色
灰色
非耐落
灰色
Top (E5128Q) A - 5
A.Part Lists
Figure 3
Top (E5128Q)
Bottom
A.Part Lists
Figure A - 4
Bottom
A - 6 Bottom
DVD Dual Drive
Figure A - 5
非耐落
志精
DVD Dual Drive A - 7
A.Part Lists
DVD Dual Drive
LCD
A.Part Lists
Figure A - 6
LCD
頭厚
非耐落
頭厚
非耐落
A - 8 LCD
Schematic Diagrams
Appendix B: Schematic Diagrams
This appendix has circuit diagrams of the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C notebook’s PCB’s.
The following table indicates where to find the appropriate schematic diagram.
Table B - 1
Diagram - Page
Diagram - Page
Diagram - Page
IBEXPEAK - M 2/9 - Page B - 16
LED, MDC, BT - Page B - 30
Clock Generator - Page B - 3
IBEXPEAK - M 3/9 - Page B - 17
USB, Fan, TP, Multi-Conn - Page B - 31
CPU 1/7 (DMI, PEG, FDI) - Page B - 4
IBEXPEAK - M 4/9 - Page B - 18
5VS, 3VS, 1.5VS - Page B - 32
CPU 2/7 (CLK, MISC, JTAG) - Page B - 5
IBEXPEAK - M 5/9 - Page B - 19
Power 3.3V/5V - Page B - 33
CPU 3/7 (DDR3) - Page B - 6
IBEXPEAK - M 6/9 - Page B - 20
Power 1.5V/0.75V, 1.8VS - Page B - 34
CPU 4/7 (Power) - Page B - 7
IBEXPEAK - M 7/9 - Page B - 21
Power 1.1VS_VTT - Page B - 35
CPU 5/7 (Graphics Power) - Page B - 8
IBEXPEAK - M 8/9 - Page B - 22
Power VGFX_Core - Page B - 36
CPU 6/7 (GND) - Page B - 9
IBEXPEAK - M 9/9 - Page B - 23
V-Core - Page B - 37
CPU 7/7 (RESERVED) - Page B - 10
New Card, Mini PCIE - Page B - 24
AC_IN, Charger - Page B - 38
DDR3 SO-DIMM_0 - Page B - 11
3G, CCD, TPM - Page B - 25
Click Board - Page B - 39
DDR3 SO-DIMM_1 - Page B - 12
Card Reader/LAN JMB251C - Page B - 26
Audio Board/USB - Page B - 40
LVDS, Inverter - Page B - 13
LAN (JMC251C), SATA HDD, ODD - Page B - 27
Power Switch & LED Board - Page B - 41
HDMI, CRT - Page B - 14
Audio Codec VIA1812 - Page B - 28
External ODD Board - Page B - 42
IBEXPEAK- M 1/9 - Page B - 15
KBC-ITE IT8502E - Page B - 29

Version Note
The schematic diagrams in this chapter
are based upon version 6-7P-E51Q5-003.
If your mainboard (or
other boards) are a later version, please
check with the Service
Center for updated diagrams (if required).
B - 1
B.Schematic Diagrams
System Block Diagram - Page B - 2
SCHEMATIC
DIAGRAMS
Schematic Diagrams
System Block Diagram
CLICK BOARD
Calpella System Block Diagram
6-71-E51Q2-D01A
POWER SWITCH BOARD
VDD3,VDD5
14.318 MHz
POWER SWITCH+HOTKEY X 3
6-71-E51QS-D01A
POWER GPU
Clock Generator
RTM875N-632-VB-GRT
AUDIO BOARD
Arrandale
PROCESSOR
rPGA989/988
USB+EARPHONE+EXT.MIC
6-71-C4508-D02A
EXTERNAL ODD BOARD
EXT. ODD
6-71-E51QN-D01
800/1067 MHz
DDR3 / 1.5V
5V,3V,5VS,3VS,1.5VS,
DDRIII
SO-DIMM0
SYSTEM SMBUS
0.1"~13
DDRIII
SO-DIMM1
B.Schematic Diagrams
SHEET 11
Sheet 1 of 42
System Block
Diagram
CRT SWITCH
INTERNAL
GRAPHICS
Ibex Peak-M
Platform
Controller
Hub (PCH)
Synaptic
810602-1703
LCD CONNECTOR,
<8"
LV DS S WI TC H
INTERNAL
GRAPHICS
128pins LQFP
1 4*14 *1.6 mm
0.5"~11"
27x27mm
1071 Ball FCBGA
INT. K/B
BIOS
SPI
Azalia Codec
VIA VT1812
INT MIC
AZALIA LINK
PCIE
SMART
FAN
SMART
BATTERY
SATA I/II 3.0Gb/s
24 MHz
100 MHz
<12"
32.768KHz
USB2.0
480 Mbps
<12"
New Card
SOCKET
(USB3)
3G CARD
(USB9)
Mini PCIE
SOCKET
(USB2)
JMICRO
JMC251 C
LAN
1"~16"
SATA ODD
USB0
USB1
USB4
AUDIO
BOARD
Bluetooth
(USB11)
CARD READER 25
MHz
RJ-45
B - 2 System Block Diagram
INT SPK L
EC SMBUS
THERMAL
SENSOR
W83L771AWG
SATA HDD
AMP
N7101
MDC CON
33 MHz
LPC
HP
OUT
INT SPK R
AZALIA
MDC
MODULE
TPM
SPI
MIC
IN
RJ-11
32.768 KHz
EC
ITE 8502E
1.1VS_VTT
AUDIO BOARD
CRT CONNECTOR
TOUCH PAD
VCORE
<=8"
0.5"~6.5"
<15"
CLICK BOARD
1.5V,0.75VS(VTT_MEM)
DMI*4
FDI
HDMI
1.8VS
Memory Termination
CCD
(USB5)
7IN1
SOCKET
Schematic Diagrams
Clock Generator
CLKGEN POWER
CLOCK GENERATOR
CL K _ V CC 1
CL K _ V CC 2
3 .3 VS
CL K _ V CC1
U7
1
5
17
24
29
27
28
XO U T
XI N
R1 3 4
3 3_ 0 4
RE F _ 0 /CP U_ S E L
30
CL K _ SDAT A
CL K _ SCL K
31
32
D_ DO T
D_ 2 7
D_ S RC
D_ CPU
D_ REF
D OT _ 96
D O T_ 9 6#
27M
2 7 M_ S S
X T A L _O U T
X T A L _I N
R E F _ 0/ C P U _ S E L
2
8
9
12
21
26
33
V DD_ S R C_ I/O
V DD_ CP U_ I/O
SD A
SC L
S R C _1 / S A T A
S R C _ 1 #/ S A TA #
S R C _2
S R C _ 2#
C P U _ S T OP #
V S S _D OT
V S S _2 7
V S S _S A T A
V S S _S R C
V S S _C P U
V S S _R E F
G ND
C P U _1
C P U _ 1#
C P U _0
C P U _ 0#
C K P W R GD / P D #
L15
3
4
C LK _B U F _D OT 9 6_ P 1 5
C LK _B U F _D OT 9 6_ N 15
C2 0 5
C 19 7
C 2 07
0 . 1u _ 1 6V _ Y 5 V _ 0 4
0 . 1 u_ 1 6 V _Y 5V _ 0 4
1u _ 6. 3 V _ X 5R _0 4
* 15 m i _l s ho rt _ 0 6
6
7
0. 1 u F n e ar t he e ve r y p o we r pi n
10
11
13
14
16
C LK _S A T A 1 5
C LK _S A T A # 1 5
C LK _P C I E _ I C H 1 5
C LK _P C I E _ I C H # 1 5
C P U _S T O P #
R 1 48
2. 2 1 K _1 % _ 04
20
19
23
22
25
3 .3 VS
1 . 1 V S _V TT
C LK _V C C 2
C LK _B U F _B C L K _P
C LK _B U F _B C L K _N
L 14
15
15
C 2 06
C1 9 6
0. 1 u _ 16 V _ Y 5 V _ 04
1 u_ 6 . 3 V _X 5 R _ 0 4
*1 5 mi l _ sh o rt _0 6
CL K _ P W RG D
V D D_ I / O c a n b e
r a ng i n g f r om
1 . 05 V to 3 .3 V
3 .3 VS
S L G 8S P 5 8 5
Sl e g o S L G8 S P 58 5 6- 0 2 -0 8 58 5 - EQ 0
Re a l te k RT M 8 75 N - 63 2 - VB - GR T
R 14 9
0 . 1u F ne a r t h e e v er y po w e r p i n
D
1 0 K _1 % _ 04
Sheet 2 of 42
Clock Generator
SMBus
CL KE N #
Q1 2
R 14 6
MT N 7 00 2 Z H S 3
1 M_ 0 4
G
S
36
Q1 1A
MT D N 70 0 2Z H S 6 R
S
D
2
EMI
CL K _ SCL K
C L K _ S C L K 1 0 , 11
6 -22 -1 4R3 1- 1B7
6 -22 -1 4R3 1- 1B6
1
S MB _ C L K
6
15
G
3 . 3V S
X1
5 VS
4
3
R N 15
2 . 2K _ 4 P 2 R _ 04
2
XIN
1
X OU T
R E F _ 0/ C P U _ S E L
C 19 4
*1 0 p_ 5 0V _N P O_ 0 6
CL K _ SDAT A
C L K _ S D A T A 1 0 , 11
C 20 2
33 p _5 0 V _ N P O_ 0 4
3 3 p_ 5 0 V _N P O_ 0 4
E MI C ap a ct i o r
S
D
S MB _ D A T A
C 1 99
5
15
4
3
G
1
2
H S X 5 30 G_ 1 4 . 31 8 18 M H z
Q1 1B
MT D N 70 0 2Z H S 6 R
CPU_SEL_During CK_PEWGD Latch Pinl
3 . 3V S
P IN _ 3 0
R1 3 6
R1 3 7
*4 . 7 K _0 4
C P U_ 0
C P U_ 1
0 ( d ef a u lt )
1 3 3M H z
1 3 3M H z
1 ( 0 .7 V - 1. 5 V )
1 0 0M H z
1 0 0M H z
R E F _0 / C P U _ S E L
1 0K _ 0 4
5V S
1 3 , 17 , 2 0, 2 1 , 2 6, 2 7 , 3 0, 3 1 , 35 , 3 6
3. 3 V
3 , 4 , 12 , 1 4, 1 5 , 1 6, 1 8 , 1 9, 2 0 , 21 , 2 3 , 24 , 2 5 , 29 , 3 0, 31 , 3 3, 3 4 , 3 5
3. 3 V S
1 0 , 11 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 18 , 1 9 , 20 , 2 1 , 23 , 2 4, 2 5 , 2 6, 2 7 , 2 8, 2 9 , 30 , 3 1 , 35 , 3 6
1. 1 V S _ V T T 4 , 6 , 7 , 14 , 1 5 , 16 , 1 9, 20 , 2 1, 3 4 , 3 5, 3 6
Clock Generator B - 3
B.Schematic Diagrams
15 C L K _ B U F _ R E F 14
VD
VD
VD
VD
VD
15
18
Schematic Diagrams
CPU 1/7 (DMI, PEG, FDI)
PROCESSOR
1/7
( DMI,PEG,FDI )
16
16
16
16
D M I _T X P 0
D M I _T X P 1
D M I _T X P 2
D M I _T X P 3
16
16
16
16
D
D
D
D
MI _ R
MI _ R
MI _ R
MI _ R
XN
XN
XN
XN
0
1
2
3
16
16
16
16
D
D
D
D
MI _ R
MI _ R
MI _ R
MI _ R
XP
XP
XP
XP
0
1
2
3
16
16
16
16
16
16
16
16
FD
FD
FD
FD
FD
FD
FD
FD
I _ T XN
I _ T XN
I _ T XN
I _ T XN
I _ T XN
I _ T XN
I _ T XN
I _ T XN
16
16
16
16
16
16
16
16
FD
FD
FD
FD
FD
FD
FD
FD
I _ T XP 0
I _ T XP 1
I _ T XP 2
I _ T XP 3
I _ T XP 4
I _ T XP 5
I _ T XP 6
I _ T XP 7
16
16
F DI_ F S Y NC 0
F DI_ F S Y NC 1
16
F DI_ IN T
16
16
F DI_ L S Y N C0
F DI_ L S Y N C1
B2 4
D2 3
B2 3
A2 2
D2 4
G2 4
F23
H2 3
D2 5
F24
E2 3
G2 3
E2 2
D2 1
D1 9
D1 8
G2 1
E1 9
F21
G1 8
0
1
2
3
4
5
6
7
D2 2
C2 1
D2 0
C1 8
G2 2
E2 0
F20
G1 9
It applies to Auburndale and Clarksfield discrete graphic designs.
If discrete graphic chip is used for Auburndale, VAXG (GFX core) rail can be connected
to GND if motherboard only supports discrete graphics and also in a common
motherboard design if GFX VR is not stuffed. On the other hand, if the VR is stuffed,
F17
E1 7
P E G_ I C OM P I
P E G _ I C O MP O
P E G_ R C O MP O
P E G_ R B I A S
DM I_ RX # [0 ]
DM I_ RX # [1 ]
DM I_ RX # [2 ]
DM I_ RX # [3 ]
DM I_ RX [0 ]
DM I_ RX [1 ]
DM I_ RX [2 ]
DM I_ RX [3 ]
DM
DM
DM
DM
I _ T X# [ 0 ]
I _ T X# [ 1 ]
I _ T X# [ 2 ]
I _ T X# [ 3 ]
DM
DM
DM
DM
I _ T X[ 0 ]
I _ T X[ 1 ]
I _ T X[ 2 ]
I _ T X[ 3 ]
FD
FD
FD
FD
FD
FD
FD
FD
I _T X # [ 0 ]
I _T X # [ 1 ]
I _T X # [ 2 ]
I _T X # [ 3 ]
I _T X # [ 4 ]
I _T X # [ 5 ]
I _T X # [ 6 ]
I _T X # [ 7 ]
FD
FD
FD
FD
FD
FD
FD
FD
I _T X [ 0 ]
I _T X [ 1 ]
I _T X [ 2 ]
I _T X [ 3 ]
I _T X [ 4 ]
I _T X [ 5 ]
I _T X [ 6 ]
I _T X [ 7 ]
F D I _F S Y N C [ 0 ]
F D I _F S Y N C [ 1 ]
C1 7
VAXG can be left floating in a common motherboard design (Gfx VR keeps VAXG from
floating).
In addition, FDI_RXN_[7:0] and FDI_RXP_[7:0] can be left floating on the PCH.
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Auburndale.
F D I _I N T
F18
D1 7
P E G_ R X # [ 0 ]
P E G_ R X # [ 1 ]
P E G_ R X # [ 2 ]
P E G_ R X # [ 3 ]
P E G_ R X # [ 4 ]
P E G_ R X # [ 5 ]
P E G_ R X # [ 6 ]
P E G_ R X # [ 7 ]
P E G_ R X # [ 8 ]
P E G_ R X # [ 9 ]
P E G_ R X# [ 1 0 ]
P E G_ R X# [ 1 1 ]
P E G_ R X# [ 1 2 ]
P E G_ R X# [ 1 3 ]
P E G_ R X# [ 1 4 ]
P E G_ R X# [ 1 5 ]
F D I _L S Y N C [ 0 ]
F D I _L S Y N C [ 1 ]
The GFX_IMON, FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and
FDI_INT signals should be tied to GND (through 1K ? % resistors) in the common
motherboard design case. Please not that if these signals are left floating, there are no
PCI EXPRESS -- GRAPHICS
D M I _T X N 0
D M I _T X N 1
D M I _T X N 2
D M I _T X N 3
Intel(R) FDI
Sheet 3 of 42
CPU 1/7
(DMI, PEG, FDI)
16
16
16
16
DMI
P E G _ RX [0 ]
P E G _ RX [1 ]
P E G _ RX [2 ]
P E G _ RX [3 ]
P E G _ RX [4 ]
P E G _ RX [5 ]
P E G _ RX [6 ]
P E G _ RX [7 ]
P E G _ RX [8 ]
P E G _ RX [9 ]
P E G_ R X [ 1 0 ]
P E G_ R X [ 1 1 ]
P E G_ R X [ 1 2 ]
P E G_ R X [ 1 3 ]
P E G_ R X [ 1 4 ]
P E G_ R X [ 1 5 ]
P E G _ TX # [ 0 ]
P E G _ TX # [ 1 ]
P E G _ TX # [ 2 ]
P E G _ TX # [ 3 ]
P E G _ TX # [ 4 ]
P E G _ TX # [ 5 ]
P E G _ TX # [ 6 ]
P E G _ TX # [ 7 ]
P E G _ TX # [ 8 ]
P E G _ TX # [ 9 ]
P E G_ T X# [ 1 0 ]
P E G_ T X# [ 1 1 ]
P E G_ T X# [ 1 2 ]
P E G_ T X# [ 1 3 ]
P E G_ T X# [ 1 4 ]
P E G_ T X# [ 1 5 ]
P E G _T X [ 0 ]
P E G _T X [ 1 ]
P E G _T X [ 2 ]
P E G _T X [ 3 ]
P E G _T X [ 4 ]
P E G _T X [ 5 ]
P E G _T X [ 6 ]
P E G _T X [ 7 ]
P E G _T X [ 8 ]
P E G _T X [ 9 ]
P E G _ TX [ 1 0 ]
P E G _ TX [ 1 1 ]
P E G _ TX [ 1 2 ]
P E G _ TX [ 1 3 ]
P E G _ TX [ 1 4 ]
P E G _ TX [ 1 5 ]
functional impacts but a small amount of power (~15 mW) maybe wasted. VAXG_SENSE
and VSSAXG_SENSE on Auburndale can be left as no connect.
DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND on Auburndale
directly if motherboard only supports discrete graphics. In a common motherboard
design, these pins are driven via PCH (even if Graphics is disabled by BIOS) thus no
external termination is required.
Thermal Sensor near U16
20 mil
B2 6
A2 6
B2 7
A2 5
P E G_ I R C O MP _ R
R2 0 9
4 9. 9 _ 1 % _0 4
E XP _R B I A S
R2 0 8
7 50 _ 1 % _0 4
K3 5
J34
J33
G 35
G 32
F3 4
F3 1
D 35
E3 3
C 33
D 32
B3 2
C 31
B2 8
B3 0
A3 1
J35
H 34
H 33
F3 5
G 33
E3 4
F3 2
D 34
F3 3
B3 3
D 31
A3 2
C 30
A2 8
B2 9
A3 0
L33
M 35
M 33
M 30
L31
K3 2
M 29
J31
K2 9
H 30
H 29
F2 9
E2 8
D 29
D 27
C 26
L34
M 34
M 32
L30
M 31
K3 1
M 28
H 31
K2 8
G 30
G 29
F2 8
E2 7
D 28
C 27
C 25
P Z 9 8 9 2 7-3 6 4 1 -01 F
3 .3 V
Analog Thermal Sensor
C 35 7
R 22 8
* 1 0m i l _s h o rt _ 0 4
3 .3 V
C R I T _ TE MP _ R E P # 19
Q 14
2
* 0. 1 u _ 16 V _ Y 5V _0 4
1
V CC
C
1
2
3
5
U1 8
VDD
D+
T HE RM
AL ER T
DGN D
S D A TA
S C LK
*W 8 3 L 7 71 A W G
B - 4 CPU 1/7 (DMI, PEG, FDI)
OU T
1 :2 ( 4m il s: 8m il s)
T H E R M_ V O L T 2 8
T H E R M_ A L E R T # 2 8
4
6
C
A
P M _E X T T S # _ E C 4
D1 6
*C D B U 0 03 4 0
7
8
4 , 1 2, 1 4 , 1 5 , 16 , 1 8 , 1 9 , 20 , 2 1 , 2 3, 2 4 , 2 5 , 2 9, 3 0 , 3 1 , 33 , 3 4 , 3 5 3. 3 V
3
C 359
GN D
0 . 1 u _ 16 V _ Y 5V _0 4
B
Q 10
*2 N 3 9 0 4
E
B.Schematic Diagrams
U 16 A
A2 4
C2 3
B2 2
A2 1
S M D_ CPU _ T HER M 1 5 ,2 8
S M C_ CPU _ T HER M 1 5 ,2 8
G7 1 1 S T9 U
C3 6 0
0. 1u _ 1 6V _Y 5 V _ 04
PLACE NEAR U16
1
2
3
Schematic Diagrams
CPU 2/7 (CLK, MISC, JTAG)
PROCESSOR
2/7
( CLK,MISC,JTAG )
1. 5 V
Processor Compensation
Signals
4 9 . 9 _1 % _ 0 4
H _ C O MP 0
R 2 13
4 9 . 9 _1 % _ 0 4
H _ C O MP 1
R 2 37
2 0 _ 1% _ 0 4
H _ C O MP 2
R 2 36
2 0 _ 1% _ 0 4
H _ C O MP 3
R 2 03
* 1 K _ 1% _ 0 4
R2 0 6
DDR3 Compensation Signals
S M _R C O MP _ 0
R2 2 9
1 0 0 _1 % _ 0 4
S M _R C O MP _ 1
R2 3 0
2 4 . 9 _1 % _ 0 4
S M _R C O MP _ 2
R2 3 1
1 3 0 _1 % _ 0 4
*1 0 m il _ s h ort _ 0 4
BSS138 ( VGS 1.5V )
Q1 3
*R J U 0 0 3N 0 3T 1 0 6
S
D
S M_ D R A MR S T #
D D R 3 _ D R A M R S T # 1 0, 1 1
R2 0 7
*1 0 0K _1 % _ 04
G
R 2 38
D R A MR S T _C T R L 9 , 1 9
TRACE WIDTH 10MIL, LENGTH <500MILS
? ? IBEX CONTROL
C3 1 1
*4 7 n _5 0 V _ 0 4
A T2 3
H _ C OM P 2
A T2 4
C OM P 3
A T2 6
C OM P 1
C OM P 0
4 9 . 9 _1 % _ 0 4
H _ C A TE R R #
R 2 39
6 8 _ 04
H _ P R OC H O T# _ D
R 2 47
* 68 _ 0 4
H _ C P U R S T#
A H2 4
H_ C A T E RR #
S K T O CC #
AK1 4
C A TE R R #
A T1 5
19 , 2 8 H _ P E C I
R2 4 8
3 6 H _ P R O C H OT #
PEC I
*1 0 m i _l s h ort _ 0 4 H _ P R O C H OT # _ D
A N2 6
P R OC H O T#
If PROCHOT# is not used, then it must be terminated
with a 50-O pull-up resistor to VTT_1.1 rail.
1 9 H _ T H R MT R I P #
THERMAL
R 2 19
AK1 5
CLOCKS
G1 6
H _ C OM P 0
B CL K _ IT P
B CL K _ IT P #
P E G _C L K
P E G _ CL K #
DP L L _ RE F _ S S C L K
D P LL _ R E F _S S C L K #
S M_ R C OM P [ 0 ]
S M_ R C OM P [ 1 ]
S M_ R C OM P [ 2 ]
P M_ E X T_ T S # [ 0 ]
P M_ E X T_ T S # [ 1 ]
AP2 6
P M _S Y N C
S Y S _ A GE N T_ P W R O K A N 1 4
* 0 _0 4
V C C P W R GO OD _ 1
R2 5 0
*1 0 m li _ s ho rt _ 0 4
R5 2
*1 0 m li _ s ho rt _ 0 4
A N2 7
19 H _C P U P W R G D
V D D P W R GO OD _ R
V C C P W R GO OD _ 0
AK1 3
S M _D R A MP W R OK
A M1 5
16 H _V TT P W R GD
V T T P W R GOO D
Connect to the Processor (VTTPWRGOOD) VTT_1.1 VR power
good signal to processor. Signal voltage level is 1.1 V.
R6 0
1 8 , 23 , 2 5 , 2 8 B U F _ P L T _R S T #
1 . 5 K _ 1 % _0 4
H_ P W RG D_ X DP
A M2 6
P L T _R S T # _R
A L1 4
T A P P W R GO OD
PWR MANAGEMENT
A L1 5
1 6 H_ PM _ S YN C
1 6 P M_ D R A M _ P W R G D
R E S E T _O B S #
TC K
TM S
T RS T #
JTAG & BPM
H_ C P UR S T #
R2 4 9
B CL K _ CP U_ P 1 9
B CL K _ CP U_ N 1 9
A R 30
AT3 0
E1 6
D 16
Sheet 4 of 42
CPU 2/7
(CLK, MISC, JTAG)
CL K_ EXP_ P 1 5
CL K_ EXP_ N 1 5
A1 8
A1 7
CL K _ DP _ P
CL K _ DP _ N
15
15
F6
S M_ D R A MR S T #
AL 1
AM 1
AN 1
S M_ R C OM P _ 0
S M_ R C OM P _ 1
S M_ R C OM P _ 2
R2 3 3
R5 4
A N 15
AP1 5
P M_ E X TT S # [ 0 ]
P M_ E X TT S # [ 1 ]
R5 3
R2 3 2
*0 _0 4
*0 _0 4
R2 3 4
*1 2. 4K _ 1 % _ 04
P _ T MS
P _ T D O _M
P _ T DI_ R
P _ P R E Q#
P _ T D O _R
R2 5 2
R2 4 4
R2 5 1
R2 4 2
R2 4 1
*5 1_ 0 4
51 _ 0 4
*5 1_ 0 4
*5 1_ 0 4
*5 1_ 0 4
XD P _ T C L K
XD P _ T R S T #
R2 4 5
R2 4 0
*5 1_ 0 4
51 _ 0 4
XD P _ T D O _M
R2 4 3
1. 1 V S _ V T T
10 K _ 0 4
10 K _ 0 4
P M _E X T T S # _E C 3
T S # _D I MM 0 _1 1 0 , 1 1
T H E R MT R I P #
P RD Y #
P R E Q#
1 6, 3 6 D E LA Y _ P W R GD
A1 6
B1 6
S M_ D R A M R S T #
DDR3
MISC
C OM P 2
H _ C OM P 1
MISC
Processor Pullups
1 .1 V S _ V T T
BC L K
B CL K #
TD I
T DO
T D I _M
T D O _M
AT2 8
AP2 7
X D P _ P RE Q #
A N 28
AP2 8
AT2 7
X D P _ TC L K
X D P _ TM S
X D P _ TR S T #
AT2 9
A R 27
A R 29
AP2 9
XD
XD
XD
XD
A N 25
DB R#
B
B
B
B
B
B
B
B
P M# [ 0 ]
P M# [ 1 ]
P M# [ 2 ]
P M# [ 3 ]
P M# [ 4 ]
P M# [ 5 ]
P M# [ 6 ]
P M# [ 7 ]
AJ 2 2
AK2 2
AK2 4
AJ 2 4
AJ 2 5
A H 22
AK2 3
A H 23
P _ TD
P _ TD
P _ TD
P _ TD
I_ R
O_ R
I_ M
O_ M
1. 1 V S _ V T T
XD
XD
XD
XD
XD
R S TI N #
Signal from PCH to Processor
Connect to PCH (PLT_RST#)
(needs to be level translated
from 3.3 V to 1.1 V).
R 61
7 5 0 _1 % _ 04
P Z 98 9 2 7-3 6 4 1 -01 F
1 .5 V S _ CP U
*1 0 m il _ s h ort _ 0 4X D P _ T D I _ M
3. 3 V
R5 0
1 . 1 K _1 % _ 0 4
R 2 35
*8 . 2 K _ 04
3 . 3V
1 . 5V
1 . 5V S _C
1 . 1V S _V
U 17
5
V D D P W R GO OD _ R
1
R6 2
R2 4 6
*1 . 5 K _ 1 % _0 4
D R A MP W R GD _ C P U
I N 3 . 3V
4
2
3
3 K _ 1% _ 0 4
3 , 1 2, 1 4 , 1 5 , 16 , 1 8 , 1 9, 2 0 , 2 1 , 23 , 2 4 , 2 5, 2 9 , 3 0 , 31 , 3 3 , 3 4, 3 5
9 , 1 0, 1 1 , 2 1 , 23 , 2 7 , 2 9, 3 1 , 3 3 , 36
P U 7, 3 1
TT 2 , 6 , 7 , 1 4, 1 5 , 1 6, 19 , 2 0 , 2 1, 3 4 , 3 5, 36
1 . 1 V S _ V T T _P W R G D 1 6 , 3 3 , 34
* MC 7 4V H C 1 G 08 D F T 1G
Intel change
4.75K -->1.1K
12K -->3K
CPU 2/7 (CLK, MISC, JTAG) B - 5
B.Schematic Diagrams
U 1 6B
H _ C OM P 3
Schematic Diagrams
CPU 3/7 (DDR3)
PROCESSOR
3/7
( DDR3 )
U16C
U16D
Sheet 5 of 42
CPU 3/7
(DDR3)
10
10
10
M_A_BS0
M_A_BS1
M_A_BS2
10
10
10
M_A_CAS#
M_A_RAS#
M_A_WE#
A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G
8
K7
J8
G
7
G10
J7
J10
L7
M
6
M
8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG
5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM
9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14
AC3
AB2
U7
AE1
AB3
AE9
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
D DR S YSTE M ME MORY A
B.Schematic Diagrams
M_A_DQ
0
M_A_DQ
1
M_A_DQ
2
M_A_DQ
3
M_A_DQ
4
M_A_DQ
5
M_A_DQ
6
M_A_DQ
7
M_A_DQ
8
M_A_DQ
9
M_A_DQ
10
M_A_DQ
11
M_A_DQ
12
M_A_DQ
13
M_A_DQ
14
M_A_DQ
15
M_A_DQ
16
M_A_DQ
17
M_A_DQ
18
M_A_DQ
19
M_A_DQ
20
M_A_DQ
21
M_A_DQ
22
M_A_DQ
23
M_A_DQ
24
M_A_DQ
25
M_A_DQ
26
M_A_DQ
27
M_A_DQ
28
M_A_DQ
29
M_A_DQ
30
M_A_DQ
31
M_A_DQ
32
M_A_DQ
33
M_A_DQ
34
M_A_DQ
35
M_A_DQ
36
M_A_DQ
37
M_A_DQ
38
M_A_DQ
39
M_A_DQ
40
M_A_DQ
41
M_A_DQ
42
M_A_DQ
43
M_A_DQ
44
M_A_DQ
45
M_A_DQ
46
M_A_DQ
47
M_A_DQ
48
M_A_DQ
49
M_A_DQ
50
M_A_DQ
51
M_A_DQ
52
M_A_DQ
53
M_A_DQ
54
M_A_DQ
55
M_A_DQ
56
M_A_DQ
57
M_A_DQ
58
M_A_DQ
59
M_A_DQ
60
M_A_DQ
61
M_A_DQ
62
M_A_DQ
63
SA_DQ
S#[0]
SA_DQ
S#[1]
SA_DQ
S#[2]
SA_DQ
S#[3]
SA_DQ
S#[4]
SA_DQ
S#[5]
SA_DQ
S#[6]
SA_DQ
S#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_M
A[0]
SA_M
A[1]
SA_M
A[2]
SA_M
A[3]
SA_M
A[4]
SA_M
A[5]
SA_M
A[6]
SA_M
A[7]
SA_M
A[8]
SA_M
A[9]
SA_M
A[10]
SA_M
A[11]
SA_M
A[12]
SA_M
A[13]
SA_M
A[14]
SA_M
A[15]
AA6
AA7
P7
Y6
Y5
P6
AE2
AE8
AD8
AF9
M_CLK_DDR0 10
M_CLK_DDR#0 10
M_CKE0 10
11 M_B_DQ
[ 63
: 0]
M_
B_DQ0
M_
B_DQ1
M_
B_DQ2
M_
B_DQ3
M_
B_DQ4
M_
B_DQ5
M_
B_DQ6
M_
B_DQ7
M_
B_DQ8
M_
B_DQ9
M_
B_DQ10
M_
B_DQ11
M_
B_DQ12
M_
B_DQ13
M_
B_DQ14
M_
B_DQ15
M_
B_DQ16
M_
B_DQ17
M_
B_DQ18
M_
B_DQ19
M_
B_DQ20
M_
B_DQ21
M_
B_DQ22
M_
B_DQ23
M_
B_DQ24
M_
B_DQ25
M_
B_DQ26
M_
B_DQ27
M_
B_DQ28
M_
B_DQ29
M_
B_DQ30
M_
B_DQ31
M_
B_DQ32
M_
B_DQ33
M_
B_DQ34
M_
B_DQ35
M_
B_DQ36
M_
B_DQ37
M_
B_DQ38
M_
B_DQ39
M_
B_DQ40
M_
B_DQ41
M_
B_DQ42
M_
B_DQ43
M_
B_DQ44
M_
B_DQ45
M_
B_DQ46
M_
B_DQ47
M_
B_DQ48
M_
B_DQ49
M_
B_DQ50
M_
B_DQ51
M_
B_DQ52
M_
B_DQ53
M_
B_DQ54
M_
B_DQ55
M_
B_DQ56
M_
B_DQ57
M_
B_DQ58
M_
B_DQ59
M_
B_DQ60
M_
B_DQ61
M_
B_DQ62
M_
B_DQ63
M_CLK_DDR1 10
M_CLK_DDR#1 10
M_CKE1 10
M_CS#0 10
M_CS#1 10
M_ODT
0 10
M_ODT
1 10
B9
D7
H7
M7
AG
6
AM
7
AN10
AN13
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
C9
F8
J9
N9
AH7
AK9
AP11
AT13
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
C8
F9
H9
M9
AH8
AK10
AN11
AR13
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG
8
T3
V9
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_DM
[7
: 0] 10
M_A_DQ
S#[7:0] 10
M_A_DQ
S[7:0] 10
M_A_A[15:0] 10
11
11
11
M_B_BS0
M_B_BS1
M_B_BS2
11
11
11
M_B_CAS#
M_B_RAS#
M_B_WE#
B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5
AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10
AB1
W5
R7
AC5
Y7
AC6
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
PZ98927-3641-01F
PZ98927-3641-01F
B - 6 CPU 3/7 (DDR3)
SB_CK[ 0]
SB_CK#[ 0]
SB_CKE[ 0]
SB_CK[ 1]
SB_CK#[ 1]
SB_CKE[ 1]
SB_CS#[ 0]
SB_CS#[ 1]
SB_ODT[ 0]
SB_ODT[ 1]
SB_DM
[ 0]
SB_DM
[ 1]
SB_DM
[ 2]
SB_DM
[ 3]
SB_DM
[ 4]
SB_DM
[ 5]
SB_DM
[ 6]
SB_DM
[ 7]
D DR S YSTE M ME MORY - B
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
10 M_A_DQ[63:0]
SB_DQS#[ 0]
SB_DQS#[ 1]
SB_DQS#[ 2]
SB_DQS#[ 3]
SB_DQS#[ 4]
SB_DQS#[ 5]
SB_DQS#[ 6]
SB_DQS#[ 7]
SB_DQS[ 0]
SB_DQS[ 1]
SB_DQS[ 2]
SB_DQS[ 3]
SB_DQS[ 4]
SB_DQS[ 5]
SB_DQS[ 6]
SB_DQS[ 7]
SB_MA[ 0]
SB_MA[ 1]
SB_MA[ 2]
SB_MA[ 3]
SB_MA[ 4]
SB_MA[ 5]
SB_MA[ 6]
SB_MA[ 7]
SB_MA[ 8]
SB_MA[ 9]
SB_MA[ 10]
SB_MA[ 11]
SB_MA[ 12]
SB_MA[ 13]
SB_MA[ 14]
SB_MA[ 15]
W8
W9
M3
V7
V6
M2
AB8
AD6
AC7
AD1
M_CL
K_DDR2 11
M_CL
K_DDR#2 11
M_CKE2 11
M_CL
K_DDR3 11
M_CL
K_DDR#3 11
M_CKE3 11
M_CS#2 11
M_CS#3 11
M_ODT2 11
M_ODT3 11
D4
E1
H3
K1
AH1
AL
2
AR4
AT
8
M
_B_DM0
M
_B_DM1
M
_B_DM2
M
_B_DM3
M
_B_DM4
M
_B_DM5
M
_B_DM6
M
_B_DM7
D5
F4
J4
L4
AH2
AL
4
AR5
AR8
M
_B_DQS#0
M
_B_DQS#1
M
_B_DQS#2
M
_B_DQS#3
M
_B_DQS#4
M
_B_DQS#5
M
_B_DQS#6
M
_B_DQS#7
C5
E3
H4
M5
AG
2
AL
5
AP5
AR7
M
_B_DQS0
M
_B_DQS1
M
_B_DQS2
M
_B_DQS3
M
_B_DQS4
M
_B_DQS5
M
_B_DQS6
M
_B_DQS7
U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1
M
_B_A0
M
_B_A1
M
_B_A2
M
_B_A3
M
_B_A4
M
_B_A5
M
_B_A6
M
_B_A7
M
_B_A8
M
_B_A9
M
_B_A10
M
_B_A11
M
_B_A12
M
_B_A13
M
_B_A14
M
_B_A15
M_B_DM[7:0] 11
M
_B_DQS#[7:0] 11
M
_B_DQS[7: 0] 11
M_B_A[15:0] 11
Schematic Diagrams
CPU 4/7 (Power)
P ROCES SOR
4/7
( PO WER )
U 1 6F
PRO CESSOR CORE POWER
2 2 u _ 6 . 3 V _ X 5 R _0 8
* 2 2 u_ 6 . 3 V _ X 5R _ 0 8
2 2 u _ 6 . 3 V _ X 5 R_ 0 8
C 356
C 355
C 354
* 2 2 u_ 6 . 3 V _ X 5 R _ 0 8
V CO RE
1 0 u _ 6 .3 V _ X 5 R_ 0 6
C 339
C 338
C 333
1 0 u _ 6 . 3 V _ X 5 R_ 0 6
C3 4 0
0 .0 1 u _ 5 0 V _ X 7 R_ 0 4
* 1 0 u_ 6 .3 V _ X 5R _ 0 6
C 347
* 1 0 u _6 .3 V _X 5R _ 0 6
C 327
1 0 u _ 6 . 3 V _ X 5 R _0 6
C 325
10 u _ 6 .3 V _ X 5 R _ 06
C3 2 6
0. 1u _ 1 0 V _ X 7 R _ 04
1 0 u _ 6 .3 V _ X 5 R_ 0 6
C 344
1 0 u _ 6 .3 V _ X 5 R_ 0 6
C 345
* 1 0 u _6 .3 V _X 5R _ 0 6
C 346
*1 0 u _ 6. 3V _X 5 R_ 0 6
C3 4 8
VTT0 _ 1
VTT0 _ 2
VTT0 _ 3
VTT0 _ 4
VTT0 _ 5
VTT0 _ 6
VTT0 _ 7
VTT0 _ 8
VTT0 _ 9
V TT 0 _ 1 0
V TT 0 _ 1 1
V TT 0 _ 1 2
V TT 0 _ 1 3
V TT 0 _ 1 4
V TT 0 _ 1 5
V TT 0 _ 1 6
V TT 0 _ 1 7
V TT 0 _ 1 8
V TT 0 _ 1 9
V TT 0 _ 2 0
V TT 0 _ 2 1
V TT 0 _ 2 2
V TT 0 _ 2 3
V TT 0 _ 2 4
V TT 0 _ 2 5
V TT 0 _ 2 6
V TT 0 _ 2 7
V TT 0 _ 2 8
V TT 0 _ 2 9
V TT 0 _ 3 0
V TT 0 _ 3 1
V TT 0 _ 3 2
V TT TOTAL 2 1A
A H1 4
A H1 2
A H1 1
A H1 0
J14
J13
H 14
H 12
G 14
G 13
G 12
G 11
F 14
F 13
F 12
F 11
E 14
E 12
D 14
D 13
D 12
D 11
C 14
C 13
C 12
C 11
B 14
B 12
A 14
A 13
A 12
A 11
C 29
C3 0
C 3 24
C3 5
C 33
C 301
C 334
1 0 u _ 6. 3V _X 5 R _ 0 6
*1 0 u _ 6. 3V _ X5 R _ 0 6
1 0 u _ 6. 3V _ X5 R _ 0 6
*1 0 u _ 6. 3V _ X5 R _ 0 6
*1 0 u _ 6 . 3 V _ X 5 R _ 0 6
2 2 u _ 6 . 3V _ X5 R _ 0 8
2 2 u _ 6 .3 V _ X 5 R_ 0 8
C 36
C 303
C3 4
C3 2 8
1 0 u _ 6. 3V _X 5 R _ 0 6
1 0 u _ 6 . 3 V _ X 5R _ 0 6
10 u _ 6 . 3 V _ X 5 R _ 0 6
*1 0 u _ 6 . 3 V _ X 5R _ 0 6
TT 0 _ 3 3
TT 0 _ 3 4
TT 0 _ 3 5
TT 0 _ 3 6
TT 0 _ 3 7
TT 0 _ 3 8
TT 0 _ 3 9
TT 0 _ 4 0
TT 0 _ 4 1
TT 0 _ 4 2
TT 0 _ 4 3
TT 0 _ 4 4
ICCMAX_VTT Max Current
for VTT Rail
SV 18
The decoupling capacitors, filter
recommendations and sense resistors on the
CPU/PCH Rails are specific to the CRB
Implementation. Customers need to follow the
recommendations in the Calpella Platform
Design Guide
1. 1V S _ V T T
V
V
V
V
V
V
V
V
V
V
V
V
CPU CORE SUPPLY
C3 3 2
2 2 u _ 6 .3 V _ X 5 R _0 8
C 318
* 2 2 u_ 6 . 3 V _ X 5R _ 0 8
C 329
*2 2 u _ 6. 3V _X 5 R_ 0 8
C 352
22 u _ 6 . 3 V _ X 5 R _ 08
C3 4 2
C1
C2
C3
C4
C5
C6
C7
C8
C9
C1 0
C1 1
C1 2
C1 3
C1 4
C1 5
C1 6
C1 7
C1 8
C1 9
C2 0
C2 1
C2 2
C2 3
C2 4
C2 5
C2 6
C2 7
C2 8
C2 9
C3 0
C3 1
C3 2
C3 3
C3 4
C3 5
C3 6
C3 7
C3 8
C3 9
C4 0
C4 1
C4 2
C4 3
C4 4
C4 5
C4 6
C4 7
C4 8
C4 9
C5 0
C5 1
C5 2
C5 3
C5 4
C5 5
C5 6
C5 7
C5 8
C5 9
C6 0
C6 1
C6 2
C6 3
C6 4
C6 5
C6 6
C6 7
C6 8
C6 9
C7 0
C7 1
C7 2
C7 3
C7 4
C7 5
C7 6
C7 7
C7 8
C7 9
C8 0
C8 1
C8 2
C8 3
C8 4
C8 5
C8 6
C8 7
C8 8
C8 9
C9 0
C9 1
C9 2
C9 3
C9 4
C9 5
C9 6
C9 7
C9 8
C9 9
C1 0 0
A F10
A E1 0
A C1 0
A B1 0
Y 10
W 10
U 10
T10
J12
J11
J16
J15
C 304
C3 0 5
C3 1 2
2 2 u _ 6 . 3 V _ X 5R _ 0 8
22 u _ 6 . 3 V _ X 5 R _ 0 8
2 2 u_ 6 . 3 V _ X 5 R _0 8
Sheet 6 of 42
CPU 4/7
(Power)
1.1VS_VTT
+ V T T_ 4 3
+ V T T_ 4 4
R 216
R 215
Please note that the
VTT Rail Values are
*1 5 m li _ s h o rt _ 0 6
*1 5 m li _ s h o rt _ 0 6
Auburndale VTT=1.05V
1 .1 V S_ VT T
1K PU t o V TT
fo r P OC
an d 1 K P D to
VCORE
GN D
R 2 25
* 1 K _ 1% _ 0 4
A N3 3
PSI #
A
A
A
A
A
A
A
A
H
H
H
H
H
H
H
P S I#
P SI#
36
1 .1 V S_ VT T
V ID [0 ]
V ID [1 ]
V ID [2 ]
V ID [3 ]
V ID [4 ]
V ID [5 ]
V ID [6 ]
P R O C_ D P R S L P V R
K3 5
K3 3
K3 4
L3 5
L3 3
M3 3
M3 5
M3 4
_V
_V
_V
_V
_V
_V
_V
ID0
ID1
ID2
ID3
ID4
ID5
ID6
R 2 26
36
36
36
36
36
36
36
1 K_ 1 % _ 0 4
R2 2 3
1 K _ 1 % _0 4
P M _ D P R S LP V R
36
R2 2 2
G 15
VT T_ SEL EC T
H _ V T TV I D 1
*1 K _ 1 % _ 0 4
TO VCORE POWER CONTROL
A N3 5
IS E NS E
V C C_ S E NS E
V S S _ S E NS E
V T T_ S E N S E
V S S _S E N S E _ V T T
A J3 4
A J3 5
B 15
A 15
IM O N
36
VC C _ SEN SE 3 6
V S S _ S E N S E 36
VT T_ SEN SE
34
V CO R E
36
1 . 1V S _ V T T 2 , 4 , 7 , 1 4 , 1 5 , 1 6, 1 9 , 2 0 , 2 1 , 3 4 , 3 5 , 3 6
P Z 98 9 2 7 -3 6 4 1- 01 F
CPU 4/7 (Power) B - 7
B.Schematic Diagrams
2 2 u _ 6 . 3 V _ X 5 R_ 0 8
C 337
2 2 u _ 6 . 3 V _ X 5 R _0 8
C 335
* 2 2 u_ 6 . 3 V _ X 5R _ 0 8
C 331
22 u _ 6 .3 V _ X 5 R _ 08
C3 2 3
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
1.1V RAIL POWER
V CO RE
1 . 1 V S _ V TT
AG 3 5
AG 3 4
AG 3 3
AG 3 2
AG 3 1
AG 3 0
AG 2 9
AG 2 8
AG 2 7
AG 2 6
A F3 5
A F3 4
A F3 3
A F3 2
A F3 1
A F3 0
A F2 9
A F2 8
A F2 7
A F2 6
AD 3 5
AD 3 4
AD 3 3
AD 3 2
AD 3 1
AD 3 0
AD 2 9
AD 2 8
AD 2 7
AD 2 6
AC 3 5
AC 3 4
AC 3 3
AC 3 2
AC 3 1
AC 3 0
AC 2 9
AC 2 8
AC 2 7
AC 2 6
A A3 5
A A3 4
A A3 3
A A3 2
A A3 1
A A3 0
A A2 9
A A2 8
A A2 7
A A2 6
Y 35
Y 34
Y 33
Y 32
Y 31
Y 30
Y 29
Y 28
Y 27
Y 26
V3 5
V3 4
V3 3
V3 2
V3 1
V3 0
V2 9
V2 8
V2 7
V2 6
U 35
U 34
U 33
U 32
U 31
U 30
U 29
U 28
U 27
U 26
R 35
R 34
R 33
R 32
R 31
R 30
R 29
R 28
R 27
R 26
P3 5
P3 4
P3 3
P3 2
P3 1
P3 0
P2 9
P2 8
P2 7
P2 6
POWER
SV 4 8
PROCESS OR UNCORE POWER
CPU VIDS
I CC M AX M a xi m um P r oc es s or
48A
SENSE LINES
V C O RE
Schematic Diagrams
CPU 5/7 (Graphics Power)
PROCESSOR 5/7
C3 6 2
2 2 u _ 6. 3V _X 5 R _ 08
2 2 u_ 6 . 3 V _ X 5 R _ 0 8
Sheet 7 of 42
CPU 5/7
(Graphics Power)
Please note that the
VTT Rail Values are
Auburndale VTT=1.05V
Clarksfield VTT=1.1V
C3 1 4
C3 0 8
22 u _ 6 . 3 V _ X 5 R _ 0 8
22 u _ 6 . 3 V _ X 5 R _ 0 8
J24
J23
H 25
V T T 1 _ 45
V T T 1 _ 46
V T T 1 _ 47
SENSE
LINES
FDI
1 .1 VS_ VT T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GRAPHICS VIDs
C 3 50
+
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG
VAXG _ SEN SE
VSSAXG _ SEN SE
GF
GF
GF
GF
GF
GF
GF
X_ V I
X_ V I
X_ V I
X_ V I
X_ V I
X_ V I
X_ V I
D[0 ]
D[1 ]
D[2 ]
D[3 ]
D[4 ]
D[5 ]
D[6 ]
G F X _ V R _E N
G F X _ DP RS L P V R
GF X_ I M O N
A R2 2
AT2 2
A M2 2
AP2 2
A N2 2
AP2 3
A M2 3
AP2 4
A N2 4
A R2 5
AT2 5
A M2 4
GP U V C C S E N S E 3 5
GP U V S S S E N S E 35
DF
DF
DF
DF
DF
DF
DF
GT _ V I D
GT _ V I D
GT _ V I D
GT _ V I D
GT _ V I D
GT _ V I D
GT _ V I D
GF X V R _ D P R S LP V R
T P _ GF X _ I M ON
_0
_1
_2
_3
_4
_5
_6
R3 6 1
R4 5
35
35
35
35
35
35
35
D F GT _ V R _ E N
*1 K _ 0 4
1 00 _ 1 % _ 0 4
1 .1 V S_ V T T
35
GF X_ I M O N 3 5
1. 5V S _ C P U
- 1.5V RAILS
1 0 u _6 . 3 V _ X 5 R _0 6
DDR3
C 34 9
1 0 u _ 6. 3V _ X5 R _ 0 6
POWER
C 364
C 371
5 6 0 u _ 2. 5V _6 . 6 * 6 . 6 *5 . 9
U 1 6G
AT 2 1
AT 1 9
AT 1 8
AT 1 6
AR 2 1
AR 1 9
AR 1 8
AR 1 6
A P2 1
A P1 9
A P1 8
A P1 6
AN 2 1
AN 1 9
AN 1 8
AN 1 6
AM 2 1
AM 1 9
AM 1 8
AM 1 6
AL 2 1
AL 1 9
AL 1 8
AL 1 6
A K2 1
A K1 9
A K1 8
A K1 6
AJ 2 1
AJ 1 9
AJ 1 8
AJ 1 6
AH 2 1
AH 1 9
AH 1 8
AH 1 6
GRAPHICS
V D D Q1
V D D Q2
V D D Q3
V D D Q4
V D D Q5
V D D Q6
V D D Q7
V D D Q8
V D D Q9
V D D Q1 0
V D D Q1 1
V D D Q1 2
V D D Q1 3
V D D Q1 4
V D D Q1 5
V D D Q1 6
V D D Q1 7
V D D Q1 8
V T T 0 _5 9
V T T 0 _6 0
V T T 0 _6 1
V T T 0 _6 2
AJ 1
AF1
AE7
AE4
A C1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
VDDQ 6A
C5 5
C3 3 6
C 330
C6 1
C5 8
1u _ 6 . 3 V _ X 5 R _ 0 4
2 2 u_ 6 . 3 V _ X 5 R _ 0 8
2 2 u _ 6. 3V _ X5 R _ 08
10 u _ 6 . 3 V _ X 5 R _ 0 6
1 0 u_ 6 . 3 V _ X 5 R _ 0 6
C3 4 1
C3 4 3
C 39
C6 0
1u _ 6 . 3 V _ X 5 R _ 0 4
1 u _6 . 3 V _ X 5 R _0 4
1 u _ 6 . 3 V _ X 5R _ 0 4
1u _ 6 . 3 V _ X 5 R _ 0 4
+ C5 3
10 0 u _ 6 . 3 V _ B _ A
1 . 1 V S _V TT
P1 0
N1 0
L1 0
K1 0
C3 2 0
C6 4
10 u _ 6 . 3 V _ X 5 R _ 0 6
1 0 u_ 6 . 3 V _ X 5 R _ 0 6
1 .1 VS_ VT T
C3 0 7
22 u _ 6 . 3 V _ X 5 R _ 0 8
22 u _ 6 . 3 V _ X 5 R _ 0 8
C3 0 9
C3 0 2
22 u _ 6 . 3 V _ X 5 R _ 0 8
22 u _ 6 . 3 V _ X 5 R _ 0 8
1 . 1 V S _V T T
C3 9 6
0 . 0 1u _ 5 0 V _ X 7 R _ 0 4
C3 5 1
0. 01 u _ 5 0 V _ X 7R _ 0 4
V T T 1 _ 48
V T T 1 _ 49
V T T 1 _ 50
V T T 1 _ 51
V T T 1 _ 52
V T T 1 _ 53
V T T 1 _ 54
V T T 1 _ 55
V T T 1 _ 56
V T T 1 _ 57
V T T 1 _ 58
PEG & DMI
C3 0 6
1.1V
1 .1 VS_ VT T
K2 6
J27
J26
J25
H 27
G 28
G 27
G 26
F26
E2 6
E2 5
V T T 1 _6 3
V T T 1 _6 4
V T T 1 _6 5
V T T 1 _6 6
V T T 1 _6 7
V T T 1 _6 8
J2 2
J2 0
J1 8
H2 1
H2 0
H1 9
C3 1 5
C3 1 3
22 u _ 6 . 3 V _ X 5 R _ 0 8
2 2 u_ 6 . 3 V _ X 5 R _ 0 8
1 .8 VS
1.8V
B.Schematic Diagrams
VG F X_ CO RE
( GRAPHICS POWER )
V C C P LL 1
V C C P LL 2
V C C P LL 3
L2 6
L2 7
M2 6
VCCPLL 0.6A
C4 1
C3 7
C 38
C 52
C 56
C5 4
1u _ 6 . 3 V _ X 5 R _ 0 4
1 u _6 . 3 V _ X 5 R _0 4
2 . 2 u _ 1 6V _ X5 R _ 06
4 . 7 u _ 6 . 3 V _ X5 R _ 0 6
1 0 u _ 6 . 3V _ X5 R _ 0 6
10 u _ 6 . 3 V _ X 5 R _ 0 6
P Z 98 9 2 7 -3 6 41 -0 1 F
1 .5 VS _ CP U
1 .8 VS
V GF X _ C OR
1 .1 VS _ V T T
1 .5 V
B - 8 CPU 5/7 (Graphics Power)
4 ,3 1
2 0 ,3 3
E 35
2 , 4, 6, 14 , 1 5 , 1 6 , 1 9 , 2 0 , 21 , 3 4 , 3 5 , 3 6
4 , 9 , 1 0 , 1 1, 2 1 , 2 3 , 2 7 , 2 9 , 3 1, 33 , 3 6
Schematic Diagrams
CPU 6/7 (GND)
PROCESSOR
6/7
( GND )
PZ98 927 -3 641 -0 1F
U16 I
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AE3 4
AE3 3
AE3 2
AE3 1
AE3 0
AE2 9
AE2 8
AE2 7
AE2 6
AE6
AD 10
AC 8
AC 4
AC 2
AB3 5
AB3 4
AB3 3
AB3 2
AB3 1
AB3 0
AB2 9
AB2 8
AB2 7
AB2 6
AB6
AA1 0
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V1 0
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K3 4
K3 3
K3 0
K2 7
K9
K6
K3
J3 2
J3 0
J2 1
J1 9
H3 5
H3 2
H2 8
H2 6
H2 4
H2 2
H1 8
H1 5
H1 3
H1 1
H8
H5
H2
G3 4
G3 1
G2 0
G9
G6
G3
F3 0
F2 7
F2 5
F2 2
F1 9
F1 6
E3 5
E3 2
E2 9
E2 4
E2 1
E1 8
E1 3
E1 1
E8
E5
E2
D3 3
D3 0
D2 6
D9
D6
D3
C3 4
C3 2
C2 9
C2 8
C2 4
C2 2
C2 0
C1 9
C1 6
B3 1
B2 5
B2 1
B1 8
B1 7
B1 3
B1 1
B8
B6
B4
A2 9
A2 7
A2 3
A9
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
Sheet 8 of 42
CPU 6/7 (GND)
VSS
VSS_ NC TF1
VSS_ NC TF2
VSS_ NC TF3
VSS_ NC TF4
VSS_ NC TF5
VSS_ NC TF6
VSS_ NC TF7
AT3 5
AT1
AR3 4
B34
B2
B1
A35
PZ9 892 7- 364 1- 01F
CPU 6/7 (GND) B - 9
B.Schematic Diagrams
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1 0
VSS1 1
VSS1 2
VSS1 3
VSS1 4
VSS1 5
VSS1 6
VSS1 7
VSS1 8
VSS1 9
VSS2 0
VSS2 1
VSS2 2
VSS2 3
VSS2 4
VSS2 5
VSS2 6
VSS2 7
VSS2 8
VSS2 9
VSS3 0
VSS3 1
VSS3 2
VSS3 3
VSS3 4
VSS3 5
VSS3 6
VSS3 7
VSS3 8
VSS3 9
VSS4 0
VSS4 1
VSS4 2
VSS4 3
VSS4 4
VSS4 5
VSS4 6
VSS4 7
VSS4 8
VSS4 9
VSS5 0
VSS5 1
VSS5 2
VSS5 3
VSS5 4
VSS5 5
VSS5 6
VSS5 7
VSS5 8
VSS5 9
VSS6 0
VSS6 1
VSS6 2
VSS6 3
VSS6 4
VSS6 5
VSS6 6
VSS6 7
VSS6 8
VSS6 9
VSS7 0
VSS7 1
VSS7 2
VSS7 3
VSS7 4
VSS7 5
VSS7 6
VSS7 7
VSS7 8
VSS7 9
VSS8 0
NCTF
U1 6H
AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35
Schematic Diagrams
CPU 7/7 (RESERVED)
PROCESSOR
7/7
( RESERVED )
1 .5 V
U1 6 E
AP2302GN
R 2 27
* 3 . 01 K _ 0 4
R 35
R 39
1 0 MV R E F _ D Q_ D I M0
1 1 MV R E F _ D Q_ D I M1
*0 _ 04
*0 _ 04
V R E F _ C H _ A _ D I MM
V R E F _ C H _ B _ D I MM
CFG3 - PCI-Express Static Lane Reversal
Sheet 9 of 42
CPU 7/7
(RESERVED)
CFG3
C FG 3
1 : Normal Operation
0 : Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
R 2 21
C F G0
C F G3
C F G4
C F G7
0 : En ab le d; An e xt er na l Di s pl ay P or t
de vi ce i s co n ne ct ed t o th e E mb ed de d
is pl ay P or t
R 2 20
* 3 . 01 K _ 0 4
RS V D3 4
RS V D3 5
RS V D3 6
R S V D _ N C TF _3 7
RS V D3 8
RS V D3 9
R 211
*0 _ 0 4
R SVD8 6
A M3 0
A M2 8
AP3 1
A L3 2
A L3 0
A M3 1
A N2 9
A M3 2
AK3 2
AK3 1
AK2 8
A J2 8
A N3 0
A N3 2
A J3 2
A J2 9
A J3 0
AK3 0
H1 6
B1 9
A1 9
C FG 7
R 2 24
* 3 . 01 K _ 0 4
R 20 5
R 20 4
*1 5 m il _ s h ort _0 6
*1 5 m il _ s h ort _0 6
H _R S V D 1 7_ R
H _R S V D 1 8_ R
A2 0
B2 0
U9
T9
A C9
AB9
C1
A3
J2 9
J2 8
A3 4
A3 3
C3 5
B3 5
A L2 6
A R2
R 2 12
* 1 00 K _ 1 % _ 0 4
* 1 K _ 1% _ 0 4
MV R E F _ D Q_ D I M 0
R 37
* 1 K _ 1% _ 0 4
A J2 6
A J2 7
R S V D _ N C TF _4 0
R S V D _ N C TF _4 1
D R A MR S T _ C T R L 4, 1 9
A P1
A T2
1 .5 V
A T3
A R1
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
R
F G [ 0]
F G [ 1]
F G [ 2]
F G [ 3]
F G [ 4]
F G [ 5]
F G [ 6]
F G [ 7]
F G [ 8]
F G [ 9]
F G [ 10 ]
F G [ 11 ]
F G [ 12 ]
F G [ 13 ]
F G [ 14 ]
F G [ 15 ]
F G [ 16 ]
F G [ 17 ]
S V D _ TP _8 6
RS V D4 5
RS V D4 6
RS V D4 7
RS V D4 8
RS V D4 9
RS V D5 0
RS V D5 1
RS V D5 2
RS V D5 3
R S V D _ N C TF _5 4
R S V D _ N C TF _5 5
R S V D _ N C TF _5 6
R S V D _ N C TF _5 7
RS V D5 8
R S V D _ TP _5 9
R S V D _ TP _6 0
KEY
RS V D6 2
RS V D6 3
RS V D6 4
RS V D6 5
A
A
A
A
A
A
A
A
A
A
A
A
A
A
L2 8
L2 9
P 30
P 32
L2 7
T3 1
T3 2
P 33
R3 3
T3 3
T3 4
P 35
R3 5
R3 2
E
F
A
D
C
A
A
15
15
2
15
15
J1 5
H1 5
A
A
R
A
A
A
A
R
A
A
A5
A4
8
D3
D2
A2
A1
9
G7
E3
V R E F _ CH _ B _ DIM M
R 38
Q 9
*A O3 4 0 2L
S
D
R 2 14
* 1 00 K _ 1 % _ 0 4
* 1 K _ 1% _ 0 4
MV R E F _ D Q_ D I M 1
R 40
* 1 K _ 1% _ 0 4
D R A MR S T _ C T R L 4, 1 9
? ? IBEX CONTROL
R S V D 6 4 _R
R S V D 6 5 _R
R 2 17
R 2 18
*1 5 m i l_ s h o rt _ 06
*1 5 m i l_ s h o rt _ 06
R SVD 1 5
R SVD 1 6
R SVD 1 7
R SVD 1 8
R SVD 1 9
R SVD 2 0
R SVD 2 1
R SVD 2 2
R S V D _ N C TF _2 3
R S V D _ N C TF _2 4
R SVD 2 6
R SVD 2 7
R S V D _ N C TF _2 8
R S V D _ N C TF _2 9
R S V D _ N C TF _3 0
R S V D _ N C TF _3 1
R
R
R
R
R
R
R
R
R
R
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
_ TP
_ TP
_ TP
_ TP
_ TP
_ TP
_ TP
_ TP
_ TP
_ TP
_6 6
_6 7
_6 8
_6 9
_7 0
_7 1
_7 2
_7 3
_7 4
_7 5
R
R
R
R
R
R
R
R
R
R
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
_ TP
_ TP
_ TP
_ TP
_ TP
_ TP
_ TP
_ TP
_ TP
_ TP
_7 6
_7 7
_7 8
_7 9
_8 0
_8 1
_8 2
_8 3
_8 4
_8 5
V 4
V 5
N 2
A D5
A D7
W 3
W 2
N 3
A E5
A D9
A P 34
V SS
P Z 9 89 2 7 -3 6 41 -0 1 F
1. 5 V
B - 10 CPU 7/7 (RESERVED)
V R E F _ CH _ A _ DIM M
? ? IBEX CONTROL
RSVD86
Connect to GND
CFG7
Clar ksfi eld (onl y f or e arly sam ples
pre- ES1) - C onne ct to G ND w ith 3.01 K Oh m/5%
resi stor
A H2 5
A K 26
AP2302GN
* 3 . 01 K _ 0 4
1 : Di sa bl le d ; No p hy si ca l D is pl ay P or t
a tt ac he d to Em be dd ed D is pl a y Po rt
C FG 4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R S V D _ N C TF _4 2
R S V D _ N C TF _4 3
CFG4 - Display Port Presence
CFG4
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
SVD
R 36
Q 8
*A O3 4 0 2L
S
D
G
B.Schematic Diagrams
C FG 0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
RESERVED
CFG0
1 : Single PEG
0 : Bifurcation enable
AP2 5
A L2 5
A L2 4
A L2 2
A J3 3
A G9
M2 7
L2 8
J1 7
H1 7
G2 5
G1 7
E3 1
E3 0
G
RS V D3 2
RS V D3 3
PCI-Express Configuration Select
A J1 3
A J1 2
4 , 1 0, 11 , 2 1 , 2 3 , 2 7, 2 9 , 3 1 , 3 3, 36
TP _R S V D 8 6
VSS (AP34) can be left NC is
CRB implementation ; EDS/DG
recommendation to GND
Schematic Diagrams
DDR3 SO-DIMM_0
SO-DIMM A
5
J D I M M2 A
M_ A _ A [ 1 5 : 0 ]
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
La yout Note :
si gna l /spa ce / signa l:
8/4/8
M
M
M
M
M_ A _ B S 0
M_ A _ B S 1
M_ A _ B S 2
M_ C S # 0
M_ C S # 1
_ CL K _ DD R0
_ CL K _ DD R# 0
_ CL K _ DD R1
_ CL K _ DD R# 1
M_ C K E 0
M_ C K E 1
M _A _C A S #
M _A _R A S #
M _A _W E #
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
_A _ A 0
_A _ A 1
_A _ A 2
_A _ A 3
_A _ A 4
_A _ A 5
_A _ A 6
_A _ A 7
_A _ A 8
_A _ A 9
_A _ A 1 0
_A _ A 1 1
_A _ A 1 2
_A _ A 1 3
_A _ A 1 4
_A _ A 1 5
S A0 _ DIM 0
S A1 _ DIM 0
2 ,1 1 C L K _ SCL K
2, 1 1 C LK _S D A T A
116
120
3 .3 VS
R N3
1 0 K _ 8 P 4R _ 0 4
1
8
S A1 _ DIM
2
7
S A0 _ DIM
3
6
S A1 _ DIM
4
5
S A0 _ DIM
5
5
5
1
1
0
0
M_ O D T 0
M_ O D T 1
M_ A _ D M[ 7 : 0 ]
S A 1 _D I M 1 1 1
S A 0 _D I M 1 1 1
5
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
M_ A _ D QS [ 7 : 0 ]
5 M_ A _ D QS # [ 7 : 0 ]
M
M
M
M
M
M
M
M
_A _ D
_A _ D
_A _ D
_A _ D
_A _ D
_A _ D
_A _ D
_A _ D
M0
M1
M2
M3
M4
M5
M6
M7
11
28
46
63
136
153
170
187
M
M
M
M
M
M
M
M
_A _ D
_A _ D
_A _ D
_A _ D
_A _ D
_A _ D
_A _ D
_A _ D
QS 0
QS 1
QS 2
QS 3
QS 4
QS 5
QS 6
QS 7
12
29
47
64
137
154
171
188
M
M
M
M
M
M
M
M
_A _ D
_A _ D
_A _ D
_A _ D
_A _ D
_A _ D
_A _ D
_A _ D
QS # 0
QS # 1
QS # 2
QS # 3
QS # 4
QS # 5
QS # 6
QS # 7
10
27
45
62
135
152
169
186
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 1 0 /A P
A1 1
A 1 2 /B C#
A1 3
A1 4
A1 5
BA0
BA1
BA2
S0 #
S1 #
CK 0
C K 0#
CK 1
C K 1#
CK E0
CK E1
CA S#
RA S#
W E#
SA0
SA1
SC L
SD A
OD T 0
OD T 1
DM
DM
DM
DM
DM
DM
DM
DM
0
1
2
3
4
5
6
7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S0
S1
S2
S3
S4
S5
S6
S7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S0 #
S1 #
S2 #
S3 #
S4 #
S5 #
S6 #
S7 #
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 8
DQ 9
D Q1 0
D Q1 1
D Q1 2
D Q1 3
D Q1 4
D Q1 5
D Q1 6
D Q1 7
D Q1 8
D Q1 9
D Q2 0
D Q2 1
D Q2 2
D Q2 3
D Q2 4
D Q2 5
D Q2 6
D Q2 7
D Q2 8
D Q2 9
D Q3 0
D Q3 1
D Q3 2
D Q3 3
D Q3 4
D Q3 5
D Q3 6
D Q3 7
D Q3 8
D Q3 9
D Q4 0
D Q4 1
D Q4 2
D Q4 3
D Q4 4
D Q4 5
D Q4 6
D Q4 7
D Q4 8
D Q4 9
D Q5 0
D Q5 1
D Q5 2
D Q5 3
D Q5 4
D Q5 5
D Q5 6
D Q5 7
D Q5 8
D Q5 9
D Q6 0
D Q6 1
D Q6 2
D Q6 3
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
_D
M_ A _ D Q [ 6 3 : 0]
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q1 0
Q1 1
Q1 2
Q1 3
Q1 4
Q1 5
Q1 6
Q1 7
Q1 8
Q1 9
Q2 0
Q2 1
Q2 2
Q2 3
Q2 4
Q2 5
Q2 6
Q2 7
Q2 8
Q2 9
Q3 0
Q3 1
Q3 2
Q3 3
Q3 4
Q3 5
Q3 6
Q3 7
Q3 8
Q3 9
Q4 0
Q4 1
Q4 2
Q4 3
Q4 4
Q4 5
Q4 6
Q4 7
Q4 8
Q4 9
Q5 0
Q5 1
Q5 2
Q5 3
Q5 4
Q5 5
Q5 6
Q5 7
Q5 8
Q5 9
Q6 0
Q6 1
Q6 2
Q6 3
5
J D I M M2 B
1 . 5V
75
76
81
82
87
88
93
94
99
1 00
1 05
1 06
1 11
1 12
1 17
1 18
1 23
1 24
3 .3 VS
20mils
C 96
C9 7
1 u _ 6 . 3V _X 5 R _ 0 4
0. 1 u _ 1 0V _X 7 R _ 0 4
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
V DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1 99
V DD SP D
77
1 22
1 25
3 .3 V S
R 72
20mils
9 M V R E F _ D Q _D I M 0
1 0 K _ 1% _ 0 4
1 98
30
4, 1 1 T S # _ D I M M0 _ 1
4, 1 1 D D R 3_ D R A M R S T#
C 18
C 19
R2 0
*0 _ 0 4
2 . 2 u _ 6. 3 V _ X 5 R _ 0 6
0 . 1 u _ 10 V _ X 7 R _ 0 4
R1 9
1
1 26
E V E N T#
R E S E T#
V R E F _D Q
V R E F _C A
* 15 m i l _s h o rt _ 06
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
M V R E F _D I M0
C8 2
C8 1
NC 1
NC 2
N C TE S T
2 . 2u _ 6 . 3 V _ X5 R _0 6
0 . 1u _ 1 0 V _ X7 R _0 4
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1 0
VSS1 1
VSS1 2
VSS1 3
VSS1 4
VSS1 5
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
S1 6
S1 7
S1 8
S1 9
S2 0
S2 1
S2 2
S2 3
S2 4
S2 5
S2 6
S2 7
S2 8
S2 9
S3 0
S3 1
S3 2
S3 3
S3 4
S3 5
S3 6
S3 7
S3 8
S3 9
S4 0
S4 1
S4 2
S4 3
S4 4
S4 5
S4 6
S4 7
S4 8
S4 9
S5 0
S5 1
S5 2
44
48
49
54
55
60
61
65
66
71
72
12 7
12 8
13 3
13 4
13 8
13 9
14 4
14 5
15 0
15 1
15 5
15 6
16 1
16 2
16 7
16 8
17 2
17 3
17 8
17 9
18 4
18 5
18 9
19 0
19 5
19 6
Sheet 10 of 42
DDR3 SO-DIMM_0
V TT _ M E M
VT T 1
VT T 2
G1
G2
20 3
20 4
GN D 1
GN D 2
A S 0 A 6 2 1-U 2 S N -7 F
CLO SE TO SO -DI MM _0
A S 0 A 6 2 1 -U 2 S N -7 F
1 .5 V
1. 5 V
+
C3 5 3
+
C3 2 1
5 60 u _ 2 . 5V _6 . 6 * 6. 6 * 5. 9
*2 2 0 u_ 2 . 5 V _ B _ A
C 57
C6 2
C7 8
C 47
C 68
C 70
1 0 u _ 6. 3 V _ X 5 R _ 0 6
10 u _ 6 . 3V _X 5 R _ 0 6
*1 0 u _6 . 3 V _ X 5 R _ 0 6
1 u _6 . 3 V _ X 5 R _ 0 4
1 u _ 6. 3V _ X 5 R _ 0 4
* 1 u_ 6 . 3 V _ X 5R _ 0 4
+
R6 3
1K _1 % _ 0 4
M V R E F _ DIM 0
C 3 16
R 65
C8 6
1 K _ 1 % _0 4
0 . 1 u_ 1 0 V _ X7 R _ 04
* 5 60 u _ 2. 5V _ 6 . 6 *6 . 6 *5 . 9
1. 5 V
C7 3
C4 8
C 44
C 67
C4 6
C7 5
C 43
0 . 1u _ 1 0 V _ X7 R _0 4
0 . 1 u_ 1 0 V _ X 7R _ 04
* 0. 1 u _ 1 0V _X 7 R _ 0 4
0 . 1 u _ 10 V _ X 7 R _ 0 4
0. 1 u _ 1 0V _X 7 R _ 0 4
0 . 1u _ 1 0 V _ X7 R _0 4
*0 . 1 u _ 1 0V _ X 7 R _ 0 4
C1 0 1
C1 0 5
C 10 4
C 106
1 0u _ 6 . 3 V _ X5 R _0 6
*1 u _ 6 . 3V _X 5 R _ 0 4
1 u _ 6. 3 V _ X 5 R _ 0 4
1 u _ 6 . 3V _X 5 R _ 0 4
4 , 9 , 1 1, 21 , 2 3 , 2 7, 2 9 , 3 1 , 3 3, 3 6 1 . 5 V
1 1, 3 3 V T T _ ME M
2 , 1 1, 1 2 , 1 3 , 14 , 1 5 , 1 6 , 17 , 1 8 , 1 9 , 20 , 2 1 , 2 3 , 24 , 2 5 , 2 6, 27 , 2 8 , 2 9, 3 0 , 3 1 , 3 5, 3 6 3 . 3 V S
V T T _M E M
DDR3 SO-DIMM_0 B - 11
B.Schematic Diagrams
5
5
5
5
5
5
5
5
5
5
5
5
5
5
CHANGE TO STANDARD
Schematic Diagrams
DDR3 SO-DIMM_1
CHANGE TO STANDARD
SO-DIMM B
5
J DI M M1 A
M_ B _ A [ 1 5 : 0]
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
B.Schematic Diagrams
La yout Not e:
si gnal /spa c e/ signa l:
8/4/8
5
M _ B_ BS0
5
M _ B_ BS1
5
M _ B_ BS2
5
M _ CS # 2
5
M _ CS # 3
5 M_ C LK _ D D R 2
5 M_ C LK _ D D R # 2
5 M_ C LK _ D D R 3
5 M_ C LK _ D D R # 3
5
M _ CK E 2
5
M _ CK E 3
5
M_ B _ CA S #
5
M_ B _ RA S #
5
M_ B _ W E #
10 S A 0 _D I M 1
10 S A 1 _D I M 1
2, 1 0 C L K _ S C LK
2 , 1 0 CL K _ S D A TA
Sheet 11 of 42
DDR3 SO-DIMM_1
5
5
5
5
_B
_B
_B
_B
_B
_B
_B
_B
_B
_B
_B
_B
_B
_B
_B
_B
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
_A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A1 0 /A P
A1 1
A1 2 /B C#
A1 3
A1 4
A1 5
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
S A 0 _ D I M1
S A 1 _ D I M1
BA0
BA1
BA2
S0 #
S1 #
CK 0
CK 0#
CK 1
CK 1#
CK E 0
CK E 1
CA S #
RA S #
W E#
SA0
SA1
SC L
SD A
116
120
M _ OD T2
M _ OD T3
M _B _D M[ 7 : 0 ]
M _B _D QS [ 7: 0 ]
5 M _ B _ DQ S # [ 7: 0 ]
M
M
M
M
M
M
M
M
_B
_B
_B
_B
_B
_B
_B
_B
_D
_D
_D
_D
_D
_D
_D
_D
M0
M1
M2
M3
M4
M5
M6
M7
M
M
M
M
M
M
M
M
_B
_B
_B
_B
_B
_B
_B
_B
_D
_D
_D
_D
_D
_D
_D
_D
QS
QS
QS
QS
QS
QS
QS
QS
0
1
2
3
4
5
6
7
12
29
47
64
137
154
171
188
M
M
M
M
M
M
M
M
_B
_B
_B
_B
_B
_B
_B
_B
_D
_D
_D
_D
_D
_D
_D
_D
QS
QS
QS
QS
QS
QS
QS
QS
#0
#1
#2
#3
#4
#5
#6
#7
10
27
45
62
135
152
169
186
OD T 0
OD T 1
11
28
46
63
136
153
170
187
DM
DM
DM
DM
DM
DM
DM
DM
0
1
2
3
4
5
6
7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S0
S1
S2
S3
S4
S5
S6
S7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S0 #
S1 #
S2 #
S3 #
S4 #
S5 #
S6 #
S7 #
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 8
DQ 9
DQ 1 0
DQ 1 1
DQ 1 2
DQ 1 3
DQ 1 4
DQ 1 5
DQ 1 6
DQ 1 7
DQ 1 8
DQ 1 9
DQ 2 0
DQ 2 1
DQ 2 2
DQ 2 3
DQ 2 4
DQ 2 5
DQ 2 6
DQ 2 7
DQ 2 8
DQ 2 9
DQ 3 0
DQ 3 1
DQ 3 2
DQ 3 3
DQ 3 4
DQ 3 5
DQ 3 6
DQ 3 7
DQ 3 8
DQ 3 9
DQ 4 0
DQ 4 1
DQ 4 2
DQ 4 3
DQ 4 4
DQ 4 5
DQ 4 6
DQ 4 7
DQ 4 8
DQ 4 9
DQ 5 0
DQ 5 1
DQ 5 2
DQ 5 3
DQ 5 4
DQ 5 5
DQ 5 6
DQ 5 7
DQ 5 8
DQ 5 9
DQ 6 0
DQ 6 1
DQ 6 2
DQ 6 3
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
1 29
1 31
1 41
1 43
1 30
1 32
1 40
1 42
1 47
1 49
1 57
1 59
1 46
1 48
1 58
1 60
1 63
1 65
1 75
1 77
1 64
1 66
1 74
1 76
1 81
1 83
1 91
1 93
1 80
1 82
1 92
1 94
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
M_ B _ D Q
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
M_ B _ D Q[ 6 3 : 0 ] 5
J D I M M1 B
1 . 5V
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
3. 3 V S
20 m ils
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
D1
D2
D3
D4
D5
D6
D7
D8
D9
D1 0
D1 1
D1 2
D1 3
D1 4
D1 5
D1 6
D1 7
D1 8
VSS1 6
VSS1 7
VSS1 8
VSS1 9
VSS2 0
VSS2 1
VSS2 2
VSS2 3
VSS2 4
VSS2 5
VSS2 6
VSS2 7
VSS2 8
VSS2 9
VSS3 0
VSS3 1
VSS3 2
VSS3 3
VSS3 4
VSS3 5
VSS3 6
VSS3 7
VSS3 8
VSS3 9
VSS4 0
VSS4 1
VSS4 2
VSS4 3
VSS4 4
VSS4 5
VSS4 6
VSS4 7
VSS4 8
VSS4 9
VSS5 0
VSS5 1
VSS5 2
199
V D DS P D
C9 8
C 99
1 u_ 6 . 3 V _ X5 R _0 4
0 . 1 u _ 10 V _ X 7 R_ 0 4
77
122
125
198
30
4 , 1 0 TS # _ D I MM 0_ 1
4 , 1 0 D D R 3 _ DR A MR S T #
C2 2
C2 3
9 M V R E F _D Q_ D I M1
R 23
* 0_ 0 4
R2 2
MV RE F _ D I M1
C8 4
C8 3
NC 1
NC 2
NC T E S T
2 . 2u _ 6 . 3 V _ X5 R _0 6
0 . 1u _ 1 0 V _X 7 R _0 4
EVEN T#
RE S E T #
1
126
V R E F _ DQ
V R E F _ CA
*1 5 m il _ s h ort _ 0 6
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
2 . 2u _ 6 . 3 V _ X5 R _0 6
0 . 1u _ 1 0 V _X 7 R _0 4
2010/01/08
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1 0
VSS1 1
VSS1 2
VSS1 3
VSS1 4
VSS1 5
44
48
49
54
55
60
61
65
66
71
72
1 27
1 28
1 33
1 34
1 38
1 39
1 44
1 45
1 50
1 51
1 55
1 56
1 61
1 62
1 67
1 68
1 72
1 73
1 78
1 79
1 84
1 85
1 89
1 90
1 95
1 96
V T T_ M E M
VTT1
VTT2
G1
G2
2 03
2 04
GN D 1
GN D 2
A S 0 A 6 2 1 -U A S N -7 F
A S 0 A 6 2 1 -UA S N -7 F
CLO SE TO SO -D IMM _1
La yout Note :
SO -D IM M_1 i s pl ac e d fa rthe r f rom t he GMCH tha n S O- DIMM _ 0
1 .5 V
1. 5 V
C8 5
C 63
C 42
C 51
C 71
C 76
C 79
*1 0 u _ 6. 3 V _ X 5 R _ 0 6
1 0 u_ 6 . 3 V _ X5 R _ 06
1 0 u_ 6 . 3 V _ X 5R _ 06
1 u _6 . 3 V _ X 5 R _ 0 4
1 u _ 6. 3 V _ X 5 R _ 0 4
1 u _ 6. 3 V _ X 5 R _ 0 4
* 1u _ 6 . 3 V _ X5 R _0 4
C1 0 9
C 25
C 66
C 22 8
C 49
C 69
C 72
C 77
C 50
C 45
0 . 1 u_ 1 0 V _ X7 R _0 4
0 . 1 u_ 1 0 V _ X7 R _ 04
0 . 1 u_ 1 0 V _ X 7R _ 04
0 . 1 u _1 0 V _ X 7R _ 04
0 . 1 u _1 0 V _ X 7R _ 04
0 . 1 u _1 0 V _ X 7R _ 0 4
0 . 1 u _1 0 V _ X 7 R _ 0 4
0 . 1 u _ 10 V _ X 7 R _ 0 4
0 . 1 u _ 10 V _ X 7 R _ 0 4
0 . 1 u _ 10 V _ X 7 R_ 0 4
C1 0 2
C 10 7
C 10 8
C 10 3
1 0 u_ 6 . 3 V _ X5 R _0 6
1 u _6 . 3 V _ X 5R _ 0 4
*1 u _ 6 . 3V _X 5 R _ 0 4
1 u _6 . 3 V _ X 5 R _ 0 4
R6 4
1 K _ 1% _ 0 4
MV R E F _ D I M 1
R 66
C8 7
1 K _ 1 % _0 4
0 . 1 u_ 1 0 V _ X7 R _0 4
1 . 5V
V T T _ ME M
B - 12 DDR3 SO-DIMM_1
4 , 9 , 1 0, 2 1 , 2 3 , 2 7, 2 9 , 3 1 , 33 , 3 6 1 . 5 V
10 , 3 3 V T T _M E M
2 , 1 0 , 12 , 1 3 , 1 4, 15 , 1 6 , 1 7, 1 8 , 1 9 , 20 , 2 1 , 2 3 , 24 , 2 5 , 2 6, 2 7 , 2 8 , 2 9, 3 0 , 3 1 , 35 , 3 6 3 . 3 V S
Schematic Diagrams
LVDS, Inverter
3 .3 V S
EDID Mode
PANEL CONNECTOR
V IN
2
1
3 R N6
4 2 . 2 K _ 4P 2 R _0 4
V I N _L C D
L 25
J _ LC D 1
80m ils
*1 5 mi l _ sh o rt _ 06
C3 0 0
C2 9 7
C2 9 4
0 . 1 u_ 5 0V _Y 5V _0 6
0 . 1 u_ 5 0V _Y 5V _0 6
0. 1u _ 50 V _ Y 5 V _ 0 6
LV D S -L C L K N
L V D S -L C L K P
17
17
L V D S -L 1 N
L V D S -L 1P
17
17
L V D S -L 0 N
L V D S -L 0P
LV D S -L C L K N
LV D S -L C L K P
LV D S -L 1 N
LV D S -L 1 P
LV D S -L 0 N
LV D S -L 0 P
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
87 2 1 6-3 0 0 6
P _ DD C_ DA T A
P _ DD C_ CL K
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
B R I GH T N E S S
B RIG HT NE S S
P _ D D C _ D A TA 17
P _ D D C _ C LK 17
28
I N V _ B L ON
LV D S -L 2N
LV D S -L 2P
LV D S -L 2N
LV D S -L 2P
17
17
3. 3 V S
C 2 91
0 . 1 u _1 6 V _ Y 5 V _ 04
P LV D D
C4
C 6
4. 7 u _ 6. 3 V _ X 5R _ 06
0 . 1 u _1 6 V _ Y 5 V _ 04
Sheet 12 of 42
LVDS, Inverter
PANEL POWER
3 . 3V S
2A
R 16
*1 5 m li _ s ho rt _ 0 6
C1 5
C1 7
0 . 1 u_ 1 6 V _Y 5 V _0 4
3 . 3V
*0 . 01 u _ 50 V _ X 7R _ 04
D1 5
P L V DD
U 1
4
5
1
VIN
VIN
C
2A
B RIG HT NE S S
AC
VO UT
C2 9 0
*0 . 1 u_ 1 6 V _Y 5 V _0 4
A
*B A V 9 9 R E C TI F I E R
3
1 7 NB _ E NAV DD
2
EN
R1 3
GN D
A P L 3 51 2 A
10 0 K _ 1% _ 0 4
G5243A 6-02-05243-9C0
APL3512A 6-02-03512-9C0
INVERTER CONNECTOR
BK L _ E N_ R
R 67
C 90
*1 0 0 K _ 1% _ 04
* 0 . 47 u _ 10 V _ Y 5 V _ 0 4
3. 3 V
1
3. 3 V
U3 A
7 4L V C 08 P W
3
Z 1 2 01
3. 3V
U 3B
7 4 LV C 0 8P W
C8 9
4
2
B L ON
6
*0 . 1 u _1 6 V _ Y 5 V _ 04
5
7
R 69
14
1 0 0K _ 1 % _0 4
19
S B _B LO N
Z 1 2 02
2 8, 3 0
L ID_ S W #
1 6, 2 8 A L L _S Y S _ P W R G D
8
1 00 K _ 1 %_ 0 4
I N V _B L O N
Z 1 2 03 1 0
U 3D
7 4 LV C 0 8P W
12
11
7
R7 0
U 3C
7 4 LV C 0 8P W
9
3. 3 V
14
1 7 B L ON
14
*1 0 mi l _ sh o rt _ 04
R 71
C9 3
1 M _0 4
0 . 1u _ 1 6V _ Y 5V _ 0 4
13
7
R6 8
14
B K L _E N
7
28
3 0, 31 , 3 2 , 33 , 3 4 , 35 , 3 6 , 37
3 , 4 , 1 4, 1 5 , 1 6, 1 8 , 1 9, 2 0 , 2 1, 23 , 2 4, 25 , 2 9 , 30 , 3 1 , 33 , 3 4 , 35
2 , 1 0, 1 1 , 1 3, 1 4 , 1 5, 1 6 , 1 7, 1 8 , 1 9, 2 0 , 2 1, 2 3 , 2 4, 25 , 2 6, 27 , 2 8 , 29 , 3 0 , 31 , 3 5 , 36
3 1 , 32
V IN
3 .3 V
3 .3 VS
S Y S 15 V
LVDS, Inverter B - 13
B.Schematic Diagrams
CLOSE TO LVDS CONN.
PIN
17
17
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
Schematic Diagrams
HDMI, CRT
HDMI PORT
L 27
1 _0 4
For ESD
5V S
5 VS
RD2
RD3
B A V 99 R E C T FI I E R B A V 99 R E C T I FI E R
C 65
0. 1 u_1 6V _ Y 5V _0 4
0. 1 u_ 16 V_ Y 5V _0 4
R 30
*4. 7 K_ 04
PC 1
R2 7
M_P OR TB _ H PD # _R
H D MI B_ D A TA 0P
T MD S D A T A2 S H I EL D 2
TMD S D A TA 2+
3
1
C 12 81 7-1 19A 5 -L
3 3. V S
C 3 10
C 59
0 . 1u _16 V _Y 5 V_ 04
* 0. 1u _1 6V _Y 5 V _0 4
5V S
1 7 D A C _ VS Y N C
1
5V S
2
3 . 3V S
7
3. 3V S
S Y N C _I N 2
S Y N C _OU T 2
V C C _S Y N C
VI D E O_ 1
V C C _V I D E O
VI D E O_ 2
V C C _D D C
VI D E O_ 3
C 2 96
0. 2 2u _1 0V _Y 5V _ 04
0 . 22 u_ 10V _ Y5 V _04
C 29 9
8
0. 2 2u_ 10 V _Y 5V _0 4
16
C R T_ VS Y N C
S Y N C _OU T 1
R 15
R 14
150 _1 %_ 04
15 0_ 1%_ 04
33 _0 4
HS Y NC
33 _0 4
V SY N C
3
B LU E
4
GR N
5
RE D
GN D
IP4772C Z16 6- 02-47721- B60
TPD7S01 9 6-0 2-07019-B 20
2 , 10 ,1 1, 1 2, 14 , 15 , 16, 1 7, 1 8, 19 , 20 2, 1, 2 3, 24 , 25 , 26, 2 7, 2 8, 29 , 30 3, 1, 3 5, 36 3. 3V S
2 , 17 , 20, 2 1, 2 6, 27 , 30 ,3 1, 3 5, 36 5V S
B - 14 HDMI, CRT
2 H D MI B_ D A TA 2P
L8
*H DMI 2 01 2F 2S F -90 0T 04-s ho rt
9
2410 mil
3
4
12
D D C D AT A
13
HS Y NC
14
V S Y NC
15
DDCL K
5
6
7
8
6
BYP
TP D 7S 0 19
3 H D MI B _D AT A2 N
1
11
10 p_ 50V _ N PO _ 04
D D C _OU T 2
C R T_ H S Y N C
1 50 _1% _0 4
GR N
B LU E
C 16
S Y N C _I N 1
15
DDCL K
14
R 10
1 0p _5 0V _N P O _0 4
DDC_ IN2
R 11
10 p_ 50 V_ N P O _0 4
12
13
1 7 D A C _H S Y N C
R1 2
D D C D A TA
C1 4
1 7 D A C _D D C A C L K
1
2
1
2
11
9
4
1
2
F C M100 5MF -6 00T 01
F C M100 5MF -6 00T 01
F C M100 5MF -6 00T 01
C1 1
D D C _OU T 1
10 p_ 50V _ N PO _ 04
DDC_ IN1
C 13
RN1
2. 2 K_ 4P 2 R _04
U 15
10
L4
L3
L2
1 0p _5 0V _N P O _0 4
4
3
RN7
2 . 2K _4 P 2R _ 04
1 7 D A C _D D C A D A TA
C 29 8
RE D
17 D A C _ R ED
17 D A C _ GR EE N
17 D A C _ BL U E
L6
*H DMI 2 01 2F 2S F -90 0T 04-s ho rt
J_ C R T1
10 8A H 1 5F S T04 A 1C C
6-19-31001-266
3 . 3V S
R 44
R4 3
TMD S D A TA 1 +
*1 0m li _s ho rt_ 04
4
3
CRT PORT
POR T C _H P D
17 P OR T C _H P D
4
3
* H D MI 20 12F 2 SF -90 0T 04 -sho rt
H D MI B _D AT A0 N
2
*LV A R 04 02- 2 40 E0 R 05 P -L F
H D MI B _D A TA 1P
C 27
2
3
1
*L VA R 0 402 - 24 0E 0R 0 5P - LF
1
5
12
18
24
27
31
36
37
43
1
4
5
S H I E LD 1
C 7 10 00 p_ 50 V_ X 7R _0 4
PC 0
A
H D MI B _D A TA 1N
2
9
7
TMD S D A TA 0+
TMD S D A TA 1 -
4
C 2 92 2 20 p_ 50 V_ N P O _04
D C C _E N #
4. 7K _ 04
2 0K _1 %_ 04
T MD S D A T A0 S H I EL D 0
6
FO R EM I
H D MI _C E C
C 29 3 22 0p _50 V _N P O _0 4
4. 7K _ 04
R 31
C3 2
TMD S C L OC K+
H D MI B _E XT 1_ S C L
13
11
R 59
*0 . 1u _16 V _Y 5 V_ 04 0 . 1u _16 V _Y 5 V_ 04
L7
PTN336 0BBS 6 -03 -03360 -030
PS8101 6-03- 081 01-032
R 57
AC
C4 0
0. 1 u_ 16 V_ Y 5V _0 4
P TN 3 36 0B B S
P I N 4 9= GN D
3. 3V S
AC
C1
C LK S H I EL D
C 2 95 1 000 p_ 50 V_ X 7R _ 04
GN D
R4 8
8
CE C
TMD S C L OC K-
R5 5
GN D [ 1]
GN D [ 2]
GN D [ 3]
GN D [ 4]
GN D [ 5]
GN D [ 6]
GN D [ 7]
GN D [ 8]
GN D [ 9]
GN D [ 10]
3 . 3V S
R 41
H D MI B _E XT 1_ H P D
R4 2
H D MI B _E XT 1_ S C L
H D MI B _E XT 1_ S D A
30
10
4
3
* H D MI 201 2F 2 SF -90 0T 04 -s ho rt
R E S ER V E D
15
*LV A R 04 02- 2 40 E0 R 05 P -L F
49
28
29
12
2
SC L
*L VA R 0 402 -24 0E 0R 0 5P - LF
V C C [ 1]
V C C [ 2]
V C C [ 3]
V C C [ 4]
V C C [ 5]
V C C [ 6]
V C C [ 7]
V C C [ 8]
34
3 5 OE _ 1
QE _ 2
Z 4 306
Z 4 307
H D MI B _C LO C KP
2
11
15
21
26
33
40
46
14
L5
1
D D C / C E C GN D
S DA
F OR E MI
H D MI B _C LO C KN
H D MI B _E XT 1_ H P D
19
17
+5 V
16
GND 1
GND 2
*4. 7 K_ 04
*4. 7 K_ 04
H D MI B _C L OC K P
H D MI B _C L OC K N
H OT P LU G D E T EC T
18
4
3
10 p_ 50 V_ N P O _0 4
R4 9
R5 8
13
14
1
2
C1 2
3. 3 VS
499 _1 %_ 04
H D MI B _D A TA 0 P
H D MI B _D A TA 0 N
H D MIB _ EX T1 _S D A
C1 0
Sheet 13 of 42
HDMI, CRT
P C0
P C1
Z 4 305
16
17
H PD _ S I N K
22 u_6 . 3V _X 5R _ 08
RN2
2 . 2K _4 P2 R _0 4
* LV A R 04 02- 2 40 E0 R 05 P -L F
R2 9
DCC_ E N#
S C L_ S I N K
S D A_ S I N K
10u _6 . 3V _X 5R _ 06
5V S
* LV A R 04 02- 2 40 E0 R 05 P -L F
*4. 7K _ 04
*0_ 04
OU T _D 4 +
OU T _D 4-
H D MI B _D A TA 1 P
H D MI B _D A TA 1 N
C 31 7
*L VA R 0 402 - 24 0E 0R 0 5P - LF
R5 6
R4 7
3 . 3V S
Z 4 304
OU T _D 3 +
OU T _D 3-
19
20
C 319
.
.
.
B.Schematic Diagrams
M_P OR TB _ H PD # _R
OU T _D 2 +
OU T _D 2-
H D MI B _D A TA 2 P
H D MI B _D A TA 2 N
R 46
H D MI _C T R LC L K
H D MI _C T R LD A TA
1 7 H D MI _C T R LC L K
17 H D MI _C T R LD A TA
OU T _D 1 +
OU T _D 1-
22
23
R5 1
17 H D MI B_ C LK B P
17 H D MI B_ C LK B N
39
3 8 I N _ D 1+
I N _ D 142
4 1 I N _ D 2+
I N _ D 245
4 4 I N _ D 3+
I N _ D 348
4 7 I N _ D 4+
I N _ D 49
8 S CL
S DA
7
HP D
25
OE #
32
1 0 D C C _E N #
R T _E N #
3
4 P C0
6 P C1
RE X T
*L VA R 0 402 - 24 0E 0R 0 5P -LF
17 H D MI B_ D 0B P
17 H D MI B_ D 0B N
C
J_ H D MI 1
AC
17 H D MI B_ D 1B P
17 H D MI B_ D 1B N
1_0 4
B A V 99 R E C T I FI E R
U2
17 H D MI B_ D 2B P
17 H D MI B_ D 2B N
A
C
A
RD1
C
R 210
FOR INTEL GRAPHIC
Schematic Diagrams
IBEXPEAK- M 1/9
IBEXPEAK - M (HDA,JTAG,SATA)
2 0m ils
1
20m ils
A
C
3
C 36 9
6 -2 2- 32 R7 6 -0 B2
6 -2 2- 32 R7 6 -0 BG
C 40 2
1 5p _ 5 0 V _ N P O _ 04
R T C_ X 1
1
2
RT CV CC
VD D3
X8
2 . 2 u _1 6 V _ X 5R _ 0 6
A
R 30 4
2 0 K _ 1% _ 0 4
6 -2 2- 32 R7 6- 0 B4
X7
* MC -1 46 _ 3 2 . 7 68 K H z
C3 9 9
1 K _ 1 % _ 04
2 . 2 u_ 1 6 V _ X5 R _ 06
J _ RT C1
1
8 5 20 5 -0 2 70 1
2
C1 4
S R T C _R T C #
D1 7
S M_ I N T R U D E R #
A1 6
P C H _ I N T V R ME N
A1 4
RT C X 1
RT C X 2
F W H0
F W H1
F W H2
F W H3
/
/
/
/
LA D
LA D
LA D
LA D
0
1
2
3
R 299
C4 0 0
1 M _ 04
2 . 2 u_ 1 6 V _ X5 R _ 06
TPM CLEAR
J O PEN 1
* OP E N _ 1 0 m li -1 MM
R T CVC C
R 29 8
3 3 0 K _ 04
F W H 4 / LF R A M E #
S R TC R S T#
I N TR U D E R #
I N TV R M E N
L D R Q0 #
L D R Q1 # / GP I O2 3
S E R IRQ
D 33
B3 3
C 32
A3 2
LP
LP
LP
LP
C 34
C_ A D
C_ A D
C_ A D
C_ A D
0
1
2
3
24 , 2 8
24 , 2 8
24 , 2 8
24 , 2 8
LP C _ F R A ME # 2 4 , 2 8
A3 4
F34
AB9
S E R IRQ
AK7
AK6
AK1 1
AK9
S A T A R XN 0
S A T A R XP 0
S AT A T XN0
SATATXP0
AH
AH
AH
AH
S A T A R XN 1
S A T A R XP 1
S AT A T XN1
SATATXP1
S E RI RQ
2 4, 2 8
2
2
B1 3
D1 3
R T C _R S T #
RT C RS T #
1
J_RTC1
R T C _X 1
R T C _X 2
Zo= 50O ? 5%
R 30 5
2 0 K _ 1% _ 0 4
LPC
RT C _ V B A T 1
1
J O PEN 2
* OP E N _ 1 0 m li -1 MM
U2 0 A
1 0 M_ 0 4
C 39 7
1 5p _ 5 0 V _ N P O _ 04
RTC CLEAR
2
R 253
C o- la yo ut X 7, X 8
R 3 02
3
4
1
D1 7
B A T 5 4C S 3
10m ils
R T C_ X 2
RTC
2
2
1
R T C _ V B A T_ 1
4
3
1 T JS 12 5 D J 4 A 4 2 0 P _ 32 . 7 6 8 K H z
2 7 ,2 9 HD A _ B IT CL K
H D A _ B C LK
D2 9
BIOS ROM
32Mbit
R1 6 3
3. 3 K _ 1 % _ 0 4
S P I_ W P #
SPKR
H D A _ R S T#
S A T A 1 RX N
S A TA 1R X P
S A T A 1 TX N
SATA1 TXP
G3 0
8
5
VD D
S I
W P#
C E#
R1 5 6
3. 3 K _ 1 % _ 0 4
S P I_ HO L D# 7
S PI_ S I
R3 8 1
27
*0 _ 0 4
2
S PI_ S O
R3 8 2
*0 _ 0 4
1
S P I_ CS 0 # R3 8 3
*0 _ 0 4
6
S P I_ S CL K R3 8 4
*0 _ 0 4
SO
3
P1
HD A _ S D IN0
F30
29
28
HD A _ S D IN1
HD A _ S D IN1
HD A _ S D IN2
F32
HD A _ S D IN3
8 51 8 _ S P I _ S C L K 2 8
4
B2 9
2 7 ,2 9 HD A _ S DO UT
VSS
D 18
C
M X 25 L 3 2 05 D M2 I -1 2 G
28
6-04-25320-A70
6-04-02532-470
6-04-26321-470
S C D3 4 0
A
R3 0 7
HD A _ DO CK _ E N #
H3 2
H D A _ D O C K _E N # / G P I O 33
J30
*1 0 m li _ s ho rt _ 0 4
H D A _ D O C K _R S T # / G P I O1 3
1 K _1 % _ 0 4
1
P C H _ JT A G _ T C K _ B U F M 3
J OP E N 3
* OP E N _ 10 m i l -1 MM
P C H _ JT A G _ T MS
J T A G_ T C K
P C H _ JT A G _ T D I
K1
P C H _ JT A G _ T D O
J2
P C H _ JT A G _ R S T #
J4
R2 9 0
R 2 87
*2 0 0 _ 06
*2 0 0_ 0 6
* 20 0 _ 0 6
R 93
R 282
J T A G_ R S T #
S P I _ S C LK
R2 8 8
*1 0 0_ 1 % _ 04
*1 0 0_ 1 % _ 04
AV3
S P I _ C S 1#
AY 3
AD 9
AD 8
AD 6
AD 5
S A T A R XN 2
S A T A R XP 2
S AT A T XN2
SATATXP2
AD 3
AD 1
AB3
AB1
AF1 6
S A T A I C OM P
S A TA I C O MP O
R 89
3 7 . 4 _ 1 %_ 0 4
R 2 78
* 1 0K _0 4
AF1 5
S A T A I C OM P I
3 .3 V S
iTPM ENABLE/DISABLE
*1 K _ 1 % _0 4 S P I _ S I
* 10 0 _ 1 % _0 4
S P I_ C S 1 #
S A TA LE D #
S P I _ M OS I
S A T A 0 G P / GP I O2 1
AY 1
S PI_ S I
S PI_ S O
T3
R2 6 4
3 3 _0 4
S P I _ S O _R
AV1
S P I_ M IS O
S A T A _ L E D#
S A TA _L E D # 2 9
Y 9
TPM FUNCTION:SPI_SI High Enable
O D D _ D E T E C T#
R 1 08
S A T A _ D E T# 1
R 2 74
V1
3 .3 VS
1 0 K_ 4
O D D _ D E T E C T # 26
S A T A 1 G P / GP I O1 9
I b e x P e ak -M _ R e v 0 _ 9
R2 8 5
Sheet 14 of 42
IBEXPEAK - M 1/9
AH 3
AH 1
AF3
AF1
BA2
S P I _ C S 0#
R 2 86
R 263
*1 0 K _ 1 %_ 0 4
SATA ODD
AF1 1
AF9
AF7
AF6
S P I_ C S 0 #
3 .3 VS
R 28 9
S A T A R XN 1 2 6
S A T A R XP 1 26
S A T A T X N1 2 6
SAT AT XP1 2 6
S P I _ C LK
P C H _ JT A G _ TM S
P C H _ JT A G _ TD I
P C H _ JT A G _ TD O
P C H _ JT A G _ R S T #
R2 9 4
SATA HDD
10 K _ 0 4
S E RIR Q
*1 K _ 1 % _0 4 H D A _S P K R
NO REBOOT STRAP: HDA_SPKR High Enable
SPI
R 29 3
6
5
9
8
1 .1 VS _ VT T
J T A G_ T D O
3 .3 VS
*2 0 K _ 1 %_ 0 4
26
26
26
26
J T A G_ T D I
3 .3 V
R2 9 5
S A T A 4 RX N
S A TA 4R X P
S A T A 4 TX N
SATA4 TXP
S A T A 5 RX N
S A TA 5R X P
S A T A 5 TX N
SATA5 TXP
K3
J T A G_ T MS
2
Flash Descriptor
Security Overide
S A T A 3 RX N
S A TA 3R X P
S A T A 3 TX N
SATA3 TXP
HD A _ S D O
ME _W E #
R 303
SPI_* = 1.5"~6.5"
S A T A 2 RX N
S A TA 2R X P
S A T A 2 TX N
SATA2 TXP
E3 2
8 51 8 _ S P I _ C S 0 # 28
SCK
H OL D #
HD A _ S D IN0
8 51 8 _ S P I _ S I 2 8
8 51 8 _ S P I _ S O
S A T A R XN 0
S A T A R XP 0
S A T A T X N0
SAT AT XP0
C3 0
2 7 ,2 9 HD A _ RS T #
U 10
S P I_ V D D
S A T A 0 RX N
S A TA 0R X P
S A T A 0 TX N
SATA0 TXP
HD A _ S Y NC
HD A _ S P K R
HD A_ SPK R
SATA
C 2 09
S H O R T 0 . 1 u _1 6 V _ Y 5V _0 4
27
IHDA
NC 1
2 7 ,2 9 HD A _ S Y N C
JTAG
3 .3 V S
1 0 K_ 0 4
*4 . 7 K _ 0 4 P C H _J T A G _T C K _ B U F
ESATA
SATATXP2
C 16 8
*0 . 0 1 u _ 50 V _ X 7 R _ 0 4
S A T A T X N2
C 16 5
*0 . 0 1 u _ 50 V _ X 7 R _ 0 4
S A T A R XN 2
C 15 5
*0 . 0 1 u _ 50 V _ X 7 R _ 0 4
S A T A R XP 2
C 16 4
*0 . 0 1 u _ 50 V _ X 7 R _ 0 4
2 3 , 2 5 , 28 , 2 9 , 3 1 , 3 2, 3 7 V D D 3
21
R TC V C C
2 , 4 , 6 , 7 , 1 5 , 1 6, 1 9 , 2 0 , 2 1, 3 4 , 3 5 , 3 6 1. 1 V S _V TT
3 , 4 , 1 2 , 1 5, 16 , 1 8 , 1 9, 20 , 2 1 , 2 3 , 24 , 2 5 , 2 9 , 30 , 3 1 , 3 3 , 3 4, 3 5 3 . 3 V
2 , 10 , 1 1 , 1 2 , 1 3, 1 5 , 1 6 , 1 7, 1 8 , 1 9 , 2 0, 2 1 , 2 3 , 2 4, 25 , 2 6 , 2 7 , 28 , 2 9 , 3 0 , 31 , 3 5 , 3 6 3 . 3V S
IBEXPEAK- M 1/9 B - 15
B.Schematic Diagrams
A3 0
Schematic Diagrams
IBEXPEAK - M 2/9
IBEXPEAK - M (PCI-E,SMBUS,CLK)
S MB _C L K
S MB _D A T A
RN 1 6
2 . 2K _ 4P 2R _ 0 4
3
2
4
1
S ML 0 _ D A T A
S ML 0 _ C L K
RN 1 1
2 . 2K _ 4P 2R _ 0 4
3
2
4
1
U 20 B
Sheet 15 of 42
IBEXPEAK - M 2/9
Lane
Lane
Lane
Lane
Lane
Lane
Lane
Lane
3 .3 V
C 1 24
C 1 23
0. 1u _ 1 0 V _ X 7 R _ 0 4
0. 1u _ 1 0 V _ X 7 R _ 0 4
P C IE _ T X N3 _ C
PC IE_ T XP3 _ C
AU 3 0
AT3 0
AU 3 2
A V3 2
C 1 19
C 1 20
0. 1u _ 1 0 V _ X 7 R _ 0 4
0. 1u _ 1 0 V _ X 7 R _ 0 4
P C IE _ T X N4 _ C
PC IE_ T XP4 _ C
B A3 2
B B3 2
BD 3 2
B E3 2
B F3 3
BH 3 3
BG 3 2
BJ 3 2
Usage
1
2
3
4
5
6
7
8
B A3 4
AW 3 4
BC 3 4
BD 3 4
WLAN
NEW CARD
3G
GLAN / CARD READER
X
X
X
X
AT3 4
AU 3 4
AU 3 6
A V3 6
BG 3 4
BJ 3 4
BG 3 6
BJ 3 6
A K4 8
A K4 7
3 .3 VS
RN 8
1 0 K _ 8P 4 R _ 0 4
1
8
2
7
3
6
4
5
P C I E C L K R Q0 #
PC
PC
PC
PE
IE C L K RQ
IE C L K RQ
IE C L K RQ
G_ B _ C LK
1#
0#
5#
RQ #
P C I E C L K R Q1 #
2 3 N E W C A R D _ C L K R E Q#
R 2 83
* 1 0m i l _ s ho rt _ 0 4
C L K _ S L O T2 _ O E #
2 3 CL K _ P CIE _ M IN I#
2 3 CL K _ P C IE _ M INI
PER N4
PER P4
PET N 4
PET P4
S M L 0_ C L K
S M L 0_ D A T A
PER N5
PER P5
PET N 5
PET P5
PER N6
PER P6
PET N 6
PET P6
S ML 0 D A TA
M 14
L P D _S P I _ I N T R #
E1 0
SM C_ C PU_ T H E R M
G 12
SM D_ C PU_ T H E R M
S M L 1 A L E RT # / G P IO 7 4
S M B _ CL K
2
S M B _ DA T A 2
18
PC H_ U PE K_ IN IT # 1 8
S ML 0 _ C L K
S ML 0 _ D A T A
PER N8
PER P8
PET N 8
PET P8
23
S MD _ C P U _ T H E R M
S MC _ C P U _ T H E R M
Controller
Link
P C I E C L K R Q 2 # / GP I O2 0
RN 1 0
2 . 2K _ 4P 2R _ 0 4
3
2
4
1
S MC _ C P U _ T H E R M 3 , 2 8
S MD _ C P U _ T H E R M 3 , 2 8
P E G _ CL K R E Q #
R2 9 1
1 0K _ 04
L A N _C L K R E Q#
R1 1 2
1 0K _ 04
T11
CL _ D A T A1
T9
C L_ R S T 1 #
10K pull-down to
GND
H 1
C L K O U T _ P E G_ A _ N
C LK OU T _ P E G _A _P
C L K O U T _ D MI _ N
C L K O U T_ D MI _P
C LK OU T _ D P _ N / C LK OU T _ B C L K 1 _ N
C L K O U T_ D P _ P / C L K O U T _ B C L K 1 _P
C L K O U T_ P C I E 2 N
C L K O U T_ P C I E 2 P
RN 1 3
1 0K _8 P 4 R _ 0 4
1
8
2
7
3
6
4
5
T13
C L K O U T_ P C I E 0 N
C L K O U T_ P C I E 0 P
C L K O U T_ P C I E 1 N
C L K O U T_ P C I E 1 P
PCH _ BT _ EN#
U S B _ OC # 8 9
LP D _ S P I _I N T R #
23
P E G _ CL K R E Q #
100-MHz Gen2 differential clock to PCIe Graphics
device.
P E G _A _ C L K R Q# / G P I O 4 7
PER N7
PER P7
PET N 7
PET P7
U S B _ OC # 8 9
CL _ C L K 1
C L K O U T_ P C I E 3 N
C L K O U T_ P C I E 3 P
C L K I N _ D MI _ N
C L K I N _ D MI _P
C L K I N _B C L K _ N
C L K I N _ B C LK _P
C L K I N _ D O T _9 6 N
C L K I N _ D O T _ 9 6P
C L K IN _ S A T A _ N / CK S S C D_ N
C L K I N _S A T A _ P / C K S S C D _P
AD 4 3
AD 4 5
AN 4
AN 2
AT1
AT3
C LK _E XP _ N 4
C LK _E XP _ P 4
P C H_ C L K _ DP _ N _ R
P C H_ C L K _ DP _ P _ R
R2 6 6
R2 6 7
A W 24
BA2 4
C L K _ D P _N
C L K _ D P _P
4
4
100-MHz differential clock from PCH to Processor.
Connect to PEG_CLK#/PEG_CLK pins of the
processo
C LK _ B U F _B C L K _ N 2
C LK _ B U F _B C L K _ P 2
F18
E1 8
C LK _ B U F _D O T9 6 _ N 2
C LK _ B U F _D O T9 6 _ P 2
AH 1 3
AH 1 2
C3 9 1
C LK _ S A T A # 2
C LK _ S A T A 2
C LK _ B U F _R E F 1 4 2
RE F CL K 1 4 IN
J42
C LK _ P C I _ F B
C L K I N _ P C I L O OP B A C K
R2 6 8
X6
F S X 5 L _2 5 M H z
1 M_ 0 4
18
2 2 p _ 50 V _N P O _ 04
6 -2 2- 2 5R 00 -1 B 4
6 -2 2- 2 5R 00 -1 B 5
2
P C I E C L K R Q 3 # / GP I O2 5
*1 0 m i l_ s h o rt _ 0 4
*1 0 m i _l s h o rt _ 0 4
C LK _ P C I E _I C H # 2
C LK _ P C I E _I C H 2
AP3
AP1
P4 1
A 8
2 3 W L A N _ CL K R E Q #
C 6
G8
S M L1 D A T A / G P I O 7 5
P C I E C L K R Q 1 # / GP I O1 8
N 4
PC H_ U PE K_ IN IT #
S M L 1 CL K / G P IO 5 8
U 4
AH 4 2
AH 4 1
J14
S ML 0 C LK
P C I E C L K R Q 0 # / GP I O7 3
AM 4 7
AM 4 8
2 3 C L K _ P C IE _ NE W _ CA R D #
2 3 C L K _ P CI E _ NE W _ CA R D
S M B _ D A TA
S M L 0 A L E RT # / G P IO 6 0
PER N3
PER P3
PET N 3
PET P3
P 9
AM 4 3
AM 4 5
C 8
P C H _ B T _E N # 2 3 , 2 9
1
PCI-E x1
P C IE _ T X N2 _ C
PC IE_ T XP2 _ C
S M B _ CL K
S M B C LK
SMBus
2 5 P C I E _ R X N 4_ G L A N
2 5 P C I E _ R X P 4 _ GL A N
2 5 P C I E _ T X N 4_ G L A N
2 5 P C I E _ T X P 4 _ GL A N
0. 1u _ 1 0 V _ X 7 R _ 0 4
0. 1u _ 1 0 V _ X 7 R _ 0 4
PC H_ BT _ EN #
S M B D A TA
PER N2
PER P2
PET N 2
PET P2
AM 5 1
AM 5 3
2 5 C LK _P C I E _G L A N #
2 5 CL K _ P CIE _ G L A N
LA N _ C LK R E Q #
C L K O U T_ P C I E 4 N
C L K O U T_ P C I E 4 P
X TA L2 5 _ I N
X T A L 2 5 _ OU T
M9
P C I E C L K R Q 4 # / GP I O2 6
AJ 5 0
AJ 5 2
P C I E C LK R Q 5 #
C L K O U T_ P C I E 5 N
C L K O U T_ P C I E 5 P
H 6
P C I E C L K R Q 5 # / GP I O4 4
A K5 3
A K5 1
P E G _ B _ CL K R Q #
C L K O U T_ P E G_ B _ N
C L K O U T_ P E G_ B _ P
P1 3
P E G _ B _ C L K R Q# / GP I O5 6
AH 5 1
AH 5 3
X T A L 25 _ I N
X T A L 25 _ O U T
AF3 8
X CL K _ R CO M P
X C L K _ R C O MP
Clock Flex
B.Schematic Diagrams
2 3 P C IE _ R X N3 _ W L A N
2 3 P C I E _ R X P 3 _W L A N
2 3 PC IE_ T XN3 _ W L AN
2 3 P C I E _ T X P 3 _W L A N
C 1 17
C 1 18
AW 3 0
B A3 0
BC 3 0
BD 3 0
PEG
P C I E _ R X N 2_ N E W _ C A R D
P CIE _ RX P 2 _ NE W _ CA RD
P C I E _ T X N 2_ N E W _ C A R D
P CIE _ T X P 2 _ NE W _ CA RD
B9
H 14
S MB A L E R T # / G P I O 1 1
From CLK BUFFER
23
23
23
23
PER N1
PER P1
PET N 1
PET P1
PCI-E*
BG 3 0
BJ 3 0
B F2 9
BH 2 9
C3 8 7
R8 7
9 0 . 9 _ 1 % _ 04
1 .1 V S_ V T T
T45
CL K O UT F L E X 0 / G P IO 6 4
P4 3
CL K O UT F L E X 1 / G P IO 6 5
T42
CL K O UT F L E X 2 / G P IO 6 6
N 50
CL K O UT F L E X 3 / G P IO 6 7
I b e x P e ak -M _ R e v 0 _ 9
3 .3 VS
2, 1 0 , 1 1 , 1 2 , 1 3 , 14 , 1 6 , 1 7 , 1 8 , 1 9, 20 , 2 1 , 2 3 , 2 4 , 2 5, 26 , 2 7 , 2 8 , 2 9 , 3 0, 3 1 , 3 5 , 3 6
1 . 1 V S _ V T T 2 , 4 , 6 , 7 , 1 4, 16 , 1 9 , 2 0 , 2 1 , 3 4, 35 , 3 6
3 .3 V
3, 4 , 1 2 , 1 4 , 1 6 , 1 8, 19 , 2 0 , 2 1 , 2 3 , 2 4, 25 , 2 9 , 3 0 , 3 1 , 3 3, 3 4 , 3 5
B - 16 IBEXPEAK - M 2/9
3 .3 V
90.9-O ? % pullup
to +VccIO
(1.05V, S0 rail)
2 2 p _ 50 V _N P O _ 04
Schematic Diagrams
IBEXPEAK - M 3/9
IBEXPEAK - M (DMI,FDI,GPIO)
U2 0 C
3
3
3
3
D MI _ R X P 0
D MI _ R X P 1
D MI _ R X P 2
D MI _ R X P 3
B C 24
B J 22
A W 20
B J 20
0
1
2
3
3
3
3
3
DM
DM
DM
DM
I _ TX N
I _ TX N
I _ TX N
I _ TX N
3
3
3
3
DM
DM
DM
DM
I _ TX P 0
I _ TX P 1
I _ TX P 2
I _ TX P 3
B D 24
B G 22
B A 20
B G 20
B D 22
B H 21
B C 20
B D 18
D MI _C OM P _ R
MI 0 R
MI 1 R
MI 2 R
MI 3 R
F DI_ R
F DI_ R
F DI_ R
F DI_ R
F DI_ R
F DI_ R
F DI_ R
F DI_ R
XN
XN
XN
XN
D MI 0 R XP
D MI 1 R XP
D MI 2 R XP
D MI 3 R XP
B E 22
B F 21
B D 20
B E 18
0
1
2
3
49 . 9 _ 1 %_ 0 4
D
D
D
D
B H 25
D
D
D
D
MI 0 T X N
MI 1 T X N
MI 2 T X N
MI 3 T X N
D
D
D
D
MI 0 T X P
MI 1 T X P
MI 2 T X P
MI 3 T X P
FD
FD
FD
FD
FD
FD
FD
FD
XN
XN
XN
XN
XN
XN
XN
XN
0
1
2
3
4
5
6
7
I_ RX P 0
I_ RX P 1
I_ RX P 2
I_ RX P 3
I_ RX P 4
I_ RX P 5
I_ RX P 6
I_ RX P 7
BA1 8
B H1 7
B D1 6
BJ 1 6
BA1 6
BE1 4
BA1 4
B C1 2
BB1 8
BF1 7
B C1 6
B G1 6
AW 1 6
B D1 4
BB1 4
B D1 2
F DI
F DI
F DI
F DI
F DI
F DI
F DI
F DI
_T X N 0
_T X N 1
_T X N 2
_T X N 3
_T X N 4
_T X N 5
_T X N 6
_T X N 7
3
3
3
3
3
3
3
3
F DI
F DI
F DI
F DI
F DI
F DI
F DI
F DI
_T X P 0
_T X P 1
_T X P 2
_T X P 3
_T X P 4
_T X P 5
_T X P 6
_T X P 7
3
3
3
3
3
3
3
3
BJ 1 4
F D I _I N T 3
F D I _I N T
D MI _ Z C OM P
FDI
MI _ R X N
MI _ R X N
MI _ R X N
MI _ R X N
DMI
D
D
D
D
BF1 3
F D I _F S Y N C 0 3
F DI_ F S Y NC 0
B H1 3
F D I _F S Y N C 1 3
F DI_ F S Y NC 1
B F 25
D MI _ I R C O MP
BJ 1 2
F D I _L S Y N C 0 3
F D I _ LS Y N C 0
B G1 4
R1 1 1
1 0 K _ 04
S Y S _ RE S E T #
T6
S Y S _ P W R OK
M6
S B _ P W RO K
S Y S _ RE S E T #
W AKE#
S Y S _ P W R OK
C L K R U N # / GP I O3 2
B 17
P W RO K
P M_ MP W R O K
R2 9 7
A U X P P W R OK _ R
10 K _ 0 4
K5
M E P W R OK
A 10
L A N _ RS T #
EXT-LAN
D9
4 P M_ D R A M _P W R G D
28
R S MR S T#
D R A M P W R OK
R3 0 0
R S MR S T #
S U S _P W R _ A C K
28 S U S _ P W R _ A C K
28
C 16
R S M R S T#
10 K _ 0 4
M1
S U S _ P W R _A C K / G P I O3 0
P5
P W R _B T N #
P W R _B T N #
A C _P R E S E N T
1 8, 2 8 A C _P R E S E N T
P M_ B A T L OW #
P W RB T N #
P7
System Power Management
3. 3 V S
S W I#
SW I#
J 12
P C I E _W A K E #
Y1
P M_ C LK R U N #
P C I E _W A K E # 2 3, 2 5
P M _C L K R U N # 2 4
3 .3 V
P8
S U S _S T A T # / GP I O6 1
S 4 _S TA T E #
P CIE _ W A K E #
R1 2 1
1 K _ 1% _ 0 4
P M_ S L P _ L A N #
R1 2 7
*1 0 K _ 0 4
S W I#
R1 3 0
1 0K _0 4
S US _ P W R _ A CK
R2 8 4
1 0K _0 4
P W R_ B T N #
R1 0 9
*1 0 K _ 0 4
A C_ P R E S E NT
R1 1 5
1 0K _0 4
P M_ B A T L OW #
R2 9 6
8 . 2 K _0 4
P M _C L K R U N #
R2 7 1
8 . 2 K _0 4
A L L _ S Y S _ P W R GD
R1 4 3
1 0K _0 4
S 4 _ S TA TE # 2 4
F3
S U S C L K / GP I O6 2
E4
S LP _ S 5 # / GP I O6 3
H7
SL P_ S4 #
S U S C # 2 8 , 33
P1 2
S US B #
S US B #
SL P_ S3 #
S L P _M #
2 3 , 28 , 3 1
3 .3 VS
K8
N2
A C P R E S E N T / G P I O 31
T P2 3
A6
BJ 1 0
B A TL O W # / GP I O 7 2
28
Sheet 16 of 42
IBEXPEAK - M 3/9
F D I _L S Y N C 1 3
F D I _ LS Y N C 1
H_ P M _ S Y N C 4
PM SY N CH
F 14
F6
R I#
S L P _ LA N #
P M_ S L P _ L A N #
2 8, 36 V C OR E _ ON
I be x P e a k- M_ R e v 0 _ 9
R1 3 9
*1 0 m il _ s ho rt _ 0 4
P M_ M P W R O K
3 .3 V
3 .3 V
3 3 1. 8 V S _ P W R GD
3
6
1 . 1 V S _ V T T_ E N
U 8C
7 4 LV C 0 8 P W
9
12
U8 D
7 4 LV C 0 8P W
4 ,3 6 DE L A Y _ P W RG D
8
11
13
A L L_ S Y S _ P W R G D
2
A L L _ S Y S _ P W R GD
7
7
R1 4 4
*1 0 m il _ s ho rt _ 0 4
S B _P W R O K
R1 4 2
*1 0 m il _ s ho rt _ 0 4
S Y S _ P W R OK
10
5
R1 4 5
7
1
4 , 3 3, 3 4 1 . 1 V S _ V T T_ P W R GD
7
SU SB#
14
14
3 3 D D R 1 . 5 V _ P W R GD
4
U8 B
74 L V C 08 P W
14
3 . 3V
U 8A
7 4 L V C0 8 P W
14
3. 3 V
10 K _ 0 4
1 2 , 28
34 1 . 1 V S _ V T T _E N
R1 4 1
2K _1 % _ 04
H _ V T T P W R GD
4
C 4 70
ON
R 13 8
1 u _ 6. 3 V _ X 5 R _ 0 4
1 K _ 1% _ 0 4
3 . 3V S
2 , 10 , 1 1 , 1 2, 1 3 , 1 4 , 15 , 1 7 , 1 8, 1 9 , 2 0, 21 , 2 3 , 2 4, 2 5 , 2 6, 27 , 2 8 , 29 , 3 0 , 3 1, 3 5 , 3 6
3 . 3V
3 , 4, 1 2 , 1 4 , 15 , 1 8 , 1 9, 2 0 , 2 1 , 23 , 2 4 , 2 5, 2 9 , 3 0 , 31 , 3 3 , 3 4, 3 5
1 . 1V S _V TT 2 , 4 , 6 , 7, 14 , 1 5 , 19 , 2 0 , 2 1, 3 4 , 3 5 , 36
IBEXPEAK - M 3/9 B - 17
B.Schematic Diagrams
1 .1 VS _ VT T
R2 6 1
3
3
3
3
Schematic Diagrams
IBEXPEAK - M 4/9
IBEXPEAK - M (LVDS,DDI)
U20D
BJ46
SDVO_TVCLKI NN BG46
SDVO_TVCLKINP
BJ48
SDVO_STALLN BG48
SDVO_STALLP
BF45
SDVO_INTN BH45
SDVO_INTP
L_BKLTEN
L_VDD_EN
Y48
L_BKLTCTL
R83
2. 37K_1%_04
LVDS_I BG
AP39
AP41
AT43
AT42
12 LVDS-LCLKN
12 LVDS-LCLKP
Sheet 17 of 42
IBEXPEAK - M 4/9
AV53
AV51
12 LVDS-L0N
12 LVDS-L1N
12 LVDS-L2N
BB47
BA52
AY48
AV47
12 LVDS-L0P
12 LVDS-L1P
12 LVDS-L2P
BB48
BA50
AY49
AV48
AP48
AP47
AY53
AT49
AU52
AT53
EMI
13
DAC_BLUE
13
DAC_GREEN
13
DAC_RED
R105
0_04
DAC_BLUE_R
*33p_50V_NPO_04
R99
0_04
DAC_GREEN_R
*33p_50V_NPO_04
R91
0_04
DAC_RED_R
C174
AY51
AT48
AU50
AT51
C170
C166
*33p_50V_NPO_04
NEAR PCH
R104
R98
R92
150_1%_04
150_1%_04
150_1%_04
DAC_BLUE_R
DAC_GREEN_R
DAC_RED_R
13 DAC_DDCACLK
13 DAC_DDCADATA
13
13
R88
1K_1%_04
DAC_HSYNC
DAC_VSYNC
DAC_IREF_R
AA52
AB53
AD53
V51
V53
Y53
Y51
AD48
AB51
L_DDC_CLK
L_DDC_DATA
L_CTRL_CLK
L_CTRL_DATA
T51
SDVO_CT
RLCLK T53
SDVO_CTRLDATA
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
BG44
DDPB_AUXN BJ44
DDPB_AUXP AU38
DDPB_HPD
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_I REF
CRT_IRTN
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38
RN5
2.2K_4P2R_04
3
2
4
1
3.3VS
Y49
DDPC_CT
RLCLK AB49
DDPC_CTRLDATA
BE44
DDPC_AUXN BD44
DDPC_AUXP AV40
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36
HDM
I_CTRLCLK 13
HDM
I_CTRLDATA 13
PCH_DDPC_HPD
HDM
IB_D2BN_C
HDM
IB_D2BP_C
HDM
IB_D1BN_C
HDM
IB_D1BP_C
HDM
IB_D0BN_C
HDM
IB_D0BP_C
HDM
IB_CLKBN_C
HDM
IB_CLKBP_C
C125
C126
C111
C112
C113
C114
C115
C116
U50
DDPD_CT
RLCLK U52
DDPD_CTRLDATA
HDMIB_D2BN 13
HDMIB_D2BP 13
HDMIB_D1BN 13
HDMIB_D1BP 13
HDMIB_D0BN 13
HDMIB_D0BP 13
HDMIB_CLKBN 13
HDMIB_CLKBP 13
5VS
BC46
DDPD_AUXN BD46
DDPD_AUXP AT
38
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
0.1u_10V_X7R_04
0.1u_10V_X7R_04
0.1u_10V_X7R_04
0.1u_10V_X7R_04
0.1u_10V_X7R_04
0.1u_10V_X7R_04
0.1u_10V_X7R_04
0.1u_10V_X7R_04
PCH_DDPC_HPD
S
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36
Q7
M
TN7002ZHS3
D
PORTC_HPD 13
R34
100K_1%_04
IbexPeak-M_Rev0_9
Connect to GND
PCH_DDPC_HPD R33
*0_04
PORTC_HPD
No Connect
External Graphics (PCH Integrated Graphics Disable)
External Graphics (PCH Integrated Graphics Disable)
2,10,11,12,13,14, 15,16,18,19,20,21,23,24,25,26,27, 28,29,30,31,35,36 3.3VS
2,13,20,21, 26,27,30,31,35,36 5VS
B - 18 IBEXPEAK - M 4/9
SDVO
AB46
V48
Dis play Port B
L_CTRL_CLK
L_CTRL_DATA
Dis play Port C
*10K_04
*10K_04
Digital Display Interface
R96
R97
LVDS
B.Schematic Diagrams
AB48
Y45
CRT
12 P_DDC_CLK
12 P_DDC_DATA
3.3VS
Dis play Port D
T48
T47
G
12 BLON
12 NB_ENAVDD
Schematic Diagrams
IBEXPEAK - M 5/9
IBEXPEAK - M (PCI,USB,NVRAM)
U2 0E
0
1
0
1
LP C
Re ser ved
PC I
SP I
R 117
*1K_ 1%_0 4
PC I_ GNT#0
R 119
*1K_ 1%_0 4
PC I_ GNT#1
( NAN D)
Understand the RED FONT define
*1 K_ 1%_0PC
4 I_G NT# 3
R12 2
J50
G42
H47
G34
3. 3VS
4
3
R N2 3
8 .2 K_8P4 R_0 4 2
1
4
3
R N1 2
8 .2 K_8P4 R_0 4 2
1
4
3
R N2 2
8 .2 K_8P4 R_0 4 2
1
5
6
7
8
5
6
7
8
5
6
7
8
I NT_ PIRQ E#
PCI _I RDY #
IN T_PI RQD #
PC I_FR AME#
PCI _PERR #
PCI_ LOC K#
PC I_D EVSEL #
PCI _SERR #
PCI_ REQ# 1
PCI _TRDY #
IN T_PI RQH #
PCI_ REQ# 0
4
3
R N2 4
8 .2 K_8P4 R_0 4 2
1
4
3
R N2 0
8 .2 K_8P4 R_0 4 2
1
5
IN T_PI RQG #
6
IN T_PI RQC #
7
I NT_ PIRQ A#
8
PCI _STO P#
5
I NT_ PIRQ B#
6
I NT_ PIRQ F#
7
PCI_ REQ# 3
8 DGPU _PWM_SELECT#
IN T_ PI RQ A#
IN T_ PI RQ B#
IN T_ PI RQ C#
IN T_ PI RQ D#
G38
H51
B37
A44
PCI _REQ #0
PCI _REQ #1
F51
A46
B45
M53
PCI _REQ #3
B ACK LI GHT C ONT RO L F ROM I GPU /D GPU
PCI _GN T# 0
PCI _GN T# 1
D GPU_ PW M_SEL EC T#
PCI _GN T# 3
F48
K45
F36
H53
IN T_ PI RQ E#
IN T_ PI RQ F#
IN T_ PI RQ G#
IN T_ PI RQ H#
B41
K53
A36
A48
PCI _SERR#
PCI _PERR#
E44
E50
PCI _IR DY #
PCI _DEVSEL#
PCI _FRAME#
A42
H44
F46
C46
PCI _LO CK#
D49
PCI _STO P#
PCI _TR DY#
D41
C48
NV_D QS0
NV_D QS1
NVRAM
0
0
1
1
Boo t B IOS Lo cat ion
NV_D Q0
NV_D Q1
NV_D Q2
NV_D Q3
NV_D Q4
NV_D Q5
NV_D Q6
NV_D Q7
NV_D Q8
NV_D Q9
NV_D Q1 0 /
NV_D Q1 1 /
NV_D Q1 2 /
NV_D Q1 3 /
NV_D Q1 4 /
NV_D Q1 5 /
/ NV_I O0
/ NV_I O1
/ NV_I O2
/ NV_I O3
/ NV_I O4
/ NV_I O5
/ NV_I O6
/ NV_I O7
/ NV_I O8
/ NV_I O9
N V_ IO 10
N V_ IO 11
N V_ IO 12
N V_ IO 13
N V_ IO 14
N V_ IO 15
NV_ALE
N V_ CLE
C/BE0#
C/BE1#
C/BE2#
C/BE3#
N V_ RB#
N V_WR #0_ RE#
N V_WR #1_ RE#
N V_ WE#_ CK0
N V_ WE#_ CK1
PI RQ A#
PI RQ B#
PI RQ C#
PI RQ D#
REQ0#
REQ1# / GPI O5 0
REQ2# / GPI O5 2
REQ3# / GPI O5 4
GNT0#
GNT1# / GPIO 51
GNT2# / GPIO 53
GNT3# / GPIO 55
PI RQ E# / GPI O2
PI RQ F# / GPI O3
PI RQ G# / GPIO 4
PI RQ H# / GPIO 5
PC IR ST#
SER R#
PER R#
IRD Y#
PAR
DEVSEL #
FR AME#
USBP0N
U SBP0P
USBP1N
U SBP1P
USBP2N
U SBP2P
USBP3N
U SBP3P
USBP4N
U SBP4P
USBP5N
U SBP5P
USBP6N
U SBP6P
USBP7N
U SBP7P
USBP8N
U SBP8P
USBP9N
U SBP9P
U SBP1 0N
USBP10P
U SBP1 1N
USBP11P
U SBP1 2N
USBP12P
U SBP1 3N
USBP13P
PL OCK#
28
BD3
AY6
USBRBIAS#
STOP#
TRD Y#
NV_R COMP
R2 65
3 2. 4_1 %_04
AV7
Sheet 18 of 42
IBEXPEAK - M 5/9
AY8
AY5
AV11
BF5
H1 8
J1 8
A18
C1 8
N2 0
P20
J2 0
L2 0
F20
G2 0
A20
C2 0
M2 2
N2 2
B21
D2 1
H2 2
J2 2
E22
F22
A22
C2 2
G2 4
H2 4
L2 4
M2 4
A24
C2 4
B25
USB_BIAS
USB_PN0
USB_PP0
USB_PN1
USB_PP1
USB_PN2
USB_PP2
USB_PN3
USB_PP3
USB_PN4
USB_PP4
USB_PN5
USB_PP5
30
30
30
30
23
23
23
23
30
30
24
24
USB PORT0
USB_PN9
USB_PP9
24
24
3G
USB_PN1 1 29
USB_PP11 2 9
BT
R3 01
USB PORT1
WLAN
NEW CARD
USB PORT2
CCD
2 1_ 1%_0 4
D2 5
USBRBI AS
M7
PME#
24 PL T_ RST#
AV9
BG8
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6
AU2
K6
P IN PLT _RST # t o B uffe r
AY9
BD1
AP15
BD8
NV_RC OMP
USB
P CI _GN T#1
NV_C E#0
NV_C E#1
NV_C E#2
NV_C E#3
PCI
PCI _GN T#0
AD 0
AD 1
AD 2
AD 3
AD 4
AD 5
AD 6
AD 7
AD 8
AD 9
AD 10
AD 11
AD 12
AD 13
AD 14
AD 15
AD 16
AD 17
AD 18
AD 19
AD 20
AD 21
AD 22
AD 23
AD 24
AD 25
AD 26
AD 27
AD 28
AD 29
AD 30
AD 31
PME#
PLT_RST#
15
28
CLK_ PC I_ FB
PCLK_KBC
R 124
R 120
22 _1 %_ 04CL K_PCI _FB_R
22 _1 %_ 04CL K_PCI _KBC_R
24
PCLK_TPM
R 133
*22 _1%_ 04 PCLK_ TPM_ PC H
D5
PL TR ST#
N52
P53
P46
P51
P48
CLKOU T_ PC I0
CLKOU T_ PC I1
CLKOU T_ PC I2
CLKOU T_ PC I3
CLKOU T_ PC I4
OC 0# / GPIO 59
OC 1# / GPIO 40
OC 2# / GPIO 41
OC 3# / GPIO 42
OC 4# / GPIO 43
O C5# / GPI O9
OC 6# / GPIO 10
OC 7# / GPIO 14
N1 6
J1 6
F16
L1 6
E14
G1 6
F12
T1 5
USB_OC #2 3
USB_OC #4 5
USB_OC #6 7
USB_OC #8 9
USB_OC #1 011
USB_OC #1 213
G PIO1 4
USB_ OC# 01 3 0
USB_ OC# 23 2 3
3. 3V
USB_ OC# 89 1 5
R1 25
R1 10
R1 13
1 0K_ 04
1 0K_ 04
*0 _0 4
AC_ PRESENT 1 6,2 8
I bex Peak -M_Re v 0_9
3.3 V
3. 3VS
*0. 1u_ 10V_ X7R _0 4
5
C18 5
U6
MC 74VH C1G 08D FT1G
1
4
15 PCH _U PEK_ INI T#
BU F_ PLT_ RST#
2
3
PLT_R ST#
USB_ OC# 67
USB_ OC# 101 1
USB_ OC# 45
PC H_ UPEK_ IN IT#
5
6
7
8
4
3
2
1
RN1 4
10 K_ 8P4R _0 4
4, 23, 25 ,28
R11 8
10 0K_1 %_ 04
2,1 0, 11, 12 ,1 3,1 4, 15, 16 ,17 ,1 9,2 0, 21, 23 ,24 ,2 5,2 6, 27, 28 ,29 ,3 0,3 1, 35, 36
3, 4, 12 ,14 ,1 5,1 6, 19, 20 ,21 ,2 3,2 4, 25, 29 ,30 ,3 1,3 3, 34, 35
3.3 VS
3.3 V
IBEXPEAK - M 5/9 B - 19
B.Schematic Diagrams
H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36
B o o t B I O S S t r ap
Schematic Diagrams
IBEXPEAK - M 6/9
IBEXPEAK - M (GPIO,VSS_NCTF,RSVD)
U 20F
E D P _ C A R D _D E T #
0213
R2 7 2
3 .3 V S
Y 3
B MB U S Y # / G P I O 0
S_GPIO CHANGE TO EDP_CARD_DET#
1 K _ 1 % _ 04
ED P_ C ARD _ D E T #
28
S M I#
28
S C I#
S MI #
C 38
D G P U _ H P D _ I N TR #
D 37
C LK OU T _ P C I E 6 N
C L K O UT _ P C IE 6 P
* 0 _ 04
27
S CI #
J32
P CH _ M UT E #
F1 0
R1 2 6
G PIO 8
* 10 K _0 4
* 1 0 K_ 0 4
S A T A 4 GP / G P IO 1 6
R 102
GP I O1 7
* 0 _ 04
B IO S _ RE C
AM 1
T A C H 0 / G P I O 17
S C L O C K / G P I O 22
*1 0 K _ 0 4
12
C R B _S V _ D E T
S B _B L ON
AB1 2
S P I_ C S # 2
V1 3
G PIO 2 7
G PIO 2 8
CRB/SV DETECT
R 280
S T P_ PC I#
NO STUFF [DETECT]
1 0 0 K_ 1 % _ 0 4
GP I O3 5
R 2 79
* 1 K _ 1 % _ 04
R 100
V3
P3
R2 6 9
3 C R I T_ T E M P _ R E P #
3. 3V
R1 2 8
BD 1 0
T H R M T R IP #
P C H _ GP I O5 7
P C H _ MU T E #
S P I_ C S #2
D R A MR S T _ C TR L
3 .3 V S
* 1 0 K_ 0 4
G P IO 1 7
SC I#
SM I#
MF G_ M OD E
ST P_ PC I#
DG
CR
DG
GP
P U _ HP D_ IN T R#
IT _ T E M P _ RE P # _ R
P U _ P R S NT #
I O3 5
1 .1 V S _ V T T
R 27 7
1 0 K_ 0 4
K B C_ R S T # 2 8
H _ CP U P W RG D
R 25 9
56_04
H_ P E CI
TP1
S A T A 3 GP / G P IO 3 7
TP2
S LO A D / G P I O 3 8
TP3
AW 2 2
R 255
56 _ 0 4
4
1. 1V S _ V T T
Calpella Design Guide.
NOTE: CRB uses a 54.9 O ? %
series resistor and 56-O pull-up.
BB2 2
AY 4 5
S D A T A OU T 0 / G P I O 39
TP4
P C I E C L K R Q 6# / GP I O4 5
TP5
P C I E C L K R Q 7# / GP I O4 6
TP6
S D A T A OU T 1 / G P I O 48
TP7
S A T A 5 GP / G P IO 4 9
TP8
G PIO 5 7
TP9
AY 4 6
F1
AV4 3
A B6
AV4 5
A A4
AF1 3
F8
M1 8
N1 8
TP 10
A4
A4 9
A5
A5 0
A5 2
A5 3
B2
B4
B5 2
B5 3
B E1
BE5 3
B F1
BF5 3
BH 1
BH 2
BH 5 2
BH 5 3
BJ 1
BJ 2
BJ 4
BJ 4 9
BJ 5
BJ 5 0
BJ 5 2
BJ 5 3
D 1
D 2
D 53
E1
E5 3
AJ 2 4
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
SS_ N
CT F _ 1
CT F _ 2
CT F _ 3
CT F _ 4
CT F _ 5
CT F _ 6
CT F _ 7
CT F _ 8
CT F _ 9
CT F _ 1 0
CT F _ 1 1
CT F _ 1 2
CT F _ 1 3
CT F _ 1 4
CT F _ 1 5
CT F _ 1 6
CT F _ 1 7
CT F _ 1 8
CT F _ 1 9
CT F _ 2 0
CT F _ 2 1
CT F _ 2 2
CT F _ 2 3
CT F _ 2 4
CT F _ 2 5
CT F _ 2 6
CT F _ 2 7
CT F _ 2 8
CT F _ 2 9
CT F _ 3 0
CT F _ 3 1
TP 11
AK4 1
TP 12
AK4 2
TP 13
M3 2
TP 14
N3 2
TP 15
M3 0
TP 16
N3 0
TP 17
H1 2
TP 18
AA2 3
TP 19
AB4 5
N C _1
AB3 8
N C _2
AB4 2
N C _3
AB4 1
N C _4
T39
N C _5
P6
I N I T 3 _3 V #
C1 0
TP 24
I be x P e a k -M _ R e v 0 _ 9
R1 0 3
*1 0 K _ 0 4
DG P U _ P R S NT #
LOW: DGPU PRESENT
B - 20 IBEXPEAK - M 6/9
4 ,2 8
3 .3 VS
Connected to PCH (THRMTRIP#)
Routing guidelines available in
BA2 2
S A T A 2 GP / G P IO 3 6
H OS T_ A L E R T # 1
R N9
1 0 K _ 8 P 4 R _0 4
1
8
2
7
3
6
4
5
R N4
1 0 K _ 8 P 4 R _0 4
1
8
2
7
3
6
4
5
1 0 K_ 0 4
C R I T _ T E MP _R E P #_ R
*1 0 K _ 0 4
*1 0 m i l _s h o rt _ 0 4
H _ TH R MT R I P # 4
RSVD
1 K_ 0 4
*0 _ 0 4
R 260
P R OC P W R G D
H 3
SV_ SET _ U P
R 256
BE1 0
AB1 3
CR B _ SV_ D E T
D R A M R S T_ C T R L
4 , 9 D R A MR S T _ C TR L
R N2 1
1 0 K _ 8 P 4 R _0 4
1
8
2
7
3
6
4
5
R C IN #
A B7
MF G _ M OD E
* 0 _ 04
R 1 14
T1
V6
S V _S E T _ U P
1 0 K_ 0 4
R1 0 7
M 11
H _ P E C I_ R
P E CI
S A T A C LK R E Q# / G P I O 3 5
DG P U _ P RS NT #
R9 5
BG 1 0
S TP _ P C I # / GP I O3 4
3 .3 V S
3 .3 V S
28
4
B C LK _ C P U _ P 4
C L K O UT _ B C L K 0 _ P / C L K O UT _ P C IE 8 P
GPIO
Y 7
SB_ BL O N
B C LK _ C P U _ N
C L K O U T _ B C L K 0 _ N / C LK OU T _ P C I E 8 N
F3 8
CPU
R2 8 1
G A2 0
AM 3
M E M _ L E D / GP I O2 4
3 .3 V S
3. 3V S
T7
A A2
NCTF
B.Schematic Diagrams
R 2 70
H 10
Sheet 19 of 42
IBEXPEAK - M 6/9
1 0 K_ 0 4
U2
A 2 0G A T E
G PIO 1 5
3 .3 V S
BIOS RECOVERY
DISABLE----NO STUFF (DEFAULT)
ENABLE-----STUFF
AF4 8
AF4 7
R 27 6
K9
BIO S_ R EC
1 0 K_ 0 4
C LK OU T _ P C I E 7 N
C L K O UT _ P C IE 7 P
L A N _ P H Y _ P W R _C T R L / GP I O1 2
H O S T _ A L E R T #1
R1 0 1
3 .3 V S
T A C H 3 / G PIO 7
P C H _ MU T E #
3. 3V
MISC
T A C H 2 / G PIO 6
R 273
AH 4 5
AH 4 6
T A C H 1 / G PIO 1
2 , 4 , 6 ,7 ,1 4 ,1 5 ,1 6 ,2 0 ,2 1, 34 , 3 5 , 3 6 1 .1 V S _V T T
3 , 4 ,1 2 , 1 4 , 1 5 , 1 6 , 1 8, 20 ,2 1 ,2 3 ,2 4 ,2 5 ,2 9 ,3 0 ,3 1, 33 , 3 4 , 3 5 3 .3 V
2 , 1 0 , 1 1 , 1 2 , 1 3, 14 ,1 5 ,1 6 , 1 7 , 1 8 , 2 0 , 2 1, 23 , 2 4 ,2 5 ,2 6 ,2 7 ,2 8 ,2 9 ,3 0, 31 , 3 5 , 3 6 3 .3 V S
Schematic Diagrams
IBEXPEAK - M 7/9
IBEXPEAK - M (POWER)
3 .3 V S
R 90
H C B 1 6 0 8K F -1 2 1 T2 5
.
1 .1 V S _ V T T
L12
H C B 1 6 0 8 K F - 12 1 T 2 5
AE5 2
C 3 93
AF5 3
0 . 0 1 u _ 50 V _X 7 R _ 04
C 392
5
1
OU T
C1 3 2
C 145
1 0 u _ 6 . 3 V _ X 5R _ 0 6
C 13 3
C1 4 6
R8 0
*2 3 . 7 K _ 1 % _ 0 4
4
IN
C 15 0
3
V S S A _ DA C [1 ]
AF5 1
V S S A _ DA C [2 ]
3 .3 V S _ V C CA _ L V D
A H3 8
R 86
V CC A L V D S
A H3 9
3 .3 VS
S HD N #
2
SET
R8 1
GN D
* A P L 5 6 0 3 -33 B
*1 0 K _ 1 % _ 0 4
* 1u _ 6 . 3 V _ X 5 R _ 0 4
V C CA DA C [2 ]
5 VS
U 5
.
AE5 0
V C CA DA C [1 ]
2 2 u_ 6 . 3 V _ X 5R _ 0 8
E[1 ]
E[2 ]
E[3 ]
E[4 ]
E[5 ]
E[6 ]
E[7 ]
E[8 ]
E[9 ]
E[1 0 ]
E[1 1 ]
E[1 2 ]
E[1 3 ]
E[1 4 ]
E[1 5 ]
0 . 1 u _1 6 V _ Y 5V _ 04
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
22 u _ 6 . 3 V _ X 5 R _ 08
1u _ 6 . 3 V _ X 5 R _0 4
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CRT
C 1 51
1 0 u _6 . 3 V _X 5 R _ 0 6
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
VCC CORE
C 17 6
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
V C C A _ D A C _ 3. 3V S
POWER
U 20G
AB2 4
AB2 6
AB2 8
AD 2 6
AD 2 8
AF2 6
AF2 8
AF3 0
AF3 1
AH 2 6
AH 2 8
AH 3 0
AH 3 1
AJ 3 0
AJ 3 1
0 .1 u _ 1 6 V _ Y 5 V _ 0 4
1 .1 V S_ V T T
APL5603-33B 6-02-56033-4C0
G9091-330T11UF 6-02-90913-4C0
*1 5 m i _l s h o rt _ 0 6
C1 5 6
V SSA_ L VD S
AK2 4
LVDS
1. 1V S _ V C C A P L L_ E XP
V C C I O[ 24 ]
L29
* B K P 1 0 0 5 H S 12 1 _ 0 4
BJ 2 4
VC C APL L EXP
.
C 1 61
C1 3 6
C 141
1 0 u_ 6 . 3 V _ X 5 R _ 06
1 u _ 6 .3 V _ X 5 R_ 0 4
1 u _ 6 . 3 V _ X 5R _ 0 4
1 u_ 6 . 3 V _ X 5 R _ 04
1 u _ 6 .3 V _ X5 R_ 0 4
AN 3 0
AN 3 1
1 .5 V S _ 1 .8 V S
3 .3 VS
25 ]
26 ]
27 ]
28 ]
29 ]
30 ]
31 ]
32 ]
33 ]
34 ]
35 ]
36 ]
37 ]
38 ]
39 ]
40 ]
41 ]
42 ]
43 ]
44 ]
45 ]
46 ]
47 ]
48 ]
49 ]
50 ]
51 ]
52 ]
53 ]
C1 3 4
1 0 u _ 6 .3 V _ X5 R_ 0 6
10 u _ 6 . 3 V _ X 5 R _ 0 6
A D3 5
3 .3 V S
VC C3 _ 3 [4 ]
C1 5 9
1 . 5 V S _ 1. 8V S
1 .1 VS _ V T T
AT1 6
V C C DM I[1 ]
A U1 6
V C C DM I[2 ]
C1 2 7
V C C I O[ 54 ]
V C C I O[ 55 ]
V C C V R M[ 1 ]
BJ 1 8
V C C I O[ 1]
*1 0 u _ 6. 3V _ X5 R _ 0 6
I b e x P e a k -M _ R e v 0 _ 9
FDI
VC C F D IPL L
1 u _ 6 .3 V _ X 5 R_ 0 4
VC
VC
VC
VC
VC
VC
VC
VC
VC
C
C
C
C
C
C
C
C
C
PN
PN
PN
PN
PN
PN
PN
PN
PN
A ND
A ND
A ND
A ND
A ND
A ND
A ND
A ND
A ND
[1 ]
[2 ]
[3 ]
[4 ]
[5 ]
[6 ]
[7 ]
[8 ]
[9 ]
A M1 6
AK1 6
AK2 0
AK1 9
AK1 5
AK1 3
A M1 2
A M1 3
A M1 5
V _ NV RA M _ V C CQ
1 .8 V S
R7 5
C1 5 2
R7 6
* 15 m i l _ sh o rt _ 0 6
0. 1u _ 1 6 V _ Y 5V _ 04
3. 3V S
VC
VC
VC
VC
C
C
C
C
ME 3 _ 3 [ 1 ]
ME 3 _ 3 [ 2 ]
ME 3 _ 3 [ 3 ]
ME 3 _ 3 [ 4 ]
A M8
A M9
AP1 1
AP9
3 .3 V S
*0 _ 0 4
3 .3 V
V C CM E3 .3 V
R 79
* 1 5 m li _ s h o rt _ 06
R 82
* 0_ 0 4
C1 3 8
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
1 .1 V S _ V C CD P L L _ F D I
R2 5 7
*1 5 m i l _ sh o rt _ 0 6
3 , 4 , 1 2 , 1 4 , 1 5 , 1 6, 18 , 1 9 , 2 1 , 2 3 , 2 4 , 2 5 , 2 9, 30 , 3 1 , 3 3 , 3 4 , 3 5
2 3 ,3 1 ,3 6
2 , 1 3 , 1 7 , 2 1 , 2 6, 27 , 3 0 , 3 1 , 3 5 , 3 6
21
7 ,3 3
2 , 1 0 , 1 1 , 1 2, 13 , 1 4 , 1 5 , 1 6 , 1 7 , 1 8 , 1 9, 21 , 2 3 , 2 4 , 2 5 , 2 6 , 2 7 , 2 8, 29 , 3 0 , 3 1 , 3 5 , 3 6
2 , 4 , 6 , 7 , 1 4 , 1 5 , 1 6, 19 , 2 1 , 3 4 , 3 5 , 3 6
1 .5 VS
Sheet 20 of 42
IBEXPEAK - M 7/9
AT2 4
AM 2 3
1 . 1 V S _ V TT
C 135
0 . 0 1u _ 5 0 V _ X 7 R _ 0 4
V C C V RM [2 ]
AT2 2
C3 7 0
C1 3 9
0. 01 u _ 5 0 V _ X 7 R _ 0 4
0. 1u _ 1 6 V _ Y 5V _ 04
V C C 3 _3 [ 1 ]
1. 1V S _ V C C A P L L_ F D I
L 28
* H C B 1 0 0 5 K F -1 2 1 T 2 0
C1 4 0
VC C3 _ 3 [3 ]
HVCMOS
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
I O[
AN 3 5
1 .1 V S _ V T T
AB3 4
DMI
C 160
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
NAND / SPI
C3 7 5
.
AB3 5
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
PCI E*
1 .1 VS _ VT T
AN 2 0
AN 2 2
AN 2 3
AN 2 4
AN 2 6
AN 2 8
BJ 2 6
BJ 2 8
AT2 6
AT2 8
AU 2 6
AU 2 8
AV2 6
AV2 8
A W26
A W28
BA2 6
BA2 8
BB2 6
BB2 8
BC 2 6
BC 2 8
BD 2 6
BD 2 8
BE2 6
BE2 8
BG 2 6
BG 2 8
BH 2 7
1 .8 VS
L 11
H C B 1 6 0 8 K F -1 2 1 T 2 5
VC C3 _ 3 [2 ]
C3 7 2
*1 0 u _ 6 . 3 V _ X 5 R _ 0 6
1 . 8 V S _V C C T X _ LV D
AP4 3
AP4 5
AT4 6
AT4 5
1 .8 VS
3 .3 V
1 .5 VS
5 VS
1 .5 VS_ 1 .8 VS
1 .8 VS
3 .3 VS
1 .1 VS_ VT T
1 . 5 V S _ 1. 8 V S
R 2 58
R 2 54
*1 5 m li _ s h o rt _ 0 6
* 0 _0 4
IBEXPEAK - M 7/9 B - 21
B.Schematic Diagrams
1 0 u_ 6 . 3 V _ X 5 R _0 6
V C CT X _ L V D S [1 ]
V C CT X _ L V D S [2 ]
V C CT X _ L V D S [3 ]
V C CT X _ L V D S [4 ]
Schematic Diagrams
IBEXPEAK - M 8/9
IBEXPEAK - M (POWER)
1 . 1 V S _ V C C A _C LK
L3 2
*H C B 1 0 05 K F -1 2 1T 2 0
U2 0 J
52mA
1 . 1 V S _ V TT
POWER
V CC A CL K [1 ]
C3 8 4
*1 0 u _6 . 3 V _ X5 R _0 6
*0 . 1 u_ 1 6 V _Y 5 V _0 4
1 .1 V S _ V T T
AP5 1
VC
VC
VC
VC
AP5 3
C3 8 3
V CC A CL K [2 ]
CIO
CIO
CIO
CIO
[5 ]
[6 ]
[7 ]
[8 ]
AF2 3
V C C LA N [ 1 ]
320mA
AF2 4
1 . 1V S _V T T
V C C LA N [ 2 ]
C1 4 3
T P _ P CH _ V CC DS W
Y2 0
DCP S US B Y P
1 u_ 6 . 3 V _X 5 R _ 0 4
C1 7 2
A D3 9
1849mA
A D4 1
C3 7 3
C1 4 8
AF4 3
2 2u _ 6 . 3V _ X 5 R _ 0 8
1u _ 6 . 3V _ X 5 R _ 0 4
AF4 1
V C C ME [ 2 ]
V C C ME [ 3 ]
V C C ME [ 4 ]
V C C ME [ 5 ]
AF4 2
V C C ME [ 6 ]
V3 9
C3 7 4
C1 4 2
V4 1
2 2u _ 6 . 3V _ X 5 R _ 0 8
1u _ 6 . 3V _ X 5 R _ 0 4
V4 2
V C C ME [ 8 ]
V C C ME [ 9 ]
Y3 9
V C C ME [ 1 0 ]
Y4 1
V C C ME [ 1 1 ]
Y4 2
1 .1 VS_ VT T
C1 7 7
V C C ME [ 1 2 ]
0 . 1 u _1 6 V _ Y 5 V _ 04
1. 1 V S _ V C C A _ A _ D P L
L3 1
H C B 10 0 5 K F -1 21 T 2 0
V9
V CC RT CE X T
DCP RT C
1 . 5 V S _ 1 . 8V S
C 3 86
C 38 1
2 2 u _6 . 3 V _ X5 R _0 8
1 u _6 . 3 V _ X5 R _0 4
R 2 62
68mA
* 0 _0 4
L3 0
H C B 10 0 5 K F -1 21 T 2 0
1. 1 V S _ V C C A _ B _ D P L
C 3 85
69mA
C 37 8
V C C V R M [ 3]
BB5 1
BB5 3
B D5 1
B D5 3
+ C 3 82
2 2 u _6 . 3 V _ X5 R _0 8
A U2 4
1 u _6 . 3 V _ X5 R _0 4
*2 20 u _ 4V _ V _ B
C 1 54
1u _ 6 . 3V _X 5 R _ 0 4
A H2 3
AJ 3 5
A H3 5
C 1 31
1u _ 6 . 3V _X 5 R _ 0 4
AF3 4
C 1 57
1u _ 6 . 3V _X 5 R _ 0 4
V CC A DP L L A [1 ]
V CC A DP L L A [2 ]
V CC A DP L L B [1 ]
V CC A DP L L B [2 ]
V C C I O[ 2 1 ]
V C C I O[ 2 2 ]
V C C I O[ 2 3 ]
1 u_ 6 . 3 V _X 5 R _ 0 4
V2 8
U2 8
U2 6
U2 4
P2 8
P2 6
N2 8
N2 6
M2 8
M2 6
L2 8
L2 6
J2 8
J2 6
H2 8
H2 6
G2 8
G2 6
F28
F26
E2 8
E2 6
C2 8
C2 6
B2 7
A2 8
A2 6
3 . 3V
142.6mA
C1 8 1
0 . 1u _ 1 6V _ Y 5V _ 0 4
3 .3 V _ V CC P US B
R1 0 6
*1 5 mi l _ sh o rt _ 06
C1 7 8
0 . 1u _ 1 6V _ Y 5V _ 0 4
1. 1 V S _ V T T
5 V _P C H _ V C C 5 R E F S U S
D 11
U2 3
C
V2 3
R 12 3
V C C I O[ 5 6 ]
S C D3 4 0
A
C1 7 5
C1 7 3
0 . 1 u _1 6 V _ Y 5 V _ 04
0 . 1 u _1 6 V _ Y 5 V _ 04
1. 05
3. 3
1. 05
1. 05
1. 05
1. 05
1. 05
0. 05 2
0. 06 9
0. 06 8
0. 06 9
0. 04 0
1. 43 2
0. 05 8
Vc cD MI
Vc cF DIP LL
Vc cI O
Vc cL AN
Vc cM E
Vc cM E3_ 3
Vc cp NAN D
1. 1
1. 05
1. 05
1. 05
1. 05
3. 3
1. 8
0. 06 1
0. 03 7
3. 06 2
0. 32 0
1. 84 9
0. 08 5
0. 15 6
Vc cR TC
Vc cS ATA PL L
Vc cS us3 _3
Vc cS usH DA
Vc cV RM
Vc cV RM
Vc cA LVD S
Vc cT X_L VD S
3. 3
1. 05
3. 3
3. 3
1. 8/ 1. 5
1. 05
3. 3
1. 8
2 (m A)
0. 03 1
0. 16 3
0. 00 6
0. 19 6
< 1 (mA )
< 1 (mA )
0. 05 9
C1 8 2
1 u_ 6 . 3 V _X 5 R _ 0 4
D 10
C
R1 1 6
K4 9
S C D3 4 0
A
1 0 0_ 1 % _0 4
3 .3 V S
5V S
C 1 83
J3 8
3. 3V S
V C C 3_ 3 [ 8 ]
L3 8
C1 6 9
M3 6
0 . 1u _ 1 6V _ Y 5V _ 0 4
V C C 3_ 3 [ 9 ]
V C C 3 _3 [ 1 0 ]
1 u _ 6. 3 V _ X 5R _ 04
N3 6
V C C 3 _3 [ 1 1 ]
P3 6
3. 3V S
V C C 3 _3 [ 1 2 ]
C1 8 0
U3 5
V C C 3 _3 [ 1 3 ]
0 . 1u _ 1 6V _ Y 5V _ 0 4
A D1 3
V C C 3 _3 [ 1 4 ]
V C C I O[ 3 ]
V1 2
Vc cA Clk
Vc cA DAC
Vc cA DPL LA
Vc cA DPL LB
Vc ca pll EX P
Vc cC ore
Vc cD MI
V CC 5 RE F
V 5 RE F
A H3 4
AF3 2
3. 3 V
S0 I ccm ax C urr en t (A )
< 1 (mA )
< 1 (mA )
< 1 (mA )
0. 35 7
5V
10 0 _ 1% _ 0 4
F24
V 5 RE F _ S US
V C C I O[ 2 ]
VCCIO 3062mA
1 .1 V S _ V T T
C1 4 7
V C C S U S 3 _3 [ 2 8 ]
PC I/G PI O/ LP C
Sheet 21 of 42
IBEXPEAK - M 8/9
Cl oc k and M is ce ll an eo us
V C C ME [ 7 ]
L3 3
*H C B 1 00 5 K F -1 2 1T 2 0
1. 1 V S _ V C C A P L L
V C C I O[ 4 ]
V C CS A T A P L L [1 ]
V C CS A T A P L L [2 ]
DCP S S T
AK3
AK1
1 . 1V S _ V T T
C3 8 8
C3 8 9
*1 u _ 6. 3 V _ X 5R _ 04
*1 0 u_ 6 . 3 V _X 5 R _ 0 6
V CC S S T
1 . 1V _ I N T_ V C C S U S
Y2 2
DCP S US
A H2 2
V C CIO [9 ]
20.4mA
P1 8
3 .3 V
A T 20
V C C S U S 3 _ 3[ 2 9 ]
V C C S U S 3 _ 3[ 3 1 ]
U2 2
V C C S U S 3 _ 3[ 3 2 ]
357mA
V1 5
V C C 3_ 3 [ 5 ]
C1 7 9
V1 6
0. 1 u _ 16 V _ Y 5 V _ 0 4
Y1 6
V C C 3_ 3 [ 6 ]
<1mA
1 . 1V S _ V T T
V C C 3_ 3 [ 7 ]
A H1 9
V C C I O[ 1 0 ]
A D2 0
V C C I O[ 1 1 ]
V CC
V CC
V CC
V CC
I O[ 1 3 ]
I O[ 1 4 ]
I O[ 1 5 ]
I O[ 1 6 ]
V C C I O[ 1 7 ]
V C C I O[ 1 8 ]
V C C I O[ 1 9 ]
V C C I O[ 2 0 ]
AT1 8
1u _ 6 . 3V _ X 5 R _ 0 4
0 . 1u _ 1 6V _ Y 5V _ 0 4
0. 1 u _ 16 V _ Y 5 V _ 0 4
2mA
RT CV C C
C1 8 6
C1 8 7
0 . 1u _ 1 6V _ Y 5V _ 0 4
0. 1 u _ 16 V _ Y 5 V _ 0 4
A1 2
V _C P U _ I O [ 2]
V CC RT C
I b ex P e a k-M _ R e v 0 _9
V CCM
V CCM
V CCM
V CCM
CP U
C1 6 2
1 .1 V S _ V T T
AF2 2
V C C I O[ 1 2 ]
V _C P U _ I O [ 1]
C1 3 7
A U1 8
B - 22 IBEXPEAK - M 8/9
SATA
U2 0
PC I/ GP IO/ LP C
V C C S U S 3 _ 3[ 3 0 ]
0. 1 u _ 16 V _ Y 5 V _ 0 4
C1 4 4
1 . 5 V S _ 1 . 8V S
U1 9
C1 8 8
3 .3 VS
V CC V RM [4 ]
RT C
B.Schematic Diagrams
1 . 1V S _V T T
V C C ME [ 1 ]
US B
A D3 8
0. 1 u _ 16 V _ Y 5 V _ 0 4
V C C S U S 3_ 3 [ 1 ]
V C C S U S 3_ 3 [ 2 ]
V C C S U S 3_ 3 [ 3 ]
V C C S U S 3_ 3 [ 4 ]
V C C S U S 3_ 3 [ 5 ]
V C C S U S 3_ 3 [ 6 ]
V C C S U S 3_ 3 [ 7 ]
V C C S U S 3_ 3 [ 8 ]
V C C S U S 3_ 3 [ 9 ]
V C C S U S 3 _3 [ 1 0 ]
V C C S U S 3 _3 [ 1 1 ]
V C C S U S 3 _3 [ 1 2 ]
V C C S U S 3 _3 [ 1 3 ]
V C C S U S 3 _3 [ 1 4 ]
V C C S U S 3 _3 [ 1 5 ]
V C C S U S 3 _3 [ 1 6 ]
V C C S U S 3 _3 [ 1 7 ]
V C C S U S 3 _3 [ 1 8 ]
V C C S U S 3 _3 [ 1 9 ]
V C C S U S 3 _3 [ 2 0 ]
V C C S U S 3 _3 [ 2 1 ]
V C C S U S 3 _3 [ 2 2 ]
V C C S U S 3 _3 [ 2 3 ]
V C C S U S 3 _3 [ 2 4 ]
V C C S U S 3 _3 [ 2 5 ]
V C C S U S 3 _3 [ 2 6 ]
V C C S U S 3 _3 [ 2 7 ]
V2 4
V2 6
Y2 4
Y2 6
Vo lt age R ai l Vol ta ge
V_ CP U_I O
1. 1/ 1. 05
V5 RE F
5
V5 RE F_S us
5
Vc c3 _3
3. 3
HD A
E [1 3 ]
E [1 4 ]
E [1 5 ]
E [1 6 ]
V C CS U S HDA
A D1 9
AF2 0
AF1 9
A H2 0
C1 6 7
1 u_ 6 . 3 V _X 5 R _ 0 4
1 4 RT C V CC
2 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 17 , 1 8 , 19 , 2 0 , 23 , 2 4 , 25 , 2 6 , 27 , 2 8 , 29 , 3 0 , 31 , 3 5 , 3 6 3 . 3 V S
2 0 1 . 5 V S _ 1 . 8V S
2 , 13 , 1 7 , 20 , 2 6 , 27 , 3 0 , 31 , 3 5 , 3 6 5 V S
4, 9 , 1 0 , 11 , 2 3 , 27 , 2 9 , 31 , 3 3 , 3 6 1 . 5 V
24 , 3 0 , 31 , 3 3 , 3 4 5 V
3 , 4 , 1 2, 14 , 1 5 , 16 , 1 8 , 19 , 2 0 , 23 , 2 4 , 25 , 2 9 , 30 , 3 1 , 33 , 3 4 , 3 5 3 . 3 V
2 , 4 , 6, 7 , 1 4 , 15 , 1 6 , 19 , 2 0 , 34 , 3 5 , 3 6 1 . 1 V S _ V T T
AB1 9
AB2 0
AB2 2
A D2 2
AA3 4
Y3 4
Y3 5
AA3 5
1. 1 V S _ V T T
1. 5 V _ V C C S U S H D A
L3 0
R1 2 9
C1 8 9
R1 3 1
1 u _6 . 3 V _ X5 R _0 4
1 .5 V
*1 5 mi l _ sh o rt _ 06
* 0_ 0 4
3 . 3V
Schematic Diagrams
IBEXPEAK - M 9/9
IBEXPEAK - M (GND)
S[ 0 ]
S[ 1 ]
S[ 2 ]
S[ 3 ]
S[ 4 ]
S[ 5 ]
S[ 6 ]
S[ 7 ]
S[ 8 ]
S[ 9 ]
S[ 1 0 ]
S[ 1 1 ]
S[ 1 2 ]
S[ 1 3 ]
S[ 1 4 ]
S[ 1 5 ]
S[ 1 6 ]
S[ 1 7 ]
S[ 1 8 ]
S[ 1 9 ]
S[ 2 0 ]
S[ 2 1 ]
S[ 2 2 ]
S[ 2 3 ]
S[ 2 4 ]
S[ 2 5 ]
S[ 2 6 ]
S[ 2 7 ]
S[ 2 8 ]
S[ 2 9 ]
S[ 3 0 ]
S[ 3 1 ]
S[ 3 2 ]
S[ 3 3 ]
S[ 3 4 ]
S[ 3 5 ]
S[ 3 6 ]
S[ 3 7 ]
S[ 3 8 ]
S[ 3 9 ]
S[ 4 0 ]
S[ 4 1 ]
S[ 4 2 ]
S[ 4 3 ]
S[ 4 4 ]
S[ 4 5 ]
S[ 4 6 ]
S[ 4 7 ]
S[ 4 8 ]
S[ 4 9 ]
S[ 5 0 ]
S[ 5 1 ]
S[ 5 2 ]
S[ 5 3 ]
S[ 5 4 ]
S[ 5 5 ]
S[ 5 6 ]
S[ 5 7 ]
S[ 5 8 ]
S[ 5 9 ]
S[ 6 0 ]
S[ 6 1 ]
S[ 6 2 ]
S[ 6 3 ]
S[ 6 4 ]
S[ 6 5 ]
S[ 6 6 ]
S[ 6 7 ]
S[ 6 8 ]
S[ 6 9 ]
S[ 7 0 ]
S[ 7 1 ]
S[ 7 2 ]
S[ 7 3 ]
S[ 7 4 ]
S[ 7 5 ]
S[ 7 6 ]
S[ 7 7 ]
S[ 7 8 ]
S[ 7 9 ]
I be x P e a k -M _ R e v 0 _ 9
V SS [8 0 ]
V SS [8 1 ]
V SS [8 2 ]
V SS [8 3 ]
V SS [8 4 ]
V SS [8 5 ]
V SS [8 6 ]
V SS [8 7 ]
V SS [8 8 ]
V SS [8 9 ]
V SS [9 0 ]
V SS [9 1 ]
V SS [9 2 ]
V SS [9 3 ]
V SS [9 4 ]
V SS [9 5 ]
V SS [9 6 ]
V SS [9 7 ]
V SS [9 8 ]
V SS [9 9 ]
V SS [1 0 0 ]
V SS [1 0 1 ]
V SS [1 0 2 ]
V SS [1 0 3 ]
V SS [1 0 4 ]
V SS [1 0 5 ]
V SS [1 0 6 ]
V SS [1 0 7 ]
V SS [1 0 8 ]
V SS [1 0 9 ]
V SS [1 1 0 ]
V SS [1 1 1 ]
V SS [1 1 2 ]
V SS [1 1 3 ]
V SS [1 1 4 ]
V SS [1 1 5 ]
V SS [1 1 6 ]
V SS [1 1 7 ]
V SS [1 1 8 ]
V SS [1 1 9 ]
V SS [1 2 0 ]
V SS [1 2 1 ]
V SS [1 2 2 ]
V SS [1 2 3 ]
V SS [1 2 4 ]
V SS [1 2 5 ]
V SS [1 2 6 ]
V SS [1 2 7 ]
V SS [1 2 8 ]
V SS [1 2 9 ]
V SS [1 3 0 ]
V SS [1 3 1 ]
V SS [1 3 2 ]
V SS [1 3 3 ]
V SS [1 3 4 ]
V SS [1 3 5 ]
V SS [1 3 6 ]
V SS [1 3 7 ]
V SS [1 3 8 ]
V SS [1 3 9 ]
V SS [1 4 0 ]
V SS [1 4 1 ]
V SS [1 4 2 ]
V SS [1 4 3 ]
V SS [1 4 4 ]
V SS [1 4 5 ]
V SS [1 4 6 ]
V SS [1 4 7 ]
V SS [1 4 8 ]
V SS [1 4 9 ]
V SS [1 5 0 ]
V SS [1 5 1 ]
V SS [1 5 2 ]
V SS [1 5 3 ]
V SS [1 5 4 ]
V SS [1 5 5 ]
V SS [1 5 6 ]
V SS [1 5 7 ]
V SS [1 5 8 ]
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
A
A
A
A
A
A
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
A
A
A
A
A
A
A
A
A
A
A
A
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
A
A
A
A
A
A
A
K3 0
K3 1
K3 2
K3 4
K3 5
K3 8
K4 3
K4 6
K4 9
K5
K8
L2
L 52
M1 1
B4 4
D 24
M2 0
M2 2
M2 4
M2 6
M2 8
A4 2
M3 0
M3 1
M3 2
M3 4
M3 5
M3 8
M3 9
M4 2
U 20
M4 6
V2 2
M4 9
M7
A5 0
B1 0
N 32
N 50
N 52
P1 2
P4 2
P4 6
P4 9
P5
P8
R2
R 52
T11
A1 2
H 48
T32
T36
T41
T47
T7
V1 2
V1 6
V2 0
V2 4
V3 0
V3 4
V3 8
V4 2
V4 6
V4 9
V5
V8
W 14
W 18
W2
F9
W 32
W 36
W 40
W 52
Y 11
Y 43
Y 47
U 20I
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
V SS
[ 1 59 ]
[ 1 60 ]
[ 1 61 ]
[ 1 62 ]
[ 1 63 ]
[ 1 64 ]
[ 1 65 ]
[ 1 66 ]
[ 1 67 ]
[ 1 68 ]
[ 1 69 ]
[ 1 70 ]
[ 1 71 ]
[ 1 72 ]
[ 1 73 ]
[ 1 74 ]
[ 1 75 ]
[ 1 76 ]
[ 1 77 ]
[ 1 78 ]
[ 1 79 ]
[ 1 80 ]
[ 1 81 ]
[ 1 82 ]
[ 1 83 ]
[ 1 84 ]
[ 1 85 ]
[ 1 86 ]
[ 1 87 ]
[ 1 88 ]
[ 1 89 ]
[ 1 90 ]
[ 1 91 ]
[ 1 92 ]
[ 1 93 ]
[ 1 94 ]
[ 1 95 ]
[ 1 96 ]
[ 1 97 ]
[ 1 98 ]
[ 1 99 ]
[ 2 00 ]
[ 2 01 ]
[ 2 02 ]
[ 2 03 ]
[ 2 04 ]
[ 2 05 ]
[ 2 06 ]
[ 2 07 ]
[ 2 08 ]
[ 2 09 ]
[ 2 10 ]
[ 2 11 ]
[ 2 12 ]
[ 2 13 ]
[ 2 14 ]
[ 2 15 ]
[ 2 16 ]
[ 2 17 ]
[ 2 18 ]
[ 2 19 ]
[ 2 20 ]
[ 2 21 ]
[ 2 22 ]
[ 2 23 ]
[ 2 24 ]
[ 2 25 ]
[ 2 26 ]
[ 2 27 ]
[ 2 28 ]
[ 2 29 ]
[ 2 30 ]
[ 2 31 ]
[ 2 32 ]
[ 2 33 ]
[ 2 34 ]
[ 2 35 ]
[ 2 36 ]
[ 2 37 ]
[ 2 38 ]
[ 2 39 ]
[ 2 40 ]
[ 2 41 ]
[ 2 42 ]
[ 2 43 ]
[ 2 44 ]
[ 2 45 ]
[ 2 46 ]
[ 2 47 ]
[ 2 48 ]
[ 2 49 ]
[ 2 50 ]
[ 2 51 ]
[ 2 52 ]
[ 2 53 ]
[ 2 54 ]
[ 2 55 ]
[ 2 56 ]
[ 2 57 ]
[ 2 58 ]
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
S[ 2 5 9 ]
S[ 2 6 0 ]
S[ 2 6 1 ]
S[ 2 6 2 ]
S[ 2 6 3 ]
S[ 2 6 4 ]
S[ 2 6 5 ]
S[ 2 6 6 ]
S[ 2 6 7 ]
S[ 2 6 8 ]
S[ 2 6 9 ]
S[ 2 7 0 ]
S[ 2 7 1 ]
S[ 2 7 2 ]
S[ 2 7 3 ]
S[ 2 7 4 ]
S[ 2 7 5 ]
S[ 2 7 6 ]
S[ 2 7 7 ]
S[ 2 7 8 ]
S[ 2 7 9 ]
S[ 2 8 0 ]
S[ 2 8 1 ]
S[ 2 8 2 ]
S[ 2 8 3 ]
S[ 2 8 4 ]
S[ 2 8 5 ]
S[ 2 8 6 ]
S[ 2 8 7 ]
S[ 2 8 8 ]
S[ 2 8 9 ]
S[ 2 9 0 ]
S[ 2 9 1 ]
S[ 2 9 2 ]
S[ 2 9 3 ]
S[ 2 9 4 ]
S[ 2 9 5 ]
S[ 2 9 6 ]
S[ 2 9 7 ]
S[ 2 9 8 ]
S[ 2 9 9 ]
S[ 3 0 0 ]
S[ 3 0 1 ]
S[ 3 0 2 ]
S[ 3 0 3 ]
S[ 3 0 4 ]
S[ 3 0 5 ]
S[ 3 0 6 ]
S[ 3 0 7 ]
S[ 3 0 8 ]
S[ 3 0 9 ]
S[ 3 1 0 ]
S[ 3 1 1 ]
S[ 3 1 2 ]
S[ 3 1 3 ]
S[ 3 1 4 ]
S[ 3 1 5 ]
S[ 3 1 6 ]
S[ 3 1 7 ]
S[ 3 1 8 ]
S[ 3 1 9 ]
S[ 3 2 0 ]
S[ 3 2 1 ]
S[ 3 2 2 ]
S[ 3 2 3 ]
S[ 3 2 4 ]
S[ 3 2 5 ]
S[ 3 2 6 ]
S[ 3 2 7 ]
S[ 3 2 8 ]
S[ 3 2 9 ]
S[ 3 3 0 ]
S[ 3 3 1 ]
S[ 3 3 2 ]
S[ 3 3 3 ]
S[ 3 3 4 ]
S[ 3 3 5 ]
S[ 3 3 6 ]
S[ 3 3 7 ]
S[ 3 3 8 ]
S[ 3 3 9 ]
S[ 3 4 0 ]
S[ 3 4 1 ]
S[ 3 4 2 ]
S[ 3 4 3 ]
S[ 3 4 4 ]
S[ 3 4 5 ]
S[ 3 4 6 ]
S[ 3 4 7 ]
S[ 3 4 8 ]
S[ 3 4 9 ]
S[ 3 5 0 ]
S[ 3 5 1 ]
S[ 3 5 2 ]
S[ 3 5 3 ]
S[ 3 5 4 ]
S[ 3 5 5 ]
S[ 3 5 6 ]
S[ 3 6 6 ]
H 49
H5
J 24
K1 1
K4 3
K4 7
K7
L 14
L 18
L2
L 22
L 32
L 36
L 40
L 52
M1 2
M1 6
M2 0
N 38
M3 4
M3 8
M4 2
M4 6
M4 9
M5
M8
N 24
P1 1
AD 1 5
P2 2
P3 0
P3 2
P3 4
P4 2
P4 5
P4 7
R2
R 52
T12
T41
T46
T49
T5
T8
U 30
U 31
U 32
U 34
P3 8
V1 1
P1 6
V1 9
V2 0
V2 2
V3 0
V3 1
V3 2
V3 4
V3 5
V3 8
V4 3
V4 5
V4 6
V4 7
V4 9
V5
V7
V8
W2
W 52
Y 11
Y 12
Y 15
Y 19
Y 23
Y 28
Y 30
Y 31
Y 32
Y 38
Y 43
Y 46
P4 9
Y5
Y6
Y8
P2 4
T43
AD 5 1
AT8
AD 4 7
Y 47
AT1 2
AM6
AT1 3
AM5
AK 4 5
AK 3 9
AV 1 4
Sheet 22 of 42
IBEXPEAK - M 9/9
I b e x Pe a k - M_ R e v 0 _ 9
IBEXPEAK - M 9/9 B - 23
B.Schematic Diagrams
U 20H
AB 1 6
VS
AA 1 9
VS
AA 2 0
VS
AA 2 2
VS
A M1 9
VS
AA 2 4
VS
AA 2 6
VS
AA 2 8
VS
AA 3 0
VS
AA 3 1
VS
AA 3 2
VS
AB 1 1
VS
AB 1 5
VS
AB 2 3
VS
AB 3 0
VS
AB 3 1
VS
AB 3 2
VS
AB 3 9
VS
AB 4 3
VS
AB 4 7
VS
AB 5
VS
AB 8
VS
AC2
VS
A C 52
VS
A D 11
VS
A D 12
VS
A D 16
VS
A D 23
VS
A D 30
VS
A D 31
VS
A D 32
VS
A D 34
VS
A U 22
VS
A D 42
VS
A D 46
VS
A D 49
VS
AD7
VS
AE 2
VS
AE 4
VS
AF 1 2
VS
Y 13
VS
A H 49
VS
AU4
VS
AF 3 5
VS
AP 1 3
VS
A N 34
VS
AF 4 5
VS
AF 4 6
VS
AF 4 9
VS
AF 5
VS
AF 8
VS
A G2
VS
A G52
VS
A H 11
VS
A H 15
VS
A H 16
VS
A H 24
VS
A H 32
VS
AV 1 8
VS
A H 43
VS
A H 47
VS
AH7
VS
A J 19
VS
A J2
VS
A J 20
VS
A J 22
VS
A J 23
VS
A J 26
VS
A J 28
VS
A J 32
VS
A J 34
VS
A T5
VS
A J4
VS
AK 1 2
VS
A M4 1
VS
A N 19
VS
AK 2 6
VS
AK 2 2
VS
AK 2 3
VS
AK 2 8
VS
AY 7
B1 1
B1 5
B1 9
B2 3
B3 1
B3 5
B3 9
B4 3
B4 7
B7
BG 1 2
B B1 2
B B1 6
B B2 0
B B2 4
B B3 0
B B3 4
B B3 8
B B4 2
B B4 9
B B5
BC 1 0
BC 1 4
BC 1 8
BC 2
BC 2 2
BC 3 2
BC 3 6
BC 4 0
BC 4 4
BC 5 2
BH 9
BD 4 8
BD 4 9
BD 5
B E1 2
B E1 6
B E2 0
B E2 4
B E3 0
B E3 4
B E3 8
B E4 2
B E4 6
B E4 8
B E5 0
B E6
B E8
B F3
B F4 9
B F5 1
BG 1 8
BG 2 4
BG 4
BG 5 0
BH 1 1
BH 1 5
BH 1 9
BH 2 3
BH 3 1
BH 3 5
BH 3 9
BH 4 3
BH 4 7
BH 7
C 12
C 50
D 51
E1 2
E1 6
E2 0
E2 4
E3 0
E3 4
E3 8
E4 2
E4 6
E4 8
E6
E8
F4 9
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
A F3 9
H 16
H 20
H 30
H 34
H 38
H 42
Schematic Diagrams
New Card, Mini PCIE
3 .3 V
C 45 9
*0 . 1 u_ 1 6 V _Y 5 V _0 4
4
U2 6
*M C 7 4V H C 1 G 08 D F T1 G
3 .3 V
5
NEW CARD(Port 8)
B U F _ P L T _R S T #
1
3
2
1 . 5 V S 3. 3 V S
3 .3 V
R 3 36
R 33 8
C2 1 0
C 2 24
C2 2 0
* 1 00 K _ 1 %_ 0 4
* 10 0 K _ 1% _ 0 4
*0 . 1 u_ 1 0 V _X 7 R _ 0 4
* 0 . 1u _ 1 0V _ X 7 R _ 0 4
*0 . 1 u_ 1 0 V _X 7 R _ 0 4
U 25
J _ NE W 1
17
A U XI N
8
N C_ RS T #
15
N C _ 3 . 3V A U X
3
N C _ 3 . 3V
36mils
48mils
N C_ P E RS T #
N C _ 1 . 5V
48mils
PER ST#
A U X OU T
2
3 .3 V IN
3 . 3 V OU T
11
1 . 5 V OU T
13
P E R S T#
12
+ 3. 3 V A U X
14
15
10
9
12
B.Schematic Diagrams
1 .5 V IN
6
19
4 , 1 8 , 25 , 2 8 B U F _ P L T _R S T #
1 8 U S B _ OC# 2 3
1 6 , 2 8, 3 1
3. 3 V
Sheet 23 of 42
New Card, Mini PCIE
1 .5 V S
3 .3 VS
P CIE _ W A K E #
1 6 , 25 P C I E _ W A K E #
1 5 N E W C A R D _ C L K R E Q#
S Y S RS T #
OC #
R 1 70
3 .3 VS
1 0 K _ 04
STBY#
17
4
11
16
19
18
1 5 C L K _ P C I E _N E W _ C A R D
1 5 CL K _ P CIE _ N E W _ CA R D#
1
S US B #
R3 4 7
N C _C P P E #
N C _C P U S B #
10
9
CP P E #
CP US B #
+ 3. 3 V
+ 3. 3 V
+ 1. 5 V
+ 1. 5 V
CP P E #
CP U S B #
W AKE#
C L K R E Q#
RE F CL K +
RE F CL K -
1 0 K _0 4
4
5
13
14
16
3 . 3V
NC
NC
NC
NC
NC
18
20
R CL K E N
S H DN #
N C _ R C L K E N R 3 39
N C _ S H D N # R 3 55
*1 0 K _ 04
*1 0 K _ 04
3 . 3V
C4 6 4
C 45 1
*0 . 1 u _1 6 V _ Y 5 V _ 04
*0 . 1 u_ 1 6 V _ Y 5 V _ 04
*0 . 1 u _1 6 V _ Y 5 V _ 0 4
P CIE _ RX P2 _ NE W _ CA RD
P C I E _ R X N2 _ N E W _C A R D
P C I E _ T X P 2_ N E W _ C A R D
P CIE _ T X N2 _ NE W _ CA R D
Port 3
* W 8 3L 3 5 1Y G
C4 4 3
15
15
15
15
7
21
G ND
G ND
22
21
25
24
3
2
1 8 U SB_ PP3
1 8 U S B _ P N3
PETp 0
PETn 0
P E R p0
P E R n0
R ESER VED
R ESER VED
U S B _D +
U S B _D -
6-02-83351-9Q0
8
7
1 5 S M L0 _ D A T A
1 5 S M L0 _ C L K
E NE P 223 1 pi n3 ,4, 15 ,2 2
h as i nte rn al ly
S MB _D A T A
S MB _C LK
* 13 0 8 01 -0 2
p ul le d h ig h (1 70K oh m)
MINI CARD (WLAN,Port 5)
La you t Sh ow "WLAN(Wima x, 802.11N)" No te
20 mil
PC IE_ W AKE#
3 . 3V S
R3 1 2
1 0K _0 4
1
3
5
7
11
13
9
15
1 5 W L A N _C L K R E Q #
1 5 C L K _P C I E _ MI N I #
1 5 C L K _P C I E _ MI N I
J _ MI N I 1
W AKE#
CO E X 1
CO E X 2
3 . 3V A U X _0
1 . 5 V _0
UIM _ P W R
U I M_ DA T A
U I M_ CL K
U I M_ R E S E T
U I M_ V P P
C L K R E Q#
RE F CL K RE F CL K +
GN D 0
GN D 1
2
6
8
10
12
14
16
3 .3 V
W LA N 1 . 5V
20 mil
1. 5 V
R3 2 5
R3 9 7
P C H_ B T _ E N#
0_ 0 4
*1 5 mi l _s h o rt _ 06
C4 3 8
*0 . 1 u _1 6 V _ Y 5 V _ 04
4
G ND5
KEY
21
27
29
35
23
25
31
33
28
W L A N _ D E T#
15 P C I E _ R X N 3 _ W L A N
1 5 P C I E _R XP 3_ W L A N
1 5 P C I E _T X N 3 _ W L A N
1 5 P C I E _ T XP 3_ W L A N
28
2 8 , 29
3 IN1
B T_ E N
R 36 2
* 0_ 0 4
R 35 9
0 _ 04
28
8 0 DE T #
3. 3 V
M INI_ CL K 1
M INI_ DA T A 1
M INI_ RS T # 1
V D D3
R 31 5
* 0_ 0 4
17
19
37
39
41
43
45
47
49
51
GN D 2
GN D 3
GN D 4
GN D 1 1
PETn 0
PETp 0
P E R n0
P E R p0
R e s e rv e d0
R e s e rv e d1
GN D 1 2
3 . 3V A U X _ 3
3 . 3V A U X _ 4
GN D 1 3
R e s e rv e d2
R e s e rv e d3
R e s e rv e d4
R e s e rv e d5
G ND6
G ND7
G ND8
G ND9
G N D 10
W _ D I S A B LE #
P E R S E T#
S MB _ CL K
S MB _ DA T A
U S B _ DUS B_ D+
3 . 3V A U X _1
1 . 5 V _1
1 . 5 V _2
3 . 3V A U X _2
LE D _ W W A N #
L E D_ W L A N#
LE D _ W P A N #
18
26
34
40
50
20
22
30
32
36
38
24
28
48
52
42
44
46
R 32 6
* 10 K _ 0 4
3. 3V S
W L A N _E N
B U F _P LT _ R S T #
B T _ DE T #
20 mil
3 .3 V A UX _ 1
40 mil
20 mil
U S B _P N 2 1 8
U S B _P P 2 1 8
R 32 9
* 15 m li _ s ho rt _ 0 6
15 , 2 9 P C H _B T _ E N #
W L A N _ L E D # 2 8 , 29
8 0 CL K
0 _ 04
4 , 9, 1 0 , 1 1, 2 1 , 2 7, 2 9 , 3 1, 33 , 3 6
2 0, 31 , 3 6
3 , 4 , 12 , 1 4 , 15 , 1 6 , 18 , 1 9 , 20 , 2 1 , 2 4, 2 5 , 2 9, 3 0 , 3 1, 3 3 , 3 4, 3 5
2, 1 0 , 1 1, 1 2 , 1 3, 14 , 1 5 , 16 , 1 7 , 18 , 1 9 , 20 , 2 1 , 24 , 2 5 , 2 6, 2 7 , 2 8, 2 9 , 3 0, 3 1 , 3 5, 3 6
1 4 , 2 5, 2 8 , 2 9, 3 1 , 3 2, 3 7
B - 24 New Card, Mini PCIE
3 .3 V
W LA N1 . 5 V
3 . 3V
8 8 91 0 -5 20 4 M-0 1
R 39 6
2 8, 2 9
28 , 2 9
1. 5 V
1. 5 V S
3 .3 V
3 .3 VS
V D D3
28
Port 2
GN D
GN D
GN D
GN D
G ND1
G ND2
5
6
1
20
23
26
G ND 1
G ND 2
Schematic Diagrams
3G, CCD, TPM
MINI CARD 3G(Port 6)
3G POWER
Layo ut Sho w "3.5G(HSDPA) " Not e
3 G_ 3. 3 V
G5243A 6-02-05243-9C0
APL3512A 6-02-03512-9C0
3 . 3V
U 12
3A 120mils
J _ 3G 1
1
3
5
W AKE#
CO E X 1
CO E X 2
7
11
13
9
15
3. 3 V A U X_ 0
1. 5V _ 0
U I M_ P W R
UI M _D A T A
UIM _ CL K
UI M _R E S E T
UIM _ V PP
CL K R E Q#
RE F C L K RE F C L K +
GN D 0
GN D 1
5
6 0mi ls
2
6
8
10
12
14
16
3 G_ 3 . 3V
3A 120mils
1
VIN
V OU T
2
U
U
U
U
U
G ND
I M_ P W R
I M_ D A T A
I M_ C L K
I M_ R S T
I M_ V P P
C 1 90
R1 76
+ C2 34
C 1 93
0. 1 u _ 16 V _ Y 5 V _ 04
0. 1 u _1 6 V _ Y 5 V _ 04
* 15 m il _ s ho rt _ 0 6
4
3
SS
C2 4 1
22 0 u_ 4 V _ V _B
EN
A P L3 5 12 A
R1 7 3
C2 3 1
*1 0 0K _1 % _0 4
0 . 1u _ 1 6V _ Y 5V _ 0 4
C 2 30
1 0u _ 6. 3 V _ X 5R _0 6
4
*0 . 01 u _ 50 V _ X7 R _0 4
GN D5
KEY
21
27
29
28
GN D 2
GN D 3
GN D 4
35
23
25
31
33
3 G_ D E T#
C4 14
0. 1 u _ 16 V _ Y 5 V _ 04
10 u _6 . 3 V _ X5 R _0 6
W _ DIS AB L E#
P E RS E T #
S M B_ CL K
S M B _D A T A
U S B _D U S B _ D+
Re s e rv ed 0
Re s e rv ed 1
GN D 1 2
3 . 3V A UX _3
3. 3 V A U X_ 1
3 . 3V A UX _4
1. 5V _ 1
GN D 1 3
1. 5V _ 2
Re s e rv ed 2
3. 3 V A U X_ 2
Re s e rv ed 3
L E D _W W A N#
Re s e rv ed 4
L E D _ W L A N#
Re s e rv ed 5
L E D _W P A N#
8 8 91 0 -5 20 4 M-0 1
18
26
34
40
50
2 8 3 G _P O W E R
20
22
30
32
36
38
24
28
48
52
42
44
46
3 G_ E N
F ro m SB G PIO Pin de fa u lt HI
Po w er P la ne : Su sp en d
28
L19
*W C M2 0 12 F 2 S -1 61 T 0 3-s h o rt
3
4
2
R 16 0
*1 5 mi l _ sh o rt _0 6
1
S3: De fi n ed
US B _ P N9
18
US B _ P P 9
18
Sheet 24 of 42
3G, CCD, TPM
3 G_ 3 . 3V
SIM CONN
6 0mi ls
3 G_ 3 . 3 V
R 14 0
4. 7 K _ 0 4
C4 1 5
+C 19 8
*0 . 1 u _1 6 V _Y 5 V _0 4
2 2 0u _ 4 V _V _ B
J_ S I M 1
R 32 2
* 10 m il _ s ho rt _ 0 4
U I M_ C L K
LOCK
(TOP VIEW)
C3
C2
C1
U I M_ RS T
U I M_ P W R
U I M_ CL K
U I M_ RS T
U I M_ P W R
C 42 4
R 31 0
* 10 m i l_ s ho rt _ 0 4
U I M_ DA T A
U I M_ V P P
U I M_ GN D
C 7
C 6
C 5
U I M_ D A T A
U I M_ V P P
OPEN
2 2 p_ 5 0 V _N P O_ 0 4
C 1 77 0 6 61 -1
S I ML OC K
[PV T- 1 ]
U 14
22 p _ 50 V _ N P O _0 4
L CL K
* 0_ 0 4 T P M_ L P C P D #
T P M_ B A D D
TP M _ P P
TPM
C 3
C2
5
L F RA M E #
L R E S E T#
S E R IRQ
C LK R U N #
L P CP D #
9
C9
0 . 1u _ 1 6V _ Y 5V _ 0 4
1 u_ 6 . 3 V _X 5 R_ 0 4
5
1 00 K _ 1% _ 0 4
G PIO
G P I O2
6
2
J _C C D1
* 0. 1 u _1 6 V _ Y 5 V _ 04
13
T P M 30 0 4
T P M 30 0 5
R7
14
G ND _1
G ND _2
G ND _3
G ND _4
3 3 0K _ 0 4
XTALI
XTALO
4
3
XTAL O
T EST I
C8
1 u _6 . 3 V _X 5 R _ 0 4
R8
PP
8
C5
1 00 K _ 1 %_ 0 4
C 25 5
X TA L I
N C_ 1
N C_ 2
N C_ 3
MJ_CCD1
R9
0 . 1 u _1 6 V _ Y 5 V _0 4
VSB
T E ST B I/B A DD
7
48 mil
1
1 u _6 . 3 V _ X5 R _ 0 4
3 .3 VS
28
TP M 30 0 1 1
TP M 30 0 2 3
TP M 30 0 3 12
HI: ACCESS
L OW: NORMAL ( Int ernal PD)
HI: 4E/ 4F H
T PM _BADD L OW: 2E/ 2F H
T PM _PP
* 15 m il _ s ho rt _ 0 6
*1 u _ 6. 3 V _ X 5R _0 4
D
R 19 9
L1
5 V_ CC D
Q4
MT P 3 4 03 N 3
S
D
C 27 2
4
11
18
25
X4
* MC -14 6 _ 32 . 7 68 K H z
1
2
6-22-32R76-0B4
C2 4 4
28
C C D_ E N
CC D _ E N
Q5
MT N7 0 02 Z H S 3
G
18
US B _ P N 5
18
US B _P P 5
2 8 C CD _D E T #
CC D _D E T #
S
22
16
27
15
L P C _ F R A ME #
P L T _R S T #
S E R I RQ
P M _C L K R U N #
V DD1
V DD2
V DD3
G
L A D0
L A D1
L A D2
L A D3
21
18 P C LK _T P M
1 6 S 4 _ S T A TE #
C4 0 5
2 2 p _5 0 V _N P O_ 0 4
CCD
5V
C2 8 0
0
1
2
3
10
19
24
C 27 7
L PC_ AD
L PC_ AD
L PC_ AD
L PC_ AD
26
23
20
17
C 2 56
L PCPD# ina ct ive t o L RST# in act ive 3 2~96 us
*0 . 1 u_ 1 6 V _Y 5 V _ 0 4
L PC r es et timing :
*0 . 1u _ 1 6V _ Y 5 V _ 04
* 0. 1 u _ 16 V _ Y 5 V _0 4
A sse rte d bef ore e nte rin g S3
1 4 , 28
18
1 4 , 28
16
C 40 3
2 2 p _5 0 V _N P O_ 0 4
3 .3 V S
TPM 1.2
1 4, 2 8
1 4, 2 8
1 4, 2 8
1 4, 2 8
C 4 04
1
2
3
4
5
8 52 0 5-0 5 0 01
From H8 default HI
C 2 50
*1 8p _ 5 0V _ N P O _ 04
* 1 8p _ 50 V _ N P O _ 04
* S L B 96 3 5 TT
X TA L O
P C LK _ T P M
R1 8 6
*3 3 _0 4
C 26 6
* 10 p _ 50 V _ N P O _0 6
X TA L I
Co-layout X4, X9
3 , 4 , 12 , 1 4 , 15 , 1 6 , 18 , 1 9, 2 0 , 2 1, 2 3 , 2 5, 2 9 , 3 0, 3 1 , 3 3, 3 4 , 35 3 . 3 V
2 , 1 0, 1 1 , 12 , 1 3 , 14 , 1 5 , 16 , 1 7 , 18 , 1 9 , 20 , 2 1, 2 3 , 2 5, 2 6 , 2 7, 2 8 , 2 9, 3 0 , 3 1, 3 5 , 36 3 . 3 V S
2 1, 3 0 , 3 1, 3 3 , 34 5 V
3 . 3V S
T P M _L P C P D #
R2 0 0
*1 0 K _0 4
T P M _P P
R1 9 0
*1 0 K _0 4
T P M _B A D D
R1 8 8
*1 0 K _1 % _ 04
R1 8 5
*1 0 K _1 % _ 04
1
2
4
3
X9
*1 T J S 12 5 D J 4 A 4 20 P _ 32 . 7 6 8K H z
6-22-32R76-0B2
6-22-32R76-0BG
3G, CCD, TPM B - 25
B.Schematic Diagrams
C 2 13
GN D 1 1
PET n 0
PET p 0
P E R n0
P E R p0
17
19
37
39
41
43
45
47
49
51
3 G_ 3 . 3V
GN D6
GN D7
GN D8
GN D9
GN D 1 0
Schematic Diagrams
Card Reader/LAN JMB251C
S D _C L K
C2 7 0
3 .3 V S
D VDD
S D_ CL K
R1 8 7
2 2 _ 1 %_ 0 4
(> 20 mi l)
S D X C _ P OW E R
U 13
26
L A N_ M DIP 0
26
L A N_ M DIN 0
*1 5 m il _ s ho rt _ 0 6
26
26
Sheet 25 of 42
Card Reader/LAN
JMB251C
DV D D
R3 4 9
L A N_ M DIP 1
L A N_ M DIN 1
3 . 3 V _ LA N
26
L A N_ M DIP 2
26
L A N_ M DIN 2
*1 5 m il _ s ho rt _ 0 6
26
26
A V D D 12 _ 5 5
L A N_ M DIP 3
L A N_ M DIN 3
L A N _ MD I P 2
L A N _ MD I N 2
A V D D 12 _ 6 2
L A N _ MD I P 3
L A N _ MD I N 3
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
MD I O1 0
MD I O9
MD I O8
V DD
V IP_ 1
V I N _1
A VD D1 2
V IP_ 2
V I N _2
GN D
A VD D3 3
V IP_ 3
V I N _3
A VD D1 2
V IP_ 4
V I N _4
R E GL X
JMC251 C
(LQFP 64)
RE X T
A V D D 33
X IN
X OU T
C LK N
CL KP
AV D D1 2
RX P
R XN
GN D
TX N
TXP
A V D D 12
M DIO 1 3
MD I O 7
C R_ CD 1 N
R3 5 0
M DIO 1 0
M DIO 9
M DIO 8
A V D D 12 _ 5 2
*1 5 m il _ s ho rt _ 0 6
J MC 25 1 _ C
R 20 2
10 u _ 6. 3V _ X 5 R _ 0 6
Pin#33
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
Pin#33
0. 1 u _ 16 V _ Y 5V _0 4
Pin#13
A V D D 1 2_ 5 2
A V D D 1 2 _ 55
V DD3
4
R 33 7
C2 8 7
C 28 9
C4 4 7
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
Pin#52
0. 1 u _ 16 V _ Y 5V _0 4
Pin#55
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
Pin#62
*1 0 u _6 . 3 V _ X 5 R _ 0 6
Pin#7
Reserved
R 3 48
* 1 5m i l _s h o rt _ 06
R 1 77
* 1 5m i l _s h o rt _ 06
R 3 54
* 0_ 0 6
DV DD
5
O UT
IN
R 3 58
* 0 _0 6
3. 3 V S V D D 3
R 2 01
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V DD RE G
VC C3 V
P W RC R
TEST
MP D
W AKE N
LA N _ L E D 2
C R _ LE D
R STN
CP P E N
GN D
V DDI O
MD I O6
MD I O1 2
MD I O1 4
C R_ CD 0 N
3 .3 V S
VC C_ CAR D
C 4 69
3
(> 20 mi l)
S HD N#
* 2 K _ 1% _ 0 4
4
(> 20 mi l)
2
SET
G ND
*G 91 4 1
R 1 98
MP D
* 1 0K _1 % _ 04
L A N_ P C IE _ W A K E # 2 8
LA N _ S C L
LA N _ S D A
B U F _P L T _ R S T # 4 , 1 8, 2 3 , 2 8
SD_ W P
M D I O 12
MD I O1 4
SD_ C D#
M PD
V D D3
3 . 3 V _L A N
C 2 33
C 42 5
C2 3 7
1 0u _ 6 . 3 V _X 5 R _ 0 6
Pin#32
0 . 1 u _1 6 V _ Y 5 V _ 0 4
Pin#32
1 0 u _6 . 3 V _ X 5R _ 06
Pin#31
0. 1u _ 1 6V _Y 5 V _0 4
Pin#31
3 . 3V _L A N
*1 M _0 4
I S ON
I S ON
R 34 4
1 00 K _ 1 % _0 4
R 19 2
*1 0 0 K _ 1% _ 0 4
3. 3V _ L A N
R3 1 9
P C IE _ W A K E #
1 6, 2 3 P C I E _ W A K E #
10 K _ 0 4
A
C
LA N _ P C I E _W A K E #
4 IN 1 SOCKET SD/MMC/MS/MS Pro
0 . 1u _ 1 0 V _X 7 R _ 0 4
0 . 1u _ 1 0 V _X 7 R _ 0 4
P C I E _ R X P 4 _ GL A N 15
P C I E _ R XN 4 _G L A N 1 5
J _C A R D -R E V 1
SD
SD
SD
SD
Card Reader
Power
V C C_ CA RD
V C C_ C A RD
R 31 6
7 5 _1 % _ 0 4
_C D #
_D 2
_D 3
_B S
S D _C L K
V C C_ C A RD
LA N X I N
C4 1 3
0 . 1u _ 1 6V _Y 5 V _ 04
1
C 26 8
2 2p _ 5 0 V _N P O _0 4
C 42 2
0 . 1 u _ 16 V _ Y 5 V _ 0 4
C2 6 1
Pin#2
22 p _ 5 0V _ N P O_ 0 4
1 0u _ 6 . 3 V _X 5 R _ 0 6
Pin#2
6- 22 -2 5R 00 -1 B4
6- 22 -2 5R 00 -1 B5
C2 4 0
*1 0 u _ 6. 3 V _ X 5 R _ 0 6
Pin#59
Reserved
0. 1 u _ 16 V _ Y 5V _0 4
Pin#59
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
Pin#2
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
Pin#21
Pl ace all ca pacit ors closed t o chip.
The s ubscript in each CAP inci cates the pin
number of JMC251/ JMC261 t hat should be
closed t o.
B - 26 Card Reader/LAN JMB251C
VC C_ CAR D
S D _D 0
S D _D 1
S D _W P
SD
SD
MS
SD
SD
SD
SD
_C L K
_D 3
_I N S #
_D 2
_D 0
_D 1
_B S
P1
P2
P3
P4
P5
P6
P7
P8
P9
P 10
P 11
P 12
P 13
P 14
P 15
P 16
P 17
P 18
P 19
P 20
P 21
CD_ S D
D A T 2 _S D
C D / D A T 3 _S D
C MD _ S D
VSS_ SD
V D D _S D
CL K _ S D
VSS_ SD
D A T 0 _S D
D A T 1 _S D
W P_ SD
V S S _ MS
V C C _M S
S C L K _ MS
D A T 3 _M S
I N S _ MS
D A T 2 _M S
S D I O / D A T 0 _ MS
D A T 1 _M S
B S _ MS
V S S _ MS
MD R 0 1 9 -C 0 -1 04 2
3 . 3 V _L A N
C 46 1
LA N _ P C I E _W A K E # 2 8
S CD 3 4 0
3 . 3 V _ LA N
F S X 5L _ 2 5 MH z
C2 4 8
C4 6 0
3. 3 V
*0 _ 0 6
V DD 3
28
X5
C 28 5
0 . 1 u _ 16 V _ Y 5V _ 0 4
R 35 7
P CI e Di ff er en ti al
P ai rs = 1 00 O hm
0 . 1u _ 1 6V _Y 5 V _ 04
2
*0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
Pin#43
* 4 . 7 K _0 4
C2 3 9
(> 20 mi l)
C4 5 3
Fo r JM C2 51 C
C4 6 3
1 0 0 K _ 1% _ 0 4
R3 2 1
3. 3 V S
( >2 0m il )
P C I E _ T X N 4 _ GL A N 15
P C I E _ TX P 4 _ GL A N 1 5
C L K _ P C I E _ G LA N 1 5
C LK _ P C I E _ GL A N # 15
R 18 4
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
Pin#43
R3 2 0
G9141
APL5603-12B(no R201,R198)
L A NX O UT
C 28 8
A0
A1
A2
1
C4 2 0
3 . 3 V _L A N
1
2
3
3 .3 V
A V D D 12 _ 7
C 28 6
G ND
3 .3 V
W P
U 27
C 23 5
C 23 6
A V D D 1 2_ 6 2
SC L
SD A
* A T 24 C 02 B N
D V D D R 3 28
*1 5 m li _ s ho rt _ 0 6
C4 4 4
DVD D
3 . 3 V _ LA N
0 . 1 u_ 1 6 V _ Y 5 V _ 0 4
Pin#7
7
VC C
6
5
D1 9
A V D D 1 2 _ 13
C 44 9
U2 1
8
C 45 7
1 2 K _ 1% _ 0 4
A V D D 1 2_ 7
* 4 . 7K _0 4
VDD 3
1
2
3
4
5
6
7
A V D D 1 2_ 7
*1 5 mi l _ sh o rt _ 0 6 8
9
10
11
12
13
A V D D 1 2 _ 13
14
MD I O 1 3
15
M DIO 7
16
MS _I N S #
DV D D
R3 5 1
C4 5 0
L A N X IN
L A N X OU T
B.Schematic Diagrams
DV D D
L A N _S C L R 31 8
(> 20 mi l)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Card Reader Pull High/Low
Resistors
Fo r JM C2 51 /2 61 o nl y
SD _ BS
SD_ D 3
S D_ D2
S D _D 1
SD_ D0
D VDD
C 276
2 . 2 u _ 6. 3 V _ X 5 R _ 0 6
3. 3V _ L A N
SD XC_ PO W ER
M DIO 1 1
L A N _ LE D 0
L A N_ L ED 1
I S ON
0 . 1u _ 1 6 V _Y 5 V _ 04
S D_ W P
M S _ INS #
* 4 . 7K _0 4
L A N _S D A
M D IO1 1
L AN_ L ED 0
LA N _ LE D 1
IS O N
GN D
V D DIO
VDD O
M D I O5
M DIO 4
M D I O3
M DIO 2
M D I O1
M DIO 0
FB1 2
G ND
LX
1 0K _0 4
*1 0 K _ 0 4
D V DD
S W F 2 5 20 C F -4 R 7 M-M
C2 7 1
R 31 1
R 31 3
.
* 4 . 7K _0 4 S D _ C D #
V C C_ C A RD
R 31 7
L3 5
R E GL X
R3 1 4
3 .3 V _ L A N
S wi tc hi ng R eg ul at or
c lo se t o PI N3 3
near Pin#41
*1 0 p _5 0 V _ N P O _ 06
1 u _ 6. 3 V _ X 5 R _0 4
JMC251C
V C C _C A R D
C4 2 3
C4 1 0
C 2 38
C4 1 9
0 . 1u _ 1 6V _Y 5 V _ 04
4. 7u _ 6 . 3V _X 5 R _ 0 6
0 . 1 u _1 6 V _ Y 5 V _ 0 4
0 . 1u _ 1 6V _Y 5 V _ 04
Near Cardreader CONN
1 4, 2 3 , 2 8 , 29 , 3 1 , 3 2, 37 V D D 3
26
D VD D
2, 10 , 1 1 , 1 2, 1 3 , 1 4 , 15 , 1 6 , 1 7, 1 8 , 1 9 , 20 , 2 1 , 2 3, 24 , 2 6 , 2 7, 2 8 , 2 9 , 30 , 3 1 , 3 5, 3 6 3 . 3 V S
3, 4 , 1 2 , 1 4, 1 5 , 1 6 , 18 , 1 9 , 2 0, 21 , 2 3 , 2 4, 2 9 , 3 0 , 31 , 3 3 , 3 4, 3 5 3 . 3 V
GN D
GN D
P2 2
P2 3
Schematic Diagrams
LAN (JMC251C), SATA HDD, ODD
GIGA LAN (JMC251C)
L2 6
25
25
25
25
L A N_ M
L A N_ M
L A N_ M
L A N_ M
DIP 0
DIN 0
DIP 1
DIN 1
25
25
25
25
L A N_ M D I P 2
L A N_ M D I N 2
L A N_ M D I P 3
L A N_ M D I N 3
L A N_ MD
L A N_ MD
L A N_ MD
L A N_ MD
IP 0
IN0
IP 1
IN1
12
11
9
8
L A N_ MD
L A N_ MD
L A N_ MD
L A N_ MD
IP 2
IN2
IP 3
IN3
6
5
3
2
10
7
4
1
DV D D
R 28
T D4 +
T D4 T D3 +
T D3 -
M
M
M
M
T D2 +
T D2 T D1 +
T D1 -
MX 2 +
M X 2MX 1 +
MX 1 -
T CT 4
T CT 3
T CT 2
T CT 1
MC
MC
MC
MC
X 4+
X 4X 3+
X3 -
T4
T3
T2
T1
13
14
16
17
L MX 1 +
L MX 1 L MX 2 +
L MX 2 -
LP 2
* S B 0 40 2 TL -0 4 0- sh o rt
1
8
2
7
3
6
4
5
D
D
D
D
LM
LM
LM
LM
X1 +
X1 X2 +
X2 -
1
2
3
6
19
20
22
23
L MX 3 +
L MX 3 L MX 4 +
L MX 4 -
R
R
R
R
D
D
D
D
LM
LM
LM
LM
X3 +
X3 X4 +
X4 -
4
5
7
8
36 7
36 8
36 9
37 0
J _ RJ 1
0 _ 04
0 _ 04
0 _ 04
0 _ 04
15
18
21
24
GST5009 LF
0 . 0 1u _ 50 V _ X 7 R _ 0 4
0 . 0 1u _ 5 0V _ X 7 R _ 0 4
7
8
4
5
1
2
L A N_ MD I N 1
L A N_ MD I P 1
3
6
C2 4
0 . 0 1u _ 5 0V _ X 7 R _ 0 4
C2 6
C 28
C 31
N
N
N
N
L6 2
L A N_ MD I N 0
L A N_ MD I P 0
T D+
T D-
TX+
TX-
N C
N C
NC
NC
R D+
R DR D_ CT
T D_ C T
RX +
R XR X _C T
T X _C T
10
9
sh i el d
sh i el d
G ND1
G ND2
GN D
DC +
DC DD +
DD -
* 0_ 0 4
* 0_ 0 4
D LM X 3D LM X 4-
* 75 _ 1 %_ 0 4
* 75 _ 1 %_ 0 4
D LM X 3D LM X 4-
E4120
PJS-08SL3B
E5120Q PJS-08S01B
MC
MC
MC
MC
T_ 1
T_ 2
T_ 3
T_ 4
R
R
R
R
24
25
26
32
7 5 _1 %
7 5 _1 %
7 5 _1 %
7 5 _1 %
_ 04
_ 04
_ 04
_ 04
N MC T _ R
L MX 1 L MX 1 +
R 36 3
R 36 4
6-21-B4010-008
C3 2 2
Sheet 26 of 42
LAN (JMC251C),
SATA HDD, ODD
1 00 0 p _2 K V _ X 7R _ 12
12
13
16
15
L MX 2 L MX 2 +
14
11
NM CT _ 2
NM CT _ 1
NOTICE:
FOR JMB251C GIGA LAN PARTS
*P 3 0 12
L26,LP1
C31,C28,C26,C24,C322
R24,R25,R26,R32,R367,R368,R369,R370
L26,L62 CO-LAYOUT
SATA HDD
FOR JMB261C 10M/100M LAN PARTS
L62,LP2
C26,C24
R24,R25,R363,R364
SATA ODD
J _ HD D1
S1
S2
S3
S4
S5
S6
S7
S A TA _ T X P 0
S A TA _ T X N 0
C 42 1
C 41 8
0 . 0 1 u _5 0 V _ X7 R _ 0 4
0 . 0 1 u _5 0 V _ X7 R _ 0 4
S A TA _ R XN 0
S A TA _ R XP 0
C 41 7
C 41 6
0 . 0 1 u _5 0 V _ X7 R _ 0 4
0 . 0 1 u _5 0 V _ X7 R _ 0 4
J _ OD D 1
S A TA TX P 0 1 4
S A TA TX N 0 1 4
S1
S2
S3
S4
S5
S6
S7
S A TA R X N 0 1 4
S A TA R X P 0 14
3 . 3V S
*1 0 u _6 . 3 V _ X5 R _0 6
22 u _ 6. 3 V _ X 5 R _ 0 8
C1 9 1
1 u_ 6 . 3 V _X 5R _0 4
2 2u _ 6 . 3V _ X 5 R _ 0 8
C4 0 7
C1 9 2
0 . 1u _ 1 6V _Y 5 V _ 0 4
C4 0 6
H D D _N C 1
H D D _N C 2
H D D _N C 3
0 . 1 u_ 1 6 V _Y 5 V _ 0 4
H D D _N C 0
C3 8 0
C3 7 9
0 . 0 1 u_ 5 0 V _X 7 R_ 0 4
0 . 0 1 u_ 5 0 V _X 7 R_ 0 4
S A T A T X P 1 14
S A T A T X N1 1 4
S A T A _ RXN 1
S A T A _ RXP 1
C3 7 7
C3 7 6
0 . 0 1 u_ 5 0 V _X 7 R_ 0 4
0 . 0 1 u_ 5 0 V _X 7 R_ 0 4
S A T A R X N1 1 4
SATAR XP1 1 4
P1
P2
P3
P4
P5
P6
5V S
C4 0 8
6-20-43740-022
C4 1 1
*0 . 0 1 u_ 5 0 V _ X7 R _ 0 4
0 . 1 u_ 1 6 V _Y 5 V _ 0 4
1 -16 2 -1 00 5 6 1
P IN G N D1 ~ 2 = G N D
C 41 2
C 40 9
P1
P2
P3
P4
P5
P6
P7
P8
P9
P1 0
P1 1
P1 2
P1 3
P1 4
P1 5
S A T A _ T XP 1
S A T A _ T XN 1
5 VS
OD D _ D E T E C T# 1 4
C3 6 1
C3 6 3
C 35 8
C 3 68
C3 6 6
*0 . 1 u _1 6 V _ Y 5 V _ 04
0. 1u _ 1 6V _ Y 5V _ 0 4
0 . 1 u_ 1 6 V _Y 5 V _0 4
1 u _ 6. 3 V _ X 5R _ 04
1 0u _ 6. 3V _ X 5 R _ 06
+
C 36 5
C3 6 7
1 0 0u _ 6 . 3V _ B _ A
*0 . 1 u _1 6 V _ Y 5 V _ 04
C 1 8 55 3 -1 13 0 5 -L
P I N GN D 1 ~ 2 = G ND
+C 2 0 3
*1 00 u _ 6. 3V _ B _ A
5V S
DV D D
3. 3 V
1. 5 V
3. 3 V S
5 VS
C 2 74
C 74
C 4 32
0 . 0 1 u_ 5 0 V _X 7 R _ 0 4
0 . 0 1u _ 5 0V _ X 7 R _ 0 4
0 . 0 1 u_ 5 0 V _X 7 R _ 0 4
2 , 1 3 , 17 , 2 0 , 21 , 2 7 , 30 , 3 1 , 35 , 3 6
25
3 , 4 , 1 2, 1 4 , 1 5, 1 6 , 1 8, 1 9 , 2 0, 21 , 2 3 , 24 , 2 5 , 29 , 3 0 , 31 , 3 3 , 34 , 3 5
4 , 9 , 1 0, 1 1 , 2 1, 2 3 , 2 7, 2 9 , 3 1, 33 , 3 6
2 , 1 0 , 11 , 1 2 , 13 , 1 4 , 15 , 1 6 , 17 , 1 8 , 1 9, 2 0 , 2 1, 2 3 , 2 4, 2 5 , 2 7, 2 8 , 2 9, 30 , 3 1 , 35 , 3 6
LAN (JMC251C), SATA HDD, ODD B - 27
B.Schematic Diagrams
0 . 0 1u _ 5 0V _X 7 R _0 4
4 0 mil
+
+
-
P J S -0 8 S O1 B
D LM X3 + R 36 5
D LM X4 + R 36 6
P 10 1 2
* 0_ 0 4
DA
DA
DB
DB
Schematic Diagrams
Audio Codec VIA1812
CODEC (VIA1812 )
1 .5 V
R 3 42
* 15 m i _l s ho rt _ 0 6
C 28 1
C 4 39
0 . 1 u_ 1 6 V _Y 5 V _0 4
1 0 u _6 . 3 V _ X5 R _0 6
5 VS_ AU D
PC BEEP
L 23
3 . 3V S _ A U D
L2 1
KBC_ BEEP
1
A
2
A
.
28
H C B 1 60 8 K F -1 21 T 2 5
C 43 3
C 4 65
0 . 1 u_ 1 6 V _Y 5 V _0 4
1 0 u _6 . 3 V _ X5 R _0 6
C2 7 8
C 28 2
C 2 83
C 26 2
0 . 1 u_ 1 6V _Y 5V _0 4
1 0 u_ 6 . 3 V _X 5 R _ 0 6
0 . 1 u _1 6 V _ Y 5 V _ 04
0 . 1 u_ 1 6 V _Y 5 V _0 4
C4 2 8
*0 . 1 u _1 0 V _ X7 R _0 4
3
BEEP
H D A _S P K R
C2 5 3
C2 4 2
* 0. 1 u _ 16 V _ Y 5 V _ 0 4
* 0. 1 u _ 16 V _ Y 5 V _ 0 4
C 2 63
AUD G
*2 2 p_ 5 0 V _N P O_ 0 4
R 3 45
R 3 41
R 3 34
R 3 33
R 3 30
14 , 2 9 H D A _S D OU T
14 , 2 9 H D A _B I T C LK
14
HD A _ S DIN 0
14 , 2 9 H D A _S Y N C
1 4, 29 H D A _ R S T #
A L C _ GP I O 0
A L C _ GP I O 1
2 2_ 1 %
2 2_ 1 %
2 2_ 1 %
2 2_ 1 %
2 2_ 1 %
2
3
A Z _ S D OU T _ R
A Z _ B IT CL K _ R
A Z _ S D IN0 _ R
A Z _ S Y NC_ R
A Z _ R S T# _ R
_0 4
_0 4
_0 4
_0 4
_0 4
5
6
8
10
11
E A P D _ MOD E
La you t No te :
C 4 40
2 2p _ 50 V _ N P O_ 04
Ver y cl ose t o Aud io C ode c
C 4 46
2 2p _ 50 V _ N P O_ 04
BEEP
R3 2 3
R3 2 4
C4 2 9
10 K _ 0 4
P C B E E P _C
5. 1 K _ 1 % _0 4
10 0 p _5 0 V _ N P O _0 4
R324
3. 3V VI A1 81 2 10 K
1. 5V VI A1 81 2 5. 1K
A LC 27 2 1K
C4 3 0
C2 4 5
C2 7 5
I N T _ MI C R 1 7 8
PC BEEP_ R
43
12
JD 1
JD 2
13
34
MI C _S E N S E R 1 8 2
20 K _ 1 %_ 0 4
HP _ S E N S E R3 5 2
5. 1 K _ 1 %_ 0 4
C 2 52
*1 0 0p _ 5 0V _ N P O_ 0 4
C 2 79
*1 0 0p _ 5 0V _ N P O_ 0 4
* 0. 1 u _ 16 V _ Y 5 V _ 0 4
* 0. 1 u _ 16 V _ Y 5 V _ 0 4
1K _1 % _ 04I N T_ M I C _ R
C 2 46
C 2 47
14
15
M IC2 _ L
M IC2 _ R
1 u _6 . 3 V _ X 5R _0 4
1 u _6 . 3 V _ X 5R _0 4
M I C 2 -V R E F O
M I C 1 -L
MI C 1 -R
MI C 1 -L
MI C 1 -R
R1 8 3
R1 7 9
75 _ 1 %_ 0 4
75 _ 1 %_ 0 4
MI C 1_ L _ C C 2 51
MI C 1_ R _C C 2 43
1 u _6 . 3 V _ X 5R _0 4
1 u _6 . 3 V _ X 5R _0 4
C4 3 6
C4 3 5
La yo ut No te :
68 0 p _5 0 V _ X7 R _0 4
6 80 p _ 50 V _ X 7R _ 04
Ve ry cl os e t o Au dio C od ec
A U DG
10 u _ 6. 3 V _ X 5R _ 06
25
38
FOR EMI
AUD G
AUD G
27
V RE F
28
M I C 1 -V R E F O
M I C 1 -V R E F O
3
A
1
A
D 23
B A T5 4 A S 3
2
MI C 1 -V R E F O-L
C
37
MO N O -OU T
DIGITAL
M IC1 _ L
M IC1 _ R
16
17
18
19
20
21
22
S P DIF O 1
S P DIF O 2
31
30
29
C PVEE
C BN
CB P
C4 5 6
C4 5 2
MI C 1 -V R E F O-R
2 . 2 u_ 1 6 V _ X5 R _ 0 6
2 . 2 u_ 1 6 V _ X5 R _ 0 6
R 33 2
N C
P C B E E P -I N
L O U T 1- L
LO U T 1 -R
S en s e A (JD 1 )
S en s e B (JD 2 )
L O U T 2- L
LO U T 2 -R
4 .7 K _ 0 4
M I C 1 -L
La you t No te :
Ver y cl ose t o Aud io C ode c
R3 3 1
L I N E 2- L
L I N E 2- R
L ay out N ot e:
ANALOG
39
41
33
32
H P OU T- L
H P O U T -R
M I C 2 -L
M I C 2 -R
H E A D P H O N E -L 3 0
H E A D P H O N E -R 3 0
23
24
L I N E 1- L
LI N E 1 -R
L I N E 1- V R E F O
M I C 2 -V R E F O
L I N E 2- V R E F O
F R ON T -L
F R ON T -R
35
36
40
M I C 1 -L
M I C 1 -R
M I C 2 -V R E F O
NEAR CODEC
J DR E F
R1 9 1
J D RE F
J_INTMIC1
2 1
5. 1 K _ 1 %_ 0 4
R 78
C2 6 7
*1 0 0 p_ 5 0 V _N P O_ 0 4
2 . 2 1 K _1 % _ 04
J_ I N T M I C 1
I N T_ M I C
A UDG
V T1 8 1 2
C 12 2
3 3 0 p_ 5 0V _X 7 R _ 0 4
5 V S _ RE A R
AMP (N7010)
1
2
88 2 66 -0 2 00 1
P C B F o o t pr in t = 8 82 6 6- 2L
R191 VIA1812 5.1K_1%_04
ALC272 20K_1%_04
A UDG
Co de c pin 1 ~ p in 11 a nd pi n 44 ~ pi n 4 8
ar e Di git al s ig nal s.
Th e ot her s ar e Ana lo g sig na ls .
M I C 1 -R
A U DG
AUD G
L ayo ut N ot e:
4 .7 K _ 0 4
N ear M IC co nn ec t
D MI C -C L K 1 / 2
D MI C -C L K 3 / 4
26
42
30
30
C4 4 8
*1 5 mi l _ sh o rt _ 06
0 . 1 u _1 6 V _ Y 5 V _ 04
0 . 1 u _1 6 V _ Y 5 V _ 04
0 . 1 u _1 6 V _ Y 5 V _ 04
0 . 1 u _1 6 V _ Y 5 V _ 04
0 . 1 u _1 6 V _ Y 5 V _ 04
E APD
48
45
1 u _6 . 3 V _ X5 R _ 0 4
3 0 M IC_ S E NS E
3 0 H P _S E N S E
D A T A -OU T
I T-C L K
D A T A -I N
Y NC
ESET#
47
46
44
AUD G
A LC _V R E F
G P I O0 / D MI C -D A T A 1 / 2
G P I O1 / D MI C -D A T A 3 / 4
S
B
S
S
R
* 0 . 1u _ 1 6V _ Y 5V _ 0 4
U2 4
AV DD1
AVDD 2
*2 2 p_ 5 0 V _N P O_ 0 4
DVSS1
D VSS2
C 2 69
DVDD
D V D D -I O
* 0. 1 u _ 16 V _ Y 5 V _ 0 4
* 0. 1 u _ 16 V _ Y 5 V _ 0 4
2 2p _ 5 0V _ N P O_ 0 4
AVSS1
AV SS2
Sheet 27 of 42
Audio Codec
VIA1812
C2 5 8
C2 5 9
C 4 54
1
9
4
7
C4 4 1
10/16 change
footprinter
L 34
H C B 1 00 5 K F -1 2 1T 2 0
C2 4 9
C4 4 2
C 43 1
C 4 45
0 . 1u _ 1 6V _ Y 5V _ 0 4
*1 u _ 6. 3 V _ X 5R _ 04
1 0 u _6 . 3 V _ X5 R _ 0 6
*1 0u _ 6 . 3V _ X 5 R _ 0 6
5 VS
J_SPK1
2 1
U 22
R3 5 3
10 K _ 0 4
F R ON T-R
R3 5 6
10 K _ 0 4
AU DG
AU DG
C4 5 8
C2 5 4
0 . 1 u _1 0 V _ X7 R _ 0 4
0 . 1 u _1 0 V _ X7 R _ 0 4
LI N LI N +
C4 6 2
C2 6 0
0 . 1 u _1 0 V _ X7 R _ 0 4
0 . 1 u _1 0 V _ X7 R _ 0 4
RIN RIN +
17
7
SPK_ EN
19
3 .3 VS
A UD G
5 VS
A UD G
R 32 7
Low mute!
1 0 0K _1 % _ 04
D2 2
C
E A P D _ M OD E R 3 3 5
*1 0 mi l _s h o rt _ 04 E A P D _ M OD E _ R
1 0 0 K _1 % _ 04
* 1 00 K _ 1 %_ 0 4
R 1 89
R 3 40
1 0 0 K _1 % _ 04
* 1 00 K _ 1 %_ 0 4
GA I N 0
GA I N 1
1
4
SPK_ EN
2
3
2 8 K B C _M U T E #
U2 3
MC 7 4 V H C 1 G0 8 D F T 1 G
0
1
1
1
0
1
10 dB
15.6 dB
21.6 dB
2
3
1
11
13
20
21
*0 . 1 u _1 0 V _ X7 R _0 4
Gain Settings
GAIN0 GAIN1 AV(inv)
0
0
6 dB
L INL IN+
PVDD
PVDD
VDD
RI NRI N+
SD #
C4 3 4
*C D B U 00 3 4 0
A
5
1 9 P C H _ MU T E #
R 3 46
R 1 97
5
9
GA I N 0
GA I N 1
LO U T +
Thermal Pad
F R ON T-L
L O UT -
70 k
45 k
25 k
J _ SPKL 1
S P K O UT L +
L2 2
8
S P K O UT L -
L2 0
18
14
10
12
F C M1 0 0 5K F -12 1 T 03
S P K OU T L+ _ R
S P K OU T L-_ R
1
2
F C M1 0 0 5K F -12 1 T 03
S P K O UT R+ 3 0
S P K O UT R- 3 0
85 2 0 4-0 2 0 01
P C B F o ot pri n t = 85 2 0 4-0 2 R
C 26 5
L 24
* 1 0m i _l s h ort _0 4
C2 7 3
1 8 0p _ 5 0V _ N P O_ 0 4
A MP _ B Y P A S S
1 80 p _ 50 V _ N P O _ 04
F OR EM I
C 42 7
4 . 7 u_ 6 . 3 V _ X5 R _ 0 6
A UD G
AUD G
N7010 6-02-07010-AL0
APA2031RI-TRG 6-02-02031-AL1
1 .5 V
3 .3 V
3 .3 V S
5V
5 VS
B - 28 Audio Codec VIA1812
A U DG
4
RO UT +
RO UT GN D
GN D
GN D
BYP ASS
GN D
E X P OS E D P A D
NC
N 70 1 0
INPUT IMPEDANCE
90 k
6
15
16
.
.
B.Schematic Diagrams
MI C 1_ L
MI C 1_ R
5 VS
C 2 84
L 36
C4 6 7
C4 6 6
C2 5 7
C4 2 6
C4 3 7
A UD G
MI C 2_ L
MI C 2_ R
H C B 16 0 8 K F -1 21 T 2 5
A U DG
* 1 u_ 6 . 3 V _X 5 R _ 0 4
C
14
.
3 .3 VS
D2 0
B A T 54 C S 3
4 , 9, 1 0 , 1 1, 21 , 2 3, 29 , 3 1 , 33 , 3 6
3 , 4, 1 2 , 1 4, 15 , 1 6, 18 , 1 9 , 20 , 2 1 , 23 , 2 4 , 25 , 2 9 , 30 , 3 1 , 33 , 3 4 , 35
2 , 10 , 1 1 , 12 , 1 3 , 14 , 1 5 , 1 6, 1 7 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 6 , 2 8, 2 9 , 3 0, 3 1 , 3 5, 3 6
2 1, 2 4 , 3 0, 3 1 , 3 3, 3 4
2 , 13 , 1 7 , 20 , 2 1 , 26 , 3 0 , 3 1, 3 5 , 3 6
Schematic Diagrams
KBC-ITE IT8502E
K BC _ A V DD
*1 5 mi l _s h o rt _0 6
C 2 08
C 2 32
C2 2 9
C2 2 5
0 . 1 u _1 6 V _ Y 5 V _ 04
10 u _ 6. 3 V _ X 5R _0 6
0 . 1u _ 1 6V _ Y 5V _ 0 4 0 . 1u _ 1 6V _ Y 5V _ 0 4
L17
H C B 1 0 0 5K F - 12 1 T2 0
.
R1 7 1
V D D3
C 19 5
V D D3
V DD 3
C2 1 8
C2 1 9
C2 2 2
0 . 1u _ 1 6V _ Y 5 V _ 0 4
*0 . 1 u _1 6 V _ Y 5 V _ 04
*0 . 1 u_ 1 6 V _Y 5 V _0 4
V D D3
U2 8
8
0 . 1 u_ 1 6 V _Y 5 V _0 4
VD D
SI
SO
CE #
S CK
C 22 6
L1 8
H C B 10 0 5 K F -12 1 T 20
P C LK _ K B C
2 3 , 2 9 W LA N _ LE D #
3 T H E R M _V O L T
2 5 LA N _ P C I E _ W A K E #
24
3 G_ D E T #
24
C C D _D E T #
37
37
S MC _ B A T
S MD _ B A T
3, 1 5 S MC _ C P U _T H E R M
3, 1 5 S MD _ C P U _T H E R M
P CIE _ W A K E #
3 G_ D E T #
C C D _ D E T#
MO D E L _ I D
LOW ACTIVE
23
23
23
18
30
30
8 0 CL K
3 IN 1
8 0D E T #
PM E#
T P _ CL K
T P _D A T A
37
V CHG _ S EL
AD
AD
AD
AD
AD
AD
AD
AD
SM
SM
SM
SM
SM
SM
C 0 / GP I
C 1 / GP I
C 2 / GP I
C 3 / GP I
C 4 / GP I
C 5 / GP I
C 6 / GP I
C 7 / GP I
PW M
PW M
PW M
PW M
PW M
PW M
PW M
PW M
74
3
( P D )K S O1 6 / GP C 3
( P D )K S O1 7 / GP C 5
(
(
(
(
(
(
(
0 / GP A 0 (
1 / GP A 1 (
2 / GP A 2 (
3 / GP A 3 (
4 / GP A 4 (
5 / GP A 5 (
6 / GP A 6 (
7 / GP A 7 (
PU
PU
PU
PU
PU
PU
PU
PU
)
)
)
)
)
)
)
)
LK 0 / G
A T0 / G
LK 1 / G
A T1 / G
LK 2 / G
A T2 / G
0
1
2
3
4
5
6
( P D )E G A D / G P E 1
( P D )E G C S # / G P E 2
( P D )E G C L K / G P E 3
)
)
)
)
)
)
( P D )W U I 5 / G P E 5
( P D )L P C P D # / W U I 6 / G P E 6
PWM/COUNTER
( P D )T A C H 0 / GP D 6
( P D )T A C H 1 / GP D 7
( P D )T MR I 0/ W U I 2 / GP C 4
( P D )T MR I 1/ W U I 3 / GP C 6
CIR
R I 1# / W U I 0 / GP D 0( P U )
R I 2# / W U I 1 / GP D 1( P U )
( P D )C R X / GP C 0
( P D )C TX / G P B 2
GP INTERRUPT
33
)I D 0 / GP H
)I D 1 / GP H
)I D 2 / GP H
)I D 3 / GP H
)I D 4 / GP H
)I D 5 / GP H
)I D 6 / GP H
EXT GPIO
PU
PU
PU
PU
PU
PU
K B -S I 0
K B -S I 1
K B -S I 2
K B -S I 3
K B -S I 4
K B -S I 5
K B -S I 6
K B -S I 7
4
5
6
8
11
12
14
15
K B -S I 0
K B -S I 1
K B -S I 2
K B -S I 3
K B -S I 4
K B -S I 5
K B -S I 6
K B -S I 7
4
5
6
8
11
12
14
15
36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55
K B -S O0
K B -S O1
K B -S O2
K B -S O3
K B -S O4
K B -S O5
K B -S O6
K B -S O7
K B -S O8
K B -S O9
K B -S O1 0
K B -S O1 1
K B -S O1 2
K B -S O1 3
K B -S O1 4
K B -S O1 5
1
2
3
7
9
10
13
16
17
18
19
20
21
22
23
24
K B -S O0
K B -S O1
K B -S O2
K B -S O3
K B -S O4
K B -S O5
K B -S O6
K B -S O7
K B -S O8
K B -S O9
K B -S O1 0
K B -S O1 1
K B -S O1 2
K B -S O1 3
K B -S O1 4
K B -S O1 5
1
2
3
7
9
10
13
16
17
18
19
20
21
22
23
24
10 0
10 1
10 2
10 3
10 4
10 5
10 6
K B C_ S P I_ CE #
K B C_ S P I_ S I
K B C_ S P I_ S O
8 51 8 _D D _ ON _ LA T C H
K B C _ S P I _ S C LK
56
57
S US B #
S US C#
93
94
95
96
97
98
99
R 16 8
C 22 3
*0 _0 4
EC MODULE CHOOSE (FOR DIFFERENCE K/B TYPE)
1
8 5 0 2_ D D _ ON _ L A T C H
8 5 0 2_ W L A N _ D E T#
8 5 0 2_ B T _ D E T #
8 5 0 2_ D D _ ON
82
83
84
16 , 2 3 , 31
16 , 3 3
AVSS
24
S MI #
19
S CI#
19
P W R _B T N # 1 6
35
17
RS M RS T # 1 6
K B C _R S T # 1 9
47
48
CP U _ F A NSE N
MC H _ T S A TN _ E C
12 0
12 4
11 9
12 3
B RIG HT NES S
3 .3V
R 157 X / R15 3 10 K
0V
0 . 1 u_ 1 6 V _Y 5 V _0 4
RN 1 9
2 . 2K _4 P 2 R _ 0 4
3
2
4
1
MO DE L_ ID
E4120
E5120Q
R 15 7
*1 0 K _ 04
V DD 3
Sheet 28 of 42
KBC-ITE IT8502E
1 0 K _0 4
C K 3 2K E
C K 3 2K
V DD 3
3 G_ D E T #
CC D_ DE T #
W L A N _L E D #
R3 7 1
R3 7 2
R3 7 3
R3 7 4
R3 7 5
R3 7 6
0_04
0_04
0_04
0_04
0_04
0_04
D D _O N _ L A T C H 3 1
W L A N_ DE T # 2 3
B T _D E T # 2 3 , 2 9
D D _O N
31
I S ON
25
C P U _F A N 3 0
R3 7 7
R3 7 8
R3 7 9
R3 8 0
* 0_ 0 4
* 0_ 0 4
* 0_ 0 4
*0 _ 0 4
85 1 8 _D D _ ON _L A T C H
85 1 8 _W L A N _D E T #
85 1 8 _B T _ D E T #
85 1 8 _D D _ ON
85 0 2 _C P U _ F A N
85 0 2 _I S O N
R3 8 5
R3 8 7
R3 8 6
R3 8 8
R3 8 9
R3 9 0
*
*
*
*
*
*
8 51 8 _S
8 51 8 _S
8 51 8 _S
8 51 8 _S
0_ 0 4
0_ 0 4
0_ 0 4
0_ 0 4
0_ 0 4
0_ 0 4
10 K _ 0 4
10 K _ 0 4
R3 6 0
*1 0K _0 4
C2 1 5
PCL K _ KB C
R1 6 4
*1 0 _0 4 P C L K _ K B C _R
*1 0p _ 5 0V _ N P O_ 0 6
SW I#
16
C H G_ E N
37
V DD 3
For 8512E
C2 0 1
0 . 1 u_ 1 6 V _Y 5 V _0 4
U 9
?? ?
R 1 3 5 1 K _ 1% _ 0 4
K B C _ F LA S H
CK 3 2 K E
CK 3 2 K
R 1 69
R 1 6 2 4 . 7 K _0 4
K B C _ H OL D #
* 10 M_ 0 4
4
3
C 22 7
B A T_ V O LT
1u _ 6. 3V _ X 5 R _ 04
4 ,1 9
H_ P EC I
R 17 5
K B C _S P I _S I _R
R3 9 1
4 7 _ 04
K B C _S P I _S I
2
K B C _S P I _S O _ R
R3 9 2
1 5 _ 04
W P#
K B C _S P I _S O
K B C _S P I _C E # _R
R3 9 3
1 5 _ 04
K B C _S P I _C E #
6
K B C _S P I _S C L K _R
R3 9 4
4 7 _ 04
K B C _S P I _S C L K
CE #
SC K
7
S M C _ C P U _ TH E R M
*0 _0 4
4
HO L D#
VSS
* MX 2 5L 3 20 5 D M 2 I -12 G
AT25F512AN for 8502
6-04-25320-A70
4-02532-470
MX25L3205DM2I-12G for 8518 6-0
6-04-26321-470
C K 3 2K E
Co -la yo ut X2 , X3
1 2 p _5 0 V _ N P O _0 4
* MC -14 6 _ 32 . 7 6 8K H z
B A T _ V OL T
1
SI
C 2 21
1 2 p_ 5 0 V _N P O_ 0 4
S H OR T
37
KBC_SPI_*_R = 0.1"~0.5"
5
SO
3
U9 U28 Co-layout
X3
R 3 9 5 * 0_ 0 4
C2 0 0
P I _C S 0 # 1 4
P I _S C L K 1 4
P I _S O 1 4
P I _S I 14
D D _O N _ L A T C H 3 1
W L A N_ DE T # 2 3
B T _D E T # 2 3 , 2 9
D D _O N
31
I S ON
25
C P U _F A N 3 0
VD D
2
12 8
R1 4 7
R1 5 0
30
8 51 8 _W LA N _ D E T #
8 51 8 _B T_ D E T#
1
2
E C Co st Do wn
12
VO LTA GE
R 157 1 0K / R 15 3 X
RX
85 0 2 _D D _ ON _L A T C H
85 0 2 _W L A N _D E T #
85 0 2 _B T _ D E T #
85 0 2 _D D _ ON
V C O R E _ O N 1 6 , 36
A L L_ S Y S _ P W R G D 1 2 , 16
19
CLOCK
NC 3
RX
V1 .0
ITE 8518E
3 G_ E N
EC_ V S S
W/0 C IR )
VE R.
R 15 3
C K 3 2K
0 _0 4 FOR I T8 512 CX /E X
0 .1 U_ 04 FO R ITE 85 12 -J( IT E8 502 -J
24
J_KB1
M OD E L_ I D
85 0 2 _D D _ ON _L A T C H
85 0 2 _W L A N _D E T #
85 0 2 _B T _ D E T #
85 0 2 _D D _ ON
85 0 2 _I S O N
85 0 2 _C P U _ F A N
75
I T8 5 02 E
1 u _6 . 3 V _ X5 R _0 4
ITE 8502E
24
S U S _P W R _ A C K 1 6
M E_ W E# 1 4
A C _ P R E S E N T 16 , 1 8
( P D )L 80 H LA T / G P E 0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R XD / GP B 0 ( P U )
T X D/G P B 1 ( PU )
C 21 6
VSS
3 . 3V S
CC D_ E N
( P D )R I N G #/ P W R F A I L # / L P C R S T# / G P B 7
1
12
27
49
91
113
1 22
UART
1 08
1 09
B T_ E N
BKL _ EN
KB C_ W R E S E T #
H OL D #
For 8502E
U9 U28 Co-layout
SM D_ B A T
SM C_ B A T
11 2
23 , 2 9
12
1 0 0K _ 1 % _0 4
4
E N 2 5 P 05 -5 0 GC P
8
LPC/WAKE UP
G I N T / GP D 5 ( P U )
7
J _ KB2
8 52 0 1- 24 0 51
10 7
WAKE UP
18
21
PD
PD
PD
PD
PD
PD
PD
WAKE UP
P F 0(
P F 1(
P F 2(
P F 3(
P F 4(
P F 5(
K B C _ H O LD #
R 15 8
W P#
FOR E5120Q
58
59
60
61
62
63
64
65
( P D )I D 7 / GP G 1
P W R S W / G P E 4( P U )
30 W E B _W W W #
VBAT
GPIO
PS/2
PS2 C
PS2 D
PS2 C
PS2 D
PS2 C
PS2 D
1 25
31
P W R _S W #
12 , 3 0
L ID_ S W #
AVCC
26
50
92
114
1 21
127
F L F R A ME # / GP G 2
F L A D0 /S C E #
F L A D 1/ S I
F L AD2 /S O
F L A D 3 / GP G 6
F L CL K /SCK
( P D )F L R S T# / W U I 7 / TM / GP G 0
C L K 0 / GP B 3
D A T 0 / GP B 4
C L K 1 / GP C 1
D A T 1 / GP C 2
C L K 2 / GP F 6 ( P U )
D A T 2 / GP F 7 ( P U )
3
C_ SP I_ S I_ R
C _ S P I _ S O_ R
C_ SP I_ CE # _ R
C_ SP I_ S CL K _ R
V DD 3
FLASH
0
1
2
3
4
5
6
7
PWM
24
25
28
29
30
31
32
34
85
86
87
88
89
90
8 0 CL K
3 IN1
8 0 DE T #
ITE 8502E
ITE 8518E
SMBUS
1 10
1 11
1 15
1 16
S M C _ C P U _T H E R M 1 17
S M D _ C P U _T H E R M 1 18
2 9 LE D _ S C R OL L#
29
L E D _ N U M#
29
L ED_ CA P#
29 L E D _ B A T _ C H G#
2 9 LE D _B A T_ F U LL #
29
L E D _P W R #
A C 0 / GP J 0
A C 1 / GP J 1
A C 2 / GP J 2
A C 3 / GP J 3
A C 4 / GP J 4
A C 5 / GP J 5
ADC
S M C_ B A T
S M D_ B A T
L C D _B R I GH T N E S S
K B C _B E E P
KBC _ BEEP
DAC
D
D
D
D
D
D
66
67
68
69
70
71
72
73
B A T _ DET
B A T _ V OL T
W L A N_ L E D#
0831
27
E C S CI# /G P D3 ( P U )
E C S MI # / G P D 4 ( P U )
K B C_ F L A S H
KB
KB
KB
KB
1
2
4
3
V D D3
3 .3 V S
1 4, 23 , 2 5 , 29 , 3 1 , 32 , 3 7
2 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 6 , 2 7, 2 9 , 3 0, 3 1 , 3 5, 36
X2
1T J S 1 25 D J4 A 4 2 0P _ 3 2 . 76 8 K H z
R 1 51
C 2 11
*1 0 m li _ sh o rt _ 04L C D _B R I GH T N E S S
6 -2 2- 32R 76 -0 B4
K B C _A G N D
6 -22 -3 2R 76- 0B 2
6 -22 -3 2R 76- 0B G
* 0. 1u _ 16 V _ Y 5 V _ 0 4
KBC-ITE IT8502E B - 29
B.Schematic Diagrams
B A T _D E T
K S O0 / P D 0
K S O1 / P D 1
K S O2 / P D 2
K S O3 / P D 3
K S O4 / P D 4
K S O5 / P D 5
K S O6 / P D 6
K S O7 / P D 7
K S O8 / A C K #
K S O 9/ B U S Y
K S O 1 0/ P E
K S O1 1 / E R R #
K S O1 2/ S LC T
K S O1 3
K S O1 4
K S O1 5
G A 20 / G P B 5
K B R S T #/ G P B 6 ( P U )
P W U R E Q # / GP C 7( P U )
L 8 0L L A T / GP E 7 ( P U )
76
77
78
79
80
81
85 0 2_ C P U _ F A N
85 1 8_ D D _ ON
85 0 2_ I S O N
W LA N _ E N
K S I0 /S T B #
KSI1 /AF D #
K S I 2/ I N I T #
K S I 3/ S LI N #
KSI4
KSI5
KSI6
KSI7
LPC K/B MATRIX
23
15
30
AP_ KEY #
30 W E B _E M A I L #
FOR E4120
J_ K B 1
* 85 2 0 1-2 4 0 51
W R ST#
1 26
4
16
20
19
GA 2 0
37
A C_ IN#
29
L E D _A C I N #
3 T H E R M _A L E R T#
37
L A D0
L A D1
L A D2
L A D3
L P CC L K
L F R A ME #
S E R IRQ
L P C R S T #/ W U I 4 / GP D 2 ( P U )
14
K B C _W R E S E T #
2 3, 2 9 W L A N _ E N
24
3 G_ P OW E R
27
K B C _M U T E #
V CC
10
9
8
7
13
6
5
22
VSTBY
VST BY
VSTBY
VSTB Y
VSTBY
VSTB Y
.
U1 1
14 , 2 4
L P C_ A D 0
14 , 2 4
L P C_ A D 1
14 , 2 4
L P C_ A D 2
14 , 2 4
L P C_ A D 3
18
P C L K _K B C
1 4, 2 4 L P C _ F R A M E #
14 , 2 4
S E RIR Q
4 , 1 8, 2 3 , 2 5 B U F _ P L T_ R S T#
K B C _ A GN D
11
3 .3 VS
0 . 1 u_ 1 6 V _Y 5 V _0 4
EC_ V CC
5
2
1
6
Schematic Diagrams
LED, MDC, BT
3 V_ BT
Bluetooth(Port8)
COSTDOWN
Po rt 1 1
3 . 3V
MJ_MDC1
20 MIL
1. 5 V
18
U S B _ P N1 1
18
U SB_ PP1 1
2 3 ,2 8
B T_ D E T#
R 2 92
11
R 1 67
* 15 m li _ s ho rt _ 0 6
3 .3 V
87 2 1 2-0 6 G0
3 .3 V
2
4
6
8
10
12
G ND
R E S E RV E D
A z a il a _S D O
R E S E RV E D
G ND
3 . 3 V Ma i n / au x
A z a il a _S Y N C
GN D
A z a il a _S D I
GN D
A z a il a _R S T #
A za il a _ B C L K
R1 6 6
3 .3 V
*0 _ 0 6
C 4 01
10mil L 16
MD C _ 3. 3 V
*1 5 mi l _s h o rt _0 6
*1 8 0 p_ 5 0 V _N P O_ 0 4
HD A _B I TC LK _R
R 15 2
3 3 _ 04
3 .3 V
10 K _ 0 4
C 21 7
C 21 2
0 . 1 u_ 1 6 V _Y 5V _0 4
2 2 p_ 5 0 V _N P O_ 0 4
2 3, 2 8
C 39 8
C 3 95
10 u _ 6. 3 V _ X 5R _0 6
3. 3 V S
6-52-52001-027
1
2
D 1
4
WLAN
LED
R Y -S P 1 5 5 H Y Y G4
C
L E D _ S C R OL L # 28
6-52-52001-027
*1 0 m li _ sh o rt _ 04
B
W L A N_ E N
M2
M -MA R K 1
H1 0
H 8
H 6 _ 3 D 3 _8 H 6_ 3 D 4 _ 4
3
4
5
1
9
8
7
6
H1 4
3
4
5
MT H 3 1 5 D 1 1 1
1
9
8
7
6
H1 3
3
4
5
MT H 31 5 D 1 1 1
1
LE D _ A C I N # 2 8
M6
M-MA R K 1
M3
M-M A R K 1
M4
M -MA R K 1
H5
3
4
5
1
9
8
7
6
H3
3
4
5
MT H 3 1 5 D 1 1 1
S2
S MD 8 0 X 80
MT H 31 5 D 1 1 1
H1 1
C 46 8
*0 . 1 u_ 1 6V _Y 5V _0 4
H6
C6 7 D 6 7
3
4
5
1
H2 1
C 1 58 D 15 8
H 20
C 15 8 D 1 5 8
H1 9
H 16
H 4 _ 0 B 7_ 0 D 3 _ 7 H 4_ 0 B 7 _0 D 3_ 7
1
H9
3
4
5
1
MT H 3 1 5 D 1 1 1
B - 30 LED, MDC, BT
1
9
8
7
6
M TH 31 5 D 1 1 1
H7
9
8
7
6
MT H 3 1 5 D 1 1 1
H2 3
C6 7 D6 7
H2 4
3
4
5
3
4
5
H2 2
1
9
8
7
6
3
4
5
MT H 31 5 D 1 1 1
9
8
7
6
1
9
8
7
6
M TH 31 5 D 1 1 1
H4
3
4
5
1
M TH 31 5 D 1 1 1
9
8
7
6
L E D _ B A T _C H G # 28
4 , 9 , 1 0, 1 1 , 2 1, 2 3 , 2 7, 3 1 , 3 3, 3 6 1 . 5V
3 , 4 , 1 2, 1 4 , 1 5, 1 6 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 3 0 , 3 1, 3 3 , 3 4, 3 5 3 . 3V
1 4, 2 3 , 2 5, 2 8 , 3 1, 3 2 , 3 7 V D D 3
2 , 1 0, 1 1 , 1 2, 1 3 , 1 4, 1 5 , 1 6, 1 7 , 1 8, 1 9 , 2 0, 2 1 , 2 3, 2 4 , 2 5, 2 6 , 2 7, 2 8 , 3 0, 3 1 , 3 5, 3 6 3 . 3V S
M TH 31 5 D 1 1 1
9
8
7
6
LE D _B A T_ F U LL # 2 8
23 , 2 8
9
8
7
6
H 15
H1 7
H 12
H 4_ 7 B 6 _0 D 3_ 7 H 4 _7 B 6 _ 0D 3 _7H 6_ 3 D 3 _ 8
1
S1
S MD 80 X 8 0
1
H1 8
H6 _ 0 D3 _ 7
1
*R Y -S P 1 5 5 H Y Y G4
E4120
B
V DD 3
H2
H1
C 1 58 D 15 8 C 1 58 D 15 8
*R Y -S P 1 5 5H Y Y G4
L E D _P W R # 28
E
M8
M-M A R K 1
BAT LED
D1 4
23 , 2 8
Q2
*D T C 1 14 E U A
BT_ EN
H2 5
M7
M-MA R K 1
R 1 95
*2 20 _ 0 4 * 2 20 _ 04
D1 3
2
Q1
D TC 11 4 E U A
M5
M -MA R K 1
R 1 96
POWER ON
LED
3
1
1
R 19 4
R 3 43
6-52-52001-027
M1
M-M A R K 1
V DD3
W L A N _L E D # 2 3 , 2 8
LE D _ C A P # 2 8
6-52-52001-027
3
Y
D5
C
LE D _ N U M# 2 8
SCROLL
LOCK
LED
R Y - S P 17 0 Y G 3 4 - 5 M
C
R Y - S P 1 70 Y G 34 - 5 M
D 4
CAPS
LOCK
LED
* 2 20 _ 04 * 22 0 _ 04
SG
BT
LED
A
A
A
C
C
R Y - S P 17 0 Y G 3 4 - 5 M
R Y - S P 1 7 0 Y G 3 4 - 5M
D2
NUM
LOCK
LED
R 1 93
2 20 _ 0 4
4
22 0 _0 4
R5
3
22 0 _ 04
D3
A
22 0 _ 04
V DD 3
2 2 0_ 0 4
1
2 2 0_ 0 4
R1
HDD/ODD
LED
V D D3
R 6
Y
R4
4
R3
2
Q3
D T A 1 14 E U A
R 2
E
C
S A TA _ L E D # 1 4
V DD3
C
B
3 .3 V S
3 . 3V S
2
3 .3 V S
SG
3. 3 V S
E
3 . 3V S
1
B.Schematic Diagrams
G ND
LED
50 mi l
*1 5m i l _s h o rt _0 6
Q1 5
MT N 7 0 02 Z H S 3
G
B T _E N
3 V_ BT
R3 0 6
5 0m il
B T _ E N#
H D A _B I T C LK 1 4 , 2 7
S
88 0 1 8-1 2 0G
*0 _ 04
From EC default HI
R 3 09
1
33 _ 0 4 H D A _S Y N C _R
22 _ 1 %_ 0H 4D A _S D I N 1 _ R
33 _ 0 4 H D A _R S T #_ R
B T _D E T #
J_ MD C1
Y
SG
R 1 61
R 1 59
R 1 55
1
3
5
7
9
11
2
33 _ 0 4 H D A _S D OU T_ R
1 8 0p _ 5 0V _ N P O _ 0 4
1 4 , 27 H D A _ S Y N C
1 4 H DA _ S DIN 1
1 4 , 27 H D A _ R S T #
R 1 65
R 30 8
1 5 , 23 P C H _ B T _E N #
D
1 4 , 27 H D A _ S D O U T
Sheet 29 of 42
LED, MDC, BT
B T _E N #
4 7 K _ 1% _ 0 4
1
3
2
1
2
3
4
5
6
4
12
J _ B T1
GN D
J _ TP4
1
L E D_ P W R #
2
L E D_ A CIN #
3
L E D_ B A T _ F UL L #
4
L E D_ B A T _ CHG #
5
6
8 52 0 1 -06 0 5 1
GN D
Schematic Diagrams
USB, Fan, TP, Multi-Conn
USB PORT*2(Port 0,Port1)
FAN CONTROL
5V S _ F A N
5 VS
5
U S B _ F L G#
U 19
F L G# V O U T 1
2
6
U S B V C C0 1
100 MIL
7
V IN 1 V O UT 2
C 94
3
1 0 u_ 6 . 3 V _X 5 R _ 0 6
4
31 , 3 3
1
2
3
4
F ON #
U 4
5V
28
GN D
GN D
GN D
GN D
8
7
6
5
8
C 1 10
C 1 21
C 1 28
G 9 90 P 1 1U
0. 1 u _1 6 V _ Y 5 V _ 04
0. 1 u _1 6 V _ Y 5 V _ 04
*1 0u _ 6 . 3V _ X 5 R _ 06
G9 90P 1 1U 6- 02 -9 901 1 -B2 0
G ND
P2 793 A 6- 02 -0 27 93- B 20
U P 75 3 4 D S A 8 -2 0
D D _O N #
FO N
V IN
V O UT
VSET
1
V IN 2 V O UT 3
E N#
C P U _F A N
UP7 53 4D 6 -02 -75 3 48- 92 0
RT9 71 5B GS 6- 02- 0 971 5- 92 0
5 VS
5 VS_ FAN
J _ F A N1
APL 35 10 6 -02 -03 5 10- 92 0
1
2
3
C 3 94
U S B V C C 01
C3 9 0
0 . 1 u _1 6 V _ Y 5 V _ 04
U S B _ V C C 01 _ 0
L10
* 15 m li _ s ho rt _ 0 6
85 2 0 5-0 3 7 01
1 0u _ 6 . 3V _ X 5 R _ 06
60 mil
+C 92
C 95
+
* 10 0 u_ 6 . 3 V _B _ A
Port 0
0 . 1 u_ 1 6 V _Y 5V _0 4
28 C P U _ F A N S E N
R 2 75
3 .3 V S
4. 7 K _ 0 4
JFAN
3
J _ US B 1
1
1
V+
U S B _P N 0
18
U SB_ PP0
4 L9
3
DA T A _ L
3
DA T A _ H
4
3 .3 V
GN D
3 .3 V
R7 4
10 K _ 0 4
R7 7
*1 0 K _0 4
CLICK CONN
FO R C LI CK B OA RD
G ND 1
GN D 2
G ND3
GN D 4
1 -28 4 -8 00 2 81
6- 21- B 440 0- 00 4
18
U S B _ V C C 0 1 _0
5 VS_ TP
5V S
U S B _ F LG #
U S B _ OC # 0 1
Sheet 30 of 42
USB, Fan, TP,
Multi-Conn
2
1
2
*W C M2 01 2 F 2 S -16 1 T 03 -s h ort
GN D 1
GN D 2
GN D 3
G ND 4
18
R9 4
* 15 m i _l s ho rt _ 0 6
80 mil
R7 3
*0 _0 4
+C 1 2 9
C1 7 1
*1 0 0u _ 6 . 3V _ B _ A
J_ T P 1
1
2
3
4
0 . 1u _ 1 6V _ Y 5V _ 0 4
Port 1
C 1 58
C1 6 3
* 1 0u _ 6. 3 V _ X 5R _ 06
1 u_ 6 . 3 V _X 5 R _ 0 4
R8 5
R8 4
10 K _ 0 4
10 K _ 0 4
C1 5 3
C1 4 9
47 p _ 50 V _ N P O _0 4
47 p _ 50 V _ N P O _0 4
T P _D A T A 2 8
T P _C L K 2 8
8 52 0 1- 04 0 51
J_ U S B 2
1
V +
2
1
2
*W C M2 01 2 F 2 S -16 1 T 03 -s h ort
D A T A _L
3
D A T A _H
4
G ND
1 -2 8 4-8 0 0 28 1
6 -21 -B4 4 00- 00 4
POWER SWITCH CONN.
CLOSE TO J_SW1
FO R PO WE R SW IT CH B OA RD
3 .3 VS
3 . 3V
C 21
Audio/B
CONN.(Port 2)
AP_ KEY#
AP_ KEY# 2 8
C2 0
Q6
G
J_ S W 2
1
2
3
4
5
6
7
8
* MT N 7 0 0 2Z H S 3
5V
0 . 0 1u _ 5 0V _ X 7 R _ 04
0. 01 u _5 0 V _ X7 R _ 0 4
1.1A 60mils
C2 1 4
0. 01 u _5 0 V _ X7 R _0 4
F OR AU DI O BO AR D
J _ A U D I O1
R 15 4
2 7 MI C 1-R
2 7 MI C 1-L
R 18 1
R 18 0
2 7 H E A D P H O N E -R
2 7 H E A D P H O N E -L
2 2 0 _0 4
2 2 0 _0 4
2 7 MI C _S E N S E
18
U S B _P N 4
R 17 2
18
U SB_ PP4
R 17 4
*1 0m i l _s h ort _0 4
*1 0m i l _s h ort _0 4
U S B N 4 _R
2 7 HP _ S E N S E
US B P 4 _ R
2 7 S P K OU T R +
2 7 S P K OU T R -
*1 5 mi l _ sh o rt _ 06
MI C 1-R
MIC 1-L
H E A D P H ON E -R R
H E A D P H ON E -LL
MI C _S E N S E
S P K _ HP #
HP _ S E NS E
U S B N 4_ R
US B P 4 _ R
S P K OU TR +
S P K OU T R -
1
2
3
4
5
6
7
8
9
10
11
12
13
14
J_ S W 1
2 0m il
1
2
3
4
5
6
7
8
9
10
*5 0 50 0 -0 10 4 1-0 0 1 L
R 21
*1 0 mi l _ sh o rt _0 4
M_ B TN # _R
W E B _W W W #
W E B _E MA I L #
LI D _S W #
A P _O N
3 .3 V S
3 .3 V
D
U SB_ PP1
3
S
18
4 L13
GN D 1
GN D 2
GN D 3
GN D 4
US B _ P N 1
GN D 1
G ND 2
GN D 3
G ND4
18
M_ B T N #
31
W EB_ W W W # 2 8
W E B _ E MA I L# 2 8
L I D _ S W # 12 , 2 8
2 0m il
MB T N
R1 8
W EB_ W W W #
W E B _ E MA I L #
LI D _ S W #
*1 0 m li _ sh o rt _ 04 M_ B T N #
AP_ KEY#
88 4 8 6-0 8 01
A P _ ON
31
3 , 4, 1 2 , 1 4, 1 5 , 1 6, 1 8 , 1 9, 2 0 , 21 , 2 3 , 24 , 2 5 , 29 , 3 1 , 33 , 3 4 , 35 3 . 3 V
2 , 13 , 1 7 , 20 , 2 1 , 26 , 2 7 , 31 , 3 5 , 36 5 V S
21 , 2 4 , 31 , 3 3 , 34 5 V
VIN
1 2 , 31 , 3 2 , 33 , 3 4 , 35 , 3 6 , 37 V I N
2, 1 0 , 1 1, 1 2 , 1 3, 1 4 , 1 5, 1 6 , 1 7, 1 8 , 1 9, 2 0 , 2 1, 2 3 , 24 , 2 5 , 26 , 2 7 , 28 , 2 9 , 31 , 3 5 , 36 3 . 3 V S
8 7 2 13 -1 4 00 G
If system has APON function, uses J_SW1
If system has no APON function, uses J_SW2
USB, Fan, TP, Multi-Conn B - 31
B.Schematic Diagrams
2 20 u _6 . 3 V _ 6. 3 * 6. 3 *4 . 2
C 80
Schematic Diagrams
5VS, 3VS, 1.5VS
VA
V IN
V IN1
SYS5 V
P C 64
P C6 3
0 .1 u_ 5 0 V _ Y 5 V _ 0 6
0 . 1u _ 5 0 V _Y 5 V _ 06
SY S5 V
P C6 2
0.1 u _ 5 0V _Y 5 V _ 06
1
VA
8
VA
7
V IN
* 1 0m i l _s h o rt _ 04
1 0K _0 4
D D _ ON #
D D _O N _ L A T C H 2 8
D D _O N #
S US B
3 0, 3 3
6
M_ B T N #
M _ B TN #
P W R _S W #
4
30
R1 3 2
D D _ O N _ L A TC H
3
30
PR2 1 1
1 0 K _ 04
VIN 1
VIN 1
2
V IN
P R 2 13
ON
DD_ON "L" TO
"H" FROM EC
P U4
P W R_ S W # 2 8
5
AP_ O N
IN S T A N T -O N
P Q4 4 A
6
D
MT D N 7 0 02 Z H S 6 R
P R 98
1 0 K _ 04
GN D
P 28 0 8 A 1
V D D3
28
P Q 44 B
3
D
M T D N 70 0 2 Z H S 6R
2 G
D D _O N
P C 1 88
16 , 2 3 , 2 8 S U S B #
S
1
5 G
P C1 8 9
S
4
* 0.1 u _ 1 6V _ Y 5 V _0 4
P R2 1 0
ON
*0 .1 u _1 6 V _ Y 5 V _ 0 4
P R2 1 2
ON
1 00 K _ 1 % _0 4
1 0 0 K _ 1 %_ 0 4
ON
C 2 64
C9 1
0. 0 1 u _ 50 V _ X 7 R _ 0 4
0 .0 1 u _5 0 V _ X 7R _ 04
0 . 0 1u _ 5 0V _X 7 R _ 0 4
5VS
1.5VS
N MOS
SYS1 5 V
3A
8
7
5V
P Q 45 A
M TN N 2 0 N 0 3 Q8
2
1
5 VS
S Y S 15 V
P R1 1 2
Power Plane
Z 3 5 06
NMO S
1 .5 V
PC1 9 2
1M _ 04
0 . 1u _ 1 6 V _ Y 5 V _ 04
Z3507
1 .5V S
P Q 1 6A
M TN N 2 0 N 0 3 Q 8
8
2
7
1
P R2 1 4
1M _ 04
3
1 M_ 0 4
V DD 5
5V
4
P C 73
P Q 45 B
M TN N 2 0 N 0 3 Q8
4
5
D D _ ON #
S US B
5
1
3. 3V S
ON
C1 3 0
C1 0 0
C 184
0.0 1 u _ 50 V _ X 7 R _ 0 4
0 . 01 u _ 5 0V _X 7 R _ 0 4
0 .0 1 u _5 0 V _ X 7R _ 0 4
1.5VS_CPU
1 .5 V
N MOS
SYS1 5 V
1 .5 V S _ C P U
8
7
3
NM OS
M T N N 20 N 03 Q 8
2
1
P R7 6
P R1 1 0
P Q4 0 B
M T N N 20 N 03 Q 8
5
P C7 0
5
D D _ ON #
P C7 1
P R1 0 9
0. 1u _ 1 6V _Y 5 V _ 04
1 0u _ 6 .3 V _X 5 R _0 6
*1 0 0 _1 % _ 0 4
SU SB
G
P Q 4A
*M T N N 20 N 0 3Q 8
2
1
P R 73
*2 2 0 _0 4
Z 3 5 10
P Q1 3
*M T N 7 0 02 Z H S 3
1 .5 V S _ CP UE N
P C2 8
P C2 7
PC 2 6
*0 .1 u_ 1 0 V _ X 7R _ 04
* 10 u _ 6 . 3V _X 5 R _ 0 6
PQ 4 B
*M T N N 20 N 0 3Q 8
5
SU SB
* 2 20 0 p _ 50 V _ X 7 R _ 0 4
6
S
2 2 0 0 p_ 5 0 V _ X7 R _0 4
ON
B - 32 5VS, 3VS, 1.5VS
P C6 9
P Q1 4 B
M T N N 20 N 0 3Q 8
6
2 2 0 0p _ 5 0V _X 7 R _ 0 4
4
4
Z3509
P C 1 67
8
7
* 1 M_ 0 4
1 M _0 4
Z 3 5 08
PJ3 MUST SHORT
SYS1 5 V
4
Power Plane
P J7
OP E N _ 2A
1
P Q1 4 A
V DD 3
3A
D
P R 1 92
1 M_ 0 4
3 .3 V
M T N N 20 N 03 Q 8
2
1
3 .3 VS
3
P Q 4 0A
8
7
VA
37
1 .5 V S _ C P U 4 , 7
1 .5 V
4 ,9 , 1 0, 11 , 2 1 , 2 3, 2 7 , 2 9 ,33 ,3 6
1 .5 V S
2 0 ,2 3, 3 6
SY S5 V
3 2 ,3 7
5V
2 1 ,2 4, 3 0 ,3 3 ,3 4
3 .3 V
3 ,4 , 1 2, 14 , 1 5 , 1 6, 1 8 , 1 9 ,20 ,2 1 ,2 3 , 24 ,2 5 , 2 9, 30 , 3 3 ,3 4, 3 5
V IN 1
32
V IN
1 2 ,3 0, 3 2 ,3 3 ,3 4,3 5 , 3 6 , 37
V D D5
32
V D D3
1 4 ,2 3, 2 5 ,2 8 ,2 9,3 2 , 3 7
3 .3 V S
2 ,1 0 ,11 ,1 2 , 1 3 , 14 , 1 5 , 1 6, 1 7 , 1 8 ,1 9,2 0 ,2 1 , 23 ,2 4 , 2 5, 26 , 2 7 ,2 8, 2 9 ,3 0 , 35 ,3 6
S Y S 1 5V
32
5 VS
2 ,1 3 ,17 ,2 0 , 2 1 , 26 , 2 7 , 3 0, 3 5 , 3 6
ON
2
3A
G
S
40 m i l
3.3VS
S Y S 1 5 V V D D3
S US B
10 0 _ 1 %_ 0 4
Z 3 51 5
P Q1 5
MT N 7 0 0 2 Z H S 3
6
4 0m i l
2
P J1 6
3.3V
P R1 1 1
22 0 0 p _5 0 V _ X 7R _ 04
P J 15
3 .3 V
10 u _ 6. 3V _ X 5 R _ 0 6
P C1 9 3
33
6
2
6
1
47 0 p _5 0 V _ X 7 R _ 0 4
P C1 9 0
0 .1 u _ 16 V _ Y 5V _0 4
G
S
5
4 7 0 p_ 5 0 V _ X7 R _0 4
P C1 9 1
PQ 1 6 B
M TN N 2 0 N 03 Q 8
P C7 2
3
4
1 .5 VS_ EN
P Q4 6 B
M T N N 20 N 03 Q 8
Z 35 1 6
3A
P Q 4 6A
M T N N 20 N 03 Q 8
2
1
3
P R 1 13
8
7
3
S Y S 1 5 V V D D5
ON
D
5V
C2 0 4
D
Sheet 31 of 42
5VS, 3VS, 1.5VS
6
B.Schematic Diagrams
5V
ON
PQ 3
*M T N 7 0 02 Z H S 3
Schematic Diagrams
Power 3.3V/5V
S YS5 V
C8 8
VIN 1
Z 36 0 4
P R 2 04
P C 1 83
2 . 2 u _1 6 V _ X 5 R _ 0 6
2 _0 6
VIN
A
P C 18 4
1 0 0 0 p_ 5 0 V _ X 7R _ 04
PR 1 9 6
L GA T E 1
P C1 6 8
0 . 0 1 u _ 50 V _ X 7 R _ 0 4
Z3613 3
P D7
B A T 54 S W GH
A 1
C
A 2
P C1 6 9
0 . 0 1 u _ 50 V _ X 7 R _ 0 4
Z3614 3
P D6
B A T 54 S W GH
A 1
C
A 2
SY S5 V
SY S1 0 V
0. 01 u _ 5 0V _X 7 R _0 4
C
P D 2 0 R B 0 5 4 0S 2
P C 16 2
2 2 00 p _ 5 0V _X 7 R _ 0 4
SY S1 5 V
I N TV C C 2
2_06
6- 13- 4223 1- 28B
P R2 0 3
4 2 2K _1 % _ 0 6
S GN D 4
P C 16 3
Z 36 0 5
2 2 00 p _ 5 0V _X 7 R _ 0 4
Z3606
1 3 7 K _ 1 % _0 4
P GN D
4 . 7 u _ 25 V _ X 5 R _ 08
9
Z3609
INT V C C2
VDD5
S Y S 5V
PQ 1 1
P1 2 0 3 BV
4
V D D5
PL 8
4 . 7 U H _ 6. 8 * 7. 3* 3 . 5
1
2
5A
PJ 2 3
1
C
5
6
7
8
P Q7
P 1 20 3 B V
P R1 8 5
P C 18 5
PD 5
P R1 9 1
1 0 K _ 1% _ 0 4
Z 36 1 2
P R1 8 7
*1 0 0 K _ 1 % _0 4
P C 16 6
P C 1 77
1 u _2 5 V _ 0 8
1 u _ 25 V _ 0 8
*2 . 2 _ 0 6
*2 2 0 p _ 50 V _ 0 4
9 3. 1 K _ 1 % _ 0 6
PC 1 6 5
CSO D1 4 0 SH
A
Z 36 1 1
P D8
*S K 3 4 S A
P C5 4
+
P C1 6 1
P C1 7 0
+
0 . 1 u _ 50 V _ Y 5 V _ 06
P C 18 6
*2 2 0 0p _ 5 0 V _ X7 R _ 04
* 10 0 p _ 50 V _ N P O _0 4
P R2 0 1
* 1 50 u _ 6 . 3V _V _A
S G ND 4
P R2 0 9
*1 5 mi l _ s ho rt _ 0 6
22 0 u _ 6 . 3V _6 . 3 * 6. 3 * 4. 2
1 0K _1 % _ 0 4
2009/12/22
S G ND 4
Sheet 32 of 42
Power 3.3V/5V
P R2 0 8
4
L GA T E 1
1 1 3 K _ 1% _ 0 4
S G ND 4
2
*O P E N - 5m m
OCP
P R 18 6
4. 7u _ 2 5 V _ X 5 R _ 0 8
Z3608
10 Z 3 6 1 0
11
D L
12
13
14
P C1 7 2
1 u _2 5 V _ 0 8
8
C
5
3
4
NC
V OU T
P GO O D
LX
P R1 9 3
15
* 0 . 1 u_ 1 0 V _ X 7 R _ 0 4
1 0 K _ 1 % _0 4
1 u _ 2 5V _ 0 8
1 0 0 0p _ 5 0 V _ X 7 R _ 0 4
P C1 7 5
VD DP
D H
IL IM
P R1 9 8
R PSV
EN /PSV
16
PC 1 7 9
P C5 3
Z3607
BST
17
P C5 2
S GN D 4
S GN D 4
S GN D 4
S YS5 V
I NT V C C2
P R2 0 2
* 1 5m i l _ sh o rt _ 0 6
PR 2 0 0
* 0 _0 6
A
P R 18 8
0 . 0 1 u _5 0 V _ X 7 R _ 0 4
0 . 0 1 u_ 5 0 V _ X 7R _ 0 4
Z3621
R TN
5
6
7
8
1
4
Z3622
VDD3
SY S3 V
5A
2
17
PAD
V DD 3
PJ 2 2
1
2
P C 1 80
1 u _2 5 V _ 0 8
*O P E N -5m m
C
P Q4 1
P 1 20 3 B V
PL 9
4 . 7 U H _ 6 . 8 *7 . 3 *3 . 5
P R 1 84
4
+
* 2. 2 _ 0 6
DL
5
2 . 94 K _ 1 % _ 0 4
6
N .C
N.C
P C 1 76
7
P R2 0 6
8
*4 7 p_ 5 0 V _ N P O _ 0 4
P C1 7 1
Rb
Z3620
V CC
G N D
V O UT
FB
P C1 8 2
Z3619
2
C
9
P C5 6
P D1 8
PD 1 7
* S K 3 4S A
P C 44
P C 1 74
0 . 1 u _5 0 V _ Y 5 V _ 0 6
2 2 0 u_ 6 . 3 V _ 6 . 3 *6 . 3 *4 . 2
P C 1 60
A
Z 3 6 17
1
3
BST
C S O D 1 40 S H
A
Z 3 6 16
PQ 8
P 1 2 0 3B V
5
6
7
8
16
15
PG D
4 . 7 u _2 5 V _ X 5 R _ 0 8
LX
11
10
PC 5 5
0. 1u _ 5 0 V _ Y 5 V _ 0 6
0. 1 u _ 5 0V _Y 5 V _ 0 6
1
2
3
EN
D H
12
N .C
Z 3 6 15
N .C
14
P C1 7 8
P U9
S C4 1 2 A
P C5 7
4. 7u _ 2 5 V _ X 5 R _ 0 8
Z3625
P R 1 97
0_04
4
Z3618
13
1 0K _1 % _ 0 4
S YS5 V
RB 0 5 4 0 S 2
1 0K _1 % _ 0 4
1
2
3
P R 1 89
P R1 9 9
C
Ra
IL IM
1 0 K _ 1 % _0 4
10 0 p _ 50 V _ N P O _ 0 4
P R1 9 4
P C1 8 7
P D2 1
OCP
*9 . 1 K _ 0 4
V IN
P R 2 07
*1 5 m i _l s h o rt _ 06
* 22 0 0 p _5 0 V _ X 7 R _ 0 4
V IN 1
SY S1 5 V
V DD 3
V D D5
S Y S 5V
V IN
31
31
1 4 , 2 3 , 2 5, 28 , 2 9 , 3 1 , 37
31
3 1 ,3 7
1 2 , 3 0 , 3 1, 33 , 3 4 , 3 5 , 36 , 3 7
Power 3.3V/5V B - 33
B.Schematic Diagrams
SC418
P C4 6
P C 18 1
1 u _2 5 V _ 0 8
7
VL D O
A G ND
PC 1 7 3
6
V IN
R T ON
18
Z3601
VD DA
1
2
FB
EN L
PU8
A
19
Z 3 6 03
PAD
S GN D 4
20
Z 3 6 02
FBL
21
7 5 K_ 0 4
S G ND 4
5
6
7
8
2 0 K _ 1 % _0 4
1
2
3
P R1 9 5
1 0 K _ 1 %_ 0 4
1
2
3
PR 1 9 0
0. 1u _ 5 0 V _ Y 5V _0 6
P R2 0 5
Schematic Diagrams
Power 1.5V/0.75V, 1.8VS
5V
3 .3 V
VIN
(1.5V=1.517V)
P R9 4
P R 96
1 . 5 M_ 0 4
1 0 _0 6
P R8 8
10 0 K _ 1% _ 0 4
A
VD DQ
PD 4
R B 0 54 0 S 2
P U3
10 _ 0 6
Z3801
3
Z3802
2
7
V D D QS
DH
* 0. 1u _ 1 0V _ X 7 R _ 0 4
1u _ 2 5V _0 8
*0 . 0 6 8u _ 5 0V _0 6 *1 5m i l _s h o rt _ 06
VSSA
P J 20
*2 0 K _ 1 %_ 0 4
P R9 2
5V
PC3 5
1 0 u_ 6 . 3 V _ X 5 R _ 0 6
P R7 9
* 22 0 u _2 . 5 V _ B _ A
PC 33
P C 15 5
+
D L
1 u _ 25 V _ 0 8
4
P C3 8
0 . 1 u_ 5 0 V _ Y 5V _0 6
15 u _ 25 V _ 6 . 3 *4 . 5 _E LN A
P Q 37
M DS 2 6 5 9
P R 87
21 Z3816
1.5V
V D DQ
OCP
PL 6
7. 1 5 K _ 1 %_ 0 4
22 Z3817
19 Z3818
P Q3 5
MD S 2 65 5
4
20
VT T
VT T
P
P
P
P
EN /PSV
11
VT TEN
GN D
GN D
GN D
GN D
2
1
1
2
25
18
16
17
PD 1 5
1u _ 2 5V _ 0 8
2 . 5 U H _ 10 * 10 * 5
PJ 9
8A
1
+
P C1 4 3
P C 1 50
+
*2 20 u _ 2 . 5V _ B _ A
0 . 1u _ 5 0V _Y 5 V _0 6
* SK3 4 SA
P R1 8 1
* 15 m i _l s h ort _ 0 6
VSSA
S C 48 6
1 .5 VEN
D
D
G
Z 38 1 9
4
1
D
S
P Q 10 B
5 M TD N 7 0 0 2Z H S 6 R
G
P J1 1
S US C #
S
1
P Q1 0 A
MT D N 7 00 2 Z H S 6 R
3 0, 3 1
D D _ ON #
5V
P R1 8 2
P R8 3
1 0 0 K _1 % _ 0 4
P R8 2
* 10 0 K _ 1 %_ 0 4
1 0 0_ 1 % _ 04
D
S US B
G
S US B
PQ 6 B
5 M T D N 70 0 2 Z H S 6 R
G
SU SB
4
V T TE N
6
3
31
DDR3 VDDQ --> 1.5V ( V POWER)
330uF*3 , 10uF*6
VTT-->0.75V ( VS POWER)
10uF*3, 1uF*4
4 0m i l
4 , 1 6 , 3 4 1 . 1 V S _ V T T _P W R G D
V T T_ M E M
0 . 1 u _ 50 V _ Y 5 V _ 0 6
2
G
2
1 6 ,2 8
P C4 8
P Q9
*M TN 7 00 2 Z H S 3
S
1 0 0K _ 1 % _ 04
6
1
D
P C 41
2 P Q 6A
S
MT D N 7 0 02 Z H S 6 R
0 . 1 u_ 5 0 V _ Y 5 V _ 06
S
ON
3 .3 V
5V
1.8VS
3. 3V
P C1 5 7
P U7
3A
V C N TL
1
V OU T
8
E N 1. 8 V S
EN
1
2
D
GN D
P C3 2
P C1 4 8
PQ 5
62 K _ 1 % _0 4
G
* 1 u_ 2 5 V _ 08
P C4 2
0. 1 u _ 50 V _ Y 5V _ 0 6
B - 34 Power 1.5V/0.75V, 1.8VS
P C1 4 9
M T N 7 00 2 Z H S 3
P C 1 56
1 0 u_ 6 . 3 V _ X 5 R _ 0 6
PR8 4
0. 1 u _ 50 V _ Y 5 V _ 0 6
SU SB
S
31
P R1 7 9
1. 2 7 K _ 1 %_ 0 4
VFB
AX6610
0 . 1 u_ 1 0 V _X 7R _ 04
1 0 K _ 04
P C 14 6
P R 81
1 .8 V S
PJ 1 0
4
2
V OU T
3
5V
VS1 .8
1 0 u _6 . 3 V _ X 5 R _ 0 6
1 .8 V S _ P W RG D
1 6 1 .8 V S _ P W RG D
1u _ 2 5V _0 8
6
VIN
VIN
P OK
1 0u _ 6 . 3V _X 5 R _0 6
5
9
7
P C 1 44
2A
P C1 4 5
1 0K _0 4
P R1 8 3
82 p _ 50 V _ N P O_ 0 4
P R1 8 0
1K _ 1 % _ 04
GS7113 6-02-07113-320
AX6610 6-02-06610-320
APL5930KC 6-02-05930-420
1 .5 V
P C1 5 2
3
P R9 3
2
OP E N _ 8 A
PD 1 6
P C3 9
V D DP 2
V D DP 2
P Q3 6
*M D S 2 6 55
4
5V
V DD P 1
1
1u _ 2 5 V _0 8
4
Z 3 8 15
VSSA
12
13
47 K _ 1 % _0 4
IL IM
LX
VDD Q
+ P C1 5 8
PC 4 5
0 . 1 u _5 0 V _ Y 5 V _ 0 6
PR8 9
*1 5 m li _ s ho rt _ 0 6
23 Z3814
1
2
3
V C CA
Z3809 14
15
PC3 6
*1 0 u _6 . 3 V _ X 5 R _ 0 6
O P E N_ 2 A
VT TS
5
Z3807
PC 5 1
1.5A
1
PC3 4
2
V T T _ ME M
1 0 u_ 6 . 3 V _ X 5R _ 06
VTT_MEM
Sheet 33 of 42
Power 1.5V/0.75V,
1.8VS
P R8 0
P C4 9
P C4 0
*1 0 u _6 . 3 V _ X 5 R _ 0 6
B.Schematic Diagrams
Z 3 80 8
P C 37
Z3806 10
1 00 0 p _5 0 V _ X 7 R _ 0 4
10 _ 0 6
PR 9 0
1 0 0 K _1 % _ 0 4
0 . 1 u_ 5 0 V _Y 5V _ 0 6
BST
C O MP
P C4 3
PC1 5 4
FB
RE F
P C1 5 3
9
PC1 4 7
5 6 0 u_ 2 . 5 V _ 6. 6* 6. 6 * 5. 9
6
8
Z3805
C
Z3803
PR9 1
*1 5 m li _ s ho rt _ 0 6
24 Z3812
Z3813
C
P R8 6
T ON
A
1 u _ 25 V _ 0 8
CS O D1 4 0 S H
A
1 u_ 2 5 V _ 08
5
6
7
8
PR 9 7
1 K _ 1 %_ 0 4
Rb
D D R 1 . 5 V _P W R G D 1 6
1
2
3
1 0 0p _ 5 0V _N P O_ 0 4
5
6
7
8
PC 5 0
5
6
7
8
P C 59
1
2
3
Ra
P R8 5
DD R1 .5 V _ P W RG D
P GD
VIN
P C 58
10 _ 0 6
C
P R 95
OP E N _ 3 A
7 ,2 0
1 2 , 30 , 3 1 , 3 2, 3 4 , 3 5 , 36 , 3 7
2 1, 2 4 , 3 0 , 31 , 3 4
3 , 4, 12 , 1 4 , 15 , 1 6 , 1 8, 1 9 , 2 0 , 21 , 2 3 , 24 , 2 5 , 2 9, 3 0 , 3 1 , 34 , 3 5
4, 9 , 1 0 , 11 , 2 1 , 2 3, 2 7 , 2 9 , 31 , 3 6
1 0 ,1 1
1 . 8V S
VIN
5V
3 . 3V
1 . 5V
V T T_ M E M
0 . 0 1 u _5 0 V _ X7 R _0 4
Schematic Diagrams
Power 1.1VS_VTT
5V
VIN
A
OCP
PD 9
R B 05 4 0 S 2
1.1VS_VTT=0.75 X (1+PR101 / PR102)
C
P R 99
6 .4 9K _1 % _ 04
5
6
7
8
5
6
7
8
P C 16 4
+
PQ 3 9
M D S 2 6 59
P Q 38
* IR F 7 4 13 Z P B F
1 5u _ 2 5V _6 . 3 *4 . 5 _ E LN A
1.1VS_VTT
4
V T T _S E N S E 6
2
3
1
2
3
1
4
1
1
9
5
6
7
8
3
4
4
P Q4 2
MD S 26 5 5
P Q4 3
MD S 26 5 5
C
VC C
5
6
7
8
B ST
V O UT
P D 19
4
SK3 4 SA
A
2
3
1
2
3
1
G ND
5
D 1
D 0
R TN
6
7
17
PAD
P C6 0
+
*OP E N -1 2 mm
P C6 8
0. 1 u _ 50 V _ Y 5 V _ 0 6
+
5V
P R1 0 6
P R 10 5
P R 1 01
P C6 5
0 _ 04
1 0 K _ 1% _ 0 4
*2 0 p_ 5 0 V _ N P O_ 0 4
P C 15 9
P C 1 51
1 u _ 25 V _ 0 8
Sheet 34 of 42
Power 1.1VS_VTT
*9 0 . 9K _1 % _ 04
P C 66
P R 1 02
0 . 1 u_ 1 0 V _X 7 R _ 0 4
2 4 K _ 1% _ 0 4
(1.1VS_VTT=1.067V)
PJ 1 4
1
2
4 0m i l
P R1 0 7
5V
1 0 K_ 0 4
PJ 1 3
1
2
1 .1V S _V TT _ E N _ R
4 0 m li
D 12
S C D3 4 0
C
P R1 0 0
*1 0 0K _ 1 % _0 4
A
3
D
P Q 1 2B
5 * 2N 7 00 2 K D W
G
6
2
G
1
4
S
P R1 0 4
*1 0K _0 4
PJ 1 2
4 0m i l
S
2
1 6 1 . 1V S _V T T _ E N
P Q1 2 A
*2 N 7 0 02 K D W
1
D
P R 1 08
1 0 0K _1 % _ 04
P C6 7
*1 u_ 2 5 V _ 08
2 ,4,6 ,7 , 1 4 ,15 ,1 6 , 19 , 2 0 ,21 , 3 5 ,3 6 1 .1 V S _ V T T
3 , 4 ,1 2 , 14 , 1 5 ,16 ,1 8 , 19 ,2 0 , 2 1, 2 3 ,2 4,2 5 , 2 9, 3 0 , 3 1, 33 ,3 5 3.3 V
2 1, 2 4 , 3 0, 31 ,3 3 5V
1 2 ,3 0,3 1 , 3 2, 3 3 , 3 5, 36 ,3 7 V I N
Power 1.1VS_VTT B - 35
B.Schematic Diagrams
DL
8
2
5 6 0u _ 2. 5V _ 6 . 6 *6 . 6 *5 . 9
15
16
2
PG D
FB
1 .1V S _V T T
P J2 1
LX
10
FB
V T T 1.1 V S
PL 7
0 .5 6U H _ 1 0* 1 0* 4. 1
11
4,1 6 , 3 3 1. 1 V S _ V T T _P W R GD
25A(15A)
0 .1u _ 5 0V _Y 5V _0 6
5 6 0 u_ 2 . 5 V _6 . 6 *6 . 6 *5 . 9
EN
PU 5
S C 41 2 A
D H
13
12
G 1
3. 3V
1 0 K_ 0 4
G 0
1 .1 V S _ V T T_ E N _R
P R1 0 3
IL IM
ON
14
P C6 1
Schematic Diagrams
Power VGFX_Core
1 .1V S _ V TT
PJ 4
2
_0
_1
_2
_3
P R7 2
1 K _0 4
4 0m i l
1
2
D F GT _V R _ E N
3.3VS
5 VS
P R4 2
P R4 8
4 70 _ 04
1 0 K_ 0 4
V IN
4 . 7 u_ 25 V _ X 5R _ 0 8
*4 . 7 u_ 25 V _ X 5R _ 0 8
4
33
P Q22
MD S 2 65 5
4
MD S 2 65 5
GN D _3 21 1
GN D _3 2 11
P R2 2 1
P R2 2 2
GN D _3 2 11
G N D _ 32 1 1
P R2 2 4
1 00 _ 1% _0 4
P R2 2 5
1 00 _ 1% _0 4
P R 22 3
S K 3 4S A
Place RTH1 close to
inductor on the same layer
P C 12 5
+
P R 1 67
1 10 K _1 %_ 0 6
P C2 0
P C 12 7
P R3 6
1 50 0 p_ 5 0V _ 04
2 2 0p _ 50 V _N PO _0 4
1 80 K _1 %_ 0 4
GN D _ 3 21 1
4 2 2K _ 1% _ 06
GP U V C C S EN S E 7
RT 1
10 0 K_ N T C _ 06 _ B
2
1
3 2 11 _ C S C O M P
P R 22 0
3 21 1 _C S C O M P
GPU
*0_ 0 4
3 3 2K _ 1% _ 06
1
PR 21 9
2 0 0K _ 1% _ 04
CPU
80 . 6K _ 1 %_ 04
0
3 2 11 _C S C O M P
App.
P D1 2
A
CS COM P
16
CSREF
C SF B
15
14
RAM P
L L INE
13
12
R T
RPM
IRE F
9
10
A GN D
2
1
P Q 23
5 6 0u _2 . 5 V _6 . 6* 6. 6 *5 . 9
* 2. 2 _0 6
2 .2 u_ 16 V _ X5 R _ 06
17
ILIM
P R2 1 8
P R 16 5
P C 19 4
7 .5K _ 1% _ 04
GPU
PC9 2
P C 80
5VS
3 2 11 _D R V L
A GN D
5VS
GN D _3 2 11
19
P GN D
47 0p _ 50 V _X 7 R _0 4
P R4 9
0 _0 4
PL 3
1 .0 U H _1 0* 10 *4 .5
1
2
18
11
8
3 2 11 _S W
DR V L
GP U
20 K _1 % _0 4
3 2 11 _D R V H
P V CC
A D P 3 21 1
C OMP
7
4 7p _ 50 V _N P O_0 4
P R 43
22
21
* 22 00 p _5 0 V_ X 7 R _0 4
6
P J 19
O PE N _8 A
23
20
FB
P C2 3
V GF X _C O R E
GP U
P C 13 2
F BR TN
5
22 0p _ 50 V _N P O_ 04
1
2
3
26
27
28
25
V ID6
V ID5
V ID4
30
31
29
V ID2
V ID 3
SW
PU2
(0. 7V~1 .77V)
P C1 4
0.2 2 u_ 50 V _ 06
DRV H
C LK E N #
PC 19 5
PR 50
1K _ 1% _ 04
BST
IMON
3
4
GPU
VIN
P R2 2 6
1 K _ 1% _0 4
P R 24 0
16 0K _ 1 %_ 04
distribute evenly betw een N side and Sside,
pref erably on secondary side.
GP U V S S S E N S E 7
P C 19 6
P C 11 2
1 00 0p _ 50 V _X 7 R _ 04
1 0 00 p_ 5 0V _ X7 R _ 04
GN D _3 21 1GN D _ 3 21 1
2 ,4 , 6 ,7,1 4,1 5 , 16 ,19 ,2 0,2 1,3 4 ,36 1. 1 V S _V T T
3,4 , 12 , 14 ,1 5,1 6,1 8 , 19 ,20 ,2 1,2 3,2 4 ,25 ,29 ,3 0,3 1,3 3 ,34 3. 3 V
4, 9 ,1 0,1 1,2 1 , 23 ,27 ,2 9,3 1,3 3 ,36 1. 5 V
7 V G F X_ C OR E
1 2,3 0 , 31 ,32 ,3 3,3 4,3 6 ,37 V IN
2 ,1 3,1 7,2 0 , 21 ,26 ,2 7,3 0,3 1 ,36 5V S
2 , 10 , 11 , 1 2,1 3,1 4 , 15 , 16 , 17 ,1 8,1 9,2 0 , 21 ,23 ,2 4,2 5,2 6 , 27 ,28 ,2 9,3 0,3 1 ,36 3. 3 V S
B - 36 Power VGFX_Core
15A(7A)
C
2
3 21 1_ C L K E N #
P R 38
0 _ 06
5
6
7
8
*1 0K _ 0 4
P C1 9
24
V CC
P WR GD
1
2
3
4. 7 K _1 %_ 0 4
G N D _ 32 1 1
5
6
7
8
0.1 u_ 5 0V _ Y 5 V _0 6
1
P Q18
MD S 2 65 9
4
P R 21 7
0_ 04
1
2
3
P R6 1
V ID 1
P R 34
PC 18
V ID0
EN
32
3. 3VS
PC 21
VGFX_CORE
5
6
7
8
GF X _IMO N
P C 83
P C1 1 6
1 u_ 6 . 3V _ X5 R _ 04
7
0 . 1u _ 50 V _Y 5 V _0 6
V GF X_ V OR E_ P G
*0 . 01 u_ 5 0V _ X 7R _0 4
P R6 2
*10 K _ 1% _0 4
PC5
1 0_ 06
PC7
Sheet 35 of 42
Power VGFX_Core
4 . 7 u_ 25 V _ X 5R _ 0 8
P R4 1
1.1 VS_ VTT
10 0 0p _5 0 V _X 7 R _ 04
B.Schematic Diagrams
7 D F GT _V R _E N
* 0. 1 u _1 0V _ X 5R _0 4
P J5
3. 3 V S
D F GT _V I D _ 0
D F GT _V I D _ 1
D F GT _V I D _ 2
D F GT _V I D _ 3
D F GT _V I D _ 4
D F GT _V I D _ 5
D F GT _V I D _ 6
*0 . 01 u _5 0V _ X 7 R _0 4
D F GT _V I D _4
D F GT _V I D _5
D F GT _V I D _6
P C 1 34
7
7
7
P C 13 3
D F GT _V I D
D F GT _V I D
D F GT _V I D
D F GT _V I D
P R 70
PR6 9
PR6 8
P R 67
P R 66
PR6 5
PR6 4
7
7
7
7
4 0 mi l
1
1K _ 04
1 K_ 0 4
1 K _0 4
* 1K _ 04
*1K _ 0 4
1K _ 0 4
*1 K _0 4
10 K _0 4
*1 K _0 4
*1 K _0 4
*1 K _ 04
1 K _ 04
1K _ 04
*1 K _0 4
1 K _0 4
P R 71
P R 59
PR5 8
PR5 7
P R 56
P R 55
PR5 4
PR5 3
3. 3 V
Schematic Diagrams
V-Core
V IN
FOR EMI
V RT T
TT S N S
A GN D
A GN D
S GN D 2
* 33 0u _ C A R 3 1 5L
0. 1 u _5 0V _ Y 5 V _0 6
P C7 6
0 . 1 u_ 5 0V _ Y 5 V _0 6
P C9 7
33 0 u_ 2 . 5V _ V _ A
CS_ PH1
*3 3 0u _ 2. 5 V _V _ A
+
56 0 u_ 2 .5 V _ 6. 6 *6 . 6 *5 . 9
A
1 00 _ 1% _ 04
+
+
* 33 0 u_ 2 . 5V _ V _A
0 . 1u _5 0 V _Y 5 V _ 06
0 . 1u _ 50 V _ Y5 V _ 06
PC1 4 0
0 . 1 u_ 5 0V _ Y 5V _ 0 6
P C 79
PC3
P C2 5
0 . 1u _ 50 V _ Y 5V _ 0 6
P C2 2
P C 75
0. 1 u _5 0V _ Y 5 V _0 6
0. 1 u _5 0 V _Y 5 V _0 6
P C3 0
0. 1 u _5 0V _ Y 5 V _0 6
P C 1 28
0 . 1u _5 0 V _Y 5 V _ 06
*4 . 7 u_ 2 5V _ X 5R _0 8
PC9 8
0 . 1 u_ 5 0V _ Y 5V _ 0 6
1 5 u_ 2 5V _ 6 . 3* 4. 5 _E L N A
P C 88
C
D
S
2 2 0u _ 6. 3 V _ 6. 3 *6 . 3* 4. 2
S
D
C S _P H 1
+
+
5 VS
G
G
HD R 2
+
P R 1 78
P C 14 1
P C 1 42
P C 1 39
P Q 31
* I R F H7 9 23
P C1 3 7
P Q 26
M D U 2 6 57
D
P C 20 1
C S _ P H2
P C 13 5
CS R E F
P R 2 33
10 0 _0 6
PR1 7 6
10
T T SN S 1 1
12
49
2 20 p _5 0 V _NP O _0 4
Sheet 36 of 42
V-Core
10 _ 06
CS _ PH2
P R 12 1
39 . 2K _ 1 %_ 0 4
10 _ 06
P C1 3 1
VIN
V CO RE
24A
P R 1 72
SK3 4 SA
* 4. 7 u_ 2 5V _ X 5 R _ 08
P R 12 6
1 . 6 K _1 % _0 4
P R1 7 1
5 . 1_ 0 6
P D 14
P C 1 05
RSP
RSN
PR7 7
5. 4 9 K _1 % _0 4
P R5
10 0 _0 6
BST 1
0 . 1u _ 50 V _ Y5 V _ 06
P C 20 2
1 5 0p _ N P O_ 5 0V _ 04
0. 1 u_ 5 0V _ Y 5 V _ 06
P R9
2_ 0 6
36
35
34
33
32
31
30
29
28
27
26
25
P C 1 29
S GN D 2
P C 86
P C 81
1 5 0p _ N P O_ 5 0V _1042 p_ 5 0V _ N P O_ 0 4
+
VCORE
P Q3 3
MD U 26 54
S
PC9 3
B S T1
D RVH1
SW 1
SW FB1
PVC C
D R V L1
P GN D
D R V L2
SW FB2
SW 2
D RVH2
B S T2
P Q2 8
MD U 2 65 4
G
G
P C 95
2
P C2 9
10 0 0p _ 50 V _X 7 R _ 04
SW FB3
PW M 3
O D3 #
I LI M
C S C O MP
C SSUM
CSREF
LL I N E
RAM P
R T
RPM
IR E F
I MON
CL K E N#
EN
P W R GD
I MON
CL K EN#
F B RT N
FB
C OM P
TR D E T #
V A RF R
PC2 0 0
5 VS
ADP321 2
VCC
PH1
PH 0
DPRSL P
P S I#
V ID 6
V ID5
V ID4
V ID3
V ID 2
V ID1
V ID0
6
P U1
37
38
39
40
41
42
43
44
45
46
47
48
4 ,1 6 DE L A Y _ P W RG D
V R _ON 1
2
3
4
5
6
7
T RDET # 8
9
5V S
+
P L5
0 . 36 UH _1 2 .9 *1 4 *3 . 8
S
3K _ 1 %_ 0 4
G
+
H DR 1
S GN D 2
24
23
22
21
20
19
18
17
16
15
14
13
P R4
3 K _1 % _0 4
+
5V S
PL 4
0 . 3 6U H _ 12 . 9* 14 *3 . 8
24A
4 H _ P R O C H O T#
P Q2 7
MD U 26 54
G
P Q 32
M D U 2 6 54
S
1 . 1V S _ V T T
SK3 4 SA
1 . 5V S
P C1 3 0
A
1 . 5V
P C6
P R1 7 0
5 . 1_ 0 6
P D 13
S
S
G
C
0 . 22 u _5 0 V _0 6
B S T2
1 0_ 0 6
D
P R 2 43
2 _0 6
S GN D2
G
D
D
P C8 2
P R2 1 6
P Q 47
M TN 70 02 Z H S 3
2 20 p _5 0 V _NP O _0 4
P R 2 34
0 _0 4
R SP
V C C _ S E NS E 6
P C 20 4
P R 2 35
0 _0 4
* 10 0 0p _5 0 V _X 7 R_ 04
H
H
H
H
H
H
H
_V I D
_V I D
_V I D
_V I D
_V I D
_V I D
_V I D
0
1
2
3
4
5
6
P R 23 6
PJ 1
10 0 _1 % _0 4
4 0m i l
1
6
6
6
6
6
6
6
*1 K _0 4
*1 K _ 04
* 1K _ 0 4
1K _ 0 4
1 K _0 4
* 1K _ 0 4
1K _ 04
P R2 0
*R _ 0 4
V S S _S E N S E 6
P R 1 55
0_ 0 4
2 PR1 5 4
P R6
P S I#
R SN
PR2 6
PR2 7
P R 28
PR2 9
PR3 0
P R 31
PR3 2
6
0_ 0 4
64 9 _1 % _0 4
S GN D 2
P R 19
6 P M _D PR S LP V R
*6 4 9_ 1 %_ 0 4
1 K_ 0 4
1 K _0 4
1 K _ 04
*1 K _0 4
*1 K _ 04
1 K _ 04
*1 K _0 4
1 u_ 2 5V _ 08
P R 2 37
0_ 0 4
5 VS
5 VS
P R 1 43
P R 23 8
P R 16 9
5 . 1 K _1 % _0 4
7 . 3 2K _ 1 %_ 0 4
P R 15 6
1 0 0K _ 0 4
0 . 0 1u _5 0 V _X 7 R_ 04
* R _ 04
6
D
5
D
M TD N 7 00 2Z H S 6R
1 6, 2 8 V C OR E_ ON
P J1 8
2
G
1
4
2
P C 20 3
1 0 0K _ N T C_ 06 _ B
S GN D 2
3
G
P Q 20 A
1
P Q2 0B
V R _ ON
MT D N 7 0 02 Z H S 6 R
T R DE T #
R T2
P R 23 9
2
1 0 K _0 4
4 0 mi l
1
T TS N S
PR1 3
PR1 4
P R 15
PR1 6
PR1 7
P R 18
PR3 3
3. 3 V S
S
P C 10 8
S
P R 1 19
*1 0K _ 04
4, 9 , 1 0, 1 1 , 21 , 2 3, 2 7, 2 9 , 31 , 3 3
2 0 , 23 , 3 1
2, 4 , 6, 7 , 1 4, 1 5 , 16 , 1 9, 2 0, 2 1 , 34 , 3 5
6
1 2, 3 0 , 31 , 3 2, 3 3, 3 4 , 35 , 3 7
2 , 13 , 1 7, 2 0 , 21 , 2 6, 2 7, 3 0 , 31 , 3 5
2, 1 0 , 11 , 12 , 1 3, 1 4 , 15 , 1 6, 1 7, 1 8 , 19 , 2 0, 2 1 , 23 , 24 , 2 5, 2 6 , 27 , 2 8, 2 9, 3 0 , 31 , 3 5
1 .5 V
1 . 5 VS
1 . 1 VS _ V T T
V C OR E
V IN
5 VS
3 . 3 VS
* 0. 1 u _1 0 V_ X 5R _0 4
V-Core B - 37
B.Schematic Diagrams
P R2
G
D
P R 1 75
1 .6 9 K _1 % _0 4
P Q 34
* I R F H 7 92 3
S
3 . 3V S
PR2 2 9
P R 23 0
P R 2 31
PR2 3 2
3 .3 VS
S GN D 2
C S C O MP
CSSU M
C S REF
CS COM P
6 80 K _ 1% _ 04
1 6 2K _ 1 %_ 0 6
47 . 5 K _1 % _0 4
8 0. 6 K _ 1% _0 4
2
P C 1 38
4 70 p_ 5 0V _ X 7R _0 4
0 . 22 u _5 0 V _0 6
P R 24 2
7 3 . 2K _ 1 %_ 0 4
P Q2 9
MD U 26 5 7
D
1 0 00 p _5 0 V _X 7R _0 4
S
1 K _ 04
P C 19 9
D
P R 22 8
4 . 7 u_ 2 5V _ X 5R _0 8
1
RT 3
10 0 K _N TC _0 6_ B
P C 13 6
1 5 00 p _5 0V _ 0 4
PC7 8
1 62 K _ 1% _ 06
PC3 1
VIN
P R 24 1
RT1 close to PL6
P C 10 1
*1 5 u_ 25 V _ 6. 3 *4 . 5 _E L N A
P C1 9 8
1 u_ 2 5V _ 0 8
2 00 K _1 % _0 6
2 00 K _1 % _0 6
1 5u _ 25 V _ 6. 3 *4 . 5_ E L N A
P R 17 3
P R 16 8
* 4. 7 u_ 2 5V _ X 5 R _ 08
P C 10 6
P R2 2 7
*4 7 K _0 4
CS _ PH1
CS _ PH2
PC8 7
S GN D 2
*1 5u _ 25 V _ 6. 3 *4 . 5_ E L N A
P C 1 97
*1 n_ 5 0V _ 0 4
Schematic Diagrams
AC_IN, Charger
CHARGER
# Charge Current 3.0A
VA
# Charge Volta ge 1 2.6V
4
V IN
1
2
3
0 . 1 u _5 0 V _ Y 5 V _ 06
*1 0m i l _s h or t _0 4
P R1 1
0 . 1 u _5 0 V _ Y 5 V _ 06
0. 1 u _ 50 V _ Y 5 V _ 0 6
0 . 1 u _5 0 V _ Y 5 V _ 06
32
31
30
29
28
27
26
25
M B 3 9A 1 3 2
S GN D 6
T OTAL
POWER
ADJ
PR1 6 6
1 0 K _1 % _ 04
P R1 6 4
V D D3
VC C
-I N C 1
+ INC 1
A C IN
A C OK
-I N E 3
AD J 1
C O MP 1
V IN
C TL 1
G ND
VR EF
TRERMAL PAD
RT
C S
A DJ 3
BATT
S G ND
24
23
22
21
20
19
18
17
33
PC 9 9
1 K _1 % _ 04
S MC _ B A T
P R1 4 7
A
B
P Q 30
S MD _ B A T
P R1 4 9
CHARGE
CURRENT
ADJ
P C 13
P R1 3 6
PC1 0
S GN D 6
2 2K _ 1 % _0 4
S G ND 6
2 2K _ 1 % _0 4
P C1 0 2
1 0 00 p _ 50 V _ X 7R _ 04 P R 1 50
S G ND 6
D TC 11 4 E U A
P C 1 17
P R1 5 2
D9
B A V 9 9 R E CT IF IE R
C
AC
A
D8
B A V 9 9 R E CT IF IE R
C
AC
A
D7
B A V 9 9 R E CT IF IE R
S GN D 6
S GN D 6
28
1 0 K _ 1% _ 0 4
B A T _ V OL T
S GN D 6
C
AC
A
D6
B A V 9 9 R E CT IF IE R
E
P D1 1
U D Z 1 6B
PR1 6 3
2 0 K _1 % _ 04
28
C
A C _I N #
C
0 . 1u _ 5 0V _Y 5 V _ 0 6
A
4 9. 9 K _ 1 %_ 0 4
B A T_ D E T
P C1 0 0
*2 2 p _5 0 V _ N P O _0 4
P C9 6
1 0 00 p _ 50 V _ X 7R _ 04 P R 1 45
AC
S G ND6
1 K _1 % _ 04
0 . 01 u _ 50 V _ X 7R _ 04
1 0K _0 4
C
V OL T _S E L
P C1 2 6
1 0 K _0 4
P C 11 4
V DD 3
R1 7
P R 15 8
VA
4. 7 u _ 25 V _ X 5 R _ 0 8
P C1 1 5
4. 7 u _ 25 V _ X 5 R _ 0 8
4. 7 u _ 25 V _ X 5 R _ 0 8
P C1 1 0
4. 7u _ 25 V _ X 5 R _ 0 8
P C1 1 9
4 . 7u _ 2 5V _ X 5 R _ 0 8
CT L 1
P C9 4
1 0 0p _ 5 0V _ N P O_ 0 4 P R 1 40
1 0K _ 1 % _0 4
0. 1 u _ 50 V _ Y 5 V _ 0 6
0. 1 u _ 50 V _ Y 5 V _ 06
0. 1 u _ 50 V _ Y 5 V _ 0 6
1
2
3
4
5
6
7
8
CT L 2
C B
OU T -1
LX
VB
O U T -2
P GN D
C E LL S
P C 1 21
*0 _ 0 4
VA
9
10
11
12
13
14
15
16
P C1 2 2
-I N E 1
O UT C 1
OU T C 2
+ INC 2
-I N C 2
AD J 2
C O MP 2
C OM P 3
PU 6
P C 1 23
P C1 1 8
PIN 25th
FOR 2S CONNECT TO GND
FOR 3S CONNECT N.C.
FOR 4S CONNECT TO VREF PIN
V A
P C 12 4
4 . 7u _ 2 5V _ X 5 R _ 0 8
P C 11 1
P R 1 44
R B 0 54 0 S 2
V IN
P C1 2 0
5
6
4
P C 10 7
1 u _2 5 V _ 08
A
39 . 2 K _ 1% _ 0 4
0 . 1 u _5 0 V _ Y 5 V _ 06
P Q2 5 B
A P 6 90 1 GS M
0 . 1 u_ 5 0 V _Y 5V _ 0 6
0 . 1 u_ 5 0V _Y 5V _0 6
0_ 0 4
P R 12
PC1 1 3
V _B A T
0 . 1u _ 5 0V _ Y 5V _ 0 6
PR1 1 5
P C 1 04
P R1 4 6
0 . 02 _ 1 %_ 3 2
3
P R1 5 7
PD 3
C
P C 10 3
PL 2
4 . 7 U H _6 . 8 *7 . 3 *3 . 5
8
0 . 1u _ 5 0V _ Y 5 V _ 06
0 . 1u _ 5 0V _ Y 5 V _ 0 6
P C1 5
# Total Pow er 60W
7
* 0_ 0 4
V_ BAT
PC1 6
PC1 7
4. 7 u _ 25 V _ X 5 R _ 0 8
0 _ 04
10 0 K _ 1% _ 0 4
1 0K _ 1 % _0 4
4 . 7 u_ 2 5 V _X 5R _0 8
PC1 2
PR1 1 7
P R 16 1
1 30 K _ 1 %_ 0 4
2
1
P C 11
PR 1
1 0K _ 0 4
P Q2 5 A
A P 6 90 1 GS M
P R 1 14
0 . 0 2 _1 % _ 32
3
2
1
0 _0 4
0 . 1 u_ 5 0 V _Y 5 V _ 0 6
PR1 1 8
*0 . 3 3 u_ 5 0 V _0 8
0. 1u _ 50 V _ Y 5 V _ 06
P Q 17
P 2 0 03 E V G
8
7
6
5
PR1 6 2
PC 2
VA
PC7 7
P C1
* 0. 1 u _ 50 V _ Y 5 V _ 0 6
0.5V/1A
0.5V/1A
V_ BAT
TO T A L_ C U R
PIN 17th CONNECT
TO BAT CONN.
CU R_ S E NS E
E4120
P R1 3 8
5
1 02 K _ 1 %_ 0 4
PR 2 3
28
28
28
V OL T _ S E L
P Q2 1
A O3 4 0 9
D
S
V _B A T
SYS5 V
P R 15 3
3 0 0K _1 % _ 04
2 M_ 1 % _0 4
B A T _ V OL T _ R
P R1 3 9
P R 14 8
P R 1 41
1 0 0K _ 1 % _0 4
1 0 0 K _1 % _ 04
G
G
P C1 0 9
60 . 4 K _ 1% _ 0 4
0 . 1u _ 5 0V _ Y 5V _ 0 6
6
28
C H G_ E N
D
2
G
S
P Q 1 9B
5 M TD N 7 0 0 2Z H S 6 R
G
4
P J 17
O P E N - 1m m
6-21-D34B0-105
S
P R 13 5
*1 5m i l _s h o rt _0 6
2
PQ 1
G
M T N 7 00 2 Z H S 3
S G ND6
SY S5 V
V D D3
VA
VIN
B - 38 AC_IN, Charger
5
3
D
1
D
P Q2
MT N 7 0 02 Z H S 3
CT L 1
1
PR1 5 1
MT D N 7 00 2 Z H S 6 R
S Y S 5V
S
P Q1 9 A
4
3
2
1
J B A T TA 2
* B T D -0 5 TI 1 G
E5120Q
V C H G_ S E L 2 8
7 6. 8 K _ 1 % _0 4
P R2 1
2 0 0 K _ 1% _ 0 4
P R2 2
* 1 0m i _l s h ort _0 4
S MC _ B A T
S MD _ B A T
B A T_ D E T
D
S YS5 V
S
B.Schematic Diagrams
PC 7 4
0 . 1 u _5 0 V _ Y 5 V _0 6
PL 1
H C B 45 3 2 K F -8 00 T 6 0
1
2
G ND 1
G ND 2
4
P R 11 6
20 0 K _ 1% _ 0 4
JA C K 1
50 9 3 2-0 0 3 01 -0 0 1
Sheet 37 of 42
AC_IN, Charger
P Q2 4
P 20 0 3E V G
5
6
7
8
3 1, 3 2
1 4 , 2 3, 25 , 2 8, 29 , 3 1 , 32
31
1 2 , 3 0, 31 , 3 2, 33 , 3 4 , 35 , 3 6
4
3
2
1
J B A T TA 1
B TD -0 5T C 1 B
Schematic Diagrams
Click Board
CLICK BOARD
C5VS
CVDD3
CR360
CR359
220_04
220_04
1
C5VS
CC3
*0.1u_16V_Y5V_04
1
POW ER O N
LED
CR361 CR358
220_04 220_04
CGND
Y
SG
CLED_BAT_FULL#
CLED_ACIN#
CLED_BAT_CHG#
6-52-55002-04B
6-52-55001-040
6-52-55002-042
6-21-91A00-106
6-21-91A10-106
6-20-94A70-104
RY-SP155HYYG4
4
2
SG
CLED_PWR#
CGND
6-21-91A00-106
6-21-91A10-106
6-20-94A70-104
RY- SP155HYYG4
4
1
CLED_PWR#
2
CLED_ACI N#
3
CLED_BAT_FULL#
4
CLED_BAT_CHG#
5
6
85201-06051
6-52-55002-04B
6-52-55001-040
6-52-55002-042
Sheet 38 of 42
Click Board
E5120Q
CSW1~ 4
4
3
1
3
RI GHT
K EY
CSW1
TJG-533-S-T/R
2
4
1
3
CTPBUTTON_L
CGND
CSW2
TJG-533-S-T/R
CH3
1
9
8
7
6
2
3
4
5
MTH237D91
CGND
2
4
CH1
1
9
8
7
6
2
3
4
5
CGND
CH4
1
9
8
7
6
2
3
4
5
MTH237D91
CGND
CGND
CSW3
*TJG-533-S-T/R
2
4
RI GHT
K EY
1
3
CTPBUTTON_L
CGND
6-53-3150B-245
6-53-3050B-240
6-53-3050B-241
MTH237D91
CGND
1
3
CTPBUTTON_R
CGND
6-53-3150B-245
6-53-3050B-240
6-53-3050B-241
2
3
4
5
LI FT
KE Y
5
6
LI FT
KE Y
1
CTPBUTTON_R
CGND
6-53-3150B-245
6-53-3050B-240
6-53-3050B-241
CH2
CSW4
*TJG-533-S-T/R
2
4
5
6
2
1
5
6
6-20-94A50-104
6-20-94AA0-104
6-20-94A70-104
CGND
CJ_TP3
1
CTP_CLK
2
CTP_DATA
3
CTPBUTTON_L
4
CTPBUTTON_R
5
6
85201-06051
5
6
CGND
CGND
CJ_TP2
CD26
6-53-3150B-245
6-53-3050B-240
6-53-3050B-241
9
8
7
6
MTH237D91
CGND
CGND
CGND
Click Board B - 39
B.Schematic Diagrams
1
CTP_DATA
2
CTP_CLK
3
4
85201-04051
2
CGND
CJ_TP1
Y
CD27
2
BAT LED
3
CC1
*0.1u_16V_Y5V_04
3
CC2
0.1u_16V_Y5V_04
CVDD3 CVDD3
1
CVDD3 CVDD3
Schematic Diagrams
Audio Board/USB
USB PORT
A _U S B V C C
AL 5
H C B 1 6 0 8K F -12 1 T 25
A _ U S B V CC
AU 1
5
6
50 mil s
+
F L G# V OU T 1
5 0mi ls
2
V I N 1 V OU T 2
A C9
3
1 0u _ 1 0V _ Y 5V _ 0 8
4
AC 1
A C7
1 0 0u _ 6 . 3V _ B _ A
0 . 1u _ 1 6V _ Y 5V _ 0 4
7
A C5
A C6
A J_ U S B 1
8
V I N 2 V OU T 3
0. 1u _ 16 V _ Y 5 V _ 0 4
0 . 1u _ 16 V _ Y 5 V _ 0 4
1
EN #
A US B _ P N 2
A R1 0
L61
4
1
*1 0 mi l _ sh o rt _ 04
3
V+
A G ND
A US B _ P N2 _ R
2
A US B _ P P 2 _ R
3
GN D
D A TA _ L
A US B _ P P 2
R T 97 1 5B GS
A G ND
A G N D A GND
A GN D
1
2
*A W C M2 0 1 2F 2 S -1 6 1T 0 3
D A TA _ H
G ND 1
GN D2
G ND 3
GN D4
A _5 V
A GN D
A _ US B VC C2
60 mil
A _U S B V C C
4
6-02-09715-920
A R1 1
G ND
*1 0 mi l _ sh o rt _ 04
B.Schematic Diagrams
U S 0 4 03 6 B C A 0 8 1
GND 1
GN D2
GND 3
GN D4
PIN SWAP
6-21-B49C0-104
6-21-B49B0-104
A G ND
TO M/B
AUDIO JACK
Sheet 39 of 42
Audio Board/USB
A MI C 1-L
A_ 5 V
AL 6
2
6
L
1
2S J -T 3 51 -S 2 3
F C M1 0 0 5K F -12 1 T 03
A C1 0
AC 4
10 0 p _5 0 V _ N P O_ 0 4
1 0 0p _ 5 0V _ N P O_ 0 4
A J_ A U D I O1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A MI C 1 -R
A MI C 1 -L
A
A
A
A
A
A
A
5 A J _ MI C 1
4
3
R
A MI C _ S E NS E
AL 4
F C M1 0 0 5K F -12 1 T 03
A MI C 1-R
HE A D P HON E -R
HE A D P HON E -L
MI C _ S E N S E
S P K _H P #
HP _ S E N S E
US B _ P N 2
US B _ P P 2
A S P K OU TR +
A S P K OU TR -
MIC IN
6-20-B2800-106
BLACK
A HP_ S E N SE
A _ A UD G
A S PK _ HP #
A H E A D P H O N E -R
A R3
6 8_ 0 4
AL 2
F C M 10 0 5K F -12 1 T 03
A H E A D P H O N E -L
A R5
6 8_ 0 4
AL 3
F C M 10 0 5K F -12 1 T 03
8 7 21 3 -14 0 0 G
5 A J _ HP 1
4
R
3
2
6
1
AR 9
AR 8
A C3
*1 K _ 1 %_ 0 4
* 1K _ 1 % _0 4
1 00 p _ 50 V _ N P O _ 04
L
2S J -T 3 51 -S 2 3
AC2
1 00 p _ 50 V _ N P O _0 4
HEADPHONE
A _A U D G A G N D
6-20-53A00-114
BLACK 6-20-B2800-106
A _ A UD G
A C1 4
0 . 1 u_ 1 6 V _Y 5 V _0 4
A C1 5
0 . 1 u_ 1 6 V _Y 5 V _0 4
A C1 3
0 . 1 u_ 1 6 V _Y 5 V _0 4
A C1 6
0 . 1 u_ 1 6 V _Y 5 V _0 4
A GN D
A SP K O UT R+
AL 7
F C M1 0 05 K F -1 2 1T 0 3
1
2
A SP K O UT R-
A L8
F C M1 0 05 K F -1 2 1T 0 3
1
2
A R1
A H3
C5 9 D5 9
AH 2
2
3
4
5
1
AH4
9
8
7
6
2
3
4
5
M T H 2 76 D 11 1
A GN D
B - 40 Audio Board/USB
9
8
7
6
1
MT H 2 7 6 D 1 1 1
A GN D A G N D
A G ND
A S P K O UT R+ _ R
A S P K O U T R -_ R
A C8
1 80 p _ 50 V _ N P O _0 4
A _ A UD G
A _ A UD G
A H1
C 5 9D 59
A C 11
1 0 0 0p _ 50 V _ X 7R _ 04
C4 5 5
1 80 p _ 50 V _ N P O _ 04
A J _ S P K R 1 J_SPK1
2 1
1
2
85 2 0 4-0 2 00 1
P C B F o ot p ri n t = 8 5 2 04 -0 2 R
*1 0 mi l _s h o rt _0 4
6-20-43150-102
6-20-43110-102
Schematic Diagrams
Power Switch & LED Board
POWER SW & LED & HOT KEY
S _ 3 .3V S
S_ 3 .3 V
S R2
S _ 3.3 V S
*B A V 99 R E CT IF I E R
22 0 _ 04
S R1
S M GN D
S _ V IN
2 0m il
Z4301
S U1
1
S D3
* HT -1 5 0N B -DT
S MG ND
SAP_ O N
2
VC C
SC 2
*0 .1 u _1 0 V _ X7 R_ 0 4
S LI D_ S W #
OU T
GND
S C6
A
S M _B T N #
SW EB_ W W W #
SW EB_ EM AIL #
S L I D_ S W #
3
S M GN D
SAP_ O N
20 mi l
20 mi l
1
2
3
4
5
6
7
8
A
SJ _ SW 2
S M _B TN #
S W E B _W W W #
S W E B _E M A IL #
S L ID_ S W #
S C1
M H2 4 8- A LF A - E S O
0 .1 u _1 6 V _ Y 5 V _0 4
SD 1
*1 00 p _ 50 V _ NP O _ 04
S MG ND
H T-1 5 0N B -DT
S M GND
6-52-56001-023
6-52-56001-028
6-52-56000-020
6-52-56001-022
6-20-94K10-108
1 0 pin & 8 pi n co- la y
S MG ND
C
8 8 48 6 -0 80 1
C
S M GN D
* 5 05 0 0-0 1 0 41 -0 0 1L
AC
1 0 0 K _1 % _ 04
S MG ND
S MGN D
6-52-56001-023
6-52-56001-028
6-52-56000-020
6-52-56001-022
S M GN D
SU1, SU2
3
6-02-00248-LC2
6-02-00268-LC1
1
FOR E5128Q
S W W W _S W 1
T J G-5 3 3-S -T /R
1
3
S W EB_ W W W #
1
3
SC 4
2
4
S A P _S W 1
T J G-5 3 3 -S -T/R
S W E B _E MA IL #
1
3
2
4
S C3
0 . 1 u_ 1 6 V _Y 5 V _0 4
S A P _O N
S C5
S R4
0 _ 04
PSW1~8
3
4
0.1 u _ 16 V _ Y 5 V _ 0 4
2
6-53-3150B-245
6-53-3050B-241
6-53-3050B-240
AP_KEY#
SR 3
* 10 0 K _ 1% _ 0 4
S MA IL _ S W 1
TJ G-5 3 3 -S -T /R
2
4
5
6
S M_ B T N#
5
6
2
4
5
6
SPW R _ SW 1
T J G-5 3 3-S -T / R
1
3
S_ VIN
6-53-3150B-245
6-53-3050B-241
6-53-3050B-240
WEB_EMAIL#
6-53-3150B-245
6-53-3050B-241
6-53-3050B-240
WEB_WWW#
5
6
6-53-3150B-245
6-53-3050B-241
6-53-3050B-240
POWER BUTTON
HOT KEY
FOR E4120Q/E5120Q
Sheet 40 of 42
Power Switch &
LED Board
SR 5
*4 7K _ 0 4
0.1 u _1 6 V _ Y 5 V _ 04
1
2
S MGN D
S M GN D
S M GN D
S MG ND
S MG ND
S MG ND
S MG ND
S M GND
S MG ND
FOR E4120Q/E5120Q
POWER BUTTON
SPW R _ SW 2
* TJ G- 53 3 -S -T / R
S M H1
2
4
S M_ B T N#
5
6
1
3
2
3
4
5
6-53-3150B-245
6-53-3050B-240
6-53-3050B-241
1
S MH3
9
8
7
6
2
3
4
5
M T H2 37 D 87
PSW1~8
3
4
S MGN D
S M H2
S MH5
H 7_ 0 D2 _ 3 H 7 _0 D 2_ 3
S MG ND
1
2
S M GN D
1
S MH 4
9
8
7
6
2
3
4
5
MT H2 3 7D 87
S M GND
1
9
8
7
6
MT H2 3 7D 1 18
S M GND
S M GN D
S MGN D
FOR E5128Q
Power Switch & LED Board B - 41
B.Schematic Diagrams
1
2
3
4
5
6
7
8
9
10
S D2
S _ 3 .3 V
S _ 3 . 3V
2 0mi l
A
SJ _ SW 1
LID SWITCH IC
C
S _ 3 .3V S
S _3 .3 V
POWER
SWITCH
LED
Schematic Diagrams
External ODD Board
B.Schematic Diagrams
ODD BOARD FOR E5120Q
QJ _ OD D 2
S1
S2
S3
S4
S5
S6
S7
Sheet 41 of 42
External ODD
Board
P1
P2
P3
P4
P5
P6
Q J_ O DD 1
S1
S2
S3
S4
S5
S6
S7
QJ _S ATA_ TXP1
QJ _S ATA_ TXN 1
QJ _S ATA_ R XN 1
QJ _S ATA_ R XP1
Q GN D
Q G ND
P1
P2
P3
P4
P5
P6
QJ _O D D_ D ETE CT#
Q _ 5VS
Q_ 5VS
QJ _S ATA_ O DD _ DA#
1- 1 62 -1 0 05 62
PI N
Q GN D
G N D1 ~2 =WG ND
2 42 00 1 -1
P IN
G N D 1 ~3 =Q G N D
Q G ND
6-21-1 4010-0 13
6-21-1 4020-0 13
6-21-1 4030-0 13
6-21-1 3A00-0 13
Q_ 5V S
Q C2
Q C1
0. 1 u_ 16 V_ Y5 V_ 04
*0 .1 u_ 1 6V_ Y 5V_ 0 4
Q G ND
B - 42 External ODD Board
Q H1
C 23 7 D9 1
QH 4
C 2 37 D 91
QG N D
Q GN D
Q H3
C 67 D 67
Q H2
C 67 D 67
Schematic Diagrams
Sequence
E 5 1 2 0 Q
D 0 2
P O W E R
S E Q U E N C E
VCCRTC
3 8 . 8 m s
RTCRST#
SPEC
V C C R T C
MIN
t o
R T C R S T #
9mS
DD_ON#
8 7 0 u s
( D D _ O N #
t o
5 V )
5V
1 . 5 m s
( D D _ O N #
t o
3 . 3 V )
3.3V
8 5 m s
PWRBTN#
1 5 0 m s
RSMRST#
2 0 m s
SUS_PWR_ACK
1 u s
t o
t o
R S M R S T # )
S U S _ P W R _ A C K )
9 8 m s
SUSC#
( R S M R S T #
2 . 1 7 m s
(VDDQ)
5 7 u s
SUSB#
( S U S C #
t o
S U S C # )
( S U S C #
t o
t o
4 . 4 m s
DDR1.5V_PWRGD
9 2 0 u s
5VS
( S U S B #
1 . 5 2
3.3VS
1 . 5 V
t o
m s ( S U S B #
( 1 . 5 V
t o
1.1VS_VTT_EN
t o
V T T _ M E M ( 0 . 7 5 V ) )
t o
m s ( 1 . 8 V S
1 . 2 7
1.1VS_VTT
D D R 1 . 5 V _ P W R G D )
Sheet 42 of 42
Sequence
m s ( S U S B #
1 . 2 7
1.8VS_PWRGD
t o
3 . 3 V S )
( S U S B #
5 . 7 5
1.8VS
( V D D Q )
5 V S )
4 . 7 5 m s
VTT_MEM(0.75V)
( V D D Q ) )
S U S B # ) )
1 . 8 V S )
t o
1 . 8 V S _ P W G D )
m s ( 1 . 1 V S _ V T T _ E N
8 . 4
m s ( S U S B #
t o
t o
1 . 1 V S _ V T T )
1 . 1 V S _ V T T )
1.1VS_PWRGD
0
m s ( 1 . 1 V S _ V T T
t o
1 . 1 V S _ P W R G D )
ALL_SYS_PWRGD
0
m s ( 1 . 1 V S _ V T T
t o
A L L _ S Y S _ P W R G D )
H_VTTPWRGD
VGFX_VCORE_EN
2
(DFGT_VR_EN)
VGFX_VID
8 . 4 7
0
m s ( A L L _ S Y S _ P W R G D
m s ( S U S B #
t o
t o
H _ V T T P W R G D )
V G F X _ V C O R E _ E N )
m s ( V G F X _ V C O R E _ E N
t o
V G F X _ V I D )
VGFX_CORE
9 . 2 9 m s ( S U S B #
VGFX_VORE_PG
0
t o
m s ( V G F X _ V C O R E
V G F X _ C O R E )
t o
V G F X _ V O R E _ P G )
2 8 0 m s ( A L L _ S Y S _ P W R G D
MEPWROK
SPEC
0.0001mS
~
t o
SPEC
MIN
P M _ M P W R O K )
500mS
2 8 0 m s ( A L L _ S Y S _ P W R G D
VCORE_ON
t o
V C O R E _ O N )
99mS
VCORE
2 . 8 4 m s ( V C O R E _ _ O N
SPEC
MAX
t o
V C O R E )
3mS
1 2 0 u s ( V C O R E
CLKEN#
t o
C L K E N # )
CLKIN_BCLK
1 . 2 m s ( C L K E N #
VCORE
PG
(DELAY_PWRGD)
SYS_PWRGD/SB_PWROK
SM_DRAMPWROK
H_CPUPWRGD
t o
6 . 4 8 m s ( V C O R E
2 9 7 . 7 2 m s
( S U S B #
t o
D E L A Y _ P W R G D )
S Y S _ P W R G D / S B _ P W R O K )
3 7 . 7 m s ( V C O R E
6 8 m s
( V C O R E
SPEC
SUS_STATE#
C L K I N _ B C L K )
t o
t o
S M _ D R A M P W R O K )
H _ C P U P W R G D )
0.05mS
1 . 6 4 m s
( H _ C P U P W R G D
SPEC
PLT_RST#
t o
~
t o
0.03mS
2 3 0 u s
( S U S _ S T A T E #
SPEC
MIN
650mS
S U S _ S T A T E # )
~
t o
2mS
P L T _ R S T # )
60us
Sequence B - 43
B.Schematic Diagrams
1.5V
( P W R B T N #
( R S M R S T #
B.Schematic Diagrams
Schematic Diagrams
B - 44
BIOS Update
Appendix C:Updating the FLASH ROM BIOS
To update the FLASH ROM BIOS you must:
•
•
•
•
•
•
•
Download the BIOS
1. Go to www.clevo.com.tw and point to E-Services and click E-Channel.
2. Use your user ID and password to access the appropriate download area (BIOS), and download the latest BIOS files
(the BIOS file will be contained in a batch file that may be run directly once unzipped) for your computer model
(see sidebar for important information on BIOS versions).
Unzip the downloaded files to a bootable CD/DVD/ or USB Flash drive
1. Insert a bootable CD/DVD/USB flash drive into the CD/DVD drive/USB port of the computer containing the
downloaded files.
2. Use a tool such as Winzip or Winrar to unzip all the BIOS files and refresh tools to your bootable CD/DVD/USB
flash drive (you may need to create a bootable CD/DVD with the files using a 3rd party software).
BIOS Version
Make sure you download the latest correct
version of the BIOS appropriate for the computer model you are
working on.
You
should
only
download BIOS versions
that
are
V1.01.XX or higher as
appropriate for your
computer model.
Note that BIOS versions
are not backward compatible and therefore
you may not downgrade your BIOS to an
older version after upgrading to a later version (e.g if you upgrade
a BIOS to ver 1.01.05,
you MAY NOT then go
back and flash the BIOS
to ver 1.01.04).
Set the computer to boot from the external drive
1. With the bootable CD/DVD/USB flash drive containing the BIOS files in your CD/DVD drive/USB port, restart the
computer and press F2 (in most cases) to enter the BIOS.
2. Use the arrow keys to highlight the Boot menu.
3. Use the “+” and “-” keys to move boot devices up and down the priority order.
4. Make sure that the CD/DVD drive/USB flash drive is set first in the boot priority of the BIOS.
5. Press F10 to save any changes you have made and exit the BIOS to restart the computer.
C - 1
C:BIOS Update
Download the BIOS update from the web site.
Unzip the files onto a bootable CD/DVD/USB Flash Drive.
Reboot your computer from an external CD/DVD/USB Flash Drive.
Use the flash tools to update the flash BIOS using the commands indicated below.
Restart the computer booting from the HDD and press F2 at startup enter the BIOS.
Load setup defaults from the BIOS and save the default settings and exit the BIOS to restart the computer.
After rebooting the computer you may restart the computer again and make any required changes to the default BIOS
settings.

BIOS Update
Use the flash tools to update the BIOS
1. Make sure you are not loading any memory management programs such as HIMEM by holding the F8 key as you
see the message “Starting MS-DOS”. You will then be prompted to give “Y” or “N” responses to the programs
being loaded by DOS. Choose “N” for any memory management programs.
2. You should now be at the DOS prompt e.g: DISK C:\> (C is the designated drive letter for the CD/DVD drive/USB
flash drive).
3. Type the following command at the DOS prompt:
C:BIOS Update
C:\> Flash.bat
4. The utility will then proceed to flash the BIOS.
5. You should then be prompted to press any key to restart the system or turn the power off, and then on again but
make sure you remove the CD/DVD/USB flash drive from the CD/DVD drive/USB port before the computer
restarts.
Restart the computer (booting from the HDD)
1. With the CD/DVD/USB flash drive removed from the CD/DVD drive/USB port the computer should restart from
the HDD.
2. Press F2 as the computer restarts to enter the BIOS.
3. Use the arrow keys to highlight the Exit menu.
4. Select Load Setup Defaults (or press F9) and select “Yes” to confirm the selection.
5. Press F10 to save any changes you have made and exit the BIOS to restart the computer.
Your computer is now running normally with the updated BIOS
You may now enter the BIOS and make any changes you require to the default settings.
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