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Download Masterclock D232 Specifications
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CS5464 Page1 Registers Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 W RA[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11111 Name I1OFF I1GAIN V1OFF V1GAIN P1OFF I1ACOFF V1ACOFF I2OFF I2GAIN V2OFF V2GAIN P2OFF I2ACOFF V2ACOFF PulseWidth PulseRate Modes Epsilon IchanLEVEL N Q1WB Q2WB TGAIN TOFF EMIN (IrmsMIN) TSETTLE LoadMIN VFRMS G Time Page Description Current DC Offset Channel 1 Current Gain Channel 1 Voltage DC Offset Channel 1 Voltage Gain Channel 1 Power Offset Channel 1 Current AC (RMS) Offset Channel 1 Voltage AC (RMS) Offset Channel 1 Current DC Offset Channel 2 Current Gain Channel 2 Voltage DC Offset Channel 2 Voltage Gain Channel 2 Power Offset Channel 2 Current AC (RMS) Offset Channel 2 Voltage AC (RMS) Offset Channel 2 Pulse Output Width Pulse Output Rate (frequency) Mode Control Ratio of Line to Sample Frequency Irms or E Channel Select Trip Level Cycle Count (Number of OWR Samples in One Low-rate Interval) Wideband Reactive Power from Power Triangle Channel 1 Wideband Reactive Power from Power Triangle Channel 2 Temperature Sensor Gain Temperature Sensor Offset Energy Channel Selector Minimum Operating Level Filter Settling Time for Conversion Startup No Load Threshold Voltage RMS Fixed Reference System Gain System Time (in samples) Register Page Select Name V1SagDUR V1SagLEVEL I1FaultDUR I1FaultLEVEL V2SagDUR V2SagLEVEL I2FaultDUR I2FaultLEVEL Page Description V Sag Duration Channel 1 V Sag Level Channel 1 I Fault Duration Channel 1 I Fault Level Channel 1 V Sag Duration Channel 2 V Sag Level Channel 2 I Fault Duration Channel 2 I Fault Level Channel 2 Register Page Select Page2 Registers Address 0 1 4 5 8 9 12 13 31 W RA[4:0] 00000 00001 00100 00101 01000 01001 01100 01101 11111 Warning: Do not write to unpublished register locations. DS682F3 27
