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Keyboard Interface
The AT83SND2CMP3 implement a keyboard interface allowing the connection of a keypad. It is based on one input with programmable interrupt capability on both high or low
level. This input allows exit from idle and power down modes.
Description
The keyboard interfaces with the C51 core through 2 special function registers: KBCON,
the keyboard control register; and KBSTA, the keyboard control and status register.
An interrupt enable bit (EKB in IEN1 register) allows global enable or disable of the keyboard interrupt (see Figure 74). As detailed in Figure 75 this keyboard input has the
capability to detect a programmable level according to KINL0 bit value in KBCON register. Level detection is then reported in interrupt flag KINF0 in KBSTA register.
A keyboard interrupt is requested each time this flag is set. This flag can be masked by
software using KINM0 bits in KBCON register and is cleared by reading KBSTA register.
Figure 74. Keyboard Interface Block Diagram
KIN0
Keyboard Interface
Interrupt Request
Input Circuitry
EKB
IEN1.4
Figure 75. Keyboard Input Circuitry
0
KIN0
KINF0
1
KBSTA.0
KINM0
KINL0
KBCON.0
KBCON.4
Power Reduction Mode
KIN0 inputs allow exit from idle and power-down modes as detailed in section “Power
Management”, page 46. To enable this feature, KPDE bit in KBSTA register must be set
to logic 1.
Due to the asynchronous keypad detection in power down mode (all clocks are
stopped), exit may happen on parasitic key press. In this case, no key is detected and
software must enter power down again.
76
AT83SND2CMP3
7524D–MP3–07/07