Download Maxim M30B Specifications

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Transcript 
Rev: 102108
DS33M33 Demo Kit
General Description
The DS33M33 demo kit (DK) is an easy-to-use
evaluation board for the DS33M33 and the DS33M33
Ethernet-over-SONET/SDH devices. The demo kit
contains an option for either T3 or E3. The T3E3 links
are complete with line interface, transformers, and
network connections. Maxim’s ChipView software is
provided with the demo kit, giving point-and-click
access to configuration and status registers from a
Windows®-based_PC. On-board LEDs indicate
receive loss-of-signal, queue overflow, Ethernet link,
Tx/Rx, and interrupt status.
Features
♦
Demonstrates Key Functions of DS33M33
Ethernet Transport Chipset
♦
Includes Ethernet PHY Supporting 10/100 and
Gigabit Modes
♦
Includes Optical SFP Module for SONET/SDH
Interface
♦
Network Connectors, Transformers, and
Termination Ease Connectivity
♦
Careful Layout Provides Signal Integrity
♦
On-Board Processor and ChipView Software
Provide Point-and-Click Access to the
DS33M33 and DS3154 Register Set
♦
Software-Controlled (Register Mapped)
Configuration Switches Facilitate Clock and
Signal Routing
♦
All System Side and Overhead Pins are Easily
Accessible for External Data Source/Sink
♦
LEDs Programmed Through GPIO Pins
Provide Status
♦
Easy-to-Read Silkscreen Labels Identify the
Signals Associated with All Connectors,
Jumpers, and LEDs
Windows is a registered trademark of Microsoft Corp.
Demo Kit Contents
DS33M33DK Board
CD Including:
ChipView Software
DS33M33 Definition Files
DS33M33DK Definition File
DS33M33DK Data Sheet
DS33M33 Data Sheet
Ordering Information
PART
DS33M33DK
TYPE
Demo Kit for DS33M33
________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or
visit Maxim’s website at www.maxim-ic.com.
_________________________________________________________________________________________________ DS33M33DK
Table of Contents
1.
BOARD FLOORPLAN ..................................................................................................................... 3
2.
PC BOARD ERRATA....................................................................................................................... 3
3.
FILE LOCATIONS ............................................................................................................................ 4
4.
BASIC OPERATION ........................................................................................................................ 5
4.1
POWERING UP THE DEMO KIT .......................................................................................................... 5
4.1.1
4.2
General .................................................................................................................................................. 5
BASIC DS33M33 INITIALIZATION ...................................................................................................... 5
4.2.1
4.3
Additional configuration for DS33M33 ................................................................................................... 5
MONITOR AND CAPTURE ETHERNET TRAFFIC ................................................................................... 5
5.
JUMPERS AND CONNECTORS ..................................................................................................... 6
6.
LINE-SIDE CONNECTIONS ............................................................................................................ 9
7.
SYSTEM CONNECTORS ................................................................................................................ 9
8.
MICROCONTROLLER ..................................................................................................................... 9
9.
POWER-SUPPLY CONNECTORS .................................................................................................. 9
10.
CONNECTING TO A COMPUTER .................................................................................................. 9
11.
INSTALLING AND RUNNING THE SOFTWARE .......................................................................... 10
12.
ADDRESS MAP ............................................................................................................................. 11
12.1
12.2
13.
OVERHEAD CPLD REGISTER MAP.............................................................................................. 11
CONTROL AND STATUS REGISTERS ............................................................................................ 12
ADDITIONAL INFORMATION/RESOURCES................................................................................ 16
13.1
13.2
13.3
DS33M33 INFORMATION............................................................................................................ 16
DS33M33DK INFORMATION....................................................................................................... 16
TECHNICAL SUPPORT ................................................................................................................. 16
14.
COMPONENT LIST........................................................................................................................ 16
15.
SCHEMATICS ................................................................................................................................ 21
List of Figures
Figure 1-1. DS33M33DK Board Floorplan................................................................................................................... 3
Figure 15-1. DS33M33 PCB Layout and Schematic Hierarchy Block Page Listing.................................................. 21
List of Tables
Table 3-1. Definition and Configuration Files .............................................................................................................. 4
Table 5-1. Jumpers and Connectors ........................................................................................................................... 6
Table 12-1. Address Map .......................................................................................................................................... 11
Table 12-2. Register Map for Overhead CPLD (Reference Designator U01) ........................................................... 11
Rev: 102108
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_________________________________________________________________________________________________ DS33M33DK
1.
Board Floorplan
Figure 1-1. DS33M33DK Board Floorplan
ETHERNET
PHY AND
CONNECTOR
OVERHEAD
FPGA AND
TEST POINTS
ETHERNET
CONFIGURATION
JUMPERS
DRIVER
CONFIGURATION
POWER
(5V)
USB
DS33M33
SPI CONFIG
JUMPERS
DDR
PRIMARY SONET OPTICAL SFP
SYSTEM SIDE
JUMPERS
ADDRESS DATABUS
TEST POINTS
SERIAL PORT
(57600-8-N-1)
COMM SELECT
JUMPERs
DS33M33-TO-LIU
REDUNDANT SONET OPTICAL
SFP
MICROPROCESSOR
DS3154 T3E3
SFP LEDs
SFP LEDs
2.
CLOCKS AND
CLOCK
SELECTION
TRANSFORMER AND NETWORK
CONNECTIONS (T3E3)
PCB Errata
There are no errata for the DS33M33DK02A0.
Rev: 102108
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_________________________________________________________________________________________________ DS33M33DK
3.
File Locations
This demo kit relies upon several supporting files, which are provided on the CD and are available as a zip file from
the Maxim website www.maxim-ic.com/DS33M33DK. All locations are given relative to the directory in the CD/zip
file called “DS33M33_def_ini_”. Table 3-1 shows the DS33M33, DS3154, and FPGA register definition files and
configuration files.
Table 3-1. Definition and Configuration Files
FILE NAME
. \parallel_mode\ _DS33M_GlobalSonet.def
FILE USAGE
Top level definition file to select in
ChipView’s register mode. This file
will autoload the remaining
definition files for the DS33M33
when parallel mode is used. (Note
the wan files still need to be loaded
(either DS)).
.\parallel_mode\DS3154DC.def
.\parallel_mode\ds33M_BufferMan.def
.\parallel_mode\ds33M_EncapDecap.def
.\parallel_mode\ds33M_GlobalEth.def
.\parallel_mode\ds33M_group.def
.\parallel_mode\ds33M_LanSubscriber.def
.\parallel_mode\DS33M_port1.def
.\parallel_mode\DS33M_port2.def
.\parallel_mode\DS33M_port3.def
.\parallel_mode\DS33M_serial_1234.def
.\parallel_mode\DS33M_TEST.def
.\parallel_mode\ds33M_Vcat.def
.\parallel_mode\Overhead_FPGA.def
.\parallel_mode\m33_eos_vcg0_port2_port3_mii.mfg
DS33M33 dependent files. These
are called by
_DS33M_GlobalSonet.def file,
which is listed above.
.\parallel_mode\m33_eos_vc3_mii100.mfg
.\parallel_mode\m33_eopos_ds3.mfg
.\parallel_mode\enc_dec_lb.mfg
.\parallel_mode\m30_rx_tx.mfg
.\parallel_mode\norm_ds3154_dlb.mfg
.\parallel_mode\m33_pos_au3_liu.mfg
.\ spi_mode.zip
.\ ParitalConfig_DS33M_100mBit.mfg
.\ ParitalConfig_DS33M_GigaBit.mfg
File for manually configuring the
DS33M33 for EoS VC3 with two
ports assigned to VCG1.
File for manually configuring the
DS33M33 for EoS VC3 mode.
File for manually configuring the
DS33M33 for EoPoS DS3 mode.
Encap/decap loopback/
M30 mode Rx and Tx
configuration. This file configures
the MAC for GMII mode and
requires a Gigabit Ethernet link.
Two files for configuring the LIU in
M33 mMode and configuring the
DS33M33 in PoS AU3 mode.
Configuration mode files for SPI™
3-wire bus mode. The default
mode for this demo kit is parallel
mode. To avoid accidental use the
SPI mode files have been provided
in a zip format.
Files to change Ethernet speed in
the MAC and Global Ethernet
section.
SPI is a trademark of Motorola, Inc.
Rev: 102108
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_________________________________________________________________________________________________ DS33M33DK
4.
Basic Operation
Note: In the following sections, software-related items are identified by bolding. Text in bold refers to items directly
from the EV kit software. Text in bold and underlined refers to items from the Windows operating system.
4.1
•
•
•
Powering Up the Demo Kit
Connect PCB power jack to the wall adapter.
Connect RS232 serial cable, or USB cable between the host PC and demo kit.
Verify that the jumpers are configured as described in Table 5-1.
4.1.1 General
•
•
Upon power-up the power LEDs (DS30, DS31, DS32 green) will be lit. Note that with DS33M3301A0 board
revision, the LED DS31 will be red when power conditions are correct.
PHY LINK LED should be lit if an Ethernet cable is connected.
Following are several basic system initializations.
4.2
Basic DS33M33 Initialization
This section covers two basic methods for configuring the DS33M33.
1. Device Driver-Based Configuration: (Note: The DS33M3302A0 board revision does not come loaded with
device drivers). If the pins J20.1+J20.2 are Jumpered the device driver will auto configure the DS33M33
upon power-up. This enables traffic to pass from the Ethernet port to the serial port. Consult the device
driver documentation for further details. To load the GUI interface for the device drivers, go to the ChipView
register mode Tools menu and select Tools→Plugins→DS33M30/M33 Device Driver Demo.
2. Register-Based Configuration: EoS VC3 with two ports assigned to VCG1.
a. Remove jumper J20.1+J20.2 to disable device drivers, and reset the board.
b. Launch ChipView.exe and select Register View.
c. When prompted for a definition file, pick the file named _DS33M33_GlobalMicroport.def. Several
additional definition files will load.
d. Go to the File menu and select File→Memory Config File→Load .MFG file. When prompted,
select the file named m33_eos_vcg0_port2_port3_mii.mfg.
4.2.1 Additional Configuration for DS33M33
•
•
•
•
4.3
•
•
•
•
Using either a patch or crossover cable, connect the Ethernet connector to an ordinary PC or network test
equipment. This should cause the link LED to turn on.
Place a loopback connector at the SONET network side; the optical LOS LEDs should go out.
At this point any packets sent to the DS33M33 are echoed back. Incoming packets (i.e., ping) should
cause the Activity LED to blink.
Note that ChipView.exe display settings can be changed using the Options→Settings menu.
Monitor and Capture Ethernet Traffic
Although ping is mentioned, it is not the recommended frame source for testing. The ping command goes
through the computer’s TCPIP stack, and sometimes is not sent out the PC’s network connector (i.e., if the
PC’s ARP cache is out of date). Additionally, ping requires two PCs, as a Windows PC with only one
adapter cannot ping itself (i.e., a local ping gets sent to local host instead of out the connector). With that
said, ping is still a valuable test once the prototyping stage is complete.
Generation and capture of arbitrary (raw) packets can be accomplished using CommView. A time-limited
demo is available at www.tamos.com/products/commview.
Wireshark (formerly Ethereal) is a free packet capture utility. Download is available at www.wireshark.org.
Adding additional Ethernet ports to a PC is rather simple when a USB-to-Ethernet adapter is used. This
allows for end-to-end testing using a single PC. When using two adapters, the PC has a different IP
address for each adapter. Test equipment allows selection of either adapter. Operating system-based
Rev: 102108
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_________________________________________________________________________________________________ DS33M33DK
network traffic is sent out the default adapter, which usually is the adapter that has recently had connection
to a live network.
5.
Jumpers and Connectors
Jumpers and connectors are listed in Table 5-1. They are listed in order of appearance on the PCB from left to
right, top to bottom (as viewed with SONET connectors port on the left side of the board).
Table 5-1. Jumpers and Connectors
SILKSCREEN
REFERENCE
FUNCTION
BASIC
SETTING
SCHEMATIC
PAGE
J05
Overhead Test Points
J05.5+J05.6
Jumpered
2
J02
Spare Connector
Not used
23
J08
Overhead Test Points
—
2
JB01
(bottom of PCB)
JTAG
—
24
DESCRIPTION
Jumpers to connect overhead
CPLD to DS33M33. Connector is
marked to show that the odd
numbered pins belong to the
CPLD.
Spare pins connected to overhead
CPLD.
Jumpers to connect overhead
CPLD to DS33M33. Connector is
marked to show that the odd
numbered pins belong to the
CPLD.
CPLD JTAG header.
If auto negotiation is enabled, this
setting advertises capability for
26
10/100/1000 speeds. If auto
negotiation is disabled, then this
setting forces 10Mb mode.
If auto negotiation is enabled this
Jumper
Bias PHY
setting advertises capability for
JP05 + JP02
P2+3 (high)
26
Speed1 + Speed0
10/100 speeds. If auto negotiation
P2+3 (high)
is disabled, this setting is not legal.
If auto negotiation is enabled, this
setting advertises capability for
Jumper
P2+3(high)
26
1000 speeds. If auto negotiation is
disabled, this setting forces
P2+1 (low)
1000Mb mode.
Note: In Gigabit mode the DS33M33 Mac must be configured with indirect Mac register MACCR bit 15 set.
Jumper
Jumper P2+3 to enable auto
JP03
Bias PHY ANEN
26
P2+3 (high)
negotiation.
Jumper P2+3 to enable full duplex;
Jumper
26
JP04
Bias PHY Duplex
P2+3 (high)
jumper P1.2 to force half duplex.
Default MDIX setting P2+3 PHY is
Jumper
JP06
Bias PHY ManMDIX
26
set to straight mode; P2+1 PHY is
P2+1 (high)
in crossover mode.
Jumper
Jumper P2+3 to enable IEEE
JP07
Bias PHY NonIEEE
26
P2+3 (high)
compliant operation.
PHY advertisement setting.
Jumper
P2+3 selects multiple node priority
JP08
Bias PHY MultiEn
26
P2+1 (high)
(switch or hub); P1+2 selects single
node priority (NIC).
P2+3 disables pair swap mode,
Jumper
26
JP09
Bias PHY MdixEn
P2+1 (high)
P2+1 enables pair swap mode
Jumper
P2+1 (low)
P2+1 (low)
Rev: 102108
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_________________________________________________________________________________________________ DS33M33DK
SILKSCREEN
REFERENCE
FUNCTION
BASIC
SETTING
SCHEMATIC
PAGE
DESCRIPTION
P2+3 PHY clock to mac output is
disabled, P1+2 PHY clock to mac
output is enabled. Mac clock only
needs to be enabled in Gigabit
mode.
Flashes for PHY Tx-Rx activity.
LED to indicate link speed–1000,
100, or 10Mbps. Only one of the
three LEDs should be lit. See JP05
+ JP02 description for setting in
GMII vs. MII mode.
LED is on in full-duplex mode.
PHY test points. The connector
pinout is compatible with existing
PHY cards, but cannot be used
with U04 on the board.
JP10
Bias PHY MacClkEn
Jumper
P2+3 (low)
26
DS14
LED activity
—
26
DS15
DS16
DS17
LED link speed
1 of the 3
should be lit
(when linked)
26
DS18
LED duplex
—
25
JB03
JB02
PHY Test Points
—
19
J16
JTAG
Jumper
J16.1+J16.3
8
J20
Runtime options
NA
1
J31
JTAG
—
31
JP25
JP26
Comm Port
Jumper
P1+2
P1+2
15
SW01
J21
Reset
Test Points
—
—
11
8
J24
Test Points
—
8
J23
Test Points
—
8
Jumper
P1+2
8
Jumper
P1+2
8
Jumper Pins 2+1 to connect to
parallel databus. Jumper pins 2+3
to connect to SPI port.
8
Jumper to pull high, leave jumper
off to pull low.
JP22
JP21
JP20
JP14
JP13
JP12
JP11
J30
SPI Bias
SWAP
CPHA
CPOL
SPI connection
CS
MISO
MOSI
SCK
Pin Bias
IFSEL_SIZE
IFSEL_STYLE
SPISEL
HIZ
DCESEL
RMIISEL
ALE
Jumper
IFSEL_STYLE
HIZ_N
(parallel mode)
J19
Clock select
Jumper P2+4
6
JP01
Clock select
Jumper P1+2
6
Rev: 102108
DS33M33 JTAG.
Currently the device drivers do not
fit in flash, and are not loaded to
the DK.
FPGA JTAG.
Jumper pins 1+2 to select the
RS232 transceiver. Jumper pins
2+3 to select the USB to serial
converter.
System reset button.
Databus test points, pins D0–D15
Address bus test points pins A0–
A13.
Test points for DS33M33 CS, WR
RD, and INT.
Jumper pins 2+1 to connect to
processor parallel databus. Leave
jumper off to pull pin low, jumper
pins 2+3 to pull pin high.
Clock selection for PHY and
Ethernet side of DS33M33.
Clad clock selection, jumper P1+2
to drive with 19.44MHz. Jumper
P2+3 to drive with 77.76MHz clock.
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_________________________________________________________________________________________________ DS33M33DK
SILKSCREEN
REFERENCE
J09
J10
J03
J04
DS02
DS03
DS08
DS09
DS05
DS04
J06
J07
FUNCTION
BASIC
SETTING
SCHEMATIC
PAGE
DESCRIPTION
Test points to view analog +differential SerDes signals. To
loopback DS33M33 Tx→Rx
remove the SFP and jumper P3+5
and P2+6.
SerDes analog test
points
—
3, 4
SFP test points
Jumper P9+10
3
Test points for SFP module.
SFP MOD0
—
3
Lit when a SFP module is installed.
SFP TXDISABLE
—
3
Lit when Tx is enabled.
SFP LOS
—
3
SFP LOS / M33 LOS
Jumper P2+3
3, 4
SFP
SFP
Software Debug
JTAG
RCLK
RNEG
RPOS
TCLK
TNEG
TPOS
Installed
Not Installed
—
—
3, 4
3, 4
15
20
Jumpered
9
LIU-to-DS33M33 connections.
Jumpered
9
LIU-to-DS33M33 connections.
Lit when fiber optic cable is
removed.
Jumper P2+3 to connect SFP LOS
to DS33M33 LOS. Jumper P2+4 to
pull DS33M33 high. Jumper P2+6
to pull DS33M33 low.
Primary SFP module.
Redundant SFP module.
ONcE EBDI.
LIU JTAG.
U03
U02
J33
J32
J13
J15
J18
J13
J15
J18
JP16
JP23
JP24
J22
J25
J26
J27
JB05
JB06
J28
J29
LIU Port Clocks
Not used
9
Jumper 1+2 to drive TCLKn with
OscSel. Jumper 2+3 to drive
TCLKn with RCLKn.
RX3
TX3
RX1
TX1
RX4 (bottom of PCB)
TX4 (bottom of PCB)
RX2
TX2
—
8
Rx Tx jumpers.
JP17
LIU_T3MCLK
Jumper
P2+3
20
JP18
LIU_ALT_MCLK
Jumper
P2+3
20
JP19
LIU_E3MCLK
Jumper
P2+3
20
JP15
Osc Select
Jumper
P2+3
20
Rev: 102108
Jumper P2+3 to drive with T3 Osc.
Jumper P1+2 to drive with
T3_MCLK_IO.
Jumper P2+3 to drive with Osc Sel.
Jumper P1+2 to drive with
Alternate MCLK.
Jumper P2+3 to drive with E3 Osc.
Jumper P1+2 to drive with
E3_MCLK_IO.
Jumper P2+3 to drive with T3 Osc.
Jumper P1+2 to drive with E3 Osc.
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_________________________________________________________________________________________________ DS33M33DK
6.
Line-Side Connections
The DS33M33DK has two optical ports: one Ethernet port and three T3E3 ports.
7.
System Connectors
System-side signals can be accessed from test point headers. The headers are clearly labeled with signal
information.
8.
Microcontroller
The microcontroller has factory-installed firmware in on-chip nonvolatile memory. This firmware translates memory
access requests from the RS-232 serial port into register accesses on the DS33M33 and the FPGAs.
9.
Power-Supply Connectors
Connect a 5.0V wall adapter to the PCB power jack. LED DS1 provides indications that a 5.0V supply is connected
properly. The board power supplies (3.3V, 2.5V, and 1.8V) are regulated to supply proper voltages to various
circuits on the board.
10.
Connecting to a Computer
Both USB and serial modes are supported.
To connect through a RS-232 serial port, set jumpers JP25 and JP26 jumpers to pins 1+2, identified in the
silkscreen as UART,PROC. Connect a standard DB-9 serial cable between the serial port on the DS33M33DK and
an available serial port on the host computer. The host computer must be a Windows-based PC. Be sure the cable
is a standard straight-through cable rather than a null-modem cable. Null-modem cables prevent proper operation.
To connect through USB, set jumpers JP25 and JP26 jumpers to pins 3+2, identified in the silkscreen as
USB,PROC. Connect a USB cable between the DS33M33DK USB connector and the PC. The host computer must
be a Windows-based PC, which should automatically recognize the device as a virtual com port and assign the
device drivers. If drivers are not automatically assigned, direct the New Hardware wizard to the driver files on the
CD in the folder marked USBdrivers_CP210x.
Rev: 102108
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_________________________________________________________________________________________________ DS33M33DK
11.
Installing and Running the Software
ChipView is a general-purpose program that supports a number of Maxim demo kits. To install the ChipView
software, run Chipview.msi from the disk included in the DS33M33DK box or from the zip file downloadable on our
website at www.maxim-ic.com/DS33M33DK.
After installation, run the ChipView program with the DS33M33DK board powered up and connected to the PC. If
the default installation options were used, one easy way to run ChipView is to click the Start button on the
Windows toolbar and select Programs→ChipView→ChipView. In the opening screen, click the Register View
button. Select the correct serial port in the Port Selection dialog box, then click OK.
Next, the Definition File Assignment window appears. This window has subwindows to select definition files for
up to four separate boards on other Maxim evaluation platforms. In the active subwindow, select the
_DS33M_GlobalSonet.def definition file from the list shown, or browse to find it in another directory. Press the
Continue button.
After selecting the definition file, the main part of the ChipView window displays the DS33M33’s register map. To
select a register, click on it in the register map. When a register is selected, the full name of the register and its bit
map are displayed at the bottom of the ChipView window. Bits that are logic 0 are displayed in white, while bits that
are logic 1 are displayed in green.
The ChipView software supports the following actions:
•
•
•
•
•
Toggle a bit. Select the register in the register map and then click the bit in the bit map.
Write a register. Select the register, click the Write button, and enter the value to be written.
Write all registers. Click the Write All button and enter the value to be written.
Read a register. Select the register in the register map and click the Read button.
Read all registers. Click the Read All button.
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_________________________________________________________________________________________________ DS33M33DK
12.
Address Map
Address space begins at 0x81000000. All offsets given in the following tables are relative to 0x81000000.
Registers in the FPGA can be easily modified using the ChipView host-based user interface software along with
the definition file named Overhead_FPGA.def.
Table 12-1. Address Map
OFFSET
DEVICE
0X6000
0X4000
0X0000
FPGA
DS3154
DS33M33
DESCRIPTION
Overhead CPLD and Clock/Signal Routing
DS3154 Line Interface Unit
DS33M33 Registers
12.1 Overhead CPLD Register Map
Table 12-2. Register Map for Overhead CPLD (Reference Designator U01)
OFFSET
0X0001
0X0002
0X0003
0X0004
0X0005
0X0006
0X0007
0X0008
0x000A
0x000D
0x000F
Rev: 102108
REGISTER
NAME
ATOH_CFG
ATOHEN_CFG
GPIOAwr
GPIOBwr
DTOH_STAT
DTOH_SEL
GPIOrd_STAT
RDOH_STAT
RDOH_SEL
TAOH_CFG
TAOHen_CFG
TYPE
Control
Control
Control
Control
Read-Only
Control
Read-Only
Read-Oonly
Control
Control
Control
DESCRIPTION
ATOH Configuration
ATOHEN Configuration
GPIO A Output Enable + Write Value
GPIO B Output Enable + Write Value
DTOH Status
DTOH Configuration
GPIO Read Values
RDOH Status
RDOH Select
TAOH Configuration
TAOHen Configuration
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_________________________________________________________________________________________________ DS33M33DK
12.2 Control and Status Registers
Register Name: ATOH_CFG
Register Description: ATOH Configuration
Register Offset: 0x0001
Bit #
Name
Default
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
This register sets the overhead transport data byte value, which is positioned by the following register,
ATOHEN_CFG.
Register Name: ATOHEN_CFG
Register Description: ATOHEN Configuration
Register Offset: 0x0002
Bit #
Name
Default
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Byte enable for overhead transport byte, the data value in ATOH_CFG is positioned in the overhead as specified
by ATOHEN_CFG. Examples follow:
ATOHEN_CFG
0
0x01
0x81
0x##
Rev: 102108
ATOH_CFG
NA
0x54
0x54
0xNN
RESULT
Data is not written onto the overhead when ATOHEN_CFG = 0.
Data value 0x54 is written onto the first byte of the transport overhead.
Data value 0x54 is written onto the last byte of the transport overhead.
Data value 0xNN is written to the 0x## byte of the transport overhead.
12 of 48
_________________________________________________________________________________________________ DS33M33DK
Register Name: GPIOAwr
Register Description: GPIO A Output Enable + Write Value
Register Offset: 0x0003
Bit #
Name
Default
7
6
—
—
0
0
5
GPIOa3
Output En
0
4
GPIOa3
Value
0
3
GPIOa2
Output En
0
2
GPIOa2
Value
0
1
GPIOa1
Output En
0
0
GPIOa1
Value
0
3
GPIOb2
Output En
0
2
GPIOb2
Value
0
1
GPIOb1
Output En
0
0
GPIOb1
Value
0
Bits 5 and 4: DS33M33 GPIOA_3 Three-State and Level
0x = FPGA three-states GPIOA_3 pin
00 = FPGA drives GPIOA_3 pin with 0.0V
01 = FPGA drives GPIOA_3 pin with 3.3V
Bits 3 and 2: DS33M33 GPIOA_2 Three-State and Level
0x = FPGA three-states GPIOA_2 pin
00 = FPGA drives GPIOA_2 pin with 0.0V
01 = FPGA drives GPIOA_2 pin with 3.3V
Bits 1 and 0: DS33M33 GPIOA_1 Three-State and Level
0x = FPGA three-states GPIOA_1 pin
00 = FPGA drives GPIOA_1 pin with 0.0V
01 = FPGA drives GPIOA_1 pin with 3.3V
Register Name: GPIOBwr
Register Description: GPIO B Output Enable + Write Value
Register Offset: 0x0004
Bit #
Name
Default
7
6
—
—
0
0
5
GPIOb3
Output En
0
4
GPIOb3
Value
0
Bits 5 and 4: DS33M33 GPIOB_3 Three-State and Level control
0x = FPGA three-states GPIOB_3 pin
00 = FPGA drives GPIOB_3 pin with 0.0V
01 = FPGA drives GPIOB_3 pin with 3.3V
Bits 3 and 2: DS33M33 GPIOB_2 Three-State and Level control
0x = FPGA three-states GPIOB_2 pin
00 = FPGA drives GPIOB_2 pin with 0.0V
01 = FPGA drives GPIOB_2 pin with 3.3V
Bits 1 and 0: DS33M33 GPIOB_1 Three-State and Level control
0x = FPGA three-states GPIOB_1 pin
00 = FPGA drives GPIOB_1 pin with 0.0V
01 = FPGA drives GPIOB_1 pin with 3.3V
Rev: 102108
13 of 48
_________________________________________________________________________________________________ DS33M33DK
Register Name: DTOH_STAT
Register Description: DTOH Status
Register Offset: 0x0005
Bit #
Name
Default
7
STAT7
0
6
STAT6
0
5
STAT5
0
4
STAT4
0
3
STAT3
0
2
STAT2
0
1
STAT1
0
0
STAT0
0
4
SEL4
0
3
SEL3
0
2
SEL2
0
1
SEL1
0
0
SEL0
0
Read value of 1 of 81 bytes selected by DTOH_SEL.
Register Name: DTOH_SEL
Register Description: DTOH Configuration
Register Offset: 0x0006
Bit #
Name
Default
7
SEL7
0
6
SEL6
0
5
SEL5
0
Byte select for overhead transport byte, the overhead byte specified by DTOH_CFG is written to DTOH_STAT.
Examples:
DTOH_SEL
0
0x80
DTOH_STAT
First byte
Last byte
RESULT
The first byte of the transport overhead is written to DTOH_STAT.
The last byte of the transport overhead is written to DTOH_STAT.
Register Name: GPIOrd_STAT
Register Description: GPIO Read Values
Register Offset: 0x0007
Bit #
Name
Default
7
—
0
6
GPIOA3
0
5
GPIOA2
0
4
GPIOA1
0
3
—
0
2
GPIOB3
0
1
GPIOB2
0
0
GPIOB1
0
Bit 6: DS33M33 GPIOA3 Pin Value
Reflects the value of DS33M33 GPIOA3 pin.
Bit 5: DS33M33 GPIOA3 Pin Value
Reflects the value of DS33M33 GPIOA2 pin.
Bit 4: DS33M33 GPIOA3 Pin Value
Reflects the value of DS33M33 GPIOA1 pin.
Bit 2: DS33M33 GPIOA3 Pin Value
Reflects the value of DS33M33 GPIOB3 pin.
Bit 1: DS33M33 GPIOA3 Pin Value
Reflects the value of DS33M33 GPIOB2 pin.
Bit 0: DS33M33 GPIOA3 Pin Value
Reflects the value of DS33M33 GPIOB1 pin.
Rev: 102108
14 of 48
_________________________________________________________________________________________________ DS33M33DK
Register Name: RDOH_STAT
Register Description: RDOH Status
Register Offset: 0x0008
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
—
0
3
—
0
2
—
0
1
—
0
0
—
0
1
B1
0
0
B0
0
Read value from the member and byte selected by RDOH_SEL[7:4] and RDOH_SEL[3:0]
Register Name: RDOH_SEL
Register Description: RDOH Select
Register Offset: 0x000A
Bit #
Name
Default
7
IF3
0
6
IF2
0
5
IF1
0
4
IF0
0
3
B3
0
2
B2
0
Bits 7 to 4: Overhead interface Member Select. Writing IF[3:0] to a value of 0 disables. Writing 1 to 10 selects
among the 10 members used in RDOH_STAT.
Bits 3 to 0: Byte Select. Writing B[3:0] to a value of 0-to-N selects the Nth byte in the member selected.
Register Name: TAOH_CFG
Register Description: TAOH Configuration
Register Offset: 0x000D
Bit #
Name
Default
7
RCLK8
0
6
RCLK7
0
5
RCLK6
0
4
RCLK5
0
3
RCLK4
0
2
RCLK3
0
1
RCLK2
0
0
RCLK1
0
Value to be written to the member and byte selected by TAOHen_CFG[7:4] and TAOHen_CFG [3:0]
Register Name: TAOHen_CFG
Register Description: TAOH Enable Configuration
Register Offset: 0x000F
Bit #
Name
Default
7
IF3
0
6
IF2
0
5
IF1
0
4
IF0
0
3
B3
0
2
B2
0
1
B1
0
0
B0
0
Bits 7 to 4: Overhead interface Member Select. Writing IF[3:0] to a value of 0 disables. Writing 1 to 10 selects
among the 10 members used in TAOH_STAT.
Bits 3 to 0: Byte Select. Writing B[3:0] to a value of 0-to-N selects the Nth byte in the member selected.
Rev: 102108
15 of 48
_________________________________________________________________________________________________ DS33M33DK
13.
Additional Information/Resources
13.1 DS33M33 Information
For more information about the DS33M33, refer to the DS33M33 data sheet at www.maxim-ic.com/DS33M33.
13.2 DS33M33DK Information
For more information about the DS33M33DK, refer to the DS33M33DK Quick View page at
www.maxim-ic.com/DS33M33DK.
13.3 Technical Support
For additional technical support, submit your questions at www.maxim-ic.com/support.
Rev: 102108
16 of 48
_________________________________________________________________________________________________ DS33M33DK
14.
Component List
DESIGNATION
QTY
DESCRIPTION
SUPPLIER
PART
C08, CB34, CB36, CB37, CB38,
CB39, CB40, CB41, CB42, CB58,
CB64, CB66, CB67, CB68, CB72,
CB79, CB92, CB101, CB104,
CB112, CB170
21
L_0603 CERAM .01uF 50V 10% X7R
AVX
06035C103KAT
See next row (begins with C02)
61
L_0603 CERAM .1uF 16V 20% X7R
AVX
0603YC104MAT
C02, C04, C05, C07, C10, C15, C18, CB05, CB06, CB09, CB10, CB11, CB12, CB16, CB21, CB22, CB23, CB25, CB28,
CB33, CB43, CB44, CB45, CB47, CB53, CB54, CB63, CB65, CB69, CB77, CB83, CB85, CB88, CB89, CB94, CB95, CB97,
CB98, CB113, CB115, CB116, CB118, CB122, CB126, CB128, CB134, CB135, CB137, CB138, CB140, CB142, CB143,
CB144, CB146, CB148, CB156, CB160, CB168, CB177, CB186, CB187
DB01
1
SCHOTTKY DIODE, 1 AMP 40 VOLT
International
Rectifier
10BQ040
DS01, DS06, DS07, DS10, DS11,
DS12, DS13, DS31
8
LED, RED/GREEN, SMD
LITEON
160-1172-1-ND
GND_TP01, GND_TP02,
GND_TP03, GND_TP04,
GND_TP11, GND_TPB01,
GND_TPB02, GND_TPB03,
GND_TPB06
9
STANDARD GROUND CLIP
KEYSTONE
DS14, DS15, DS16, DS17
J34
4
1
LUMEX
AMP
UB02, UB04, UB06
3
RPB24, RPB26
2
U10
1
LED, GREEN/GREEN, SMD
L_CONN, DB9 RA, LONG CASE
SPI SERIAL EEPROM 2M 8 PIN SOIC
2.7V to 3.6V
RESISTOR, 4 PACK, 50 OHM 2PCT
QUAD 0603
IC, SINGLE-CHIP USB TO UART
BRIDGE, 28 PIN QFN
J32
1
U04
Atmel
4954
67-1362-1-ND
747459-1
AT25F2048N10SU-2.7
KOA
CN1J4TTD500G
SIL
CP2101
L_TERMINAL STRIP, 10 PIN, DUAL
ROW, VERT DO NOT POPULATE
DNP
DNP
1
GIG PHYTER V, 10/100/1000
ETHERNET PHYSICAL LAYER, 128
PIN QFP
National
Semiconductor
DP83865DVH
U07
1
QUAD DS3/E3/STS1 LIU 144P BGA
Maxim
DS3154
U05
1
IC, ETHERNET OVER SDH/SONET
(EoS), -40C TO 85C, 256-PIN CSBGA
Maxim
DS33M33N
XB01
1
ECL
EC1-8.000M
See next row (begins with C01)
79
Digi-Key
ECJ-1VB0J475M
XTAL LOW PROFILE 8.0MHZ
0603 CERAM 4.7uF 6.3V
MULTILAYER
C01, C03, C06, C09, C11, C12, C13, C14, C16, C23, CB03, CB04, CB07, CB14, CB15, CB17, CB18, CB19, CB20, CB24,
CB26, CB27, CB29, CB30, CB31, CB32, CB46, CB49, CB55, CB60, CB62, CB70, CB73, CB74, CB75, CB76, CB78, CB82,
CB84, CB86, CB90, CB91, CB93, CB96, CB100, CB102, CB103, CB106, CB107, CB109, CB110, CB114, CB117, CB119,
CB120, CB121, CB123, CB127, CB129, CB131, CB132, CB133, CB136, CB139, CB141, CB147, CB150, CB153, CB154,
CB162, CB163, CB165, CB167, CB173, CB175, CB181, CB182, CB183, CB190
See next row (begins with CB50)
Rev: 102108
20
0603 CERAM .1uF 16V 10%
Panasonic
ECJ-1VB1C104K
17 of 48
_________________________________________________________________________________________________ DS33M33DK
CB50, CB56, CB57, CB61, CB71, CB80, CB81, CB87, CB99, CB105, CB108, CB149, CB151, CB152, CB155, CB161,
CB166, CB172, CB179, CB180
See next row (begins with C17)
21
1206 CERAM 10uF 10V 20%
Panasonic
ECJ-3YB1A106M
C17, C19, C20, C21, C22, C24, CB188 , CB01, CB02, CB08, CB13, CB35, CB48, CB51, CB52, CB59, CB111, CB124,
CB125, CB130, CB169
CB164, CB184
CB178
2
1
L_1206 CERAM 1uF 16V 10%
1206 CERAM 4.7uF 25V 10% X5R
Panasonic
Panasonic
ECJ-3YB1C105K
ECJ-3YB1E475K
CB158, CB159, CB185, CB189
4
L_D CASE TANT 68uF 16V 20%
Panasonic
ECS-T1CD686R
RB09, RB10
RB12, RB13
2
2
RES 0603 100 Ohm 1/16W 1%
RES 0603 1.00K Ohm 1/16W 1%
Panasonic
Panasonic
ERJ-3EKF1000V
ERJ-3EKF1001V
RB17, RB19, RB20, RB21, RB22,
RB23, RB24, RB25
8
RES 0603 332 Ohm 1/16W 1%
Panasonic
ERJ-3EKF3320V
RB16
R02, R04, R05, RB04, RB27
RB01, RB02, RB29 , RB05
R03
R01, RB06, RB11
RB08
RB14, RB15
RB07, RB26 , RB28, RB30
RB03, RB18
SW01
1
5
4
1
3
1
2
4
2
1
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
ERJ-3EKF9761V
ERJ-3GEY0R00V
ERJ-3GEYJ103V
ERJ-3GEYJ105V
ERJ-3GEYJ202V
ERJ-3GEYJ222V
ERJ-3GEYJ300V
ERJ-3GEYJ331V
ERJ-6ENF1002V
EVQPAE04M
RPB18
1
RES 0603 9.76K Ohm 1/16W 1%
RES 0603 0.0 Ohm 1/16W 5%
L_RES 0603 10K Ohm 1/16W 5%
RES 0603 1.0M Ohm 1/16W 5%
RES 0603 2.0K Ohm 1/16W 5%
RES 0603 2.2K Ohm 1/16W 5%
RES 0603 30 Ohm 1/16W 5%
RES 0603 330 Ohm 1/16W 5%
RES 0805 10K Ohm 1/10W 1%
SWITCH MOM 4PIN SINGLE POLE
RESISTOR, 4 PACK, 100 OHM 5PCT
QUAD 0603
Panasonic
EXB-V8V101JX
RPB01, RPB02, RPB05, RPB14,
RPB20, RPB30, RPB36, RPB48,
RPB52
9
RESISTOR, 4 PACK, 1K OHM 5PCT
QUAD 0603
Panasonic
EXB-V8V102JX
RPB03, RPB08, RPB10, RPB11,
RPB12, RPB13, RPB29, RPB32,
RPB33, RPB40, RPB41, RPB43,
RPB45, RPB47, RPB49, RPB50,
RPB51, RPB54, RPB55, RPB56,
RPB57, RPB58, RPB60, RPB61,
RPB62, RPB63, RPB64
27
RESISTOR, 4 PACK, 10K OHM 5PCT
QUAD 0603
Panasonic
EXB-V8V103JX
RPB19, RPB21, RPB28
3
RESISTOR, 4 PACK, 2.2K OHM 5PCT
QUAD 0603
Panasonic
EXB-V8V222JX
RP02, RP03, RP04, RP05, RP06,
RP07, RP08, RP09, RP10, RP11,
RP12, RP13, RPB15, RPB16,
RPB17, RPB23, RPB25, RPB27,
RPB31, RPB34, RPB35, RPB37,
RPB44
23
RESISTOR, 4 PACK, 30 OHM 5PCT
QUAD 0603
Panasonic
EXB-V8V300JX
RP01, RPB04, RPB06, RPB07,
RPB09, RPB22, RPB38, RPB39,
RPB42, RPB46, RPB53, RPB59
12
RESISTOR, 4 PACK, 330 OHM 5PCT
QUAD 0603
Panasonic
EXB-V8V331JX
L01, L02, LB01, LB02, LB03,
LB04
6
1uH ±10% 0805 Multilayer Ceramic
400 mA
TDK
GLF2012T1R0M
Rev: 102108
18 of 48
_________________________________________________________________________________________________ DS33M33DK
HEADER, 14 PIN, DUAL ROW, VERT
Samtec
HDR-TSW-107-14T-D
CONNECTOR, SINGLE LEVEL,
GIGABIT RJ-45, 10 PIN
IC, FPGA, 1.2V, 20X20 TQFP, 144
PIN
IC, FPGA, 1.2V, 20X20 TQFP, 144
PIN
Halo
Electronics
HFJ11-1G02E
LAT
LFE2-6E-5TN144C
LAT
LFEC3E-3T144C
12
L_LED, RED, SMD
Panasonic
LN1251C
DS02, DS03, DS08, DS09, DS29 ,
DS18, DS30, DS32
8
L_LED, GREEN, SMD
Panasonic
LN1351C
UB09
1
Maxim
MAX1793EUE-18
UB08
1
Maxim
MAX1793EUE-25
UB10, UB11, UB13
3
Maxim
MAX1793EUE-33
UB01, UB03
2
Maxim
MAX1963EZT120-T
UB07
1
Maxim
MAX811TEUS-T
U09
1
Motorola
MMC2107
J03, J04, J23
3
J33
J35
JB08
See next row (begins with JP01)
J01, J30
2
J11
1
U08
1
U01
1
DS04, DS05, DS28 , DS19, DS20,
DS21, DS22, DS23, DS24, DS25,
DS26, DS27
Digi-Key
S2012-05-ND
1
1
1
IC, LINEAR REG 1.5W, 1.8V or Adj,
1A, 16TSSOP-EP
IC, LINEAR REG 1.5W, 2.5V or Adj,
1A, 16TSSOP-EP
IC, LINEAR REG 1.5W, 3.3V or Adj,
1A, 16TSSOP-EP
IC, LDO REGULATOR WITH
RESET,1.20V OUTPUT 300 MA, 6
PIN SOT23
MICROPROCESSOR VOLTAGE
MONITOR, 3.08V RESET, 4PIN
SOT143
MMC2107 PROCESSOR
TERMINAL STRIP, 10 PIN, DUAL
ROW, VERT
100 MIL 2*7 POS JUMPER
TYPE B SINGLE RT ANGLE, BLACK
100 MIL 2 POS JUMPER
NA
Digi-Key
NA
NA
WM17108-ND
NA
27
100 MIL 3 POS JUMPER
NA
NA
JP01, JP02, JP03, JP04, JP05, JP06, JP07, JP08, JP09, JP10, JP11, JP12, JP13, JP14, JP15, JP16, JP17, JP18, JP19,
JP20, JP21, JP22, JP23, JP24, JP25, JP26, JPB01
TEST POINT, 1 PLATED HOLE, DO
TPB01, TPB02, TPB03
3
NA
NA
NOT STUFF
DOUBLE DATA RATE (DDR) SDRAM
MT46V16M16TGU06
1
MICRON
2-2-2 TIMING 256MBITX16 TSSOP
75E
CY62148DV30LU11, U12
2
CYPRESS SRAM 4Mbit*8
CYPRESS
70SXI
Dual RS-232 transceivers with 3.3V/5V
UB14
1
MAXIM
MAX3233E
internal capacitors
TEST POINTS FOR SMD 50 PIN, 2
NA_NOTPOPULAT
JB02
1
NA
ROW VERTICAL
ED
UB05 , UB12
2
HIGH SPEED INVERTER
FAIRCHILD
NC7SZ86
NON POPULATED HEADER, 14 PIN,
NOPOP-HDR-TSWJ24
1
Samtec
DUAL ROW, VERT
107-14-T-D
DO NOT POPULATE L_2 PIN
NOPOP-TSW-102JB05, JB06
2
Samtec
HEADER, .100 CENTERS, VERTICAL
07-T-S
TERMINAL STRIP, 6 PIN, DUAL
NOPOP-TSW-103J09, J10
2
Samtec
ROW, VERT NOT POPULATED
07-T-D
NOPOP TERMINAL STRIP, 16 PIN,
NOPOP-TSW-108J21
1
Samtec
DUAL ROW, VERT
07-T-D
OSCILLATOR, CRYSTAL CLOCK,
YB04
1
SaRonix
NTH089AA-34.368
5.0V - 34.368 MHZ
SOCKETED OSCILLATOR, CRYSTAL
NTH089AA3YB05
1
SaRonix
CLOCK, 3.3V - 25.000 MHZ
25.000+SOCKET
OSCILLATOR, CRYSTAL CLOCK,
YB03
1
SaRonix
NTH089AA3-44.736
3.3V - 44.736 MHZ
Rev: 102108
19 of 48
_________________________________________________________________________________________________ DS33M33DK
JB09
1
JB03
1
U02, U03
2
CONN 2.1MM/5.5MM PWRJACK RT
ANGLE PCB, closed frame, high
current 24VDC@5A also requires 5V
ACDC adapter INPUT 100-240VAC
50-60HZ 0.6A OUTPUT DC 5V 2.6A.
PN DMS050260-P5P-SZ. MODEL 3Z161WP05
PLUG, SMD, 50 PIN, 2 ROW
VERTICAL
SFP host / receptacle
HB01, HB02, HB03, HB04, HB05
5
Rubber bumper 0.5 inch
YB01
1
YB02
1
T01
1
CB145, CB157, CB171, CB174,
CB176
5
J22, J25, J26, J27, J28, J29
OSCILLATOR, CRYSTAL CLOCK,
3.3V - 19.44 MHZ
OSCILLATOR, CRYSTAL CLOCK,
3.3V - 77.76 MHZ
XFMR, OCTAL T3/E3, 1 TO 2, SMT
32 PIN
CUI, INC
PJ-002AH
Samtec
SFM-125-L2-S-D-LC
PARTS_KIT
SFP_HOST-TYCO
NA
SJ5518-0
SaRonix
SaRonix
SOCKET+NTH089A
3-19.44
SOCKET+NTH089A
3-77.7600
Pulse
T3049
D CASE TANT 470uF 6.3V 20%
KEM
T491D477M006AS
6
L_2 PIN HEADER, .100 CENTERS,
VERTICAL
Samtec
TSW-102-07-T-S
J06, J07, J12, J13, J14, J15, J17,
J18, J19, J20, JB04, JB07
12
TERMINAL STRIP, 6 PIN, DUAL
ROW, VERT
Samtec
TSW-103-07-T-D
J16, J31, JB01
3
Samtec
TSW-105-07-T-D
J02, J05, J08
3
Samtec
TSW-108-07-T-D
Rev: 102108
L_TERMINAL STRIP, 10 PIN, DUAL
ROW, VERT
TERMINAL STRIP, 16 PIN, DUAL
ROW, VERT
20 of 48
_________________________________________________________________________________________________ DS33M33DK
15.
Schematics
The DS33M33DK schematics are featured in the following pages. The schematic contains five hierarchal blocks:
Microcontroller, DS3154, Ethernet PHY, Ethernet Test Points, and Overhead CPLD.
All signals inside a hierarchy block are local, with exception for VCC and ground. In-port and out-port connectors are
used to allow signals inside a hierarchy block to become accessible as pins on the hierarchy blocks symbol. From
here blocks are wired together as if they were ordinary components. Figure 15-1 shows the system diagram in
terms of hierarchal blocks with schematic page numbers given for each functional block.
Figure 15-1. DS33M33 PCB Layout and Schematic Hierarchy Block Page Listing
OVERHEAD CPLD
PAGE 10 SYMBOL
ETHERNET PHY
PAGE 6 SYMBOL
SCHEMATIC
PAGES 23-24
POWER SUPPLY
SCHEMATIC
PAGES 11-12
SCHEMATIC
PAGES 19, 25-26
SONET SFP
PAGES 4-5
DDR
PAGE 7
DS33M33
CLOCKS AND CONFIGURATION
PAGES 6,8
SCHEMATIC
PAGES 1-10
LIU TEST POINTS
PAGE 9
µP BLOCK
PAGE 1 SYMBOL
SCHEMATIC
PAGES 13-18
DS3154 LIU BLOCK
PAGE 9 SYMBOL
SCHEMATIC
PAGES 20-22
Rev: 102108
21 of 21
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses
are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products.
8D6
A
B
C
D
8B2
CS_X2
CS_X3
TE3_L_CS
CPLD_CS
6B4
16B3v
RESET_LAN
RESET_SYS
ADDR<13..0>
8
6A5 25MHZOSC_TO_PROC
17C6v
9B1
1B5
10B4
13B6v
1A2
8B5
10B5 9C1
17C4v
17A5v
11B3
1B1
8B3
WR_RW
17A5v
DATA<7..0>
PROC_OSCIN
RESET_OUT
RESET_IN
7
A_DUT_<13..0>
D_DUT<7..0>
WR_RW
HIERARCHY
SPI_SCK
SPI_CS
SPI_MOSI
6
BLOCK NAME:
MISC_IO<12..1>
EN_SOURCE_TIME
ENABLE_DRV
ENABLE_CLBK
SPI_MISO
BLOCK
MICROPROCESSOR
_motprocrescard_dn
P.1,13-18
P.2,10,23-24
P.2,9,20-22
P.3-4
P.5-6,19,25-26
P.7
P.6
P.8
P.11-12
RD_DS
ALE_DUT
CS_X1
CS_X1
M3X_ALE
INT2
INT3
INT4
M3X_INT
TE3_INT
PHY_INT
8A2
17C4v
10B5
9C1
9C3
8C6
17A6v
10B5
8D3
8D4
1D3
17C6v
17C6v
8C1 1D3
13B7v
14D1v
6B4
17C4v
9C1 8C1 RD_DS
1D3 10B5
8A8
MICROPORT.
OVERHEAD.
T3E3 LIU I/F.
SERDES.
ETHERNET.
DDR MEMORY.
OSCILLATORS.
BIAS+CONFIG.
POWER.
5
3
1
6
4
2
6
4
2
_rc_top_dn_.
5
3
1
CONN_6P_U
J20
SPI_MISO
SPI_SCK
SPI_SS
SPI_MOSI
V3_3
INDEX
13B7v
5
13B7v
13B6v
N3
M3X_JTDO
8A7
M2
M3X_MT2
8B8
4
MT2
MT1
MT0
HIZ*
<CON_PARENT_NAME>
A1
M3X_MT1
8B8
B1
M3X_HIZ_N
8B2
B2
F5
M3X_TEST_EN
8A8
M3X_MT0
IFSEL[1]
N5
M3X_IFSEL_SIZE
8A2
8B8
IFSEL[0]
M3X_IFSEL_STYLE P7
8A2
TEST
SPISEL
N6
RST*
JTDO
JTDI
JTCLK
JTMS
M3X_SPISEL
C1
P2
M3X_JTDI
8A8
RESET_SYS
N2
M3X_JTCLK
8A7
9B1
P1
M3X_JTMS
8A7
JTRST*
8A2
10B4
PARENT BLOCK:
8D4
8A3
11B3
13B6v
8D4
1A8
8D3
8D3
13B6v
N4
M3X_JTRST_N
8A6
U05
3
3
17A5v
STEVE SCULLY
2
P.1,13-18
10/03/2007
DATA<15..0>
1
1/26(TOTAL)
PAGE: 1/12(BLOCK)
DATE:
17C4v
15
D[15]
8B5
14
L9
K12
D[14]
1A8
13
J11
D[13]
10B5
12
D[12]
OF DS33M33DK
DS33M33DK01A0
ENGINEER:
9C1
11
D[10]
H11
10
L8
D[9]
H12
9
M11
D[11]
8
N11
8D7
D[7]/CPOL
D[8]
8D7
D7_SPI_CPOL
M10
D[6]/CPHA
MICROPORT.
TITLE:
BEGINNING
CONTROL
DS33M33_U
8D7
D5_SPI_SWAP
D6_SPI_CPHA
M7
4
M9
D[4]
M8
3
8D3
D2_SPI_CLK
N9
D[2]/SCLK
N10
8D4
D1_SPI_MOSI
N7
D[1]/SDI
1
D[3]
8D4
D0_SPI_MISO
N8
2
D[0]/SDO
RPB34
D[5]/SPISWAP
A[0]
0L12
CONTENTS /
4
A[1]
1P13
DS33M33DK
5
A[2]
2M12
ALE
6
A[3]
3R13
7
A[4]
4N13
8
A[5]
5T13
M4
INT*
M6
RD*/DS*
M5
WR*/R/W*
L5
CS*
E14
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE1
A[6]
6R14
N14
12
:
A[7]
7P14
WR_RW
A[8]
8T14
RD_DS
A[9]
9L13
A[13]
T15
13
CR-1
17C4v
1A8
13B7v
8A8
1B8
8C1
17C4v
REFCLK
A[10]
M3X_CLADCLK
1A8
8D3
8C2
8B2
8A2
N12 M3X_ALE
9B2
R15
10
M3X_CS
10B7
6C6
10B7
M3X_CLKA
M3 1
CLKA
A[11]
M13
11
8
L2
CLKB
A[12]
M3X_INT
9B2
10B7
M3X_CLKB
7
2
6A7
10B7
M3X_CLKC
6
30
3
K2
CLKC
5
4
ADDR<13..0>
A
B
C
D
A
B
C
:
8
8
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE2
11
13
15
1
3
5
7
CPLD_TAOHVLD
CPLD_RDOH
CPLD_RDOHSOF
CPLD_RDOHVLD
CPLD_ATOH
CPLD_ATOHEN
CPLD_ATOHSOF
10B7
10B7
10C7
10C7
10B7
10C4
15
CPLD_DTOHSOF
CPLD_DTOHCLK
10C7
10C7
8
6
16
14
12
10
2A6
2A6
4
2
6
16
14
12
10
8
6
4
2
6
CONN_16P
15
13
11
9
7
5
3
1
J05
CONN_16P
15
13
11
9
7
5
3
1
J08
BLOCK NAME:
13
CPLD_DTOH
10C7
7
11
CPLD_ATOHCLK
10C7
10C7
10C4
9
7
10C5
9
5
CPLD_TAOH
10C5
CPLD_TAOHSOF
3
CPLD_OH1
10C7
CPLD_TAOHEN
1
CPLD_OHCLK
10C7
7
1
3
4
M3XOH_DTOHCLK
5
2
1
4
3
2
1
4
3
2
1
4
M3XOH_DTOH
3
4
M3XOH_ATOHEN
2B6
2
1
M3XOH_ATOH
M3XOH_TAOHEN
M3XOH_TAOH
30
5
6
7
8
5
6
5
6
5
6
7
5
6
100
5
6
7
RPB18 8
30
RP03 8
30
7
RPB17 8
30
7
RP04 8
RPB16
3
2
M3XOH_DTOHSOF
M3XOH_ATOHCLK
M3XOH_ATOHSOF
M3XOH_ATOHEN
M3XOH_ATOH
3
4
2B6
2C6
2C6
2A6
2A6
M3XOH_RDOHVLD
M3XOH_RDOHSOF
M3XOH_RDOH
M3XOH_TAOHVLD
M3XOH_TAOHSOF
M3XOH_TAOHEN
M3XOH_TAOH
M3XOH_OH1
M3XOH_OHCLK
_rc_top_dn_.
16
14
12
10
8
6
4
2
16
14
12
10
8
6
4
2
7
2
30
RPB15 8
1
5
DTOHCLK
DTOHSOF
DTOH
ATOHCLK
ATOHSOF
ATOHEN
ATOH
RDOHVLD
RDOHSOF
RDOH
TAOHVLD
TAOHSOF
TAOHEN
TAOH
OH1
OHCLK
CB34
.01UF
CB37
.01UF
CB36
.01UF
CB40
.01UF
G12
B15
F12
G13
F14
G14
F13
J13
H14
J12
K14
J15
J14
H13
K13
M14
U05
4
OVERHEAD I/F
4
TRANSPORT OVERHEAD I/F
D
CR-2
DS33M33_U
3
SYSTEM I/F
E16
TDPB
RDPB
3
M3X_LOS2
M3X_LOS1
ENGINEER:
3B5
3C6
3D6
3C5
3C5
4C6
4C6
4C5
4C5
2
P.2,10,23-24
P.2,9,20-22
3B6
4B6
STEVE SCULLY
DS33M33DK01A0
F16
M16
100
M3X_SFP2_RDN
100
OVERHEAD.
T3E3 LIU I/F.
LOSB
LOSA
RB10
M3X_SFP2_RDP
G16
TDNB
RDNB
3B5
M3X_SFP2_TDP
H16
RDNA
D16
3D6
3D6
M3X_SFP2_TDN
K16
RDPA
4B5
4B5
M3X_SFP1_RDP
L16
TDPA
M3X_SFP1_RDN
4D6
M3X_SFP1_TDP
N16
RB09
4D6
M3X_SFP1_TDN
P16
2
TDNA
TITLE:
STS-3
10/03/2007
1
2/26(TOTAL)
PAGE: 2/12(BLOCK)
DATE:
1
A
B
C
D
A
B
C
:
8
THIS SUBCIRCUIT
IS
NOT FOR PRODUCTION
.01UF
5
3
1
5
3
1
6
4
2
CONN_6P_U
J09
6
4
2
2C2
2B2
M3X_SFP2_TDN
M3X_SFP2_TDP
3B5
3B5
M3X_SFP2_RDP
M3X_SFP2_RDN
3A7
3A5
3A1
5
SFP2_LOS 3
5
3
1
6
4
2
4
5
7
3A1
SFP2_RATE
6
7
10K
2
3
3A1
SFP2_LOS
RPB12 8
3A5
1
3B3
SFP2_MOD1
3C3
SFP2_MOD0
3
SFP2_MOD2
4
10K
2
5
6
7
3B2
3A5
3B3
3B2
3C2
3B7
M3X_LOS2
6
2B2
BLOCK NAME:
6
4
2
PULLUPS FOR OPEN DRAIN PINS
8 RPB11 1
SFP2_TX_FAULT
3A3
V3_3
3B2
1
J06
CONN_6P_U
2B2
2B2
3C5
3C5
AND LOOPBACK ONLY
PLACE / ROUTE CAPS AND TESTPOINT
SUCH THAT THEY CAN REMOVED WITHOUT IMPACT
CB39
FOR OBSERVATION
USE
.01UF
6
1K
5
6
7
RPB14 8
V3_3
_rc_top_dn_.
4
3
2
1
3B7
3B2
3A7
3C2
3B3
18
M3X_SFP2_TDP
3A1
5
3A3
11
12
13
VEER
RD-
RD+
VEER
VCCR
VCCT
VEET
TD+
TD-
VEET
4
V3_3
SFP2_LOS
1
GREEN
GREEN
RED
2
4
DS05 3
4
330
5
6
LB02
SFP_HOST
1UH
MOD0 IS GROUNDED IN THE SFP
SERVES AS DEVICE DETECT
V3_3
DS02
RPB09
2
1
1
8
SFP2_MOD0
DS08
1
2
7
SFP2_TXDISABLE 2
M3X_SFP2_RDN
M3X_SFP2_RDP
15
SFP2_VCCR
3D3
14
16
SFP2_VCCT
3D2
17
19
20
M3X_SFP2_TDN
3A7
3C6
3D6
2B2
2B2
2B2
2C2
3D6
3D6
5
SFP2_VCCR
3
TX_FAULT
VEET
U02
3C2
3A7
3
SFP2_I2C_CLK
9
7
5
ENGINEER:
10
8
6
4
2
10
8
6
4
2
2
P.3-4
STEVE SCULLY
SERDES.
9
7
5
3
1
J03
3A5
CONN_10P
DS33M33DK01A0
SFP2_TXDISABLE
TITLE:
3A5
3B2
SFP2_I2C_SDA
3
SFP2_DEV_DETECT 1
10
9
SFP2_TX_FAULT
3C2
3C2
3B1
VEER
VEER
LOS
3A7
3B7
3A1
SFP2_LOS
8
3A7
3A1
SFP2_RATE
7
RATE
SFP2_DEV_DETECT
SFP2_MOD0
6
3A5
3A7
MOD-DEF0
3A3
SFP2_RATE
SFP2_LOS
3A3
SFP2_I2C_CLK
SFP2_MOD1
5
3A7
3A3
MOD-DEF1
3A5
MOD-DEF2
3A3
3A7
SFP2_I2C_SDA
SFP2_TXDISABLE
3A3
SFP2_VCCT
SFP2_MOD2
4.7UF
CB32
4
3
1UH
LB04
SFP2_TX_FAULT
4.7UF
2
1
3B5
V3_3
2
4.7UF
CB33
3A7
TX_DISABLE
3B5
CB23
7
.1UF
CB24
8
CB31
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE3
CB42
D
CR-3
CGND
CGND
CGND
CGND
CGND
CGND
CGND
CGND
CGND
CGND
CGND
21
22
23
24
25
26
27
28
29
31
30
.1UF
3B2
3A7
3B7
10/03/2007
3B2
1
3/26(TOTAL)
PAGE: 3/12(BLOCK)
DATE:
3A7
3A5
1
A
B
C
D
A
B
C
:
8
THIS SUBCIRCUIT
IS
NOT FOR PRODUCTION
.01UF
5
3
1
J10
5
3
1
6
4
2
CONN_6P_U
6
4
2
2C2
2C2
M3X_SFP1_TDN
M3X_SFP1_TDP
4B5
4B5
M3X_SFP1_RDP
M3X_SFP1_RDN
4A7
4A5
4A1
SFP1_LOS
5
3
5
3
1
4
10K
5
6
7
4A1
SFP1_RATE
7
2
3
4A1
SFP1_LOS
1
4A5
RPB03 8
4B3
4C3
SFP1_MOD1
SFP1_MOD2
SFP1_MOD0
3
2
4
10K
5
6
7
4B2
4A5
4B3
PULLUPS FOR OPEN DRAIN PINS
8 RPB10 1
SFP1_TX_FAULT 4A3
V3_3
4B2
1
J07
4B2
4C2
6
4B7
4 M3X_LOS1
2
6
BLOCK NAME:
6
4
2
CONN_6P_U
2C2
2C2
4C5
4C5
AND LOOPBACK ONLY
PLACE / ROUTE CAPS AND TESTPOINT
SUCH THAT THEY CAN REMOVED WITHOUT IMPACT
CB38
FOR OBSERVATION
USE
.01UF
6
4
3
2
1K
4B7
5
6
7
RPB01 8
_rc_top_dn_.
2B2
1
4B2
V3_3
4A7
4C2
4A1
4A3
4A7
4C6
2C2
4B3
4C6
2C2
4D6
2C2
2C2
4D6
18
M3X_SFP1_TDP
11
12
13
VEER
RD-
RD+
VEER
VCCR
VCCT
VEET
TD+
TD-
VEET
4
V3_3
5
SFP1_LOS
1
DS04
GREEN
GREEN
RED
2
4
3
4
330
5
6
LB01
SFP_HOST
1UH
MOD0 IS GROUNDED IN THE SFP
SERVES AS DEVICE DETECT
V3_3
DS03
RPB06
2
1
1
8
SFP1_MOD0
DS09
2
1
2
7
SFP1_TXDISABLE
M3X_SFP1_RDN
M3X_SFP1_RDP
15
SFP1_VCCR
4D3
14
16
SFP1_VCCT
4D2
17
19
20
M3X_SFP1_TDN
5
SFP1_VCCR
3
TX_FAULT
VEET
U03
4C2
4A7
3
SFP1_I2C_CLK
9
7
5
ENGINEER:
10
8
6
4
2
10
8
6
4
2
2
P.3-4
STEVE SCULLY
SERDES.
9
7
5
3
1
J04
CONN_10P
DS33M33DK01A0
SFP1_TXDISABLE
TITLE:
4A5
4B2
SFP1_I2C_SDA
3
SFP1_DEV_DETECT 1
10
9
SFP1_TX_FAULT
4C2
4C2
4B1
VEER
VEER
LOS
4A5
4A7
4B7
4A1
SFP1_LOS
8
4A7
4A1
SFP1_RATE
7
RATE
SFP1_DEV_DETECT
SFP1_MOD0
6
4A5
4A7
MOD-DEF0
4A3
SFP1_RATE
SFP1_LOS
4A3
SFP1_I2C_CLK
SFP1_MOD1
5
4A7
4A3
MOD-DEF1
4A5
MOD-DEF2
4A3
4A7
SFP1_I2C_SDA
SFP1_TXDISABLE
4A3
SFP1_VCCT
SFP1_MOD2
4.7UF
CB17
4
3
1UH
LB03
SFP1_TX_FAULT
4.7UF
2
1
4B5
V3_3
2
4.7UF
CB22
4A7
TX_DISABLE
4B5
CB16
7
.1UF
CB30
8
CB29
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE4
CB41
D
CR-4
CGND
CGND
CGND
CGND
CGND
CGND
CGND
CGND
CGND
CGND
CGND
21
22
23
24
25
26
27
28
29
31
30
.1UF
4B2
4A7
4B7
10/03/2007
4B2
1
4/26(TOTAL)
PAGE: 4/12(BLOCK)
DATE:
4A7
4A5
1
A
B
C
D
A
B
C
:
8
8
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE5
7
7
6C3
6
TXD[3]
7 R4
1
2
3
4
3
2
1
0
_rc_top_dn_.
ETH_TXD<7..0>
TXD[4]
5 P5
RP10 8 T4
4
4
30
5 R3
6 P4
5
TXD[0]
TXD[1]
TXD[2]
TXD[5]
TXD[6]
7 P6
6 R5
3
30
2
TXD[7]
5
TXCLK
T6
TXEN
6
4
R2
TXERR
RP08 8 R6
6C3
3
P3
1
5
ETH_TX_CLK
6C3
30
1
2
U05
5
7
6
ETH_TX_EN
6C4
BLOCK NAME:
6C4
6B1
7
8 RPB27
GMII_TX_ER_
6
DS33M33_U
ETHERNET MAC I/F
4
RXD[0]
RXD[1]
RXD[2]
RXD[3]
RXD[4]
RXD[5]
RXD[6]
RXD[7]
RXCLK
RXDV
RXERR
LANCLKO
D
CR-5
MDC
ETH_MDC
6B4
P12
MDIO
ETH_MDIO
6B4
R12
COL
ETH_COL_DET
R7
CRS
6D4
DCESEL
M3X_DCESEL
P11
RMISEL
8B2
T7
ETH_RX_CRS
6D4
LANCLKI
6A5
T12
M3X_RMIISEL
8B2
GTXCLK
M3X_LAN_CLK
T3
1 RP11 8 T5
GTXCLK
6C4
6A1
4
6
3
30
7 T2
2
M3X_LAN_CLKO
6A7
5
4
7
6
5
4
3
2
1
0
P10
R10
T10
P9
R9
T9
P8
R8
6D3
3
ENGINEER:
6D3
6C3
2
STEVE SCULLY
2
P.5-6,19,25-26
DS33M33DK01A0
ETHERNET.
TITLE:
ETH_RXD<7..0>
ETH_RX_CLK
6D4
ETH_RXDV
R11
T8
6C4
ETH_RX_ERR
T11
3
10/03/2007
1
5/26(TOTAL)
PAGE: 5/12(BLOCK)
DATE:
1
A
B
C
D
A
B
C
D
GND
1
OSC
GND
1
OUT
OUT
VCC
5
8
8
4
1
25.000MHZ_3.3V_SOCKET
19.44MHZ_3.3V_SOCKET
4
1
OSC
YB01
I24
VCC
77.76MHZ_3.3V_SOCKET
4
1
1UH
YB02
L01
25B1v
5
8
5
8
4
3
2
1
6B1
7
6C3
30
I22
5
3
1
J19
6
4
2
1D3
10B7
6
4
2
4
3
2
1
6
30
_rc_top_dn_.
ETH_REF_CLK
USED IN RMII
30
19B3v
19B3v
25A1v
5C3
TX_ER_
6A1
5
25A7v
19B3v
25B1v
RESET_B
PHY_INT
MDC
MDIO
PHY_INT
RESET_LAN
ETH_MDC
ETH_MDIO
4
3
ENGINEER:
19B3v
19B3v
25A7v
25B7v
STEVE SCULLY
2
P.5-6,19,25-26
DS33M33DK01A0
ETHERNET.
19B3v
25B1v
5A4
6C4
6C3
6C4
5C6
6A7
1
6/26(TOTAL)
PAGE: 6/12(BLOCK)
DATE:
10/03/2007
GMII_TX_ER_
GTXCLK
CLK_TO_MAC
GMII_CLKFROM_MAC
GMII_TX_ER_
GMII_CLKTOMAC_BUF
SPARE
1
ETHERNET CONNECTOR (I.M.
BUS)
IS INTENDED FOR USE AS TESTPOINTS
NOT CONNECTION TO A RESOURCE CARD
RESET_B
PHY_INT
MDC
MDIO
OSC25M
BLOCK
_phy_imbus_mb_dn
HIERARCHY
ETHERNET (LAN)
CONNECTORS
PT2_TX_EN
PT2_TX_CLK
PT2_TXD<3..0>
PT2_RX_ERR
PT2_RX_CRS
PT2_RX_CLK
PT2_RXDV
PT2_RXD<3..0>
PY25MHZOSC
TITLE:
ETH_TXD<7..4>
ETH_RXD<7..4>
PT2_COL_DET
PHYOSC25M
5B6
6C4
6B1
25B7v
6A7
LAN_CLK
19B3v
19B3v
19B3v
AV_LAN_CLK
25B7v
5A4
6B1
LAN_CLK
GTXCLK
5C6
PT1_TX_EN
GMII_TX_ER_
CLK_TO_MAC
TX_EN
PT1_TXD<3..0>
PT1_RX_ERR
PT1_TX_CLK
5B6 6C4
25B7v
ETH_TX_CLK
19C3v
ETH_RX_ERR
PT1_RX_CRS
PT1_RX_CLK
ETH_RX_CRS
PT1_RXDV
PT1_RXD<3..0>
PT1_COL_DET
ETH_RX_CLK
ETH_TXD<3..0>
ETH_RXD<3..0>
2
SINGLE 50 PIN
I.M.
CARD PLUG-CONNECTORS
USED ON BOTTOM OF MOTHERBOARD
FOR CONNECTION TO ETHERNET CARD
ETH_RXDV
ETH_TXD<7..0>
19C3v
19C3v
25A1v
5A5
25A1v
5C3
25B7v
6D3 5B2
19C3v
ETH_COL_DET
V3_3
ETH_TX_EN
CLKTOMAC
CLKTOMAC_TESTPNT
GMII_CLKFROM_MAC
19B3v
MHZ)
6B4
5A5
ETH_RXD<7..0>
19C3v
3
TX_CLK
TXD<7..0>
RX_ERR
RX_CRS
RX_CLK
RXDV
RXD<7..0>
25A1v
4
CLOCK TESTPOINTS:
REFCLK & CLKC
TESTPOINTS ARE IN THE PHY BLOCK
CLKA AND CLKB TESTPOINTS ARE IN THE LIU BLOCK
IS ONLY
MODE (50
1A8
BLOCK
I23
COL_DET
_phy_dp83865bvh_dn
HIERARCHY
5
SPARE<4..1>
25B4v
5A4
AV_LAN_CLK
M3X_LAN_CLK
RB14
RB15
30
6B4
25MHZOSC_TO_PROC
9B2
5 PY25MHZOSC
6
7
RP13 8
M3X_CLADCLK_TO_LIU
BLOCK NAME:
CLK_TO_MAC
5
3
1
6
M3X_CLADCLK
CONN_6P_U
5
6
7
RPB23 8
REFC_25M
V3_3
2
M3X_CLKC
7
M3X_LAN_CLKO
1D2
OUT
VCC
5A4
10B7
19B3v
GND
1
OSC
YB05
JP01
JMP_3
.1UF
C04
V3_3
8
4.7UF
C03
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE6
.1UF
C02
:
3
1
4.7UF
C01
CR-6
ONLY
GMII
RB08
2.2K
A
B
C
D
A
8
DDR_RAS
DDR_WE
DDR_CKE
DDR_CKINV
DDR_CK
DDR_CS
DDR_LDM
DDR_UDM
7C3
7C3
7C3
7C3
7C3
7C3
7C3
7C3
V2_5
DDR_CAS
7C3
12
11
10
9
8
7
6
5
4
3
2
DDR_BA1
4.7UF
7C3
CB74
DDR_BA0
.1UF
B
CB110
1
A8
B8
D10
A10
A9
B9
C9
C10
D9
D11
C11
B10
A11
C12
B11
A12
B12
A13
B13
A14
C14
D13
C13
.1UF
7B3
4.7UF
CB89
D12
FOR DDR
SDUDM
SDLDM
SDCS*
SDCLKP
SDCLKN
SDCLKEN
SDWE*
SDRAS*
SDCAS*
SDBA[1]
SDBA[0]
SDA[12]
SDA[11]
SDA[10]
SDA[9]
SDA[8]
SDA[7]
SDA[6]
SDA[5]
SDA[4]
SDA[3]
SDA[2]
SDA[1]
SDA[0]
7
SDRAM I/F
DS33M33_U
CB49
0
4.7UF
DDR_A<12..0>
6
BLOCK NAME:
4.7UF
U05
7
6
7D2
13
12
11
10
9
8
7
6
5
4
3
2
1
0
B4
B5
A5
A6
B6
A7
D7
D6
C6
D5
C5
D4
C4
C3
SDDQ[14]
SDDQ[13]
SDDQ[12]
SDDQ[11]
SDDQ[10]
SDDQ[9]
SDDQ[8]
SDDQ[7]
SDDQ[6]
SDDQ[5]
SDDQ[4]
SDDQ[3]
SDDQ[2]
SDDQ[1]
SDDQ[0]
_rc_top_dn_.
14
A4
SDDQ[15]
5
DDR_DQ<15..0>
7C1
DDR_LDQS
C7
SDLDQS
15
7C1
DDR_UDQS
B7
A3
.01UF
.01UF
CB72
C08
7A1
CB75
DDR_VREF
4.7UF
4.7UF
CB76
CB63
.1UF
V2_5
RB12
1.00K
RB13
1.00K
SDUDQS
10B3
5
4
4
7C8
7B8
32
31
30
29
2
1
0
35
36
37
38
39
40
28
41
42
26
27
22
23
21
44
45
3
4
5
6
7
8
9
10
11
12
DDR_BA0
DDR_BA1
DDR_CAS
DDR_RAS
DDR_WE
DDR_CKE
DDR_CK
DDR_A<12..0>
7B8
7B8
7B8
7B8
7B8
7B8
7B8
24
46
DDR_CKINV
DDR_CS
20
DDR_LDM
7B8
7B8
47
DDR_UDM
7A8
3
3
DS33M33DK01A0
ENGINEER:
2
P.7
STEVE SCULLY
7D5
10B3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS
UDQS
DDR_VREF
MT46V16M16BG75
U06
DDR MEMORY.
TITLE:
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
BA0
BA1
CAS
RAS
WE
CKE
CK
CS
CK_INV
LDM
UDM
V2_5
2
DNU
DNU
19
50
C
7A4
CB146
NC
NC
NC
NC
NC
14
53
43
25
17
8
.1UF
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
58
6
64
12
52
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE7
.1UF
VSS
VSS
VSS
48
34
66
D
:
CB83
CR-7
CB102
18
1
33
VDD
VDD
VDD
.01UF
15
55
9
3
61
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CB58
49
VREF
CB90
4.7UF
CB85
3
2
1
0
5
4
2
10/03/2007
7C4
1
7/26(TOTAL)
PAGE: 7/12(BLOCK)
DATE:
DDR_DQ<15..0>
4
7
8
54
8
9
56
5
10
57
10
11
59
7
12
60
6
13
62
11
14
63
13
15
7C5
DDR_LDQS
16
65
7C5
DDR_UDQS
51
1
A
B
C
D
A
B
5
6
1K
8
4
3
1
2
8C1
7
1B8
8
1D3
M3X_MT2
1B5
1C5
1C5
1C5
1C5
4
5
6
7
RPB29 8
10K
1B1
8D6
5
6
8B3
1A8
8C6
8B3
1A8
1A8
V3_3
8B3
M3X_TEST_EN
6
8
M3X_JTDI
M3X_JTDO
V3_3
10
4
2
GND
7
5
3
1
J16
7
9
7
5
3
1
FOR INT
5
6
CONN_10P
VCC
TDO
TDI
TCK
TMS
PULLUP
M3X_JTCLK
M3X_JTMS
INSTANTIATE
4
330
7
2
3
RPB53 8
1
10B5
10B5
10B5
8D6
FPGA
1C5
V3_3
6
BLOCK NAME:
M3X_JTRST_N
IN
DS28
V3_3
1B1
1B1
8D4
1B1
8D3
6
DATA<7..0>
DATA<7..0>
DATA<7..0>
_rc_top_dn_.
NEEDS FOR MT1
9C3
9C3
8D6
9C3
8D4
NEEDED)
DOUBLE CHECK BIAS
8D3
D7_SPI_CPOL
8D3
D6_SPI_CPHA
8C6
D5_SPI_SWAP
8D4
1C1
1C1
MT0 & MT2 ATTACED TO RPACK
AS TESTPOINTS FOR PROTO BOARD (NOT
M3X_INT
1B5
2
M3X_MT1
1B5
3
1
M3X_MT0
4
10K
7
2
3
RPB33 8
7
1
1B5
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE8
8 RPB32
:
2
2
2
7
5
6
JP20
C
D
CR-8
3
1
3
JP21
3 1
1A8
9
11
13
9
11
13
5
1A2
ADDR<13..0>
9C1
7
7
8B3
8B3
13
11
9
7
5
3
1
14
12
10
8
6
4
2
J24
8C6
8C6
14
12
10
8
6
4
2
1A8
1A8
CONN_14P
5
5
1
8D3
3
8D4
5
6
3
1
8D6
10B5
4
1K
7
2
3
V3_3
RPB36 8
1
5
8D6
8
6
4
2
1A8
9C3
2
2
1B1
1
0
15
13
11
9
7
5
3
1
JMP_3
16
14
12
10
8
6
4
2
5
6
7
1K
4
1A8
13
11
9
7
5
3
1
14
12
10
8
6
4
2
J30
1D3
2
14
12
10
8
6
4
2
8D3
2
2
CONN_14P
313
211
1 9
8 RPB52
3 5
4 7
5
6
2 3
1K
7
0
14
12
10
8
6
4
2
CS_X1
M3X_CS
1 1
8C2
SPI_SS
DATA<7..0>
D2_SPI_CLK
SPI_SCK
8 RPB48
16
14
12
10
8
6
4
2
1A8
1B5
1B1
8B3
1C1
1A5
JMP_3
2
JMP_3
10
8
6
4
2
M3X_ALE
5
M3X_IFSEL_SIZE
7
5
6
1D3
10K
10K
4
3
2
1
4
3
2
1
RD_DS
9C1
WR_RW 9C1
8 RPB50
6
M3X_HIZ_N
7
M3X_DCESEL
M3X_SPISEL
10
8
6
4
2 M3X_INT
8 RPB49
CONN_10P
9
7
5
3
1
M3X_RMIISEL
1D3
8A2
9
7
5
3
1
M3X_IFSEL_STYLE
5A4
1A8
M3X_CS
V3_3
J23
10B5
10B5
1B8
1A8
1A8
8A8
1
1B5
8A2
3
4
INVERTER
ENGINEER:
STEVE SCULLY
2
P.8
M3X_ALE
DS33M33DK01A0
1
BIAS+CONFIG.
TITLE:
M3X_SPISEL
UB05
NC7SZ86_U
8B2
1A8
1D3
10/03/2007
1D3
1D3
1
8/26(TOTAL)
PAGE: 8/12(BLOCK)
DATE:
ALE SHOULD BE TIED HIGH FOR NON-MULTIPLEXED
ADDRESS
OPERATION AND TIED TIED LOW DURING SPI MODE (SPISEL=1).
REMOVE THIS INVERTER TO MAKE USE OF THE JUMPER OPTIONS FOR ALE (ABOVE)
V3_3
3
9C3
8C6
CONN_16P
15
13
11
9
7
5
3
1
J21
1D3
JMP_3
1A8 10B5
8D6 8D4
DATA<15..0>
10B5
15
13
11
9
7
5
3
1
DATA<7..0>
D1_SPI_MOSI
SPI_MOSI
DATA<7..0>
D0_SPI_MISO
SPI_MISO
8C6
4
1B1
1C1
1B5
1B1
8D3
8D3
9C3
9C3
8D4
8D4
0
12
10
10B5
10B5
8D6
1C1
1A5
4
3
1
3
JP12
1
1
3
JP22
JP14
1
JP13
1
3
JP11
A
B
C
D
A
B
C
D
M33_RCLK1 F3
9C1
9C1
9C1
9C1
9D1
H3
8
M33_RPOS3
M33_RCLK3
M33_RNEG3
RNEG/RLCV
K4
RPOS/RDAT
RLCLK
J3
PORT
M33_GPIOA2
M33_GPIOB2
H5
J6
GPIOA
GPIOB
7
PORT
M33_GPIOB3
K3
GPIOB
BLOCK NAME:
6
M33_GPIOA3
L4
GPIOA
M33_TPOS3
M33_TNEG3
TPOS/TDAT
J5
K5
TNEG
TLCLK
M33_TCLK3
M33_TPOS2
G5
TPOS/TDAT
J4
M33_TNEG2
H6
TNEG
TLCLK
M33_TCLK2
M33_GPIOB1
F2
GPIOB
G3
M33_GPIOA1
G2
GPIOA
10C4
10C4
10C4
10C4
10C4
10C4
_rc_top_dn_.
9A5
9A5
9C4
9C4
9C4
9A5
9A5
9C4
9D4
9D4
9A5
9A5
9D4
M33_TPOS1
D2
TNEG
TPOS/TDAT
9D4
9D4
M33_TCLK1
M33_TNEG1
E3
6
F4
TLCLK
DS33M33_U
RPOS/RDAT
U05
PORT
DS33M33_U
RNEG/RLCV
RLCLK
U05
RPOS/RDAT
RNEG/RLCV
RLCLK
DS33M33_U
F3
H3
J2
J2
M33_RNEG2 H4
M33_RPOS2 H2
M33_RCLK2
M33_RNEG1 G4
M33_RPOS1 E2
9D1
9D1
9D1
9D1
U05
PORT / PIN ASSIGNMENTS
DS33M33_RCLK1
IS AT PIN
DS33M33_RCLK2
IS AT PIN
DS33M33_RCLK3
IS AT PIN
7
5
M33_TPOS3
4
3
5
6
13
11
9
7
5
3
1
14
12
10
8
6
4
2
J01
14
12
10
8
6
4
2
CONN_14P
13
11
M33_GPIOB3
7
2
10K
9
M33_GPIOA3
RPB08 8
1
3
7
3
1
5
M33_GPIOB1
M33_GPIOA1
4
5
3
M33_TNEG3
M33_GPIOB2
6
1
J18
M33_TCLK3
5
10K
7
RPB13 8
3
5
M33_TNEG2
M33_TPOS2
1
J15
6
4
2
6
4
2
5
3
1
6
4
2
0
1
2
3
4
5
6
7
CONN_6P_U
5
3
1
CONN_6P_U
5
3
1
CONN_6P_U
6
4
2
6
4
2
4
4
3
2
1
4
3
2
1
5
6
330
5
6
7
RPB04 8
330
7
RPB07 8
5
6
7
4
3
2
1
4
3 3
4 4
3 3
4 4
3 3
4 4
3
1 1
2 2
1 1
2 2
1 1
2 2
8D3
DS01
DS06
DS07
V3_3
8D6
5
LIU_RNEG3
LIU_RPOS3
21C2v
INT
RST
21C3v
1D2 1D3 10B7
10B7 20A2v
20A3v
M3X_CLADCLK_TO_LIU
8D4
3
LIU_RCLK3
I/F.
2
5
3
1
6
4
2
5
3
1
TE3_INT
20A5v
10B4
9A8
9A8
9A8
9B8
9C8
9C8
9D8
9D8
9D8
1B8
20B5v
21C4v
21C8v
04/15/2007
1B5
20D8v
1D3
1D3
1
9/26(TOTAL)
PAGE: 9/12(BLOCK)
DATE:
1A8
1A8
1A8
21D2v
21D6v
1A2 10B5
1A8 8B5
21C2v
21C3v
21C6v
21C4v
10B5
10B5
11B3
1A8
RD_DS 8C1
WR_RW 8C1
RESET_SYS
6C6
J17
M33_RPOS2
M33_RNEG2
M33_RCLK2
J14
M33_RNEG1
M33_RPOS1
M33_RCLK1
J12
1
M33_RCLK3
M33_RNEG3
4
M33_RPOS3
6
2
6
4
2
6
4
2
ADDR[5..0]
6
4
2
CONN_6P_U
P.2,9,20-22
STEVE SCULLY
LIU
6
4
2
CONN_6P_U
5
3
1
CONN_6P_U
TE3_L_CS
0
1
2
3
4
5
1
LIU_RPOS2
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
CS
RD_DS
WR_RW
3
5
LIU_RNEG2
1
LIU_RCLK2
BLOCK
DS33M30M31M33EE01A0
ENGINEER:
T3E3
TITLE:
RED_GREEN
RED_GREEN
RED_GREEN
1K
8 RPB02
5
3
2
1K
7
6
1
8 RPB05
1B1 10B5
1A8 8B3 8C6
21C8v
21D3v
21D7v
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
LIU_TPOS3
LIU_TNEG3
LIU_TCLK3
LIU_TPOS2
LIU_TNEG2
LIU_TCLK2
HIERARCHY
21C7v
5
LIU_RPOS1
LIU_TPOS1
_ds3154_liublock_dn
6
3
LIU_RCLK1
LIU_RNEG1
1
LIU_TNEG1
LIU_TCLK1
2
TO ALLOW LOOPBAK T--R
4
2
3
PLACE TESTPOINTS
DATA[7..0]
BUG FIX:
PCB REV 01A0 HAD THE
DATABUS TAPS WRONG [0:7]
THIS HAS BEEN FIXED IN THE
FPGA.
9A6
9A6
9A6
9B6
9C6
9C6
1
M33_TNEG1 3
M33_TPOS1 5
M33_TCLK1
J13
4
M33_TCLK2
9D6
9D6
9D6
M33_GPIOA2
2
1
5
E3_MCLK_IO
M3X_CLKB
8
T3_MCLK_IO
M3X_CLKA
CR-26 : : @\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE9
CR-9
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE1_I9@\_RC_LIB\.\_DS33M30DK_DN_\(SCH_1):PAGE7
ALTERNATE_MCLK
A
B
C
D
A
8
2B7
2B7
23A5v
23A4v
CPLD_RDOH
CPLD_RDOHSOF
CPLD_RDOHVLD
CPLD_TAOHSOF
CPLD_TAOHVLD
CPLD_RDOH
CPLD_RDOHSOF
CPLD_RDOHVLD
CPLD_TAOHSOF
CPLD_TAOHVLD
23D7v
6A7
9B2
CPLD_OHCLK
CPLD_OHCLK
23D7v
CPLD_OH1
CPLD_OH1
1D2
1D2
1D3
CP_DUT_CLKC
M3X_CLKC
6
BLOCK NAME:
CP_DUT_CLKB
M3X_CLKB
7
CP_DUT_CLKA
M3X_CLKA
CP_DUT_CLADCLK
CPLD_DTOHSOF
CPLD_DTOHSOF
M3X_CLADCLK
CPLD_DTOHCLK
CPLD_DTOHCLK
9B2
2C7
23A6v
CPLD_DTOH
CPLD_DTOH
23D7v
2C7
23A6v
CPLD_ATOHSOF
CPLD_ATOHSOF
6C6
2B7
23A5v
CPLD_ATOHCLK
CPLD_ATOHCLK
1D3
2C7
23A5v
23D7v
2C7
2C7
23A6v
23A6v
2C7
23A6v
2B7
2B7
23A5v
23A5v
2B7
23A5v
_rc_top_dn_.
5
RD_DS
WR_RW
CPLD_CS 1A8
ADDR<3..0>
DATA<7..0>
1B1
1A2
9C3
9C1
1A8
8B3
8C6
8D3
23C7v
23C7v
1A8
9A6
9A6
9B6
9B6
9C6
9C6
4
8D6
7D5
7D2
E12
E9
E5
B16
DDR_VREF E8
23C4v
V1_8
V2_5
23B4v
24B4v
23D6v
23D6v
23D6v
23D6v
23D6v
23D6v
1B5
8D4
23C7v
9A5
9A5
11B3
23B7v
1D3
1D3
8B5
1A8
1A8
9C1
8C1
23C7v
9C1
M33_GPIOB3
8C1
M33_GPIOB3
M33_GPIOB2
CPU_RESET
RD
WR
CPLD_CS
ADDR<3..0>
DAT<7..0>
M33_GPIOA3
M33_GPIOB1
9B1
9A5
M33_GPIOB2
RESET_SYS
9A5
M33_GPIOA2
9A5
M33_GPIOA3
9A5
23A5v
M33_GPIOB1
1A8
23A6v
23A6v
2B7
23A5v
M33_GPIOA2
2C7
2C7
2B7
M33_GPIOA1
CPLD_TAOHEN
CPLD_TAOH
CPLD_ATOHEN
CPLD_ATOH
M33_GPIOA1
CPLD_TAOHEN
CPLD_TAOH
CPLD_ATOHEN
CPLD_ATOH
BLOCK
overheadcpld_dn_
HIERARCHY
VREF
VDDQ_2.5V[7..1]
VDDP_2.5V
VDDP_2.5V
VDDP_2.5V
AVDD_1.8V
U05
3
3
DS33M33DK01A0
ENGINEER:
M15
F15
K15
D15
P15
H15
D1
F1
H1
HVDDB_3.3V
RVDDA_1.8V
RVDDB_1.8V
TVDDA_1.8V
TVDDB_1.8V
TVDD1_1_8V
TVDD2_1_8V
TVDD3_1_8V
2
V3_3
HVDDA_3.3V
P.2,10,23-24
STEVE SCULLY
OVERHEAD.
TITLE:
PWR & GND
DS33M33_U
V1_8
2
RHVSSA
L15
4
RHVSSB
E15
5
TVSSA
N15
6
K1
CVDD_1.8V
TVSSB
G15
7
AVSS
A16
M1
CVDD_1.8V
TVSS1
E1
B
8
CVSS1
L1
VDD18[12..1]
TVSS2
G1
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE10
CVSS2
N1
VDD33[6..1]
TVSS3
J1
C
:
VSS[22..1]
D
CR-10
VSSQ[7..1]
10/03/2007
1
10/26(TOTAL)
PAGE: 10/12(BLOCK)
DATE:
V1_8
1
A
B
C
D
A
B
V5_0
8
4.7UF
CB156.1UF
CB1634.7UF
IN4
RST
SHDN
5
6
7
IN2
IN3
3
4
RST
SHDN
6
7
IN4
IN1
7
1.8V
10
17
GND
11
15
14
13
GND
SET
OUT4
OUT3
OUT2
OUT1
12
17
GND
MAX1793_U
2
5
2.5V
10
11
15
14
13
GND
SET
OUT4
OUT3
OUT2
UB09
IN3
C13
IN2
CB144.1UF
.01UF
3
V1_8
CB139
BLOCK NAME:
6
V2_5
1
.1UF
_rc_top_dn_.
330
CB52
10UF
CB109
RB28
4.7UF
CB87
4.7UF
330
V2_5
4
CB140
.1UF
.1UF
CB187
.1UF
CB132
V3_3
1A8
1B5
10B4
9B1
PARENT BLOCK:
5
<CON_PARENT_NAME>
4
3
.1UF
V3_3
RESET_SYS
REGULATOR OUTPUT AND V2.5
SHOULD
TO BUILD
0.05
OHM OF RESISTANCE
SHARING BETWEEN THE 2.5V
1% REGULATORS
FOR THIS IS:
1 INCH LONG, 10 MIL WIDE, 1 OZ COPPER
GREEN
UB124 DS30
1
2
NC7SZ86_U
BUFFER
RB30
TRACES BETWEEN
BE LONG ENOUGH
TO ENSURE LOAD
TRACE GEOMETRY
V1_8
2
GREEN
V3_3
V2_5 1
DS32
CB182
CB183
CB170
4
12
CB59
1
2
OUT1
10UF
470UF
CB145
4.7UF
IN1
.1UF
4.7UF
C16
CB129
2
CB148
MAX1793_U
.1UF
UB08
CB28
C
.1UF
CB99
V3_3
.1UF
4.7UF
V3_3
4.7UF
CB186
D
CB21
CB166
4.7UF
1
.1UF
10UF
CB51
.1UF
10UF
CB91
5
CB120
CB03
CB111
C15
4.7UF
CB82
4.7UF
4.7UF
.1UF
CB50
4.7UF
4.7UF
4.7UF
CB80
CB123
CB117
CB104
V3_3
CB14
3
V3_3
2
4
V2_5
ENGINEER:
UB07
3.08V
2
RESET*
VCC
MAX811_U
GND
MR*
2
P.11-12
STEVE SCULLY
DS33M33DK01A0
POWER.
TITLE:
CB27
.01UF
4.7UF
4.7UF
6
CB26
7
CB136
8
3
1
3
4
SW01
2
1
4.7UF
CB81
V1_8
10/03/2007
4.7UF
1
11/26(TOTAL)
PAGE: 11/12(BLOCK)
DATE:
1
.1UF
4.7UF
CB103
CB48
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE11
CB133
:
4.7UF
4.7UF
4.7UF
CB175
CB1504.7UF
CB119
CB127
1
2
4.7UF
CB126
CB181
10UF
CB174 470UF
2
470UF
CB157
4.7UF
CB25
.1UF
CB57
CB121
CB171470UF
CB141
CB35
.1UF
.1UF
CB56
4.7UF
1
2
.1UF
.1UF
.1UF
4.7UF
C23
4.7UF
CB143
.1UF
C18
4.7UF
4.7UF
10UF
CB86
CB138
CB118
4.7UF
CB108
CB128
CB142
.1UF
CB61
.1UF
.1UF
CB12
CB116
.1UF
C12
.1UF
.1UF
CB131
CB04
CB05
CB115
4.7UF
4.7UF
CB06
CB122
4.7UF
CB71
.1UF
.1UF
.1UF
CB55
.1UF
.1UF
CB105
.1UF
CR-11
CB60
.1UF
A
B
C
D
A
B
8
GND_TP03
IN3
IN4
RST
SHDN
4
5
6
7
10
17
GND
7
GND_TPB01
1
6
BLOCK NAME:
GND_TP02
GND_TP01
GND_TP11
11
15
14
13
GND
SET
OUT4
OUT3
OUT2
OUT1
1% REGULATOR
SHDN
IN4
5
RST
IN3
4
7
IN2
3
6
IN1
GND_TP04
GND_TPB02
17
GND
12
10
11
15
14
13
GND
SET
OUT4
OUT3
OUT2
12
68UF
2
OUT1
MAX1793_U
UB10
IN2
3.3V
IN1
3
CB159
C19
10UF
2
R04
0.0
C21
10UF
_rc_top_dn_.
R02
0.0
UB11
V3_3
4.7UF
5
4.7UF
CB13
CB154
CB153
PARENT BLOCK:
470UF
3.3V
5
DS31
V5_0
.1UF
CB190
HB02
CB169
<CON_PARENT_NAME>
4
4.7UF
CB161
GND
SET
11
17
OUT4
15
GND
OUT3
14
10
OUT2
13
HB04
3.3V
3
1
.1UF
ENGINEER:
CB189
2
68UF
V5_0
JB09
2
P.11-12
STEVE SCULLY
DS33M33DK01A0
7
6
5
4
3
2
.1UF
CB155
POWER.
TITLE:
SHDN
RST
IN4
IN3
IN2
IN1
MAX1793_U
4.7UF
CB151
OUT1
HB05
3
.1UF
CB167
UB13
.1UF
CB152
12
10UF
CB162
MOUTING HARDWARE
HB01
HB03
POWEROK 12A8
R05
0.0
4.7UF
CB180
10UF
C24
V3_3
4
.1UF
CB149
1
2
6
10UF
7
68UF
2
1
2 CB185
MAX1793_U
2
3.3V
GND_TPB03
POWEROK
V5_0
V5_0
GND_TPB06
12A4
8
C17
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE12
1 RPB59 8
1
2 CB176
10UF
CB173
7
2
1
2
1
1
12/26(TOTAL)
PAGE: 12/12(BLOCK)
DATE:
10/03/2007
1 AMP
DB01
L1
100O100MZH
C1
10UF
C
:
330
10UF
C22
D
CR-12
10UF
.1UF
68UF
CB158
1
2
4.7UF
CB172
GREEN
3 3
1 1
4 4
2 2
RED
6
3
.1UF
CB179
5
4
RED_GREEN
C20
10UF
CB188
A
B
C
D
A
B
C
54
55
56
57
58
61
ICOC21
ICOC20
ICOC13
ICOC12
ICOC11
ICOC10
70
PROCSER_IN
8
69
68
SCI2_IN
PROCSER_OUT
66
SCI2_OUT
TEST 63
53
ICOC22
GND
52
ICOC23
RXD1
TXD1
RXD2
TXD2
TEST
ICOC10
ICOC11
ICOC12
ICOC13
ICOC20
ICOC21
ICOC22
ICOC23
U09
INT6*
D
8
7
MMC2107
CONTROL
INT7*
89
7
15D5
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE2_I10@\_RC_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE1
84
:
TIM_16H_8L
EB3*
INT5*
96
82
88
EB3
EB2
EB2*
INT4
98
16B4
79
15C8
17C7
YC0
80
100
EB1*
INT3*
USER_LED1
USER_LED2
71
RUN_KIT_USR
KIT_STATUS
INT2
17B7
14D2
90
16C5
16C6
1B6^
INT0*
1B8^
91
14B4
16C4
75
108
14B7
EB1
EB0
INT2*
PQB0
PQA4
107
MOSI
OUT
CR-13
104
PQB3
INT1*
72
101
EB0*
PQB3
PQB2
PQB1
105
PQB2
106
PQB1
109
124
6
6
16C4
1A8^
1A6^
22
ONCE_DE_B
SPI_CS
143
94
SPI_SCK
OUT
15D4
OUT
16B4
16C5
5
16C6
PARENT BLOCK:
1B6^
16B8
4
27
30
31
34
35
15
14
13
12
11
\_rc_top_dn_\
25
22
21
20
17
16
15
12
10
7
5
4
3
16
17
18
19
93
20
CPUCLK_OUT
21
120 PROC_RESET_OUT
18C2
128
14D1
23
RESET_IN
CS0
118
86
85
15D5
24
CS2
83
14B7
25
CS3
14B4
26
TC1
78
81
CS1
27
TC2
28
67
62
2
1
30
29
144
4
31
CSE1
CSE0
16A3
5
60
_motprocrescard_dn.
SS*
DE*
SCK
RSTOUT*
CLKOUT
RESET*
CS0*
CS1*
CS2*
CS3*
TC1
TC2
CSE0
CSE1
BLOCK NAME:
15D6
YCO
SPI_MOSI
SPI_MISO
16C5
110
PQA3
XTAL
125
15D6
PQB0
PQA3
PQA1
PQA0
PQA1
111
15D5
EXTAL
130
15D5
PQA4
16C6
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
U09
3
MMC2107
PORT
3
DS33M33DK01A0
ENGINEER:
2
1
VDDSYN
14A2
14A5
14C7
14D7
16A1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
V3_3
10
9
8
7
6
5
4
11
13
14
23
24
26
28
0
11
6
50
12
139
1
13
137
49
14
136
3
15
134
2
16
132
47
17
131
29
19
18
20
119
122
21
117
121
22
116
1
STEVE SCULLY
2
P.1,13-18
10/03/2007
BLOCK
1
13/26(TOTAL)
PAGE: 1/6(BLOCK)
DATE:
OF PROCESSOR HIERARCHY
PD<31..0>
MICROPORT.
TITLE:
BEGINNING
36
10
135
16D2
RW
37
9
D10
16C4
14B7
95
38
8
D9
59
RW
OE 14B4
RCON 14C7
97
OE*
39
7
D8
99
SHS*
40
6
D7
41
5
D6
TA*
TA
TEA
102
TEA*
42
VSSA
VRH
113
VRH
D4
112
VRL
4
D5
15D3
43
VSSF
92
VSTBY
FLASH_VPP
3
VSS4
87
46
2
VSS3
VPP
D1
48
1
TDI
115
VDDA
D0
51
PQA0
74
VDDF
0
TCLK
103
VDDH
114
TRST*
123
VDDSYN
73
142
141
VDD8
VSSSYN
126
VSS8
140
133 ONCE_TDI
2107_TDO
15D4
129
VDD7
VSS7
127
TDO
77
VDD6
VSS6
76
TMS
65
VDD5
VSS5
64
138
XTAL
OSC_MCU
ONCE_TCLK
ONCE_TRST_B
ONCE_TMS
15D3
45
VDD4
RB27
0.0
33
VDD3
44
D3
CB160
.1UF
19
VDD2
32
D2
CB164
1UF
9
VDD1
VSS2
18
VSS1
8
MISO
IN
1A6^
PA<22..0>
A
B
C
D
A
B
16D4
14A5
8
13A1
14A2
13A2
ENABLE
13D3
4
25
13
12
PA<19..1>
27
28
14
9
3
15
26
31
16
10
2
17
23
1
18
11
30
19
PD<28>
PD<22>
PD<23>
PD<21>
PD<16>
PD<17>
PD<26>
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
U12
I142
CY62148V
7
V3_3
PD<18>
PD<19>
RCON
13A2
13A2
13A2
16A1
13A2
BOOT
INTERN/EXTERN
16A1
FLASH
14A5
16A1
W/ PLL
14A2
14A2
14A2
16A1
DRIVE
INTERNAL
XTAL
FULL
16A1
13A2
16A1
13A2
13A2
4
3
2
1
4-MBIT
(512K
X 8)
CY62148V
5
6
10K
10K
5
6
7
29
28
27
26
25
24
19
18
17
15
14
13
5
5
16A1
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
U11
I203
CY62148V
4
V3_3
4-MBIT
(512K
X 8)
CY62148V
4
\_rc_top_dn_\
PA<19..1>
27
9
PARENT BLOCK:
13A1
14D7
26
23
25
4
28
3
31
10
11
12
13
14
15
16
2
1
18
17
30
19
LOAD TO GND
14A8
14C7
16D4
13A2
WHEN SET FOR
BOOT INTERNAL
D18 HAS A 10K
PD<31..24>
V3_3
_motprocrescard_dn.
30
20
6
31
21
BLOCK NAME:
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
5
6
7
RPB62 8
10K
7
RPB61 8
RPB57 8
4
3
2
1
4
3
2
1
6
RESET CONFIGURATION
5
8
C
14A2
16A1
MASTER MODE 14A2
14A5
16A1
7
32
A6
6
7
D
8
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE2_I10@\_RC_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE2
29
VCC
A5
7
6
A4
8
:
24
WE*
EB0
OE
CS0
22
OE*
A3
5
A7
16
GND
9
CR-14
5
8
A6
6
CE1*
4
32
VCC
7
A2
10
3
29
WE*
A5
7
6
A1
11
2
24
A4
8
5
A3
9
A0
12
1
16B4
13D7
16C4
14B7
13D3
16C4
14B7
13B5
OE*
EB1
OE
CS0
22
CE1*
4
A7
16
GND
A2
10
3
A1
11
2
A0
12
1
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
22
21
20
19
18
17
16
20
19
18
17
15
14
13
3
13A2
1B8^
DS33M33DK01A0
PD<23..16>
ENGINEER:
17B7
IN
IN
IN
WR_RW
RD_DS
CS_X1
CS_X2
CS_X3
PROC_OSCIN
16A1
P.1,13-18
14D7
MISC_IO<12>
MISC_IO<11>
MISC_IO<10>
MISC_IO<9>
THIS
EN_SOURCE_TIME
ENABLE_CLBK
ENABLE_DRV
NULL NETS
(NOT USED IN
MISC_IO<8..1>
2
4
INT4
RESET_OUT
D_DUT<7..0>
14C7
7
3
INT2
OUT
IN
IN
IN
17A5
18C2
1
14/26(TOTAL)
PAGE: 2/6(BLOCK)
10/03/2007
17C3
17D3
17D3
1A8^
1A8^
1A8^
1A8^
1A8^
17C7
17C3
17C3
17A4
1A8^
1A8^
1A8^
1A8^
15D5
17C3
17C7
DATE:
IO
IO
IO
IO
IO
1
13B5
1A8^
16A3
17C7
DESIGN)
IO
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
5
6
2
INT3
10K
I219
RPB56 8
1
RESET_IN
A_DUT_<13..0>
13A7
1B8^
17C7
2
17B7
1B8^
STEVE SCULLY
MICROPORT.
TITLE:
23
21
3
A
B
C
D
A
B
C
D
13A7
8
15B8
PRT1_IN
PRT1_OUT
8
PRT1_IN
15A8
15B8
7
PRT1_OUT
15A8
5
4
3
2
1
2
330
1
RB26
E
D
C
B
A
J34
J
H
G
F
FORCEOFF*
VCC
R1IN
T1OUT
R1OUT
FORCEON
T1IN
T2IN
INVALID*
R2OUT
9
8
7
6
7
4
6
BLOCK NAME:
5
6
7
10K
1
V3_3
18C2
JP26
UART_DIGOUT
15B8
15B2
15B8
15B2
5
RESET_IN
15B2
CB177
4.7UF
13
11
9
7
5
3
1
REGIN
7
4
SUSPEND_HIGH
RST*
9
SUSPEND_LOW*
VBUS
8
12
USBDP
4
CP2101
U10
10K
5
6
7
RPB64 8
V3_3
3
4
1
2
27
1
2
DTR*
DSR*
DCD*
RI*
19
20
21
22
NC8
NC9
NC10
NC11
DS33M33DK01A0
18
NC7
ENGINEER:
15B5
7
5
6
10K
5
6
7
RPB60 8
10K
15A5
2
P.1,13-18
4
STEVE SCULLY
MICROPORT.
TITLE:
3
28
3
2
23
CTS*
SSPL
1
24
RXD
RTS*
15B4
USB_DIN
25
RPB58 8
USB_DOUT
26
2
TXD
VDD IS A
(UNUSED) OUTPUT
ON CP2101 CHIP
4
2
1
FLASH_VPP 3
SSPL 11
USBDM
5
2
13A6
1
14
13A6
3
JB08
ONCE_TRST_B
12
V5_0
ONCE_DE_B
10
13B5
8
6
4
2
ALIGN KEY
ONCE_TMS
CON14P
\_rc_top_dn_\
13A6
V3_3
2107_TDO
ONCE_TCLK
13D6
PARENT BLOCK:
1
2
3
4
USB
13B5
J35
14D1
VDD
DATDAT+
GND
USB_DOUT
JP25
UART_DIGIN
USB_DIN
1A8^
_motprocrescard_dn.
2
PROCSER_IN
2
3
13A7
2
XTAL
PROCSER_OUT
RPB63 8
13B8
16B5
11
12
13
14
15
16
17
18
19
20
13B8
1
16B5
V+1
V+2
C1+
C1-
C2+
C2-
V-
GND
T2OUT
R2IN
UB14
MAX3233E
2
DS29
PLACE PADS FOR CAP
BUT DO NOT POPULATE
CONN_DB9P
10
9
6
5
4
3
2
1
V3_3
UART_DIGOUT
UART_DIGIN
17C7
1
1.0M
GREEN
KIT_STATUS
1
R03
15A5
15A5
1
2
1
2
ONCE_TDI
10K
RB29
8.0MHZ
USB
13D6
2
1
OSC_MCU 13A6
CB178
4
.1UF
XB01
3
3 1
1
5
1
2
5
GND
3
6
NC1
10
7
NC2
13
8
CB184
2
1
1
2
J33
CON14P
NC3
14
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE2_I10@\_RC_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE3
NC4
15
:
NC5
16
CR-15
1UF
6
VDD
NC6
17
10/03/2007
1
PAGE: 3/6(BLOCK)
15/26(TOTAL)
DATE:
DTR AND RTS
USE RPACK
CONNECTION AS
TESTPOINTS
1
A
B
C
D
A
B
C
4
5
6
8
GND
8MBIT
CS*
SCK
SO
SI
I37
7
AT26DF081_U
4
HOLD*
WP*
3
7
VCC
8
THIS MEMORY IS FOR
SERIAL BOOT (IF
USED)
SPI_SCK
13B5
16C5
16C6
1A6^
10K
7
2
3
I40
RPB54 8
1
V3_3
UB06
3.3V
7
1
6
2
5
16B5
PROC_CS
6
16B8
1A6^
1B6^
1A6^
_motprocrescard_dn.
16C5
13A7
16C5
5
1A6^
5
13B8
13B8
15A7
13B5
13D3
13D7
13A1
EB1
15
PL13B
PL13A
PL12B
PL12A
PL8B
PL8A
PL6B
PL6A
55
PB14A
(PCLKC7_0)
(PCLKT7_0)
(VREF1_7)
30
31
PL20B
PL20A
18
19
21
24
2
P.1,13-18
14C7
13A2
14A5
25
28
14D7
14A2
24
27
(LLM0_GPLLC_IN_A**)
1
10/03/2007
97_IO
1
16/26(TOTAL)
PAGE: 4/6(BLOCK)
DATE:
PD<31..16>
PL22A
23
26
25
20
23
19
17
18
20
16
17
(LLM0_GPLLT_IN_A**)
LLM0_PLLCAP
(LLM0_GDLLC_FB_A)
(VREF1_6)
PL16B
PL18B
(VREF2_6)
(PCLKC6_0)
PL15B
PL16A
(PCLKT6_0)
PL15A
(LLM0_GDLLT_FB_A)
STEVE SCULLY
MICROPORT.
ENGINEER:
2
PL18A
DS33M33DK01A0
29
3
FPGA
LFE2-6-T144
LATTICE
28
TITLE:
56
PB14B
(VREF2_7)
27
\_rc_top_dn_\
4
14
13
12
10
8
7
PROCSER_IN
SPI_CS
13D7
4
CS0
5
PL4A
3
PL4B
PL2B
2
PL2A
EB0
OE
14 1
I36
U08
57
PB16A
3
58
PB16B
PA<19..0>
PROCSER_OUT
13B5
14B4
PROC_CS
SPI_SCK
SPI_MISO
SPI_MOSI
1B6^
16C6
13B5
16C6
13A7
15A7
16B8
13A7
16C6
14B4
14B4
14B7
14A5
PARENT BLOCK:
16C6
1A6^
1B6^
14B7
14B7
14A8
4
26
BLOCK NAME:
13B5
16C5
13A7
SPI_SCK
SPI_MISO
SPI_MOSI
6
59
PB18A
D
8
71
PB28A(VREF2_4)
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE2_I10@\_RC_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE4
PB2A (VREF2_5)
RESET_OUT 37
14D1
:
PB24A
(BDQS24*)
67
1A8^
PB2B (VREF1_5)
38
CS2
63
PB6A (BDQS6*)
CR-16
72
PB28B(VREF1_4)
13C5
NC
45
53
PB13B(PCLKC4_0)
PB4A
40
PB4B
41
65
PB20B
43
NC
46
52
PB13A(PCLKT4_0)
13D4
RW
PB22A
PB6B
44
13
66
12
PB8A(PCLKT5_0)
11
49
10
62
9
PB22B
8
PB8B(PCLKC5_0)
7
50
6
68
5
PB20A
4
69
3
PB24B
2
PB26A
1
70
0
PB26B
17
60
18
PB18B
19
A
B
C
D
8
13A7
1A8^
7
1B8^
PA<19..0>
CS_X3
CS_X2
PROC_OSCIN
14C1
14C1
13A7
14D2
14D2
1B8^
PR29A
80
INT4
(D0)
(D6)
BANK 2
SPI_MOSI
7
5
6
5
LATTICE
D_DUT<7..0>
_motprocrescard_dn.
14C1
BANK 3/8
RD_DS
CS_X1
0
1
2
3
4
5
6
7
8
9
113
114
115
116
118
119
121
122
123
125
126
129
130
PT24B
PT24A
PT22B
PT22A
PT20B
PT20A
PT18B
PT18A
PT16A
PT14B
PT14A
PT12B(PCLKC1_0)
PT12A(PCLKT1_0)
12
13
0
2
1
3
PARENT BLOCK:
\_rc_top_dn_\
4
A_DUT_<13..0>
14C1
WR_RW
112
PT26A
14C1
14C1
ALE_DUT
111
OUT
ENABLE_CLBK
110
PT28A(VREF1_1)
INT3
ENABLE_DRV
127
124
109
NC
NC
PT28B(VREF2_1)
4
PT26B
97_IO
BANK 0
FPGA
LFE2-6-T144
5
11
BLOCK NAME:
6
PR26A
82
INT2
(D7)
(PCLKC3_0)
(PCLKT3_0)
(VREF2_3)
(VREF1_3)
(RLM0_GDLLC_IN_A**)
(RLM0_GDLLT_IN_A**)
1A8^
PR25B
84
MEM_SO
CPUCLK_OUT
PR15B
PR15A
101
100
PR16B
98
15
16
PR16A
PR17B
PR17A
99
96
97
RLM0_PLLCAP
93
(RLM0_GPLLC_IN_A**)
(RLM0_GPLLT_IN_A**)
PR20B
PR20A
91
92
U08
6
22
KIT_STATUS
1A8^
1A8^
14D1
PD<31..16>
15C8
13A1
14A5
14A8
7
4
A
B
8
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE2_I10@\_RC_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE5
(PCLKC2_0)
103
PR13B
C
:
PT6B
136
D
CR-17
PT6A
137
(PCLKT2_0)
PR13A
104
PR2A (VREF1_2)
108
PR2B (VREF2_2)
107
PT10B(PCLKC0_0)
131
PT10A(PCLKT0_0)
134
PT4B
140
PT4A
141
PT2B (VREF2_0)
143
BANK 1
PT2A (VREF1_0)
144
10
3
14B1
14C1
DS33M33DK01A0
ENGINEER:
2
2
P.1,13-18
STEVE SCULLY
MICROPORT.
TITLE:
1A8^
1A8^
1A8^
1A8^
3
10/03/2007
1
31/39(TOTAL)
PAGE: 5/6(BLOCK)
DATE:
1
A
B
C
D
A
8
18B2
3
2
6
1
MEM_SO
MEM_SCK
MEM_CS
18B2
18B2
18B5
18B2
VCC
TDO
TDI
TCK
2
3
1
CS*
SCK
SO
SI
UB04
I15
2.7V
10
8
6
4
2
GND
HOLD*
WP*
VCC
GND
SHDN*
IN
4
5
6
4
7
3
8
6
L_TDO
L_TDI
L_TCK
L_TMS
BLOCK NAME:
RST*
IC
OUT
UB03
MAX1963
I23
AT25160A_U
V3_3
5
7
GND
7
5
3
CONN_10P
MEM_SI
9
7
5
TMS
18C4
18C4
18B5
18B5
4
3
2
1
V3_3
V3_3
10K
5
6
7
I9
RPB51 8
18C4
18C4
CB124
L_TCK
L_TMS
5
5
V1_2
18B2
18D6
18D6
18C3
MEM_SCK
_motprocrescard_dn.
.1UF
1
CB134
1
.1UF
I13
CB135
J31
.1UF
6
CB137
7
10UF
B
8
10UF
18B5
18C6
18C6
18B5
PARENT BLOCK:
18B7
18C4
18C4
18D6
18D6
4
97_IO
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCIO0
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
139
117
106
89
64
42
31
9
85
VCCJ
TMS
TDO
TDI
TCK
I5
U08
18A5
6
39
90
142
35
36
34
33
32
\_rc_top_dn_\
V3_3
L_TMS
L_TDO
L_TDI
L_TCK
4
V1_2
3
(DOUT/CSON)
(BUSY/SISPI)
SPI_CS(DI/CSSPON)
PR24B
MISO
CCLK
3
RB18
DS33M33DK01A0
132
ENGINEER:
18B7
2
14D1
18B7
P.1,13-18
10K
STEVE SCULLY
MICROPORT.
TITLE:
XRES
86
MEM_CS
18B7
MEM_SI
88
87
18B5
13B5
MEM_SCK
RESET_IN
2
78
79
DONE
76
74
73
77
75
INITN
CFG2
CFG1
CFG0
PROGRAMN
SPICLK
CORE VCC
CONNECT XRES TO GND
WITH 1% 10K RES
PR25A
PR24A
1.2V
BANK_8
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE2_I10@\_RC_LIB\.\_MOTPROCRESCARD_DN\(SCH_1):PAGE6
CB125
C
:
CB130
16
22
29
48
54
83
94
102
128
135
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
11
21
30
47
51
61
81
95
105
120
133
138
D
CR-18
10UF
ALL LOW
FOR SPI
15D5
1A8^
10/03/2007
1
31/39(TOTAL)
PAGE: 3/5(BLOCK)
DATE:
1
A
B
C
D
A
B
C
D
IO
IO
IO
IO
IO
:
6C3^
19A8
RESET_B
MDIO
MDC
19A4
19A4
LAN_CLK
19A8
19A8
19A4
19C1
7
1
19
17
PT1_TX_CLK
13
3
15
11
2
9
5
0
3
1
PT1_TX_EN
RESET_B
7
23
IO
LAN_CLK
OSC25M
35
1
7
49
MDC
IO
47
MDIO
19B2
45
PT2_TX_CLK
19B6
43
41
3
PT2_TX_EN
39
2
37
33
0
31
29
27
GMII_CLKTOMAC_BUF 25
GMII_TX_ER_
GMII_CLKFROM_MAC 21
19A8
19B4
PHY_INT
8
19C4
PT2_TXD<3..0>
19B4
19C1
19C1
6B3^
6B3^
19B4
6B3^
19A4
19A4
19A4
19C4
19C4
19B4
19B4
6B1^
6B3^
19B4
6B1^
19B4
19D1
6C3^
6B1^
6B3^
PT1_TXD<3..0>
19D1
19D1
GND
V3_3
6C3^
19C4
I68
I67
8
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
SPARE
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
19C1
19B2
PT1_RX_ERR
19A7
19B2
19B2
PT2_RX_CRS
PT2_RXDV
PT2_RXD<3..0>
SPARE
19A8
19C2
PT1_COL_DET
PHY_INT
19C2
PT1_RX_CLK
V3_3
19C2
PT1_RXDV
V1_8
PT1_RXD<3..0>
6
PT1_RX_CRS
19A2
19A2
PT2_COL_DET
PT2_RX_ERR
19C1
19C1
19C1
19C1
19C2
6B3^
19B2
6C3^
6D3^
6D3^
6D3^
6D3^
19B1
19C1
19B2
19B2
19D1
19D1
19D1
19C2
19D1
19C1
6C3^
6D3^
5
6C3^
6C3^
6C3^
6C3^
19B8
19D1
19D1
19A8
19C1
19C1
PT1_TX_CLK
6B3^
19A8
19A8
19A8
6
_phy_imbus_mb_dn.
PARENT BLOCK:
5
GMII_CLKTOMAC_BUF
GMII_TX_ER_
GMII_CLKFROM_MAC
19B4
19B4
19B4
19
17
15
13
11
9
7
5
23
IO
LAN_CLK
OSC25M
MDC
MDIO
PT2_TX_CLK
PT2_TX_EN
4
19B8
19B8
19B8
6B1^
6B1^
6B1^
3
2
1
0
49
47
45
43
41
39
37
35
33
31
29
27
GMII_CLKTOMAC_BUF 25
GMII_TX_ER_
\_rc_top_dn_\
IO
IO
IO
3
2
1
0
3
1
GMII_CLKFROM_MAC 21
19A8
19B8
RESET_B
PT1_TX_EN
PT2_TXD<3..0>
19B8
6B3^
19C1
6B3^
19A4
19A4
19A4
19C8
19C8
19B8
19B8
19B8
6B3^
6B1^
6B1^
19C7
PT1_TXD<3..0>
19B8
19D1
6B1^
19C8
6B3^
4
CONNECTORS FOR LAN MOTHERBOARD TO RESOURCE CARD
19A2
PT2_RX_CLK
V2_5
3
2
1
0
3
2
1
0
BLOCK NAME:
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
JB03
SMT
SFM-125-L2-S-D-LC
NA
I78
@\_rc_lib\.\_rc_top_dn_\(sch_1):page5_i3@\_rc_lib\.\_phy_imbus_mb_dn\(sch_1):Page1
6C3^
V3_3
CR-45
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
V1_8
PT1_RXDV
PT2_RX_CLK
PT2_RXDV
PT2_RX_CRS
3
19A6
19A6
19A6
19B6
19B6
ENGINEER:
6B3^
19B6
6C3^
6D3^
6D3^
6D3^
STEVE SCULLY
2
P.5-6,19,25-26
DS33M33DK01A0
ETHERNET.
19C1
19C1
19C1
19C1
19C6
6D3^
19B1
19C1
19B6
19B6
19D1
19D1
19D1
19C6
19D1
19C1
2
6C3^
6D3^
PT2_RXD<3..0>
PT2_RXDV
PT2_RX_CRS
PT2_RX_ERR
PT2_COL_DET
PT2_RX_CLK
PT2_TX_CLK
PT2_TX_EN
PT2_TXD<3..0>
PT1_RXD<3..0>
PT1_RXDV
PT1_RX_CRS
PT1_RX_ERR
PT1_COL_DET
PT1_RX_CLK
PT1_TX_CLK
PT1_TX_EN
PT1_TXD<3..0>
1
10/03/2007
BLOCK
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
1
19/26(TOTAL)
PAGE: 1/1(BLOCK)
DATE:
PHY CONNECTOR HIERARCHY
PT2_RX_ERR
PT2_COL_DET
TITLE:
19A7
19A8
19B6
19C6
19C6
19C1
PT2_RXD<3..0>
SPARE
PHY_INT
PT1_RX_ERR
PT1_COL_DET
PT1_RX_CLK
V3_3
19C6
PT1_RXD<3..0>
PT1_RX_CRS
V2_5
3
2
1
0
3
2
1
0
BEGIN/END
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
JB02
SMTTP
NA_NOTPOPULATED
NA
I130
3
A
B
C
D
A
B
C
47D8
20A1
20A4
20B6
20B6
4
1
4
1
4
L02
1UH
RST
OUT
8
GND
1
OUT
VCC
34.368MHZ_5.0V
YB04
OSC
GND
1
VCC
44.736MHZ_3.3V
OSC
V3_3
LUI_HW
LIU_ALT_MCLK
LIU_E3MCLK
LIU_T3MCLK
YB03
20B6
20A3
20C6
47A6 OUT
10B2^
INT
3
5
8
5
8
330
4
3
2
1
RED
1
4
30
7
5
6
7
2
3
RP09 8
46B6
5
6
2
1
IN
10K
7
RPB40 8
5
6
7
10B2^
E3OSC
T3OSC
47A6
DS19
OSCSEL
6
21B2
20A4
LIU_TEST
20B3
21B5
21B7
JP18
M8
J9
J5
H9
H1
E12
E9
D8
D9
A5
2
_ds3154_liublock_dn.
LIU_ALT_MCLK
OSCSEL
5
PARENT BLOCK:
ALTERNATE_MCLK:
FOR 19.44MHZ
FOR 77.76MHZ
IO
20B6
20A6
21B4
4
21B5
21B7
NC4
NC3
NC2
NC1
HIZ
JTDO
JTDI
JTCLK
JTMS
JTRST*
\_rc_top_dn_\
9B3^
20C8
21B2
OR
DS3154
CONTROL
DS3254
ALTERNATE_MCLK
STMCLK
RCINV
TEST*
TCINV
RST*
E3MCLK
HW
TBIN
RBIN
T3MCLK
REG CACR[AMCSEL1:0]=00
REG CACR[AMCSEL1:0]=10
21B4
LIU_ALT_MCLK
RST
LIU_E3MCLK
LUI_HW
LIU_T3MCLK
20C7
20A4
20C8
21A6
20A1
20C8
20A3
BLOCK NAME:
JP15
2
20A3
20A1
9B2^
20C8
20C8
U07
V3_3
D7
2
VDD1
VSS1
21C4
VDD2
VSS2
E7
RPB38 8
E8
1
VDD3
VSS3
MOT
F7
ALE
VSS4
21D3
4
VSS5
F8
D6
F9
E5
VSS6
E6
G5
5
F4
VDD4
VSS7
D
6
F5
VDD5
VSS8
G4
V3_3
.1UF
C10
F6
VDD6
G6
7
4.7UF
C09
G7
VDD7
VSS9
8
.1UF
C07
G8
VDD8
H5
H7
VDD10
VSS10
@\_rc_lib\.\_rc_top_dn_\(sch_1):page13_i204@\_rc_lib\.\_ds3154_liublock_dn\(sch_1):Page1
3
1
4.7UF
C14
G9
VDD9
H6
H8
VDD11
VSS11
J7
VDD12
VSS12
J6
:
JP17
L10
K2
C11
B3
20B6
JTDO
J4
20B2
20B2
20A2
2
3
4
3
2
1
T3OSC
10K
3
RST
TCK
TMS
TDI
TDO
LIU
9B3^
20C8
I/F.
20B4
JP19
2
E3OSC
9B3^
20C8
10/03/2007
IO
20B6
20A7
1
1
1/3(BLOCK)
20/26(TOTAL)
PAGE:
DATE:
E3_MCLK_IO
LIU_E3MCLK
BLOCK
2
20C4
JTMS
JTCLK
20C3
20B3
JTDI
JTRST
20B3
JTDO
P.2,9,20-22
STEVE SCULLY
LIU
10
8
6
4
2
2
HIERARCHY
CONN_10P
GND
VCC
5
3
1
J32
DS33M33DK01A0
IO
20C6
20A7
9
7
5
3
1
V3_3
V3_3
ENGINEER:
T3E3
TITLE:
BEGIN
T3_MCLK_IO
5
6
7
RPB55 8
LIU_T3MCLK
LIU_TEST
JTDI
H4
J8
JTCLK
JTMS
20B2
D5
20B2
E4
JTRST
D4
3
1
CR-46
3
1
3
1
A
B
C
D
A
B
C
D
C5
21A6
21A8
9C2^
9C3^
DATA3
DATA4
DATA5
DATA6
DATA7
10C2^ 47C3
10C2^ 47D2
10C2^ 47C2
10C2^ 47D6
DATA2
DATA1
DATA0
21D8
21D8
21C8
22C5
22C5
21A8
9C3^
22D8
8
A2
1
TPOS
TNEG
TDSB
TLBO
TCLK
TTS*
TJA
TDSA
TDM*
RPOS
RNEG
RMON
RLB
RCLK
RTS*
RJA
STS
LLB
TXP
TXN
RXP
RXN
E3M
PRBS
IN
IN
10C2^ 47C6
IN
IN
IN
IN
21C8
21C8
21D7
OR
RLOS*
DS3154
PORT
ADDR3
ADDR2
ADDR1
21C2
21D3
21C3
21D7
21C7
21A8
TXN1
G1
20A4
7
9C3^
9C3^
9C3^
9C3^
9C3^
21B7
21C6
21B2
OUT
IN
IN
IN
47C8
47C3
47C4
46D8
46B6
6
TDSB
TLBO
TCLK
TTS*
TJA
TDSA
TDM*
RMON
RLB
47B7
RCLK
RTS*
RJA
STS
LLB
2
10B2^
10B2^
30
4
3
LIU_RCLK2
LIU_TCLK2
20A4
LIU_RNEG2
21B5
5
21B7
9C2^
CS
E11
B7
D11
21C1
21D4
21D4
21C4
22C3
1
21B2
21D1
21D1
TPOS
TNEG
TDSB
TLBO
TCLK
TTS*
TJA
TDSA
TDM*
RPOS
RNEG
RMON
RLB
RCLK
RTS*
RJA
STS
LLB
TXN
RXN
3
5
LIU_TCLK4
\_rc_top_dn_\
4
TXN3
A6
JB07
5
3
6
4
6
4
2
20A4
21A8
21B5
21B2
21B2
21B2
1
TTS*
TJA
TDSA
TDM*
RTS*
RJA
STS
LLB
30
2
5
6
7
ENGINEER:
I/F.
20A4
21B2
21A4
20A6
2
21A8
21C1
21B5
21B2
22B3
22B3
21B7
9C2^
1
1
21/26(TOTAL)
PAGE: 2/3(BLOCK)
10/03/2007
DS33M33
DATE:
21B2
9C2^
9C3^
21A4
21A8
21A8
22A7
21B4
21A3
21A3
P.2,9,20-22
21A3
LIU_RCLK4
LIU_TCLK4
OSCSEL
LIU_RNEG4
LIU_RPOS4
STEVE SCULLY
LIU
TXN4
M7
21A3
TXP4
M6
TDM4
L7
K4
ADDR3
22C8
DATA7
TTS4
J3
L5
M5 LIU_TCLK4
K5
ADDR2
21A4
K7
21A4
L4 LIU_TNEG4
22B8
M4 LIU_TPOS4
M2 PRBS4
LIU_RCLK4
TXN
RXN
RPB44 8
TXP
RXP
E3M
TCLK
TDSB
RMON
TLBO
TNEG
RNEG
RLB
TPOS
RPOS
47B4
RCLK
PRBS
OR
RLOS*
DS3154
PORT
DS33M33DK01A0
JPB01
JMP_3
RNEG4 4
RCLK4 2
RPOS4 3
RXN4 L1
RXP4 K1
ADDR0K6
DATA5 H2
ADDR1L6
J2
RTS4 L2
RCLK4M3
DATA6 H3
J1
RNEG4K3
RPOS4L3
2
PORT 4 OF DS3254 IS NOT USED WITH
IT IS A SPARE PORT IN THIS DESIGN
DS3253 IS RECOMMENDED FOR DS33M33
U07DS3254
RLOS4M1
T3E3
TITLE:
3
LIU_RNEG4
LIU_RPOS4
21B7
OUT
21B2
21D3
OUT
21C3
22A3
22A3
21A8
9C2^
21A8
9C3^
9C2^
21A8
22C8
IN
LIU_RCLK4
21B3
IN
22B7
21D3
OUT
22D3
22D3
3
IN
9C3^
47B4
22C8
22A7
21C3
20A6
TXP3
A7
CONN_6P_U
2
20D8
RD_DS
TTS3
C9 TDM3
B6
D10
B8
LIU_RCLK3
1
MOT
A8LIU_TCLK3
C8
C6
LIU_TCLK3
LIU_TNEG4
2
OSCSEL
1
30
22B8
A9LIU_TPOS3
B9LIU_TNEG3
A11PRBS3
LIU_RCLK3
LIU_RPOS3
6
LIU_RNEG3
5
7
RPB31 8
TXP
RXP
E3M
PRBS
OR
RLOS*
DS3154
PORT
LIU_TPOS4
JP23
JMP_3
RNEG3 4
RCLK3 2
RPOS3 3
RXN3B12
ALE C7
RXP3 C12
22C3
20D8
21A6
22C8
RTS3 B11
RCLK3A10
PARENT BLOCK:
21B4
47B5
22B5
22B5
22A7
22C8
21B2
OUT
OUT
21C5
20A6
TXN2
F12
OUT
TXP2
TDM2
TTS2
G12
J10
F11
K9
H11
H12LIU_TCLK2
E10
H10
47B5
21B4
RNEG3
C10
D12
IN
IN
IN
RLOS3A12
RPOS3
B10
21B4
22B7
4
U07 DS3254
F10
LIU_RPOS2
OSCSEL
22C8
J11LIU_TNEG2
LIU_RCLK2
TXN
RXN
2
TXP
RXP
5
J12LIU_TPOS2
L12PRBS2
_ds3154_liublock_dn.
10C2^
10C2^
10C2^
47D8
46C7
JP24
BLOCK NAME:
WR_RW
RD_DS
OUT
IN
RNEG2 5
21D6
JMP_3
TNEG
RNEG
1
TPOS
RPOS
E3M
PRBS
OR
RLOS*
8 RPB37
21D6
M11
M10
G10
L8
G11
RCLK2 7
RPOS2 6
21C6
RXN2
RXP2
ADDR5
L11
RTS2
L9
K12
K8
ADDR4
RCLK2
21B5
22A5
22A5
RST
INT
CS
9C3^
21A8
21B4
47B7
22D5
OUT
20A6
9C2^
21A8
22D5
OUT
TXP1
TDM1
IN
21A8
9C2^
K10
M9
K11
RNEG2
M12
DS3154
PORT
U07 DS3254
6
RPOS2
RLOS2
9C3^
IN
IN
22B7
22C8 22D8
DATA3
TTS1
F1
D3
G2
C4
E2
LIU_RCLK1
ADDR4
ADDR5
9C3^
9C3^
DATA0
E3
E1LIU_TCLK1
DATA4
G3
D2LIU_TNEG1
LIU_TCLK1
OSCSEL
ADDR0
2
9C3^
30
22C8
D1LIU_TPOS1
B1PRBS1
7
LIU_RCLK1
6 LIU_RPOS1
5 LIU_RNEG1
7
RPB35 8
IO
IO
IO
IO
IO
IO
IO
IO
JP16
JMP_3
RNEG1 4
RCLK1 2
RPOS1 3
RXN1
DATA2 F3
RXP1 A3
DATA1 F2
WR_RWB5
B4
RCLK1 C1
RTS1 B2
INT
C3
RNEG1
20D8
21B8
21A6
C2
RPOS1
A4
A1
RLOS1
10C2^ 47C3
9B2^
21B8
21B8
22B7
A1
M12
A12
U07 DS3254
PORT LOCATIONS
RLOS1 IS AT PIN
RLOS2 IS AT PIN
RLOS3 IS AT PIN
3
1
8
@\_rc_lib\.\_rc_top_dn_\(sch_1):page13_i204@\_rc_lib\.\_ds3154_liublock_dn\(sch_1):Page2
3
1
:
3
1
CR-47
3
1
A
B
C
D
A
B
C
D
4
1
2
3
4
RTS4
TTS1
TTS2
TTS3
TTS4
21C5
21C3
21C7
21D2
21D3
21D5
21D7
21C2
21C3
10K
4
PRBS4
330
5
5
6
7
2
3
4
21D6
21D4
21D3
21C2
4
3
7
21C52
5
10K 21C3
6
RPB45 8
5
6
1
2
3
4
TDM1
TDM2
TDM3
TDM4
RLOS4 4
3
RLOS3
10K
2
RLOS2
7
1
21C71
V3_3
1
21D8
5
6
RPB41 8 RLOS1
V3_3
3
8
7
6
RPB43 8
10K
RPB47 8
V3_3
7
5 1
6
1
1
7
330
5 1
6
7
1
1
RPB46 8 1
330
7
RPB42 8 1
RPB39 8
ACCESS POINTS FOR
2
7UNUSED PRBS SIGNALS
1
PRBS3
PRBS2
PRBS1
3
21C5
2
RTS2
RTS3
21C6
1
RTS1
21C8
8
2
2
2
RED
2
RED
2
2
2
2
6
BLOCK NAME:
DS26
DS24
DS21
DS23
DS27
DS25
DS20
DS22
6
_rc_top_dn_.
21C6
TXP2
TXN2
RXP2
RXN2
21C6
21C5
21C5
21C8
RXP1
RXN1
21C8
21C7
TXP1
TXN1
21C7
PARENT BLOCK:
5
5
RB23
332
RB17
332
RB25
332
\_rc_top_dn_\
RB22
332
9
4
2
1:2
T01
1
1:2
T01
6
1:2
T01
5
4
1:2
T01
3
2
1
12
11
10
4
29
30
31
32
21
22
23
24
1
1
1
2
1
2
2
3
I/F.
8
7
1:2
T01
4
1:2
T01
3
1:2
T01
8
1:2
T01
2
25
26
27
28
17
18
19
20
BLOCK
6
5
16
15
14
13
7
P.2,9,20-22
STEVE SCULLY
LIU
DS33M30M31M33EE01A0
ENGINEER:
T3E3
2
HIERARCHY
RXP4
21C3
RXN4
21C3
END LIU
TITLE:
3
TXP4
TXN4
RXP3
21C2
21C2
21C4
RXN3
TXP3
21C4
21C3
TXN3
21C3
RB21
332
RB19
332
RB24
332
RB20
332
1
1
1
2
2
2
@\_rc_lib\.\_rc_top_dn_\(sch_1):page13_i204@\_rc_lib\.\_ds3154_liublock_dn\(sch_1):Page3
S
J28
G
:
S
J29
G
CR-48
1
S
S
J26
G
S
J27
G
2
S
JB06
G
2
S
J22
G
1
04/15/2007
1
8/34(TOTAL)
PAGE: 8/11(BLOCK)
DATE:
JB05
G
S
J25
G
A
B
C
D
A
B
C
V3_3
11B5^
G
R
8
GND
V3_3
3 3
2 2
2 2
DS10
R
3 3
RED_GREEN
1 1
44
G
2 2
DS12
R
3 3
RED_GREEN
1 1
44
G
DS11
R
2 2
3 3
RED_GREEN
1 1
44
G
DS13
330
RP01
7 33
8 32
31
PL18B/VREF2_6
7
PL18A/VREF1_6
PL16B
PL16A
PL15B
PL15A/LDQS15
PL14A
27
30
PL13B
26
PL14B
PL13A
25
29
PL12B/LLM0_PLLC_FB_A
PL12A/LLM0_PLLT_FB_A
22
1
23
PL11B/LLM0_PLLC_IN_A
21
2
0
PL11A/LLM0_PLLT_IN_A
20
PLL
INPUT
3
5 35
PL9B/PCLKC7_0
9
4
PL9A/PCLKT7_0
8
6 34
PL8B
7
3
PL8A
6
2
PL7B
5
1
PL7A
ADDR<3..0>
RED_GREEN
1 1
44
IN
IN
141
PT10B
142
PT10A
PT12B
PT13A
BANK 5
PLL
INPUT
PT14A/TDQS14
PT14B
PT15A
PT15B
PT16A/VREF2_0
I/O
PORT
U01
overheadcpld_dn_.
PT16B/VREF1_0
97_IO
LFEC_T144_U
6
BLOCK NAME:
PB10A
39
11B5^
PB10B
40
PT12A
BANK 7
PT13B
BANK 0
PB11A
41
BANK 6
PLL
INPUT
PL2B/VREF1_7
42
3
PB11B
4
PB13B
43
WR
PB14A/BDQS14
45
RD
46
PB15A
IN
PB14B
47
11B5^
PT17A/PCLKT0_0
PT17B/PCLKC0_0
140
139
124
PT18A
CP_DUT_CLADCLK
23A3
23A3
23A3
10B7^
10B7^
10B7^
10B7^
M33_GPIOA1
M33_GPIOB1
M33_GPIOA2
M33_GPIOB2
M33_GPIOA3
M33_GPIOB3
J02
1
3
5
120
PT20A
9
2
16
15
14
14
13
12
12
11
10
9
8
7
6
5
4
3
2
1
4
6
8
10
16
4
74
78
\_rc_top_dn_\
PR18A/VREF1_3
75
PR16B
79
PR14B/RLM0_PLLC_FB_A
PR16A
81
PR14A/RLM0_PLLT_FB_A
76
82
PR13B/RLM0_PLLC_IN_A
77 0.0
83
PR13A/RLM0_PLLT_IN_A
PR15B
85
PR12B/DI/CSSPI*
88
PR11A/D7/SPID0
PR15A/RDQS15
87
86
PR12A/DOUT/CSO*
100
102
PR8B
PR9B/PCLKC2_0
103
PR8A
101
104
PR7B
PR9A/PCLKT2_0
105
106
PR2B/VREF1_2
PR7A
107
PR11B/BUSY/SISPI
PLL
INPUT
115
CONN_16P
114
113
112
111
4
PR2A/VREF2_2
PARENT BLOCK:
5
PLL
INPUT
118 13
116 15
5
BANK 4
122
PT19A/VREF1_1
7
119 11
PT20B
PT21A
PT21B
PT22A/TDQS22
23A3
CP_DUT_CLKA
CP_DUT_CLKB
CP_DUT_CLKC
138
137
135
134
133
132
131
130
129
127
123
PT18B
121
PT19B/VREF2_1
BANK 1
CPLD_OHCLK
IN
11C7^
PB19B/CS*
59
PB21A/D2/SPID5
PB21B/D1/SPID6
PB22A/BDQS22
PB22B/D3/SPID4
PL2A/VREF2_7
11C7^
PB15B
PB20A/VREF2_4
60
2
CPLD_OH1
IN
48
PB16A/VREF2_5
PB17A/PCLKT5_0
51
61
CPLD_RDOHVLD
CPLD_CS
CPLD_TAOH
11C5^
49
PB16B/VREF1_5
53
PB20B/D0/SPID7
IN
CPLD_TAOHEN
11C5^
50
PB17B/PCLKC5_0
62
CPLD_ATOH
64
11B5^
11B7^
PB18A/WRITE*
56
CPLD_ATOHEN
11C5^
D
CPLD_TAOHSOF
IN
CPLD_TAOHVLD
PB18B/CS1*
65
CPLD_ATOHSOF
IN
11C5^
PT22B
6
11B7^
57
66
CPLD_ATOHCLK
IN
PB23A
PT23A
PT25A
7
IN
58
CPLD_RDOHSOF
CPLD_RDOH
PB19A/VREF1_4
67
BANK 2
PT25B
8
IN
11C7^
11C5^
68
CPLD_DTOHSOF
CPLD_DTOH
IN
11C7^
BANK 3
PB23B/D4/SPID3
PB24B/D5/SPID2
PB25B/D6/SPID1
@\_rc_lib\.\_rc_top_dn_\(sch_1):page12_i24@\_rc_lib\.\overheadcpld_dn_\(sch_1):Page1
11C7^
11C5^
69
CPLD_DTOHCLK
IN
11C7^
70
:
IN
OUT
11C7^
CR-49
IN
11B7^
OUT
OUT
IN
PLL
INPUT
OUT
RB04
MEM_CS
MEM_SCK
3
3
ENGINEER:
2
BLOCK
1
0
2
3
4
5
6
7
1
10/03/2007
IO
23/26(TOTAL)
DATE:
DAT<7..0>
1
PAGE: 1/2(BLOCK)
SIGNALS FORSIGNALS FOR
HIERARCHY INTERFACE
P.2,10,23-24
STEVE SCULLY
DS33M33DK01A0
FOR TQFP144
2
CPLD HIERARCHY
OVERHEAD.
TITLE:
BEGIN
MEM_SCK MUST BE AT PIN77
CP_DUT_CLADCLK
24B8
CP_DUT_CLKA
IN
24C8
49D7
11B7^
CP_DUT_CLKB
IN
24C8
49D7
11B7^
IN
MEM_SI
49D7
11B7^
CP_DUT_CLKC
IN
IO
IO
IO
IO
IO
MEM_SO
49D7
11B7^
M33_GPIOA1
M33_GPIOB1
M33_GPIOA2
M33_GPIOB2
M33_GPIOA3
M33_GPIOB3
IO
10B5^
A
B
C
D
A
B
8
8
23B3
2
3
1
V3_3
UB02
I27
2.7V
10
8
6
4
7
GND
SHDN*
IN
I29
RST*
IC
4
5
4
7
3
8
L_TDO
L_TDI
V3_3
V3_3
24C4
24C4
24C4
24C4
6
BLOCK NAME:
OUT
UB01
MAX1963
6
GND
HOLD*
WP*
VCC
AT25160A_U
CS*
MEM_CS
1
SCK
MEM_SCK 6
SO
SI
24B1
2
5
MEM_SO
23B4
VCC
TDO
TDI
TCK
CONN_10P
GND
7
5
23C4
23C4
MEM_SI
9
7
5
3
.1UF
3
RB01
10K
RB02
10K
L_TCK
V1_2
CB01
10UF
10UF
CB08
CB09
.1UF
overheadcpld_dn_.
24C1
PARENT BLOCK:
5
11B5^
L_TMS
L_TDO
L_TDI
4
CPU_RESET
\_rc_top_dn_\
IN
24D6
24D6
24D6
24D6
L_TCK
CFG1
CFG0
90
91
LOW FOR
MODE
ALL
SPI3
PROGRAM*
CFG2
89
93
TMS
TDO
TDI
TCK
17
18
16
14
CONTROL
2
PLACE
3
ENGINEER:
BLOCK
DONE
INIT*
2
P.2,10,23-24
STEVE SCULLY
OVERHEAD.
DS33M33DK01A0
END CPLD HIERARCHY
TITLE:
126
VCCAUX2
97
95
94
54
VCCAUX1
CCLK
19
VCCJ
10
99
VCC2
VCC3
XRES
92
RESISTOR
13
VCC1
V3_3
CLOSE TO PIN
NEEDS 10K,1%
U01
LFEC_T144_U
I12
97_IO
GND3A/GND4
72
L_TMS
GND3B
80
2
GND4
63
TMS
GND5
52
1
73
VCCIO3A
3
84
VCCIO3B
GND6A
28
4
GND0
55
VCCIO4A
GND6B/GND5
37
1
CB11
136
VCCIO0A
128
71
VCCIO4B
GND7/GND0
I18
5
GND8
15
JB01
6
.1UF
143
VCCIO0B
GND1
38
VCCIO5A
GND9
96
7
CB10
110
VCCIO1A
117
44
VCCIO5B
GND10
98
@\_rc_lib\.\_rc_top_dn_\(sch_1):page12_i24@\_rc_lib\.\overheadcpld_dn_\(sch_1):Page2
CB02
125
VCCIO1B
GND2/GND1
24
VCCIO6A
NC1
11
C
:
10UF
108
VCCIO2
109
36
VCCIO6B
144
1
VCCIO7
NC2
12
24A5
1
10/03/2007
RB05
1
2/2(BLOCK)
24/26(TOTAL)
PAGE:
DATE:
TPB01
I7
TPB02
I3
MEM_SCK
RB03 10K
V3_3
V1_2
1
1
D
CR-50
10K
A
B
C
D
A
B
C
V3_3
8
8
GND
V3_3
6D4^
6C4^
25B1
25B7
TXD<4>
TXD<5>
TXD<6>
68
67
66
3
4
5
6
2
8 RP06
7
6
4
5
6
25C1
7
TX_ER_
25A2
4
3
2
1
44
45
46
47
41
4
3
RXDV_BUF
30
50
51
52
RX_ERR_BUF
5
1
5
3
7
4
6
2
3
2
7
1
30
56
1
8 RP07
55
57
RX_CLK_BUF
25B2
0
61
TX_ER_
25C1
79
62
5
6
BLOCK NAME:
1K
7
RPB30 8
RX_DV/RCK
RX_ER/RXDV_ER
RXD<7>
RXD<6>
RXD<5>
RXD<4>
RXD<3>/RX3
RXD<2>/RX2
RXD<1>/RX1
RXD<0>/RX0
RX_CLK
TX_ER
GTX_CLK/TCK
TX_EN/TXEN_ER
6
TXD<3>/TX3
71
2
TXD<7>
TXD<2>/TX2
72
65
TXD<1>/TX1
75
1
7
TXD<0>/TX0
25A2
25A7
RXD<7..0>
25D1
6C4^
25C1
TX_EN
6C4^
TX_CLK/RGMII_SEL0
76
COL
0
39
TX_CLK_BUF
CRS/RGMII_SEL1
TCK
TMS
TDO
TDI
TRST*
60
COL_DET_BUF
GMII_CLKFROM_MAC
25C1
6C4^
6C4^
3 27
4 24
40
5
6
30
2 28
7
32
1 31
8 RP02
RX_CRS_BUF
TXD<7..0>
25B2
25B2
25A2
2.0K
RB11
V1_8
V2_5
INPUT
TXERR
TXEN
TXD[0:7]
GTXCLK
MDC
CLKIN
OUTPUT
COL
CRS
RXER
RXDV
RXD[0:7]
RXCLK
TXCLK
CLKTOMAC
CLKOUT
5
2
25B2
85
LINK1000LED_ANEN
A0_DUPLEX
RPB20 8
1
2
3
4
MULTI_EN_STRAP__TX_TRIGGER
MDIX_EN_STRAP
MAC_CLK_EN_STRAP__TX_SYN_CLK
13
14
17
18
95
94
89
88
LINK1000_LED/AN_EN_STRAP
PHYADDR<2>_STRAP
PHYADDR<3>_STRAP
PHYADDR<4>_STRAP
4
A0_DUPLEX
\_rc_top_dn_\
25A3
330
RB07
1
2.0K
RB06
DS18
MAC_CLK_EN_STRAP/TX_SYN_CLK
MDIX_EN_STRAP
MULTI_EN_STRAP/TX_TRIGGER
PHYADDR<1>_STRAP
DUPLEX_LED/PHYADDR<0>_STRAP
LINK100LED_DUPLEX
10
1K
V3_3
5
6
7
3
26C4
26C4
25B3
25B3
25C7
25D1
6B4^
V2_5
6B4^
26C6
25D2
26C6
6B4^
25A7
25A7
25C7
STEVE SCULLY
2
7
30
BLOCK
RXDV_BUF 5
RX_ERR_BUF
6
30
8 RP05
5
6
RX_CRS_BUF
7
COL_DET_BUF
CLKOUT_BUF
30
8 RP12
5
6
7
8 RPB25
RXD<7..0>
RXDV
RX_CRS
RX_ERR
COL_DET
RX_CLK
TX_CLK
TX_EN
IN
MDC
PHY_INT
RESET_B
MDIO
4
3
2
1
4
3
2
1
4
3
2
1
25C1
6C4^
25C1
6C4^
25C1
6D4^
6D4^
6D4^
6D4^
6C4^
6D4^
6D4^
6C4^
6C4^
6C4^
6C4^
25B7
6C4^
6B4^
6D4^
6C4^
6D4^
6D4^
10/03/2007
25C1
25C1
25C1
25C1
1
25/26(TOTAL)
PAGE: 1/2(BLOCK)
DATE:
RXDV
RX_ERR
RX_CRS
COL_DET
CLKOUT
TPB03
CLKTOMAC_TESTPNT
CLKTOMAC
TX_CLK
25A8
25A1
25A1
25A1
25B1
25B1
25B1
25B7
25B7
25B1
25B1
25A7
6C4^
25B7
25B3
RX_CLK
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
SPARE<4..1>
CLKTOMAC
TXD<7..0>
1
LAN_CLK
CLKTOMAC_TESTPNT
TX_ER_
CLKTOMAC_BUF
25C7
IO
IO
IO
IO
IO
IO
PHYOSC25M
GMII_CLKFROM_MAC
25C3
25D6
25C3
TX_CLK_BUF
P.5-6,19,25-26
DS33M33DK01A0
ENGINEER:
26C6
25C3
6B4^
RX_CLK_BUF
26C6
6B4^
6B4^
6B4^
2
PHY HIERARCHY
ETHERNET.
TITLE:
BEGIN
26C4
25A4
26B6
26B6
26B6
9
LINK10LED_SPEED1
LINK100_LED/DUPLEX_STRAP
26B6
26C4
8
ACTIVITYLED_SPEED0
MAN_MDIX_STRAP__TX_TCLK
26D4
LINK10_LED/SPEED1_STRAP
6
NON_IEEE_STRAP
0603_2PCT_50
ACTIVITY_LED/SPEED0_STRAP
MAN_MDIX_STRAP/TX_TCLK
1
CLKTOMAC_BUF
87
CLK_OUT
CLK_TO_MAC
25B2
CLKOUT_BUF
86
CLK_IN
5
MDID_N
MDID_N4
26B3
127
MDID_P
7
6
MDID_P 3
26B3
126
MDIC_N2
26B3
121
MDIC_N
RPB248
MDIC_P 1
26C3
120
MDIC_P
5
MDIB_N
6
MDIB_N 4
26C3
115
MDIB_P 3
26C3
114
MDIB_P
7
MDIA_N
MDIA_N 2
26C3
109
MDIA_P
PHYOSC25M
6B4^
0603_2PCT_50
RPB268
26C3
MDIA_P 1
PHY_INT
26C6
6B4^
108
3
25D2
MDIO
80
MDC
MDIO
INTERRUPT*
25D2
MDC
3
81
NON_IEEE_STRAP
4
MAINTAIN 50OHM
STIPLINE
TO V2_5PHY
7
V1_8
PARENT BLOCK:
PIN61
PIN62
[PIN76:PIN65]
PIN79
PIN81
PIN86
PIN39
PIN40
PIN41
PIN44
[PIN56:PIN45]
PIN57
PIN60
PIN85
PIN87
DP83865_U
U04
34
VDD_SEL_STRAP
_phy_dp83865bvh_dn.
PLACE 9.76K
RES
CLOSE TO BG_REF
V3_3
90
IO_VDD<1..12>
RESET_B
33
RESET*
5
92
CORE_VDD<1..8>
6
96
RB16
9.76K
102 BG_REF
BG_REF
123
1V8_AVDD1_<1..5>
7
98
1V8_AVDD2
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE5_I23@\_RC_LIB\.\_PHY_DP83865BVH_DN\(SCH_1):PAGE1
100
1V8_AVDD3
D
:
PLACE MDI RESISTORS
CLOSE TO PHY
2V5_AVDD<1..2>
VSS<1..35>
128
CR-25
GREEN
A
B
C
D
A
2
2
DS17
GREEN_GREEN
2 2
1 1
44
GREEN_GREEN
2 2
3 3
RPB19 5
2.2K
4
LACTOB
V3_3
L10OB
1 1
44
3 3
DS16
GREEN_GREEN
2 2
3 3
DS15
RPB19 6
2.2K
3
V3_3
L100OB
1 1
44
2 2
3 3
GREEN_GREEN
RPB19 7
2.2K
2
1 1
44
CB20
4.7UF
CB100
4.7UF
CB18
4.7UF
CB78
4.7UF
CB84
4.7UF
CB46
4.7UF
4.7UF
CB70
4.7UF
8
CB15
4.7UF
C06
4.7UF
DS14
4
3
2
1
7
JP08
2
6B4^
6B4^
6B4^
2
JMP_3
JP06
25D2
25D2
25D6
25C3
PHY_INT
MDIO
25B3
25B3
25B3
5 ACTIVITYLED_SPEED0
6 LINK10LED_SPEED1
2
BLOCK NAME:
6
2
4
3
2
1
R01
2.2K
_phy_dp83865bvh_dn.
4
3
2
2.2K
5
25B3
V1_8
PARENT BLOCK:
5
6
7
V3_3
\_rc_top_dn_\
4
MAC_CLK_EN_STRAP__TX_SYN_CLK
5
25A3
MDIX_EN_STRAP
6
25B3
MULTI_EN_STRAP__TX_TRIGGER
MAN_MDIX_STRAP__TX_TCLK
NON_IEEE_STRAP
4
7
RPB28 8
2.0K
RESET_B1 RPB21 8
25B3
25C3
7 LINK100LED_DUPLEX
CB98
.1UF
CB65
.1UF
330
2
25D2
JMP_3
JP07
RPB22 8 LINK1000LED_ANEN
JP10
JMP_3
JP09
CB69
.1UF
CB97
.1UF
V3_3
CB07
4.7UF
C11
4.7UF
JMP_3
CB47
.1UF
CB94
.1UF
CHECK THAT 2.2K
RES USE THE SAME RPACK
STRAP OPTIONS HERE DO NOT FOLLOW DATASHEET
JP02
JMP_3
JP05
JMP_3
2
V3_3
L1000OB
2.2K
CB95
.1UF
CB77
.1UF
B
CB96
1
CB45
.1UF
C05
.1UF
C
JP04
JMP_3
3
1
3
1
3
2
CB68
.01UF
JP03
CB66
.01UF
1
3
1
CB19
4.7UF
CB165
4.7UF
3
1
3
1
D
CB43
.1UF
CB107
4.7UF
3
1
3
1
JMP_3
4.7UF
RPB19 8
CB73
JMP_3
4.7UF
V3_3
CB114
4.7UF
5
CB106
4.7UF
25A3
25A3
V2_5
0.01
3
ENGINEER:
BLOCK
STEVE SCULLY
2
P.5-6,19,25-26
DS33M33DK01A0
ETHERNET.
TITLE:
UF X4
J11
1
CAPS FOR DECOUPLE
OF MX.+-
.01UF
.01UF
CB92
CB101
1000PF,
750
2KV
X4
SH2
V2_5
10/03/2007
12
11
CB62
1
26/26(TOTAL)
PAGE: 2/2(BLOCK)
DATE:
J8
MX3-
J7
MX3+
J5
MX2-
J4
MX2+
J6
MX1-
J3
MX1+
J2
MX0-
J1
MX0+
.01UF
SH1
CMR CHOKES
.01UF
CB112
CONN_HFJ11_1G02E_U
GND
VCC
TD3-
TD3+
TD2-
TD2+
TD1-
TD1+
TD0-
TD0+
2
END PHY HIERARCHY
10
9
V2_5
8
MDID_N
5
MDIC_N
25B3
25B3
4
MDIC_P
25C3
7
6
MDIB_N
25C3
MDID_P
3
MDIB_P
25C3
25B3
2
1
MDIA_N
MDIA_P
25C3
25C3
3
CB79
6
CB54
.1UF
V3_3
7
CB113
.1UF
3
CB53
.1UF
CB88
.1UF
4.7UF
8
CB93
@\_RC_LIB\.\_RC_TOP_DN_\(SCH_1):PAGE5_I23@\_RC_LIB\.\_PHY_DP83865BVH_DN\(SCH_1):PAGE2
CB64
.01UF
1
CB168
.1UF
CB44
.1UF
:
CB147
CB67
.01UF
CR-26
4.7UF
A
B
C
D
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