Download Intel T1/E1 User's Manual

LXD386 — Evaluation Board for
Quad T1/E1 Applications
Developer Manual
January 2001
As of January 15, 2001, this document replaces the Level One document
LXD386 — Evaluation Board for Quad T1/E1 Applications User Guide.
Order Number: 249215-001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXD386 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
LXD386 — Evaluation Board for Quad T1/E1 Applications Developer Manual
Contents
1.0
General Description .................................................................................................. 5
1.1
2.0
Overview ........................................................................................................................ 7
2.1
2.2
2.3
2.4
3.0
LXD386 Packing List ............................................................................................. 7
Equipment Requirements...................................................................................... 7
Control Modes ....................................................................................................... 7
Factory Settings .................................................................................................... 8
Hardware Mode Set-Up and Operation.............................................................. 9
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
4.0
Features ................................................................................................................ 5
Power Connections ............................................................................................... 9
Hardware Mode Selection ..................................................................................... 9
Loopback Mode Selection ..................................................................................... 9
Clock Edge Selection ............................................................................................ 9
Output Enable Selection......................................................................................10
Code Selection ....................................................................................................10
Monitoring Address Selection..............................................................................10
Jitter Attenuator Selection ...................................................................................10
Line Buildout Selection........................................................................................11
Master Clock Setup .............................................................................................11
JTAG Boundary Scan Port ..................................................................................12
Framer/ASIC Connection ....................................................................................12
LED Indicators.....................................................................................................13
Line Interface.......................................................................................................13
Board Protection..................................................................................................13
Software Mode Set-Up and Operation .............................................................14
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
i8051 Microcontroller Board ................................................................................14
Evaluation Board Set-up .....................................................................................14
Test Equipment Connections ..............................................................................14
Power Connections .............................................................................................14
Evaluation Board Software..................................................................................15
Software Installation and Start-Up.......................................................................15
Hardware Set-up Screen.....................................................................................15
Quitting the Program ...........................................................................................15
Configuration Screen...........................................................................................16
4.9.1
Communications Modes .....................................................................16
4.9.2
Registers ............................................................................................16
4.9.3
Setting Individual Transceiver Operating Modes................................16
4.9.4
Apply to all Channels..........................................................................17
4.9.5
Exit .....................................................................................................17
Registers Screen.................................................................................................18
4.10.1
Setting Registers ................................................................................18
4.10.2
Status Indicators.................................................................................18
4.10.3
Control Buttons...................................................................................18
4.10.4
Interrupts ............................................................................................18
4.10.5
Reset ..................................................................................................18
LXD386 — Evaluation Board for Quad T1/E1 Applications Developer Manual
iii
5.0
Evaluation Board Schematics............................................................................. 20
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LXD386 Evaluation Board..................................................................................... 6
Default Switch Settings ...................................................................................... 11
Jumper Block JP5 ............................................................................................... 12
Jumper Block JP2 ............................................................................................... 12
Jumper Block JP 31 ............................................................................................ 13
Hardware Set-up Screen..................................................................................... 16
Configuration Screen .......................................................................................... 17
Registers Screen................................................................................................. 19
Evaluation Board Schematic — Data/Control ..................................................... 20
Evaluation Board Schematic — Line Interface Unit ............................................ 21
Evaluation Board Schematic — Monitoring......................................................... 22
Evaluation Board Schematic — LOS Detector.................................................... 23
Evaluation Board Schematic — Analog .............................................................. 24
Evaluation Board Schematic — Digital I/O.......................................................... 25
1
2
LOOP/DLOOP Switch Settings ............................................................................. 9
JP5 Jumper Settings ........................................................................................... 11
Tables
iv
LXD386 — Evaluation Board for Quad T1/E1 Applications Developer Manual
Evaluation Board for Quad T1/E1 Applications — LXD386
1.0
General Description
The LXD386 evaluation board is a versatile tool for engineers designing T1/E1 short haul
applications using the LXT386.
The evaluation board operates in one of two modes: Software (Host) mode or Hardware mode. In
Software mode, the device is controlled with the PC based configuration and monitoring software
through an i8051 microcontroller interface. In Hardware mode, the device and channel controls are
set using shorting blocks and DIP switches located on the LXD386 evaluation board.
The evaluation board provides banana jacks for each channel’s line interface to allow connection of
a T1/E1 pattern generator/analyzer. A connector is also provided for each channel’s framer or backend ASIC interface.
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
Software and Hardware controllable
ZIF LQFP socket for easy swapping of LXT386
Banana jacks for power and line interfaces
10-pin connectors for framer/ASIC interface
8-pin connector for IEEE 1149.1 compliant JTAG boundary scan port
LED indicators for LOS alarm
On-board 2.048/1.544 MHz reference clock oscillator
Switches and shorting blocks for Hardware mode operation
Compatible with Intel external i8051 microcontroller board
PC-based software for ease of use
Socketed transformer and termination components for easy experimentation
Built-in overvoltage protection for line interface and power supply
Developer Manual
5
LXD386 — Evaluation Board for Quad T1/E1 Applications
Figure 1. LXD386 Evaluation Board
6
Developer Manual
Evaluation Board for Quad T1/E1 Applications — LXD386
2.0
Caution:
Overview
CMOS devices are static (ESD) sensitive. Take all industry standard precautions when handling the
evaluation board, LXT386 chip, and other sensitive electronic components.
Before proceeding with any evaluation board operations, review the specifications for the LXT386
transceiver.
2.1
LXD386 Packing List
The evaluation board kit contains the following components:
•
•
•
•
•
•
•
2.2
LXD386 evaluation board with the LXT386 installed.
2.048 MHz oscillator installed, additional 1.544 MHz oscillator supplied.
i8051 microcontroller interface board and PC serial port cable.
PC compatible diskettes containing software for using the evaluation board in Software mode.
Shorting block kit for selecting Hardware mode.
LXD386 user guide.
LXT386 data sheet.
Equipment Requirements
The evaluation board kit includes all the circuit components needed for a successful evaluation.
However, the following lab equipment is required:
•
•
•
•
•
2.3
Power Supply +3.3V DC (+5VDC for TVCC optional)
Telecom cable or cable simulator (optional).
T1/E1 pattern generator/analyzer.
1.544/2.048 MHz clock source (optional).
For Software mode: an IBM compatible PC with minimum 386 40 MHz processor, available
serial port, mouse, VGA monitor, DOS 5.0+, and Microsoft Windows 3.1 or later version,
Windows 9x is recommended.
Control Modes
The LXT386 has two basic operating modes: Hardware mode or Software (Host) mode. In
Hardware mode, operation of the LXT386 is established by hard-wiring the pins. In Software
mode, operation of the LXT386 is controlled by an external microprocessor that communicates
with the LXT386’s internal registers via either a serial or parallel interface.
The LXD386 evaluation board supports both hardware and software modes.
Developer Manual
7
LXD386 — Evaluation Board for Quad T1/E1 Applications
2.4
Factory Settings
When shipped from the factory, the LXD386 evaluation board’s switches and jumpers are set for
software mode and parallel microprocessor interface.
8
Developer Manual
Evaluation Board for Quad T1/E1 Applications — LXD386
3.0
Hardware Mode Set-Up and Operation
3.1
Power Connections
The evaluation board has two power planes (VCC and TVCC) each of which is tied to a separate
red colored banana jack.
1. Connect the +3.3 VDC power supply to the VCC jack.
2. Connect either a +3.3 VDC or +5.0 VDC power supply to the TVCC jack.
3. Connect the power supply ground lead(s) to the black (GND) banana jack.
Jumper JP1 is provided to allow LXT386 current consumption measurements and must be installed
for normal board operation. Jumper JP3 allows measurement of the current in the TVCC power
supply only. It must also be installed for normal operation.
3.2
Hardware Mode Selection
To enable the Hardware mode of operation:
1. Set the MODE switch in switch block S1 to the LOW position.
2. Insert the two shorting blocks, provided with the evaluation board kit, into 20-pin sockets JP4
and JP6.
3.3
Loopback Mode Selection
The LXT386 LOOP/DLOOP signals are set by switches in switch block S1. Depending on the
LOOPn/DLOOPn combination selected for a particular channel, a different operation or loopback
mode is selected. Please refer to Table 1.
Table 1.
LOOP/DLOOP Switch Settings
LOOPn
DLOOPn
Channel #n Operation
Open
x
Normal Mode
LOW
x
Remote Loopback
HIGH
LOW
Analog Local Loopback
HIGH
HIGH
Digital Local Loopback
1. “x” means “don’t care”
3.4
Clock Edge Selection
The phase relation between RCLK and RPOS/RNEG is set by the CLKE switch in switch block
S4. Please refer to the “CLKE” signal pin in the LXT386 data sheet for details.
Developer Manual
9
LXD386 — Evaluation Board for Quad T1/E1 Applications
3.5
Output Enable Selection
The OE switch in switch block S4 controls the operation of the LXT386 output drivers. For normal
operation (driver outputs enabled), set the OE switch to the ON position. Setting the OE switch to
OFF forces the output drivers to the high impedance state.
3.6
Code Selection
In Hardware mode, the MO-INT-CO switch in switch block S4 selects the line encode/decode. To
select AMI encode/decode set to the ON position. To select B8ZS/HDB3 encode/decode set to the
OFF position.
3.7
Monitoring Address Selection
Switch block S3 sets the Protected Monitoring Addresses A0 through A3. The factory default
setting is 0000 (no monitoring). See the LXT386 data sheet for details.
3.8
Jitter Attenuator Selection
In Hardware mode, the JASEL switch in switch block S1 selects the position of the Jitter
Attenuator in the data path:
• Transmit path = LOW
• Receive path = HIGH
• JA disabled = center
10
Developer Manual
Evaluation Board for Quad T1/E1 Applications — LXD386
Figure 2. Default Switch Settings
S3
O
F
F
1
2
3
CLKE
OE
MO-INT-CO
4
MUX
S4
O
F
F
1
2
3
A0
A1
A2
4
A3
S2
O
F
F
1
2
3
S1
LOOP2
LOOP3
LOOP4
LOOP5
3
LOOP6
LOOP7
MODE
JASEL
7
2
1
NOTE:
OFF position = Low = ’0’
4
5
6
8
9
10
3.9
HIGH
LOOP0
LOOP1
4
LOW
LEN2
LEN1
LEN0
Line Buildout Selection
Switch block S2 is used to select the transmit pulse shaping for T1 mode operation, as well as T1/
E1 mode selection. The factory default is 000 (E1 mode). Refer to the LXT386 data sheet for T1
pulse shape details.
3.10
Master Clock Setup
The on-board 2.048 MHz oscillator can be used for MCLK source. An additional 1.544 MHz
oscillator is included for use in T1 operation mode. A BNC connector (J1) is provided to allow use
of an external MCLK source. J1 is internally terminated into 50Ω. Jumper block JP5 is used to
configure MCLK. Table 2 describes the options available with JP5. The factory setup for JP5 sets
internal oscillator timing as illustrated in Figure 3.
Table 2.
JP5 Jumper Settings
JP5 Setting
HIGH
Data recovery mode
EXT
External MCLK source at BNC (J1)
INT
Internal oscillator
LOW
Developer Manual
Operation
Receiver power-down
11
LXD386 — Evaluation Board for Quad T1/E1 Applications
Figure 3. Jumper Block JP5
3.11
JTAG Boundary Scan Port
The eight pin connector JP2 shown in Figure 4 provides access to the IEEE 1149.1 compliant
JTAG boundary scan port for board testing purposes.
Figure 4. Jumper Block JP2
3.12
Framer/ASIC Connection
Ten pin connectors provide access to the digital signals necessary for interfacing with the back-end
Framer/Mapper or ASIC. Figure 5 represents one of the four connectors with the factory jumper
connecting RCLK to TCLK.
12
Developer Manual
Evaluation Board for Quad T1/E1 Applications — LXD386
Figure 5. Jumper Block JP 31
3.13
LED Indicators
Loss of Signal (LOS) status for each channel is indicated by four LEDs, labeled D3 through D6. If
the board is being used in the Software mode, the state of these LEDs will also be displayed on the
registers display screen.
3.14
Line Interface
Access to the line interface is provided through the green and white banana jacks. The TIP signal
is routed to the white jacks for both transmit and receive directions. The RING signal is routed to
the green jacks for both directions.
An octal transformer is used for channels 1 to 3 (one transformer port is unused). Transformers in
channel 0 and line resistors /capacitors for channels 0 to 3 are socketed for easy swapping. Jumpers
JP7 to JP14 can be used to bypass the transmit series resistors for T1 applications with
TVCC=3.3V. See the LXT386 Data Sheet for details on transmit interface options.
3.15
Board Protection
The LXD386 evaluation board is equipped with both power supply and line surge protection. Two
Transient Voltage Suppressors (TVS) are included for power supply protection (5V/3.3V). For the
T1/E1 line interface, the transmitters are protected with Schottky diodes and the receivers are
protected by series 1KΩ input resistors. This protection is sufficient for G.703 Annex B
compliance.
Developer Manual
13
LXD386 — Evaluation Board for Quad T1/E1 Applications
4.0
Software Mode Set-Up and Operation
4.1
i8051 Microcontroller Board
An i8051 microcontroller interface board is provided with the evaluation board kit. Connect the
i8051 microcontroller board to the evaluation board at the 96 pin header labeled CON1. Connect
the microcontroller board to an available serial (COM) port on your PC using the cable provided in
the evaluation board kit.
Instead of the i8051, a user supplied microcontroller board may also be used to control the
LXT386. Evaluation board connector CON1 provides access to all the relevant LXT386
microprocessor interface signals.
4.2
Evaluation Board Set-up
The evaluation board contains switches and jumpers to select various operating parameters. All
other parameters are controlled through the evaluation board software. When using the i8051
microcontroller provided with the kit, set the evaluation board switches and jumpers as follows:
1. Select software mode by removing the shorting blocks from sockets JP4 and JP6.
2. Set the MODE switch (in switch block S1) to select serial or parallel mode:
— HIGH for parallel mode (factory default)
— Center position for serial mode
3. Set the JASEL switch (in switch block S1) to the center position.
4. Set MO-INT-CO switch (in switch block S3) to HIGH (Intel microprocessor).
5. Set MUX switch (in switch block S3) to HIGH (Multiplexed microprocessor address/data
bus).
6. Set CLKE switch (in switch block S3). Refer to “CLKE” signal pin in LXT386 data sheet for
details.
7. Set OE switch (in switch block S3) as described in “Output Enable Selection” on page 10.
8. Set the jumper on JP5 as described in “Master Clock Setup” on page 11.
4.3
Test Equipment Connections
The evaluation board contains connectors to interface an external pattern generator and other test
equipment. See page 9 for details.
4.4
Power Connections
Connect power supply as described in “Power Connections” on page 9.
14
Developer Manual
Evaluation Board for Quad T1/E1 Applications — LXD386
4.5
Evaluation Board Software
When operating the evaluation board in the software mode, the software provided with the kit will
be used to configure the LXT386 and to monitor its operation. This software provides a point-andclick, user friendly interface with on-line help screens. Refer to the data sheet for detailed
information about the LXT386 transceiver.
4.6
Software Installation and Start-Up
The minimum PC system requirements are:
•
•
•
•
•
•
IBM compatible PC
386/40 MHz CPU (Pentium class recommended)
Available serial port
Mouse
VGA monitor
DOS version 5.0 or higher and Microsoft Windows 3.1 (Windows 9x recommended)
Begin the installation procedure by running the Setup.exe file on the installation diskette #1.
Follow the on-screen prompts to complete the software installation.
4.7
Hardware Set-up Screen
Whenever the LXT386 software is run, the Hardware Set-up screen will appear first on the monitor
(see Figure 6). This screen is used to select the PC serial port to be used. Select an available serial
port and click the OK button.
4.8
Quitting the Program
The program can be terminated at any time by clicking the “Exit” control button, located at the
right side of the screen.
Developer Manual
15
LXD386 — Evaluation Board for Quad T1/E1 Applications
Figure 6. Hardware Set-up Screen
4.9
Configuration Screen
The configuration screen shown in Figure 7 is the next screen to appear on the monitor. It is the
primary control interface with the evaluation board. A graphical representation of each channel is
shown in a tabbed display box, along with the control buttons described in the following
paragraphs.
4.9.1
Communications Modes
The option buttons located in the communications modes box are used to set the microprocessor
interface mode to parallel interface or serial interface.
Note:
4.9.2
The selected communication mode must match the evaluation board MODE switch setting (see
“Evaluation Board Set-up” on page 14). The factory default setting is parallel mode.
Registers
Clicking the Registers control button will select the Registers screen, enabling read/write access to
all the LXT386 registers. See “Registers” on page 16.
4.9.3
Setting Individual Transceiver Operating Modes
Select the transceiver channel you wish to configure by clicking on the corresponding tab symbol.
Once a channel has been selected, set the operating mode by clicking on one of the three loopback
modes.
16
Developer Manual
Evaluation Board for Quad T1/E1 Applications — LXD386
4.9.4
Apply to all Channels
Clicking the “Apply to All Channels” control button will configure the other three channels to the
settings displayed for the currently selected channel.
4.9.5
Exit
The exit control button can be used at any time to close the software.
Figure 7. Configuration Screen
Developer Manual
17
LXD386 — Evaluation Board for Quad T1/E1 Applications
4.10
Registers Screen
4.10.1
Setting Registers
The Registers screen (see in Figure 8) allows direct control of all the LXT386 registers. Each
register is labeled by its functional name and hex address. Right click on a register name for on-line
help.
4.10.2
Status Indicators
Display boxes within the Registers screen show the state settings for individual bit positions of
each register. Each of the 4 least significant bits of these registers control the corresponding
transceiver channel, except where otherwise noted in the LXT386 specifications. The check boxes
beside the “Mode” column denote enabling of read/write step modes.
4.10.3
Control Buttons
Clicking on the “Read All” button will initiate a global read of all LXT386 registers. Clicking on
the “Read Step” and “Write Step” buttons performs the indicated action only on registers that have
the enable box checked. The “Back” button is used to return to the configuration screen, and the
“Exit” control button can be used at any time to close the software.
4.10.4
Interrupts
The Interrupt indicator is located in the lower right corner. This indicator will turn red whenever
there are pending interrupts in the LXT386. Interrupts are cleared by reading the corresponding
Status Monitor register. When all interrupts are cleared, the Interrupt indicator will turn Green. See
Figure 8.
4.10.5
Reset
While operating the evaluation board in Software mode, reset is accomplished by using the write
step function to write to the software reset register address 0Ah.
18
Developer Manual
Evaluation Board for Quad T1/E1 Applications — LXD386
Figure 8. Registers Screen
Developer Manual
19
R/W/RD
CS
OE
ALE/SCLK/AS
DS/WR/SDI
MUX
MOT/INTL
a32
a31
a30
a29
a28
a27
a26
a25
a24
a23
a22
a21
a20
a19
a18
a17
a16
a15
a14
a13
a12
a11
a10
a9
a8
a7
a6
a5
a4
a3
a2
a1
ALE/SCLK/AS
MOT/INTL
MUX
VCC
LOOP1/D1
LOOP3/D3
DLOOP1/D5
DLOOP3/D7
A1
A3
R/W/RD
CS
OE
ALE/SCLK/AS
DS/WR/SDI
INT
ACK/RDY/SDO
MUX
MOT/INTL
96 Pin DIN Connector Male
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
b32
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
TRST
TMS
TCK
TDO
TDI
INT
CS
R6
100K
R5
100K
100K
R7
96 Pin DIN Connector Male
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CON1B
100K
R8
c32
c31
c30
c29
c28
c27
c26
c25
c24
c23
c22
c21
c20
c19
c18
c17
c16
c15
c14
c13
c12
c11
c10
c9
c8
c7
c6
c5
c4
c3
c2
c1
100K
R9
100K
R10
MODE
R/W/RD
CLKE
ACK/RDY/SDO
DS/WR/SDI
VCC
4.7K
R1
LOOP0/D0
LOOP2/D2
DLOOP0/D4
DLOOP2/D6
A0
A2
A4
96 Pin DIN Connector Male
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CON1C
VCC
VCC
10K
R4
10K
R3
10K
R2
LOOP0/D0
LOOP1/D1
LOOP2/D2
LOOP3/D3
DLOOP0/D4
DLOOP1/D5
DLOOP2/D6
DLOOP3/D7
A0
A1
A2
A3
A4
MCLK
MODE
CLKE
90
91
92
93
94
95
96
97
2
98
83
82
3
80
81
85
86
87
88
89
78
79
84
99
1
U1A
LXT386
LOOP0/D0
LOOP1/D1
LOOP2/D2
LOOP3/D3
LOOP4/D4
LOOP5/D5
LOOP6/D6
LOOP7/D7
R/W/RD
CS
OE
ALE/SCLK/AS
DS/WR/SDI
INT
ACK/RDY/SDO
A0
A1
A2
A3
A4
MCLK
MODE
CLKE
MUX
MOT/INTL
VCC
JP1
.1uF
.1uF
.1uF
C4
C5
C6
AT1
AT2
TRST
TMS
TCK
TDO
TDI
.1uF
C3
77
76
72
71
69
73
70
25
18
58
51
.1uF
C2
LOS0
LOS1
LOS2
LOS3
.1uF
C1
8
9
68
67
4
6
75
VCC_0
VCC_1
VCC_2
VCC_3
VCCIO
VCC_DIG
VCC_ANA
20
GND_0
GND_1
GND_2
GND_3
GNDIO
GND_DIG
GND_ANA
R12
100K
100K
TDI
AT1
AT2
TRST
TMS
TCK
TDO
R11
LOS0
LOS1
LOS2
LOS3
Date:
Size
B
Title
2
4
6
8
Wednesday, September 15, 1999
Document Number
DATA/CONTROL
Sheet
1
of
6
FIREBIRD - LXD386 DEMO BOARD
LEVEL ONE COMMUNICATIONS
HEADER 4X2
1
3
5
7
JP2
JTAG PORT
Rev
A4
5.0
10
11
66
65
5
7
74
CON1A
LXD386 — Evaluation Board for Quad T1/E1 Applications
Evaluation Board Schematics
Figure 9. Evaluation Board Schematic — Data/Control
Developer Manual
TCLK3
TPOS3/TDATA3
TNEG3/UBS3
RCLK3
RPOS3/RDATA3
RNEG3/BPV3
TCLK2
TPOS2/TDATA2
TNEG2/UBS2
RCLK2
RPOS2/RDATA2
RNEG2/BPV2
TCLK1
TPOS1/TDATA1
TNEG1/UBS1
RCLK1
RPOS1/RDATA1
RNEG1/BPV1
TCLK0
TPOS0/TDATA0
TNEG0/UBS0
RCLK0
RPOS0/RDATA0
RNEG0/BPV0
57
56
55
54
53
52
64
63
62
61
60
59
12
13
14
15
16
17
19
20
21
22
23
24
LXT386
TCLK3
TPOS3/TDATA3
TNEG3/UBS3
RCLK3
RPOS3/RDATA3
RNEG3/BPV3
TCLK2
TPOS2/TDATA2
TNEG2/UBS2
RCLK2
RPOS2/RDATA2
RNEG2/BPV2
TCLK1
TPOS1/TDATA1
TNEG1/UBS1
RCLK1
RPOS1/RDATA1
RNEG1/BPV1
TCLK0
TPOS0/TDATA0
TNEG0/UBS0
RCLK0
RPOS0/RDATA0
RNEG0/BPV0
U1B
C10
.1uF
.1uF
C13
C14
RTIP3
RRING3
TTIP3
TRING3
RTIP2
RRING2
TTIP2
TRING2
RTIP1
RRING1
TTIP1
TRING1
RTIP0
RRING0
49
48
46
45
42
43
39
40
37
36
34
33
30
31
27
28
.1uF
C12
TTIP0
TRING0
.1uF
C11
33uF TANT
RTIP3
RRING3
TTIP3
TRING3
RTIP2
RRING2
TTIP2
TRING2
RTIP1
RRING1
TTIP1
TRING1
RTIP0
RRING0
TTIP0
TRING0
C17
.1uf
TVS 3.3V
D2
Date:
Size
B
Title
Wednesday, September 15, 1999
Document Number
LIU
Sheet
2
of
6
FIREBIRD - LXD386 DEMO BOARD
LEVEL ONE COMMUNICATIONS
TP6
TESTPOINT
C16
.01uf
TP5
TESTPOINT
C15
68 uF
VCC
TVS 5V
D1
TP4
TESTPOINT
1
1
C9
.1uf
TP3
TESTPOINT
BLACK
BN3
RED
BN2
C8
.01uf
TP2
TESTPOINT
-
+
C7
68 uF
TVCC
TP1
TESTPOINT
BANANA JACK
BANANA JACK
3.3 VOLTS
RED
1
1
+
BN1
1
TVCCP
+
1
JP3
BANANA JACK
TVCC
1
26
35
38
47
TVCC0
TVCC1
TVCC2
TVCC3
TGND0
TGND1
TGND2
TGND3
29
32
41
44
1
Developer Manual
1
TVCC
Rev
A4
Evaluation Board for Quad T1/E1 Applications — LXD386
Figure 10. Evaluation Board Schematic — Line Interface Unit
21
22
19
17
15
13
11
9
7
5
3
1
PROTECTED MONITORING
ADDRESS SELECT
VCC
1
2
3
4
1
2
3
4
1
2
3
4
Hardware mode
JA Select
20
18
16
14
12
10
8
6
4
2
LINE BUILDOUTS
CS
DLOOP3/D7
DLOOP2/D6
DLOOP1/D5
DLOOP0/D4
LOOP3/D3
LOOP2/D2
LOOP1/D1
LOOP0/D0
JP4
HEADER 10X2
SW DIP-4
SW DIP-4
S4
SW DIP-4
S3
S2
8
7
6
5
8
7
6
5
8
7
6
5
CLKE
OE
MOT/INT/CODEN
MUX
LEN0
LEN1
LEN2
SWLOOP7
SWLOOP6
SWLOOP5
SWLOOP4
SWLOOP3
SWLOOP2
SWLOOP1
SWLOOP0
MODE
R17
4.7k
1
2
3
4
5
6
7
8
9
10
R18
4.7k
R19
4.7k
TriState10
S1
20
11
R20
4.7k
VCC
R21
4.7k
4.7K
R16
R22
4.7k
R23
4.7k
R24
4.7k
2
4
6
8
10
12
14
16
18
20
HEADER 10X2
1
3
5
7
9
11
13
15
17
19
JP6
EXT. MCLK
J1
BNC
7
1
C
VCC
R15
50 Ohms
8
14
CLKE
OE
MOT/INTL
MUX
A3
A2
A1
A0
DS/WR/SDI
R/W/RD
ALE/SCLK/AS
EXTCLK
2
4
6
8
Date:
Size
B
Title
HEADER 4X2
1
3
5
7
JP5
4.7k Ohms
VCC
50 Ohms R14
VCC
R13
XTAL
2.048MHZ
GND
X
X1
Wednesday, September 15, 1999
Document Number
MONITOR
Sheet
3
of
6
FIREBIRD - LXD386 DEMO BOARD
LEVEL ONE COMMUNICATIONS
MCLK
Rev
A4
LXD386 — Evaluation Board for Quad T1/E1 Applications
Figure 11. Evaluation Board Schematic — Monitoring
Developer Manual
LOS3
LOS2
LOS1
LOS0
R35
25K
R30
25K
R29
25K
R28
25K
VCC
VCC
VCC
+
+
Developer Manual
+
+
VCC
14
6
14
9
10
11
47uF TANT
7
C29
6
1
2
3
47uF TANT
15
C28
9
10
11
47uF TANT
7
C27
1
2
3
47uF TANT
15
C26
U2A
74LS221
A
B
CLR
REXT/CEXT
CEXT
U5B
74LS221
A
B
CLR
REXT/CEXT
CEXT
U5A
74LS221
A
B
CLR
REXT/CEXT
CEXT
U2B
74LS221
A
B
CLR
REXT/CEXT
CEXT
Q
Q
Q
Q
Q
Q
Q
Q
12
13
12
10
4
5
9
5
13
4
12
2
4
5
1
13
74LS32
U3D
74LS32
U3C
74LS32
U3B
74LS32
U3A
11
8
6
3
1
2
4
6
8
U4A
74LS240
G
A1
A2
A3
A4
Y1
Y2
Y3
Y4
U2
18
16
14
12
C18
.1uf
VCC
U3
C19
.1uf
U4
LOS3
LOS2
LOS1
Date:
Size
B
R31
330 Ohms
330 Ohms
R34
330 Ohms
R33
330 Ohms
R32
VCC
LEVEL ONE COMMUNICATIONS
LED YEL.
LED YEL.
D6
LED YEL.
D5
LED YEL.
D4
D3
X1
C25
.1uf
Wednesday, September 15, 1999
Document Number
LOS 1
Sheet
4
of
6
FIREBIRD - LXD386 DEMO BOARD
C21
.1uf
LOS0
U5
Title
C20
.1uf
Decoupling
Caps
Rev
A4
Evaluation Board for Quad T1/E1 Applications — LXD386
Figure 12. Evaluation Board Schematic — LOS Detector
23
24
RRING1
RTIP1
TTIP2
TRING2
RTIP2
RRING2
TRING3
TTIP3
RRING3
RTIP3
D18
D16
TVCC
TVCC
R43
D14
D12
R54
1K
C34
.22uF
15 Ohms
15 Ohms
R39
15 Ohms
R41
R53
15 Ohms
R50
15 Ohms
JP8
11 Ohms
R45
11 Ohms
R47
560pF
C33
5
R52
T2B
T2C
TG-49-1505-NX
15
14
11
12
13
38
37
36
39
40
28
27
26
29
30
33
32
31
34
35
TG-49-1505-NX
T2A
TG-49-1505-NX
10
9
6
7
8
4
15 Ohms
C37
1
2
3
R51
560pF
JP10
JP14
11 Ohms
R59
11 Ohms
R57
R48
1K
TVCC
1K
.22uF
C35
JP12
.22uF
C31
D22
D20
R37
D10
D8
1K
TVCC
1K
R55
1K
R49
GREEN
WHITE
TRING0
TVCC
D7
D9
TVCC
D21
D19
BN14
WHITE
TTIP0
RRING0
RTIP0
TVCC
D17
RTIP1x 1
GREEN
TRING1
TTIP1
D15
RRING1x1
BN9
BN11
WHITE
BN5
BN7
BN19
WHITE
BN17
GREEN
BN15
WHITE
BN13
GREEN
BN12
GREEN
TTIP2x 1
TRING2x1
RTIP2x 1
RRING2x1
TRING3x 1
TTIP3x 1
RRING3x1
RTIP3x 1
TVCC
D13
D11
1K
R42
1K
R36
JP13
11 Ohms
R58
11 Ohms
R56
JP11
JP9
11 Ohms
R46
11 Ohms
R44
JP7
.22uF
C30
C36
C32
560pF
560pF
Date:
Size
B
Title
15 Ohms
R40
15 Ohms
R38
PE-65351
23
22
21
24
25
1:2CT
PE-65351
T3
1
3
5
1
3
5
1
1
1
1
1
1
WHITE
BN10
GREEN
BN8
WHITE
BN6
GREEN
BN4
BN18
WHITE
BN16
GREEN
Wednesday, September 15, 1999
Document Number
ANALOG
Sheet
5
of
6
Rev
A4
LEVEL ONE COMMUNICATIONS
TRING0x
TTIP0x
RRING0x
RTIP0x
TRING1x
TTIP1x
FIREBIRD - LXD386 DEMO BOARD
2
6
1:2CT
2
6
T1
TG-49-1505-NX
20
19
16
17
18
T2D
LXD386 — Evaluation Board for Quad T1/E1 Applications
Figure 13. Evaluation Board Schematic — Analog
Developer Manual
Developer Manual
TCLK3
TPOS3/TDATA3
TNEG3/UBS3
LOS3
TCLK2
TPOS2/TDATA2
TNEG2/UBS2
LOS2
TCLK1
TPOS1/TDATA1
TNEG1/UBS1
LOS1
TCLK0
TPOS0/TDATA0
TNEG0/UBS0
LOS0
R70
100k
100k
100k
100k
R69
R67
100k
100k
R66
R64
100k
100k
R63
R61
R60
100k
R71
100k
R68
100k
R65
100k
R62
2
4
6
8
10
2
4
6
8
10
2
4
6
8
10
2
4
6
8
10
HEADER 5X2
1
3
5
7
9
JP18
HEADER 5X2
1
3
5
7
9
JP17
HEADER 5X2
1
3
5
7
9
JP16
HEADER 5X2
1
3
5
7
9
JP15
CHANNEL 3
RCLK3
RPOS3/RDATA3
RNEG3/BPV3
CHANNEL 2
RCLK2
RPOS2/RDATA2
RNEG2/BPV2
CHANNEL 1
RCLK1
RPOS1/RDATA1
RNEG1/BPV1
CHANNEL 0
RCLK0
RPOS0/RDATA0
RNEG0/BPV0
Date:
Size
B
Title
Wednesday, September 15, 1999
Document Number
DIGITAL I/O
Sheet
6
of
6
FIREBIRD - LXD386 DEMO BOARD
LEVEL ONE COMMUNICATIONS
Rev
A4
Evaluation Board for Quad T1/E1 Applications — LXD386
Figure 14. Evaluation Board Schematic — Digital I/O
25