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User Manual
Pluto 5 Controller
Document No. 80-15151 Issue 6
HEBER LTD
nd
September 2005
Current Issue :-
Issue 6 – 2
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Issue 5r1 – 14 May 2004
th
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Document No. 80-15151 Issue 6
HEBER LTD
HEBER LTD
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Chalford
Stroud
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GL6 8NT
England
Tel: +44 (0) 1453 886000
Fax: +44 (0) 1453 885013
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File Name: H:\pluto5\manuals\pluto_5_controller.doc
Document No. 80-15151 Issue 6
HEBER LTD
Page i
CONTENTS
1
INTRODUCTION.................................................................................................................... 1
2
NEW IN THIS RELEASE ....................................................................................................... 1
3
OVERVIEW ............................................................................................................................ 1
4
CIRCUIT SCHEMATIC DESCRIPTION ................................................................................ 2
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
5
SHEET 1 .................................................................................................................................. 2
SHEET 2 .................................................................................................................................. 2
SHEET 3 .................................................................................................................................. 2
SHEET 4 .................................................................................................................................. 2
SHEET 5 .................................................................................................................................. 2
SHEET 6 .................................................................................................................................. 2
SHEET 7 .................................................................................................................................. 2
SHEET 8 .................................................................................................................................. 3
SHEET 9 .................................................................................................................................. 3
SHEET 10 ................................................................................................................................ 3
SHEETS 11, 12 & 13 ................................................................................................................ 3
CIRCUIT OPERATION .......................................................................................................... 4
5.1
POWER SUPPLIES..................................................................................................................... 4
5.2
RESET AND POWER FAIL DETECTION ......................................................................................... 4
5.3
BATTERY BACKUP .................................................................................................................... 5
5.4
THE MC68340 PROCESSOR ..................................................................................................... 5
5.4.1 CPU32 Processor Module ................................................................................................. 6
5.4.2 SIM40 System Integration Module..................................................................................... 6
5.4.3 DMA Controller Module ..................................................................................................... 8
5.4.4 Serial Module ..................................................................................................................... 8
5.4.5 Timer Module ..................................................................................................................... 9
5.5
FPGA.................................................................................................................................... 10
5.6
EPROM SOCKETS / EPROM AUTOSELECT FEATURE ............................................................. 10
5.7
EPROM ADDRESS LINE SCRAMBLING IN 16 BIT MODE ............................................................ 11
5.7.1 2*27C040 EPROMs ......................................................................................................... 11
5.7.2 2*27C801 EPROMs ......................................................................................................... 11
5.8
MEMORY EXPANSION.............................................................................................................. 13
5.9
OPEN DRAIN OUTPUTS, OP0-63............................................................................................. 13
5.10
AUX OUTPUTS, AUX0-7 ........................................................................................................ 14
5.11
INPUTS, IP0-31 ...................................................................................................................... 14
5.12
DIL SWITCHES ....................................................................................................................... 15
5.13
SOFTWARE CONTROLLED INDICATOR LED............................................................................... 15
5.14
ON-BOARD PUSH BUTTON ...................................................................................................... 15
5.15
MULTIPLEXER ......................................................................................................................... 15
5.16
MULTIPLEXED LAMP CURRENT SENSE ..................................................................................... 17
5.17
SOUND GENERATION .............................................................................................................. 18
5.18
STEREO AMPLIFIER AND VOLUME CONTROLS........................................................................... 18
5.19
SERIAL I/O ............................................................................................................................. 19
2
5.20
INTERNAL I C BUS .................................................................................................................. 19
5.20.1 Real Time Clock............................................................................................................... 19
2
5.20.2 E PROM........................................................................................................................... 19
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Page ii
6
MACHINE OPERATION ...................................................................................................... 20
6.1
DRIVING REELS ...................................................................................................................... 20
6.2
READING THE DIL SWITCHES .................................................................................................. 20
6.3
READING THE SWITCH INPUTS ................................................................................................. 20
6.4
INTERFACING TO COIN & NOTE ACCEPTORS ............................................................................ 21
6.5
INTERFACING TO COIN PAYOUT MECHANISMS .......................................................................... 21
6.6
DRIVING VACUUM FLUORESCENT DISPLAYS (VFD) .................................................................. 21
2
6.7
USING THE EXTERNAL I C BUS ............................................................................................... 21
6.8
DRIVING METERS ................................................................................................................... 21
6.9
MAKING SOUNDS .................................................................................................................... 21
6.9.1 Single Channel/Single Speaker (Mono) Mode ................................................................ 22
6.9.2 Dual Channel/Dual Speaker (Stereo) Mode .................................................................... 22
6.9.3 Known DMA Problems..................................................................................................... 22
6.10
USING MULTIPLEXED LAMPS ................................................................................................... 22
6.11
USING MULTIPLEXED LEDS .................................................................................................... 22
6.12
USING THE MULTIPLEX EXPANSION CONNECTOR ..................................................................... 23
6.13
ADDING VIDEO CAPABILITIES................................................................................................... 23
7
SOFTWARE DEVELOPMENT ............................................................................................ 24
8
CONNECTOR TYPES AND PIN OUTS .............................................................................. 25
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
8.20
8.21
SCHEDULE OF CONNECTOR TYPES.......................................................................................... 25
P1 – RS232 CHANNEL A ....................................................................................................... 26
P2 – DATAPORT (RS232 CHANNEL B).................................................................................... 27
P3 – POWER INPUT ................................................................................................................ 27
P4 – MULTIPLEXED LAMP SINKS ............................................................................................. 28
P5 ULTREX – MULTIPLEXED LEDS .......................................................................................... 28
P5 BOX HEADER – MULTIPLEXED LEDS .................................................................................. 29
P6 – MULTIPLEXED LAMPS SOURCES...................................................................................... 29
P7 ULTREX – REELS .............................................................................................................. 30
P7 BOX HEADER – REELS ...................................................................................................... 31
P8 ULTREX – GENERAL I/O #1 ............................................................................................... 32
P8 BOX HEADER – GENERAL I/O #1 ....................................................................................... 33
P9 ULTREX – GENERAL I/O #2 ............................................................................................... 34
P9 BOX HEADER – GENERAL I/O #2 ....................................................................................... 34
P10 – LOUDSPEAKERS ........................................................................................................... 35
P11 – MULTIPLEX EXPANSION ................................................................................................ 35
P12 – AUX OUTPUTS ............................................................................................................. 35
2
P13 – EXTERNAL I C BUS ...................................................................................................... 36
P14 – IO EXPANSION CARD CONNECTOR ............................................................................... 36
P15 – MEMORY EXPANSION CARD CONNECTOR...................................................................... 37
P16 – BACKGROUND DEBUG MODE CONNECTOR .................................................................... 37
Document No. 80-15151 Issue 6
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Page iii
LIST OF TABLES
Table 1. Allocation of MC68340 Pins Controlled by SIM40 Module........................................................ 7
Table 2. Allocation of MC68340 Pins Controlled by DMA Module .......................................................... 8
Table 3. Allocation of MC68340 Pins Controlled by Serial Module......................................................... 9
Table 4. Allocation of MC68340 Pins Controlled by Timer Module......................................................... 9
Table 5. Possible EPROM Configurations ............................................................................................ 10
Table 6. Re-Mapping of Address Lines in 2*27C040 Mode .................................................................. 11
Table 7. Re-Mapping of EPROM Contents in 2*27C040 Mode ............................................................ 11
Table 8. Re-Mapping of Address Lines in 2*27C801 Mode .................................................................. 11
Table 9. Re-Mapping of EPROM Contents in 2*27C801 Mode ............................................................ 12
Table 10. Mapping of Open Drain Outputs (OP0-63) to TPIC6259 Devices ........................................ 13
Table 11. Mapping of Inputs IP0-31 ...................................................................................................... 14
Table 12. Mapping of DIL Switch Inputs................................................................................................ 15
2
Table 13. I C Slave Addresses for RTC, U40 ....................................................................................... 19
2
2
Table 14. I C Slave Addresses for E PROM, U37 ................................................................................ 19
Table 15. Recommended Reel Stepper Motor Drive Connections ....................................................... 20
Table 16. AMP Ultrex Connector Part Numbers ................................................................................... 25
Table 17. Tyco Box Header Connector Part Numbers.......................................................................... 25
Table 18. AMP MTA-100 Connector Part Numbers .............................................................................. 26
Table 19. AMP MTA-156 Connector Part Numbers .............................................................................. 26
LIST OF FIGURES
Figure 1 - Schematic Sheet 1 - Root Sheet........................................................................................... 38
Figure 2 - Schematic Sheet 2 - CPU ..................................................................................................... 39
Figure 3 - Schematic Sheet 3 - FPGA................................................................................................... 40
Figure 4 - Schematic Sheet 4 - Memory................................................................................................ 41
Figure 5 - Schematic Sheet 5 - Sound .................................................................................................. 42
Figure 6 - Schematic Sheet 6 - Outputs ................................................................................................ 43
Figure 7 - Schematic Sheet 7 - Inputs................................................................................................... 44
Figure 8 - Schematic Sheet 8 - Power Supply ...................................................................................... 45
Figure 9 - Schematic Sheet 9 – IO Connectors..................................................................................... 46
Figure 10 - Schematic Sheet 10 - Reset/Battery/RS232....................................................................... 47
Figure 11 - Schematic Sheet 11 - Lamp Column/LED Digit Drives....................................................... 48
Figure 12 - Schematic Sheet 12 - Lamp Row Drives ............................................................................ 49
Figure 13 - Schematic Sheet 13 - LED Segment Drives....................................................................... 50
Figure 14 - Pluto 5 Component Ident .................................................................................................... 51
Figure 15 - Photograph of Pluto 5 with Ultrex Connectors (Pluto 5U)................................................... 52
Document No. 80-15151 Issue 6
HEBER LTD
Page 1
1 INTRODUCTION
The Pluto 5 Controller board is a natural progression in the Pluto family of products. It builds on the
proven reliability and technical excellence of previous Pluto boards and provides improved
performance and flexibility at lower cost. This manual covers the detail of the hardware operation of
Pluto 5 Controller board, other boards in the system have their own manuals.
2 NEW IN THIS RELEASE
•
Section 6.9 has revised audio information.
3 OVERVIEW
The Pluto 5 Controller board is a low cost, high performance single board controller for amusement
machines. An 8 reel machine with 256 lamps, 32 LED digits, Linewriter display, Coin Acceptors, Note
Acceptors and Payout Hoppers can be controlled without any additional boards.
Single channel sound can be played through one or two speakers. Two Channel (mono or stereo)
sound is available by plugging in an additional IC.
Pluto 5 boards are supplied with either Ultrex or Box Header connectors.
Pluto 5 with Ultrex connectors is referred to as Pluto 5U.
Pluto 5 with Box Header connectors is referred to as Pluto 5B.
These connectors and all the other connectors on the Pluto 5 board are documented in Section
8 - Connector Types and Pin Outs in this user manual.
Add-on boards are available to increase the number of lamps by up to 512, LED Digits by up to 64 as
well as CGA/VGA Video and Memory Expansion.
The numbering system on all Pluto 5 boards is consistent, in that, where Lamps and LEDs are
involved the product name has a suffix X/Y. X is the number of lamps and Y is the number of LED
digits that that product drives. The Pluto 5 Controller board is available as a Pluto 5 128/16
Controller and a Pluto 5 256/32 Controller.
Document No. 80-15151 Issue 6
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Page 2
4 CIRCUIT SCHEMATIC DESCRIPTION
This section is a walk through of the Pluto 5 Controller board (56-14084) circuit schematics, Figures
1-13 of this document. A detailed description is given in Section 5 “CIRCUIT OPERATION”.
4.1
Sheet 1
This sheet shows the interconnection between the remaining sheets of this drawing.
4.2
Sheet 2
This sheet shows the following items:
•
•
•
•
4.3
Motorola MC68340 Processor.
Pull-up resistors on Address Bus, Data Bus and other Control Signals.
Push Button Switch, SW3.
P16 “BACKGROUND DEBUG MODE” connector.
Sheet 3
This sheet shows the FPGA.
4.4
Sheet 4
This sheet shows the following memory related circuits:
•
•
•
4.5
Sockets for 1 or 2 EPROMs, U1 and U2
64Kbytes Battery backed RAM, U3 and U4
P15 “MEMORY EXPANSION” connector for plug-in Memory Cards
Sheet 5
This sheet shows the following sound related circuits:
•
•
•
•
4.6
Standard Sound Channel #1, U8 (OKI MSM6585).
Optional Sound Channel #2, U39 (OKI MSM6585).
TDA7057AQ Stereo Audio Amplifier.
P10, “LS” connector for loudspeakers.
Sheet 6
This sheet shows the 64 Open Drain Outputs, OP0-63.
4.7
Sheet 7
This sheet shows the following circuits:
•
•
External inputs, IP0-31
Two 8 way DIL switches, SW1 and SW2
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HEBER LTD
Page 3
4.8
Sheet 8
This sheet shows various Power Supply related functions:
•
•
•
•
•
•
4.9
Current sensing +12V Meter supply
Power fail detection.
Current sensing from Lamp Multiplex.
Fuse and +5V regulator.
Voltage rail overvoltage and transient protection.
P3 “PWR IN” power input connector
Sheet 9
This sheet shows the following I/O connectors.
•
•
•
•
•
•
P7 “REELS” carries enough I/O lines to run 6 reels, including a sub set of the lamp multiplexer and
power supplies for the motors.
P8 “I/O 1” and P9 “I/O 2” are general purpose I/O.
P11 “MULTIPLEX EXPANSION” provides signals for the connection of Multiplex Expansion
boards.
P12 “AUX OUTPUTS” provides 6 open drain TTL outputs, typically for driving VFD displays.
2
2
2
P13 “I C” provides a connector for external I C expansion, e.g. E PROM modules. Note that the
2
lines used to implement this connector are different to the lines allocated for the internal I C bus to
U40 and U37.
P14 “I/O EXPANSION” is a position for a daughter board for I/O expansion.
4.10 Sheet 10
This sheet shows the following circuits and connectors:
•
•
•
•
•
•
•
Reset circuit and LED.
Battery Backup for RAM and optional Real Time Clock.
2
Optional I C Real Time Clock socket, U40, PCF8583.
2
2
Optional I C E PROM socket, U37, 24C04 (512 bytes) or 24C08 (1024 bytes).
RS232 buffers.
P1 “RS232” is a general purpose RS232 serial communication port.
P2 “DATAPORT” is the BACTA standard Dataport.
4.11 Sheets 11, 12 & 13
These sheets show the Multiplex Lamp and LED drive circuits and connectors.
•
•
•
•
•
•
Sheet 11 shows the Lamp Columns/Digits Sink drivers.
Sheet 12 shows the Lamp Row/Source drivers
Sheet 13 shows the LED Segment drivers
P4 “LAMP SINKS” is the Lamp Array Column/Sink outputs
P5 “LED” is the connector for the 32 or 16 LED digits.
P6 “LAMP SRC” is the Lamp Array Row/Source outputs
Document No. 80-15151 Issue 6
HEBER LTD
Page 4
5 CIRCUIT OPERATION
This section describes how some elements of the circuit operate and their capabilities and limitations.
A subsequent section deals with how the various capabilities of the board are used to implement
specific amusement machine functions.
5.1
Power Supplies
The Power Input to the board is on P3. There are 3 input voltages required, +12V, -12V and 36V or
48V for the lamp multiplex.
The +12V supply is fused by F1 (3.15A) as it comes on the board. From the un-fused (input) side, the
+12V is distributed to the Reel Connector, P7 where it may be used to provide the supply for the
Stepper Motors.
From the fused side, the +12V is used for the following:
•
•
•
•
•
Regulated via U15 to provide the Vcc (+5V) supply for the board. This will draw up to 250mA from
the +12V rail.
To provide the Power Supply for the Stereo Audio Amplifier, U32. The load current drawn by this
will depend on the audio volume, etc. but is not likely to exceed an average of about 200mA.
Monitored by U16B to detect imminent failure of the +5V supply and cause a Level 7 (NonMaskable) Interrupt, NMI-. The interrupt will occur if the +12V supply drops below approximately
7.8V.
To provide the Power Supply for the multiplexed LED drive circuits. With 32 LED digits fitted and
all having all segments illuminated, the current drain is likely to be between 400mA and 550mA.
Distributed to various connectors, P1, P2, P8, P9, P12 and P14 for optional use by external
circuits.
When connecting external loads to the Fused +12V outputs on P1, P2, P8, P9, P12 and P14 make
sure that the total current drawn is within the rating of fuse F1 (3.15A), making due allowances for the
other loads as described above.
The –12V supply input provides the negative supply for the 1488 RS232 Transmitter Buffer, U33, and
the –12V supply required on the DATAPORT Connector, P2.
The Lamp Multiplex supply should be +36V or +48V, depending upon the duty cycle employed by the
software. See Section 6.10, “Using Multiplexed Lamps” for more information.
Transient suppressers (Tranzorbs) are fitted on the +12V supply (fused side), -12V supply and Vcc to
protect these lines against any overvoltage.
5.2
Reset and Power Fail Detection
TL7705 device, U17, (see Schematic Sheet 10 - Reset/Battery/RS232), provides the system reset. At
power up, the system is held in a reset state (RESET- low, RESET high) for about 5 seconds. This
time is determined by C14. The processor may initiate a full hardware reset at any time by asserting
Port B, pin 0 (PB0) low, which will trigger the TL7705 via the RESIN- pin. The RESET lines will also be
immediately asserted by the TL7705 if the Vcc line drops below 4.75V.
While the system is in a reset state, i.e. RESET- is low, a red LED, LD1, is illuminated.
The power fail detection is a simple threshold detection on the 12V rail using one section of the quad
comparator LM339 (U16B), see Schematic Sheet 9 - IO Connectors.
When the +12V input falls below a threshold of approximately 7.8V, the output of the comparator goes
low which causes a Level 7 interrupt (NMI) to the processor. This will occur BEFORE the 7805
regulator drops out of regulation and the Vcc line starts to drop, thus giving the processor a period of
time to react before the RESET is asserted by the TL7705, U17. The main purpose of giving the
Document No. 80-15151 Issue 6
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Page 5
processor the NMI in advance of the RESET is to avoid the risk of an incomplete RAM write operation
occurring if the RESET were to be asynchronously asserted while such an operation was being
carried out.
The time available between the assertion of NMI and the assertion of RESET will depend on the rate
of fall of the +12V line, which will obviously be dependent upon the power supply and the loading on
the +12V, but will typically be several milliseconds.
5.3
Battery Backup
A backup battery, BT1, is provided (see - Schematic Sheet 10 - Reset/Battery/RS232) to allow the two
RAMs U3 and U4 to retain data while the board is powered down and to keep the optional Real Time
Clock chip, U40, running.
BT1 is a two cell rechargeable NiMH (Nickel Metal Hydride) battery, capacity 70mA/hr. The circuit
comprising BT1, Q2, R43 and R132 provides the battery trickle charge and switchover of the secured
power supply rail, Vbatt.
While Vcc is at 5V, current flows through the base-emitter junction of Q2 through R43 into the battery.
On charge, the voltage on BT1 will be about 2.6V so the current through R43 will be (5-VBE-2.6)/3300,
about 0.5mA. Thus Q2 will be turned ON and Vbatt will be a VCEsat below Vcc. Current will therefore
also flow through R132 into Vbatt, (5-VCEsat-2.6)/3300, about 0.7mA. Total trickle charge current is
therefore 0.5 + 0.7 = 1.2mA. The specification of the cells calls for a trickle charge of between .01C
and .03C. C is 70mA, so the acceptable range is between .7mA and 2.1mA.
When power is removed, Vcc collapses to ground. The base-emitter junction of Q2 is now reverse
biased and therefore no current flows through R43 and Q2 is OFF. Vbatt is now connected to the
positive end of BT1 via R132. The discharge current into the RAMs and RTC should not exceed 40µA,
which will result in a voltage drop in R132 of less than 0.15V. This gives a worst case battery life in
excess of two months, and in practice much higher.
When on battery backup it is vital that the RAMs are placed in the standby state by ensuring that the
CS- line is high. Q1 and R42 achieve this. When the RESET- line goes low, which may occur either as
a result of a Reset occurring or Vcc collapsing, Q1 turns OFF causing the CS- lines to the RAMs to be
pulled to Vbatt by R42.
5.4
The MC68340 Processor
Full details of the operation of the processor is given in the Motorola MC68340 User Manual [see
Adobe Acrobat File 68340um.pdf, plus Addenda files 68340um_ad.pdf and 68340um_ad2.pdf]
The MC68340 contains the following functional blocks:
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Page 6
5.4.1
CPU32 Processor Module
The CPU32 is a processing core which is basically 68000 code compatible but with a number of
enhancements. For full details of operation please refer to both the Motorola MC68340 User Manual
and the Motorola M68000 Family Programmers Reference Manual [see Adobe Acrobat File
68kprm.pdf].
All modern 68000 Compilers and Assemblers have various options for the target CPU. When
generating code for the Pluto System, the CPU32 option should be used.
If the Compiler/Assembler is old it is possible that it may not have a CPU32 option. In this case, the
Compiler (if used) should be run with the 68000 option set. The assembler may be run in 68020 mode
which will allow the use of the MOVES command which is required during initialisation to set up the
Module Base Address Register (MBAR) in the MC68340. Care must be taken not to write code that
calls any other 68020 instructions that may not be implemented on the CPU32.
The Pluto 5 Development Kit includes a suitable C Compiler and Assembler.
5.4.2
SIM40 System Integration Module
This module controls various aspects of the operation of the processor, such as configuration, clock,
external bus, etc.
When used in the Pluto System, the main considerations in the use of this module are:
5.4.2.1
Module Base Address Register
Set the Module Base Address Register, MBAR, to a suitable address during initialisation.
This sets the base address of all the internal module registers. In the example code it is set
in Module “except.asm” to value 0xffff f000. There is nothing magic about this value, but
obviously it must be set to an address that is clear of any other devices in the processor
memory map. This register must be set before any other module initialisation is attempted.
5.4.2.2
Chip Selects
Set-up the 4 Chip Select outputs, CS0- to CS3-. The Pluto 5 System allocates these as
follows:
CS0 - is used to map the system programme memory. This consists of any EPROM fitted to
the on-board EPROM sockets, U1 and U2 plus any extra EPROM or FLASH devices fitted to
the Memory Expansion Connector, P14. Exact mapping, within the area defined by CS0-, is
carried out be the system FPGA.
CS1 - is used to map the on-board, battery backed RAM and, if fitted, any external RAM on
a memory card on connector P15.
CS2 - is used to map both the internal registers of the FPGA and the on-board I/O,
CS3 - is normally spare and is available on the I/O expansion connector, P14. Its main use is
for the selection of the optional add-on CGA/VGA Video Card.
After hardware reset, CS0- will be asserted for memory accesses anywhere in the memory
map which allows the processor to boot. However, the chip selects must be programmed
immediately after Reset and prior to any function or subroutine calls, because until they are,
CS1- will not be active and therefore it will not be possible for the processor to access RAM.
Example code for setting up the 4 pairs of Chip Select Base and Mask registers is given in
Module except.asm
5.4.2.3
Periodic Interrupt Timer.
The “sim40_m.c” Module in the Sample Software sets this timer to provide a high priority
1mS interrupt which is normally used by the software to provide basic system timing. This
function is controlled by the PICR and the PITR.
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Page 7
5.4.2.4
Clock Synthesiser Control
The SYNCR controls the operation of the main processor clock. The MC68340 is provided
with a 32.768KHz reference to which the main clock is phase locked. After reset, the main
clock defaults to 8.39MHz. The maximum clock frequency of the standard MC68340 is
16.77MHz.
5.4.2.5
System Protection
The SYPCR controls the bus monitors and software watchdog. Other safeguards in the
design give adequate protection against programme malfunction as a result of noise, etc.
The Software Watchdog feature is disabled, however, it could be used if required.
The Bus Monitor should be enabled and may be left set at its default of 64 clock cycles timeout.
5.4.2.6
SIM40 Module Pin Allocations
Pins under the control of the SIM40 module are allocated as follows.
Table 1. Allocation of MC68340 Pins Controlled by SIM40 Module
NAME
PA0/A24-
PIN
123
I/O
O
PA1/A25/IACK1-
122
O
PA2/A26/IACK2-
121
O
PA3/A27/IACK3-
120
I
PA4/A28/IACK4-
117
I/O
PA5/A29/IACK5-
116
I/O
PA6/A30/IACK6-
115
I/O
PA7/A31/IACK7-
114
I/O
PB0/MODCK
PB1/IRQ1-/CS1PB2/IRQ2-/CS2PB3/IRQ3PB4/IRQ4-/CS3PB5/IRQ5PB6/IRQ6PB7/IRQ7CS0-/AVEC-
87
2
3
4
5
8
9
10
1
O
O
O
I
I/O
I/O
I/O
I
O
Document No. 80-15151 Issue 6
FUNCTION
To I/O Expansion Connector P14, Pin b1, 3K3 pull-up &
RESET to Sound Channel #1, U8
To I/O Expansion Connector P14, Pin b2, 3K3 pull-up &
RESET to Sound Channel #2, U39
To I/O Expansion Connector P14, Pin b3, 3K3 pull-up &
Drive for Indicator LED LD2
To I/O Expansion Connector P14, Pin b4, 3K3 pull-up &
Push Button SW3 Input
To I/O Expansion Connector P14, Pin b5, 3K3 pull-up &
2
2
SCL line (I C) to RTC, U40 and E PROM, U37
To I/O Expansion Connector P14, Pin b6, 3K3 pull-up &
2
2
SDA line (I C) to RTC, U40 and E PROM, U37
Drives S1 pin on SFX Channel #2 (U39) 3K3 pull-up &
MPX Lamp Current Sense Input
Drives S2 pin on SFX Channel #2 (U39) 3K3 pull-up &
MPX Lamp Short Circuit Sense Input
Drive LOW to initiate hardware reset.
CS1- Maps RAM
CS2- Maps FPGA registers and I/O
Vmeter current sense input.
To I/O Expansion Connector P14, Pin a3
To I/O Expansion Connector P14, Pin b15, 3K3 pull-up
To I/O Expansion Connector P14, Pin b16, 3K3 pull-up
IRQ7-/NMI input from Power Fail Detection Circuit
CS0- Maps ROM, both on-board U1/U2 and on Memory
Expansion Connector (via FPGA).
HEBER LTD
Page 8
5.4.3
DMA Controller Module
The DMA Module provides 2 DMA Channels. On the Pluto 5 these are used for sending sound data
from the Programme Memory to the OKI MSM6585 Sound Chip(s). DMA Channel 1 is used to send
data to Sound Channel #1, which is fitted as standard to the Pluto 5 Board. DMA Channel 2 is used for
the optional add-on Sound Channel #2 if fitted (IC39).
The DMA channel should be set to work in following modes:
•
•
•
•
•
•
External request
Dual address
Source address incrementing (Memory)
Destination address not incrementing (FPGA sound register)
Transfer size = byte
Interrupt on completion
Pins controlled by the DMA module are allocated as follows:
Table 2. Allocation of MC68340 Pins Controlled by DMA Module
PIN
DREQ1DACK1DONE1DREQ2DACK2DONE2-
5.4.4
NO.
16
15
14
13
12
11
I/O
I
O
IO
I
O
IO
FUNCTION
SFX Channel 1 DMA request
No connection
Not used, 3K3 pull-up
SFX Channel 2 DMA request
No connection
Not used, 3K3 pull-up
Serial Module
The Serial Module provides Asynchronous Comms on 2 Channels, Channel A and Channel B. It is
functionally very similar to the 1681/68681 range of DUARTs.
Channel A is buffered to RS232 levels and connected to connector P1. Signals RX, TX, RTS and CTS
are provided.
Channel B is buffered to RS232 levels and connected to DATAPORT connector P2. Signals RX, TX,
RTS and CTS are provided.
The 4 Channel A signals are also made available on the TTL Expansion Connector, P14, at TTL
levels. Thus, alternative interfaces may be provided on an Add-on Board to allow, say, RS485 or Mars
HII interfaces to be implemented.
The exact set up of the Serial Module will obviously depend upon the functionality required.
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Pins controlled by the Serial module are allocated as follows:
Table 3. Allocation of MC68340 Pins Controlled by Serial Module
PIN
RXDA
NO.
33
I/O
I
TXDA
32
O
RXDB
TXDB
OP0/RTSA-
25
24
29
I
O
O
OP1/RTSBOP4/RXRDYAOP6/TXRDYACTSA-
23
27
26
28
O
O
O
I
CTSB-
22
I
5.4.5
FUNCTION
RX DATA Channel A, P1, Pin 2 (RS232 level) &
To IO Expansion Connector P14, Pin c9 (TTL level)
TX DATA Channel A, P1, Pin 3 (RS232 level) &
To IO Expansion Connector P14, Pin c10 (TTL level)
RX DATA Channel B, DATAPORT P2 (RS232 level)
TX DATA Channel B, DATAPORT P2 (RS232 level)
RTS Channel A, P1, Pin 5 (RS232 level) &
To IO Expansion Connector P14, Pin c12 (TTL level)
RTS Channel B, DATAPORT P2 (RS232 level)
SFX Channel #1 – U8, Pin S1 (Select Sample Rate)
SFX Channel #1 – U8, Pin S2 (Select Sample Rate)
CTS DUART Channel A, P1, Pin 4 (RS232 level) &
To IO Expansion Connector P14, Pin c11 (TTL level)
CTS Channel B, DATAPORT P2 (RS232 level)
Timer Module
The Timer Module provides 2 General Purpose Timers.
The Pluto 5 Board uses these to provide a variable duty-cycle signals on TOUT1 and TOUT2 that is
used to control the volume setting on each channel of the TDA7057AQ Stereo Audio Amplifier.
Timer 1 (TOUT1) controls the volume of Sound Channel #1. Timer 2 TOUT2) controls the volume of
Sound Channel #2 if it is fitted. If Sound Channel #2 is not fitted, then Timer 2 may be used for other
purposes.
See Section 6.9, “Making Sounds” for detailed information on the operation of the Volume Controls.
Pins TGATE1- and TGATE2- are allocated as general purpose inputs which are used to read the SCL
2
and SDA lines on the External I C Connector, P13.
Pins controlled by the Timer Module are allocated as follows:
Table 4. Allocation of MC68340 Pins Controlled by Timer Module
PIN
TGATE1TIN1
TOUT1
TGATE2TIN2
TOUT2
NO.
79
81
80
36
34
35
I/O
I
I
O
I
I
O
FUNCTION
2
Read External I C line SCL on P13, Pin 3 (inverted)
Not Used – Strapped To Vcc
Variable Duty Cycle Volume Control SFX Channel #1
2
Read External I C Line SDA on P13, Pin 2 (inverted)
Not Used - Strapped To Vcc
Variable Duty Cycle Volume Control SFX Channel #2
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5.5
FPGA
The Pluto 5 Controller is fitted with an 84 lead PLCC socket, position U6, into which is plugged an
FPGA. The standard FPGA type used is an Actel A40MX04-PL84. The purpose of fitting an FPGA to
the system is twofold. First, to allow the Pluto 5 Controller to be uniquely configured for each user of
the system to give commercial and software security (see the FPGA SECURITY MANUAL).
Secondly, it allows particular advanced features, for example, the EPROM Autoselect and Multiplex
dimming, to be economically implemented.
The following main functions are carried out by the FPGA:
•
•
•
•
•
•
•
•
•
•
Control automatic EPROM mode selection
Generate control signals for on-board EPROM and RAM
Generate control signals for Memory Expansion Connector P15.
Generate DMA requests and multiplex data for Sound Channels 1 & 2.
Control and drive of data to Multiplex Arrays, both on-board MPX1 and expansion MPX2.
Provide various levels of Software Security.
Form an oscillator with 14.75MHz resonator:
Generate Main Clock, EXTAL for MC68340 Processor @32.768kHz.
Generate clock for MC68340 Serial Module @3.6864MHz.
Generate clock for OKI MSM6585 devices, U8/39 @640KHz.
5.6
EPROM Sockets / EPROM Autoselect Feature
The 2 EPROM positions, U1 and U2, are configured such that 4 possible configurations of programme
memory are possible (assuming no external memory expansion via P15):
Table 5. Possible EPROM Configurations
U1
U2
Mode
Configuration
Total Size
27C040
27C040
27C801
27C801
omit
27C040
omit
27C801
8 bit
16 bit
8 bit
16 bit
512k*8
512K*16
1024k*8
1024k*16
512Kbyte
1Mbyte
1Mbyte
2Mbyte
Addresses
scrambled
no
yes
no
yes
It is not necessary to change any links on the board in order to switch between different memory
configurations. All relevant switching is carried out within the FPGA, which contains an “EPROM
Autoselect” feature. After Power-up, during the reset period, the FPGA reads the top byte address of
U1. Data contained in this byte defines the memory configuration required and the FPGA
sets up the control lines to the EPROM sockets accordingly, so that, at the end of reset, the
processor is able to read the EPROM(s) correctly.
Thus, after the final linked EPROM software module has been created, prior to being blown into
EPROM, the top location of the memory must be overwritten with suitable data to signify the EPROM
configuration that will be used.
This is the feature referred to as EPROM Autoselect. A full operational description of this feature is
given in the User manual for the FPGA in use on the Pluto 5 Controller Board.
As with the Pluto 1 System, in order to facilitate the option to use either 1 or 2 EPROMs, i.e. run in 8
bit or 16 bit mode, it is necessary to have some scrambling of the address lines to the EPROMs when
operating in 16 bit mode. Therefore, prior to blowing 16 bit EPROMs, the data must be re-arranged to
compensate. A software utility is provided with the Pluto 5 Development Kit to carry this out.
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Note that this scrambling of address lines is applicable ONLY to sockets U1 and U2 on the Pluto 5
Controller Board. Any EPROM sockets on Memory Expansion Cards are connected 1:1 to the
address bus and do NOT require any special processing.
5.7
5.7.1
EPROM Address Line Scrambling in 16 Bit Mode
2*27C040 EPROMs
In 16 bit mode, running with 2 * 27C040 EPROMs, the scrambling of the address lines cause the
following effect on the memory mapping in the EPROMs. Note that this table applies to the re-mapping
that occurs to the EPROM contents, rather than the actual address lines.
Table 6. Re-Mapping of Address Lines in 2*27C040 Mode
68340 Address Bus
A0
A1-A18
A19
EPROM Address
Not Used in 16 Bit Mode
A2-A19
A1
Thus, for example, addresses will be translated as follows so the contents of the EPROM must be rearranged to compensate:
Table 7. Re-Mapping of EPROM Contents in 2*27C040 Mode
68340 Access Address
0000
0000
0000
0000
0000
0000
0002
0004
0006
0008
|
0007 FFFC
0007 FFFE
0008 0000
0008 0002
|
000F FFFC
000F FFFE
5.7.2
Will Read From This Location in
EPROM
0000
0000
0000
0000
0000
0000
0004
0008
000C
0010
|
000F FFF8
000F FFFC
0000 0002
0000 0006
|
000F FFFA
000F FFFE
2*27C801 EPROMs
In 16 bit mode, running with 2 * 27C801 EPROMs, the scrambling of the address lines cause the
following effect on the memory mapping in the EPROMs. Note that this table applies to the re-mapping
that occurs to the EPROM contents, rather than the actual address lines.
Table 8. Re-Mapping of Address Lines in 2*27C801 Mode
68340 Address Bus
A0
A1-A18
A19
A20
Document No. 80-15151 Issue 6
EPROM Address
Not Used in 16 Bit Mode
A2-A19
A1
A20
HEBER LTD
Page 12
Thus, for example, addresses will be translated as follows so the contents of the EPROM must be rearranged to compensate:
Table 9. Re-Mapping of EPROM Contents in 2*27C801 Mode
68340 Access Address
Will Read From This Location in
EPROM
0000 0000
0000 0002
0000 0004
|
0007 FFFC
0007 FFFE
0008 0000
0008 0002
|
000F FFFC
000F FFFE
0010 0000
0010 0002
0010 0004
|
0017 FFFC
0017 FFFE
0018 0000
0018 0002
|
001F FFFC
001F FFFE
0000 0000
0000 0004
0000 0008
|
000F FFF8
000F FFFC
0000 0002
0000 0006
|
000F FFFA
000F FFFA
0010 0000
0010 0004
0010 0008
|
001F FFF8
001F FFFC
0010 0002
0010 0006
|
001F FFFA
001F FFFA
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5.8
Memory Expansion
Various optional memory cards may be fitted to the Memory Expansion Connector P15. Seven lines
from the FPGA are included along with 16 data lines and 21 address lines.
The default functionality of the FPGA lines allows memory cards fitted with up to 4 EPROM or FLASH
devices to be accommodated along with a pair of RAM devices with no additional mapping
components.
If a memory card is fitted with 5V FLASH devices, then Write facilities are available. EPROM
Autoselect is also available with devices fitted on a Memory Card.
5.9
Open Drain Outputs, OP0-63
A block of 64 Open Drain Outputs, OP0-63, are provided by 8 off TPIC6259 devices U22-U29 (see
Schematic Sheet 6 - Outputs).
These are memory mapped as the least significant byte of a block of 8 words of address space. The
chip select for these devices, CS_OP-, is provided by the FPGA. Consult the User Manual of the
FPGA being used for exact mapping.
Please note that the chips are bit wide, not byte wide. Thus, Bit 0 of each word drives one device,
U22: Bit 1 drives U23, etc.
Table 10. Mapping of Open Drain Outputs (OP0-63) to TPIC6259 Devices
Bit
Pin
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
D7
U29
OP63
OP55
OP47
OP39
OP31
OP23
OP15
OP7
D6
U28
OP62
OP54
OP46
OP38
OP30
OP22
OP14
OP6
D5
U27
OP61
OP53
OP45
OP37
OP29
OP21
OP13
OP5
D4
U26
OP60
OP52
OP44
OP36
OP28
OP20
OP12
OP4
D3
U25
OP59
OP51
OP43
OP35
OP27
OP19
OP11
OP3
D2
U24
OP58
OP50
OP42
OP34
OP26
OP18
OP10
OP2
D1
U23
OP57
OP49
OP41
OP33
OP25
OP17
OP9
OP1
D0
U22
OP56
OP48
OP40
OP32
OP24
OP16
OP8
OP0
Addr.
Base+14
Base+12
Base+10
Base+8
Base+6
Base+4
Base+2
Base+0
Basically, the drive capability of these devices is 250mA per output, continuous, with all outputs ON. If
less than 8 outputs are ON in any one package, or any outputs are operating with a small load, the
capacity of the other outputs increases. For example, at 25°C, the TPIC6259 can sink 400mA
continuously from 3 outputs. Please refer to the data sheet for the TPIC6259 (tpic6259.pdf) for
details.
When allocating any output to a load greater than 250mA, consideration should be given to the
loading on each device. See Section 6.1, “Driving Reels” for details on driving standard reel
mechanism stepper motors.
Note also that, because they are MOSFETs, the outputs are resistive (<2Ω) and do not suffer from the
minimum saturation voltage of about 1V which would be the case if they were darlingtons. Therefore,
at low currents, they pull down close to Gnd and may be safely used to drive TTL Inputs, Switch
Strobes, Coin Mechanism Enables, etc.
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5.10 AUX Outputs, AUX0-7
8 auxiliary TTL level open drain outputs are provided by U30 (see Schematic Sheet 9 - IO
Connectors). U30 is a TPIC6B259 which functions exactly the same as the TPIC6259 devices used to
drive OP0-63, but with a lower drive capability (see data sheet “tpic6b259.pdf”).
They are memory mapped as the least significant bit of a block of 8 bytes of address space at an
address determined by the FPGA fitted to the board. See the appropriate FPGA User Manual for
details.
They are open drain outputs fitted with 1K pull-up resistors to Vcc.
AUX0-5 are routed to connector P12 “AUX OUTPUTS”.
2
AUX6-7 are routed to Connector P13 “I C”.
5.11 Inputs, IP0-31
External inputs are catered for by 32 input lines, IP0-31 (see Schematic Sheet 7 - Inputs). Like the
Open Drain outputs these are memory mapped as the least significant byte of a block of 4 words of
address space.
Each input is provided with a 3K3 pull-up resistor to Vcc (+5V) and feeds into a 74HC family device
(rather than 74HCT). This give the inputs a low level threshold of <1.5V and a high threshold of
>3.5V. The 47K resistor in series with the input protects the 74HC253 devices from noise spikes or
high voltages on the inputs.
The 1.5V low threshold allows the inputs to be safely driven as a multiplexed array with a diode in
series with each switch with the strobes generated using a number of the Open Drain Outputs, OP063, described above.
The 32 inputs are mapped as shown in the following table. The top 4 bits of each word are read as
“1”s and bits 8 to 11 contain the DIL Switch Settings (as described in the next section). The base
address is defined by the FPGA.
Table 11. Mapping of Inputs IP0-31
D15-12
Base+6
D11-8
0xF
D7
IP31
D6
IP30
D5
IP29
D4
IP28
D3
IP27
D2
IP26
D1
IP25
D0
IP24
IP23
IP15
IP7
IP22
IP14
IP6
IP21
IP13
IP5
IP20
IP12
IP4
IP19
IP11
IP3
IP18
IP10
IP2
IP17
1P9
IP1
IP16
IP8
IP0
DIL
SW
Base+4
Base+2
Base
0xF
0xF
0xF
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5.12 DIL Switches
The Pluto 5 board is equipped with two 8 way DIL Switches, SW1 and SW2. These are read at the
same addresses as the 32 Inputs (see preceding Section).
Table 12. Mapping of DIL Switch Inputs
D15-D12
Base+6
Base+4
Base+2
Base
0xF
0xF
0xF
0xF
D11
SW2:8
SW2:6
SW2:4
SW2:2
D10
SW2:7
SW2:5
SW2:3
SW2:1
D9
SW1:8
SW1:6
SW1:4
SW1:2
D8
SW1:7
SW1:5
SW1:3
SW1:1
D7-D0
IP31-24
IP23-16
IP15-8
IP7-0
5.13 Software Controlled Indicator LED
LD2 is a green LED that may be turned on or off under software control (see Schematic Sheet 9 - IO
Connectors). The LED may be used to provide an indication that software is running or perhaps for
fault diagnosis.
The PORTA2 line from the MC68340 SIM40 Module drives the LED. After reset, the PORTA pins are
high impedance and pulled high by resistor network N11. This signal passes through the inverter U7F
which thus turns ON the LED. Therefore, initially and with no action on the part of the software, the
LED will be ON indicating that Vcc is present.
If the software sets PORTA2 pin as an output and drives it low, the LED will go OFF.
The PORTA pins are taken to the I/O Expansion Connector P14. Future I/O Expansion Cards may use
the PORTA2 pin for some other function, in which case this will have to be taken into consideration
when operating the indicator LED.
5.14 On-board Push Button
A Push Button Switch, SW3, is provided on the board (see Schematic Sheet 2 - CPU). The function of
this switch is at the discretion of the user of the board.
It is connected so as to pull the PORTA3 line from the MC68340 SIM40 Module to Gnd when
operated.
The PORTA pins are taken to the I/O Expansion Connector P14. Future I/O Expansion Cards may use
the PORTA3 pin for some other function, in which case the possible interaction with SW3 will have to
be taken into account.
5.15 Multiplexer
The Pluto 5 Controller board provides hardware assistance (within the FPGA) to the Processor
allowing two 32*16 Multiplex Arrays (referred to below as MPX1 and MPX2) to be controlled. From a
“logical” or software point of view, these arrays are uncommitted and may be configured to be either
Lamp or LED drives, depending on what interface components are fitted. When running the lamps
from a 48V supply, a 1 in 16 duty cycle is employed on the column strobes (sinks) allowing the full
capabilities of the two arrays, MPX1 and MPX2 to be utilised. If the multiplexed lamps are run from a
36V supply, a 1 in 8 duty cycle must be utilised and the useable size of the two arrays reduces to
32*8.
The Pluto 5 256/32 Controller Board is intended for customers who run with a 48V lamp supply and
require the maximum drive capability of the board. It has ½ of MPX1 configured as a 16*16 (256)
Lamp Drive Array and the other ½ configured as a 16*16 (32 seven-segment digits) LED Drive Array.
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The Pluto 5 128/16 Controller Board is intended for users who require less drive capability or who
wish to run the lamps at 36V. It has ¼ of MPX1 configured as a 16*8 (128) Lamp Drive Array and the
other ¼ configured as a 16*8 (16 seven-segment digits) LED Drive Array.
The other 32*16 Multiplex Array (MPX2) is utilised by adding external low-cost Pluto 5 Multiplex
Expansion Boards, wired to Connector P11. Each board only requires 5 signal wires from P11 plus
Power Supplies.
Pluto 5 Multiplex Expansion Boards will be available in a number of different sizes, but all based on
providing additional 8*8 blocks of either Lamp or LED drivers. Thus, the basic Pluto 5 configuration
may be expanded externally by another 8 blocks which may be any mix of Lamps or LEDs.
Pluto 5 Multiplex Expansion Boards may also be added to Multiplex Array MPX1 (which is already
used by the on-board drivers). Thus, for example, the Pluto 5 128/16 Controller Board, running at
48V, could have Expansion Boards added to increase its drive capability to that of the Pluto 5 256/32
Controller Board.
The Lamp Multiplex Drive Circuitry is designed to drive 12V, 100mA bulbs. However, it is permissible
for a small number (up to 16) of positions to drive either a higher power bulb (12V, 180ma) or a pair of
100mA bulbs. These "high load" positions should be arranged such that no more than one is on any
one Row or Column drive.
Multiplex Array MPX1 has hardware assistance from the FPGA to enable dimming control. Dimming
level may be set independently for each of the 16 Column strobes, e.g. the 8 lamps on one Column
Strobe could be set to one brightness level while the 8 lamps on a different Column Strobe could be
set to another brightness. The overall basic timing of the multiplexing remains under software control
allowing “overdrive” of lamps for special effects.
Multiplex Array MPX2 may be optionally configured with its full 32*16 capacity without the availability
of hardware assisted dimming, or with 16*16 capability with the hardware assisted dimming facility
intact. This option is selected by a bit in the FPGA – see the relevant FPGA User Manual for details.
Dimming is achieved changing the data presented to the Lamp Row/LED Segment drives at an
adjustable time within the 1mS strobe time. Thus each lamp/LED has two bits of data associated with
it in software – the first bit is the data applied during the first part of the 1mS Strobe period, the second
bit is applied during the second period. The duration of the period that the first bit is applied for may be
set in units of 1/16 mS.
The multiplex is software driven. Every 1mS, data for the next strobe is written to the FPGA which in
turn formats and serialises the data before clocking out the MPX1 data to the on-board 4094 shift
registers (U18,U19,U20,U21,U35,U36) and the MPX2 data, via P11, to any Multiplex Expansion
Boards used.
The exact format of the data to be written each millisecond is determined by the design of the FPGA
being used, but in general it is as follows.
•
•
•
•
•
•
32 bits of MPX1 Row/Segment data. First period data.
32 bits of MPX1 Row/Segment data. Second period data.
32 bits of MPX2 Row/Segment data. First period data.
32 bits of MPX2 Row/Segment data. Second period data.
4 bits defining Column/Digit strobe number to activate.
4 bits defining First Period duration (units of 62.5 S).
Consult the User Manual of the actual FPGA in use for exact details of operation.
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5.16 Multiplexed Lamp Current Sense
A facility is provided to allow the processor to check the 256/128 possible lamp positions of MPX1 to
determine:
a.
b.
Is a light bulb present?
Is there a short circuit in this position?
This facility is intended to be run at power up and, perhaps, as a production test. The facility cannot be
used during normal operation of the machine.
A resistance of approximately 24mΩ is implemented, as a copper track on the PCB, between common
source connection of all the Lamp Column/LED Digit sinks, Q35-50 and Gnd (see Schematic Sheet 11
- Lamp Column/LED Digit Drives). The voltage across this resistor is compared against 2 thresholds
formed by resistor chain R124, R125 and R126 by comparators U16C and U16D (see Schematic
Sheet 8 - Power Supply). These thresholds correspond to nominal currents of about 375mA and 4.8A.
The outputs of the 2 comparators, U16C and U16D are connected to processor lines PORTA6 and
PORTA7. The current sensing comparators may be disabled by SFX_CLK being enabled. When
SFX_CLK, a 640kHz clock, is enabled by setting a bit in the FPGA (see FPGA User Manual), the “+”
inputs of the 2 comparators are pulled up to about +5V by D21/C9/C10 which forces the comparator
outputs (which are open collector) OFF. In this state the lines PORTA6 and PORTA7 are free to be
used as outputs driving the S1 & S2 pins of SFX Channel #2 or as required by any card fitted to the
I/O Expansion Connector, P14. When the SFX-CLK is turned OFF (and forced low), any voltage on
C9/10 is discharged by R127, and the current sensing circuit is enabled.
With no current through the Column/Digit Sinks, both outputs PORTA6/7 will be LOW because V+ < Von the comparators. When the current through the 24mΩ resistor exceeds a nominal 375mA, PORTA6
will go high. When the current exceeds a nominal 4.8A, PORTA7 will also go high.
The sequence of operation to test a lamp is as follows:
•
•
•
•
•
•
•
•
•
•
•
Turn off SFX_CLK in FPGA to enable circuit.
Turn off all Row/Digit drives on MPX1.
Ensure PORTA6 and PORTA7 both read 0
Turn on lamp to be tested on multiplex by writing appropriate data to FPGA.
Start a 1mS timer.
Loop watching lines PORTA6 and PORTA7.
If PORTA7 line goes high, there is a short circuit in this position, so immediately disable the
multiplex drives by turning off Multiplex OE line in the FPGA.
If PORTA6 line goes high but not PORTA7, then there is a light bulb connected and apparently
working.
If 1mS timer times out without either line going high, then either no bulb present or it is open
circuit.
Record result and go on to next bulb.
When complete, act as required on results. Re-enable SFX-CLK to allow Sound Channels to work.
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5.17 Sound Generation
The sound generation circuits are shown on Schematic Sheet 5 - Sound.
U8 and (optionally) U39 are the source of Sound Channel 1 & 2 respectively with the audio output
being pin 10, Aout. These OKI MSM6585 devices are 4 bit ADPCM D-A converters capable of running
at sample rates of 4KHz, 8KHz, 16KHz or 32KHz. This rate is selected by software by setting levels on
the S1 and S2 pins. On Channel 1 (U8) these pins are controlled by the OP4 and OP6 lines from the
MC68340 Serial Module. On Channel 2 (U39) these pins are controlled by the PORTA6 and PORTA7
lines from the MC68340 SIM40 Module.
The VCK- output from the MSM6585 is a square wave at the sampling frequency selected by S1 and
S2. The MSM6585 reads the 4 bit sample immediately after the rising edge of VCK-.
The VCK- from the MSM6585 is connected to the FPGA where it is divided by 2 to produce a DMA
Request signal to the processor. Sound data is transferred, a byte at a time (1 byte = 2 * 4 bit sound
samples), to the appropriate register within the FPGA by the DMA Module if a sound is being played.
The FPGA in turn presents alternately the high and low nibble to the MSM6585 OKI chip.
The sound channel requests a byte of data (via the FPGA) at half the sound sample rate. E.g., if the
MSM6585 has been set to run at 16KHz sample rate, the FPGA will issue DMA requests at 8KHz.
These requests are issued continuously to the DMA Module, but in times of silence, the DMA
channels are inactive and therefore no new data is transferred into the FPGA sound register. In this
case, the user must ensure that the last data written to the FPGA sound register before a period of
silence is 0x80. This will ensure that, during a silent period, the MSM6585 is being continuously fed a
repeated sequence of alternate 0x8 and 0x0 nibbles. This keeps the ADPCM converter in its quiescent
state. If the sound data is generated using the Heber Sound Solutions software, the last byte of the
data is always 0x80, so this condition will automatically be satisfied.
Sound Channel 1 (U8) is fitted as standard and uses DMA Channel 1. Sound Channel 2 (U39) is
optional and uses DMA Channel 2.
The RESET pin of each channel is under individual software control. Pin PORTA0 drives SFX
Channel #1 RESET. Pin PORTA1 drives SFX Channel #2 RESET. After Power –Up, these pins will
default to being inputs and therefore the Resistor network N11 will pull them High, holding both Sound
Channels in a RESET state. Before the Sound Channels can be used, these two pins must be set as
outputs by the SIM40.
5.18 Stereo Amplifier and Volume Controls
The Stereo Amplifier is shown on Schematic Sheet 5 - Sound.
U32 is a Philips TDA7057AQ Stereo Audio Amplifier with independent DC volume controls. Note that
the loudspeaker outputs, on Connector P10, are bridge driven so neither of the loudspeaker wires may
be connected to Gnd.
The DC volume controls of the TDA7057 work over the range 0.4V(min) to 1.2V (Max). The variable
duty cycle outputs on pins TOUT1/2 from the two timers in the MC68340 Timer Module are integrated
by the combination of two 3K3 resistors and a 1µF capacitor (R108, R109, C45 on Channel 1: R110,
R113, C46 on Channel 2) to provide the control voltage needed. The control voltage is given by the
formula 2.5*{duty cycle} where “duty cycle” is the proportion of the time that the TOUT Pin is HIGH.
Normally, Sound Channel 1 (U8, DMA Channel 1) feeds Amplifier Section 1 (volume control - Timer
Channel 1) driving LS1. Sound Channel 2 (U39, DMA Channel 2) feeds Amplifier Section 2 (volume
control – Timer Channel 2) driving LS2.
A pin on the Loudspeaker Connector, P10, pin 3, which allows the output signal from Amplifier
Channel 1 to be fed back into the input of Amplifier Channel 2. This allows various alternative modes
Document No. 80-15151 Issue 6
HEBER LTD
Page 19
of operation, for example, if only Sound Channel 1 is fitted, then by linking the LS1+ output to the
feedback pin, the same signal can drive BOTH loudspeakers. See Section 6.9, “Making Sounds”
below for a more detailed explanation of the different operational modes that are possible.
5.19 Serial I/O
P1 provides connections to RS232 Channel A, Data Receive & Transmit plus RTS/CTS.
P2 provides connections to RS232 Channel B, Data Receive & Transmit plus RTS/CTS and is in the
format specified by the BACTA standard.
Operation of the above two ports is determined by the operation of the Serial Module in the MC68340
Processor. Refer to the Serial Module Section of Motorola MC68340 User Manual for a full
explanation.
5.20 Internal I2C Bus
2
An internal I C Bus is implemented using SIM40 Lines PORTA4 (SCL) and PORTA5 (SDA). This bus
allows the processor to read and write the optional Real Time Clock chip, U40, and the optional
2
E PROM, U37. If neither of these devices is fitted, then these 2 lines are also available on the I/O
Expansion Connector P14 and are free for other uses.
5.20.1 Real Time Clock
2
U40 is a position that accepts a Philips PCF8583 I C Real Time Clock. The standard Pluto 5 Controller
has a socket fitted in this position along with the 32.768KHz Crystal, X2. However, the PCF8583 IC is
NOT fitted as standard but is available as an optional extra or may be fitted by the user.
2
The I C Slave Address of the RTC is as follows:
2
Table 13. I C Slave Addresses for RTC, U40
READ:
WRITE:
0xA1
0xA0
5.20.2 E2PROM
2
U37 position is fitted with a socket that accepts an “Industry Standard” E PROM, 24C04 (512 bytes) or
24C08 (1024 bytes) with pin 7, which serves a different function on devices from different
manufacturers, connected to GND. The Pluto 5 Controller Boards, as standard, do not have an
2
E PROM fitted but they are available as an optional extra or may be fitted by the user.
We strongly recommend that, if a user supplies or fits his own devices, that only NM24C04 or
NM24C08 devices should be used (manufactured by Fairchild or National Semiconductor). Heber
cannot offer Technical Support for the use of devices from alternate manufacturers.
2
2
To avoid a clash of I C addressing between the PCF8583 RTC and the 24Cnn E PROM, A2 (Pin 3) of
2
the E PROM is strapped to Vcc and A0/A1 to GND and this socket is restricted to accepting devices
no larger than the 24C08. Note, however, that there is no such size restriction on the devices that may
2
be connected via P13, the External I C Bus Connector.
2
2
The I C Slave Address of each of the 256 byte “Page Blocks” in the E PROM, U37, is as follows:
2
2
Table 14. I C Slave Addresses for E PROM, U37
READ
WRITE
BLOCK 0
24C04 or 24C08
0xA9
0xA8
Document No. 80-15151 Issue 6
BLOCK 1
24C04 or 24C08
0xAB
0xAA
BLOCK 2
24C08 only
0xAD
0xAC
BLOCK 3
24C08 only
0xAF
0xAE
HEBER LTD
Page 20
6 MACHINE OPERATION
This section discusses how various standard amusement machine functions can be implemented.
6.1
Driving Reels
Up to six 12V Stepper Motor Reel Mechanisms may be connected to the “REEL” connector, P7. +12V
outputs are available for the motor common connection and GND/Vcc are available for the Opto
supply. A 6*6 subset of the Lamp Multiplex is configured so up to 6 lamps per reel may be
accommodated, in either “sinking” or “sourcing” mode (depending on the wiring of the Reel
Mechanism. 6 inputs, IP0-5, are provided for the Opto Inputs
When driving stepper motor reels, because the maximum (static) current load of each winding is
400mA (assuming 30Ω, 12V windings), it is important to connect the motors to distribute the load
evenly amongst the TPIC6259 driver chips.
The recommended method of connection is to wire the reel motors as follows:
Table 15. Recommended Reel Stepper Motor Drive Connections
REEL 1
REEL 2
REEL 3
REEL 4
REEL 5
REEL 6
OP0-3
OP4-7
OP8-11
OP12-15
OP16-19
OP20-23
This guarantees that a maximum of 3 motor windings are driven simultaneously by any one TPIC6259
device which is within the ratings of the device even under the worst case of a reel being stationary
and unchopped. Of course, when the motor is running or is being chopped the average current drops
significantly.
Extra reels could be connected via pins on the other connectors. Providing the software chops the
current to the reels when they are not spinning, an extra 2 reels can be wired to OP24-27 and
OP28-31 and should allow the TPIC6259s to remain within their ratings.
NB: The +12V outputs on P7 Pins 45-50 are fed directly from the +12V Input to the Pluto 5 Board on
P3, Pin 4. It does not go via Fuse F1 on the board.
6.2
Reading the DIL Switches
The state of the DIL Switches may be read at any time by reading the memory locations as described
in Section 5.12.
6.3
Reading the Switch Inputs
The 32 switch inputs may be read at any time by reading the memory locations as described in
Section 5.11 above.
In most applications, these inputs should be debounced in software. A typical debounce algorithm
might be to read the switches every 1mS, but only register a change of state on the input after it has
been stable for 3 consecutive readings.
It is possible to implement, say, a 256 multiplexed switch input array by using, 8 of the Open Drain
Outputs OP0-63 as strobes and 8 of the Inputs IP0-31. In this case, a diode would need to be
connected in series with each switch.
Document No. 80-15151 Issue 6
HEBER LTD
Page 21
6.4
Interfacing to Coin & Note Acceptors
Most Coin or Note Acceptors have open collector (“sink to ground”) outputs. These may be connected
directly to any of the Pluto 5 Inputs (IP0-31). Mechanism “Enable” or “Control” inputs may usually be
driven directly from any of the Pluto 5 Open Drain Output lines (OP0-63).
6.5
Interfacing to Coin Payout Mechanisms
Payout Hoppers that require relatively low drive currents, e.g. Coin Controls Universal Hopper, may be
driven directly from an Open Drain Output. Higher current devices, such as 50Vac or 24Vdc Payout
Solenoids, should be driven using Open Drain Outputs via a suitable Triac or Relay Interface Card.
Heber produces a number of suitable interfaces.
6.6
Driving Vacuum Fluorescent Displays (VFD)
The standard VFD/Linewriter display used in most Gaming/Amusement Machines is driven by 3 TTL
level signals, Clock, Data and Reset.
Connector P12 has 6 TTL level outputs which could drive up to 2 display modules.
The mapping of these outputs as the LSB of 6 bytes makes it convenient for the software to implement
the bitwise drive required.
6.7
Using the External I2C Bus
2
Connector P13 is intended for driving external boards containing I C Bus components. A common use
2
for this could be the provision of a removable E PROM Module for use in Spain or any other country
with a similar requirement.
2
Heber have available a small PCB containing a NM24C04 or NM24C08 E PROM that plugs directly on
to P13.
On this connector, the SDA line is driven by the Open Drain Output, AUX7 and may be read by the
68340 Timer Module as the (inverted) TGATE2- signal.
Similarly, the SCL line is driven by AUX6 and read by TGATE1.
6.8
Driving Meters
Electromechanical Meters or Counters should be 12V DC parts. The common +12V supply to them
should be the Vmeter+ supply from Connector P9 (“I/O 2”), pin B17 and each should be driven by an
Open Drain Output (OP0-63).
As the meter is pulsed ON, the software should check that the Vmeter Current Sense Input has
operated, i.e. that pin PORTB4 has gone high.
Because of possible delays in responding to a meter being turned on it is recommended that the
software checks the current sense pin immediately before the meter is turned OFF at the end of a
pulse. To detect tampering or a failure of the current sense circuitry, the software should also check
that the current sense pin goes LOW when no meter is operated.
6.9
Making Sounds
Loudspeaker outputs on connector P10 are bridge driven, so do NOT connect either connection of a
loudspeaker to ground or to any other loudspeaker drive. Ideally 8Ω loudspeaker(s) should be used,
but higher impedance components could be used without any risk of damage to the amplifier. The use
of 3 or 4ohm loudspeakers should be avoided.
Document No. 80-15151 Issue 6
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Page 22
It is possible to run the sound in the following modes:
6.9.1
Single Channel/Single Speaker (Mono) Mode
This is the lowest cost option, using the standard Pluto 5 Board with a single loudspeaker.
The optional SFX Channel 2, U39, is not fitted and only SFX Channel 1, U8, is operational. A single
loudspeaker is connected to LS1 pins (1 & 2) only. Pins 3,4,5 should be left open.
6.9.2
Dual Channel/Dual Speaker (Stereo) Mode
In Stereo Mode, the optional second channel IC U39 is fitted and 2 loudspeakers are used, connected
to LS1 and LS2 pins. Pin 3 is left open. Channel 1 Volume Control will adjust the level of LS1, Channel
2 Volume Control will adjust the level of LS2.
In this mode true stereo sound effects may be reproduced, although the subjective effect heard by the
player will depend upon the placement of the loudspeakers in the cabinet.
6.9.3
Known DMA Problems
The “E” version of the Motorola 68340 mask that is current at the time of this manual being written
(MC68340PV16E, Mask # 2G67F) exhibits a DMA fault which can cause audible disturbances on a
sound effect.
This disturbance occurs when the memory area being transferred to the SFX Register in the FPGA
includes the hexadecimal address range xxx3 FFxx. (x meaning any hexadecimal digit).
Thus, to avoid this problem occurring, precautions should be taken when linking sound effect modules
Into the final EPROM map. We suggest that, programme and EPROM size permitting, the area from
hex 0000 0000 to 0003 FFFF (256Kbytes) be reserved for the executable portion of the code, with
sound effects commencing at hex address 0004 0000. If the total EPROM size exceeds 1Mbyte, then
no sound effect should include data in the range 0013 FF00 to 0013 FFFF. Similarly, with larger
EPROM maps, regions at 0023 FFxx, 0033 FFxx, etc should also be avoided.
There is NO problem with code execution in these areas, the only difficulty occurs when a Sound DMA
transfer passes through these regions.
We believe that these problems are reduced or eliminated when the Function Code Register (FCR)
in the DMA Module is initialised to value 0xDD.
6.10 Using Multiplexed Lamps
On all Multiplex lamp outputs, the Column Drives, LC0-15, SINK current to ground and the Row
Drives, LR0-15, SOURCE current from the Lamp Supply (+36V or +48V). Thus, any lamps should be
connected between a Row and a Column drive with their series diodes orientated with the cathode
towards the Column Drive.
The choice of operation at 36V or 48V is determined by the Power Supply and the software. When
running at 48V, the software will sequentially drive all 16 Columns, LC0-15, on a 1/16 duty cycle, each
column being ON for 1mS and OFF for 15.
When running at 36V, the software will sequentially drive only the first 8 Columns (LC0-7) on a 1/8
duty cycle, each column being ON for 1mS and OFF for 7.
The Lamp Multiplex Drive Circuitry is designed to drive 12V, 100mA bulbs. However, it is permissible
for a small number (up to 16) of positions to drive either a higher power bulb (12V, 180ma) or a pair of
100mA bulbs. These "high load" positions should be arranged such that no more than one is on any
one Row or Column drive.
6.11 Using Multiplexed LEDs
The multiplexed LED drive circuit is intended to be used with Common Cathode digits, either 7
segment plus decimal point or 14 segment. The common cathode connection of each digit should be
Document No. 80-15151 Issue 6
HEBER LTD
Page 23
connected to a digit drive output, DIG0-15, on connector P5. Each digit drive output can drive two 7
Segment Digits, the segment anodes for one connecting to drive SEG0-7 and the other to SEG8-15.
By convention, segment “a” would connect to SEG0 or SEG8.
Alternatively, 14 segment starburst digits can be used, in which case each digit output would drive one
digit and the 14 segment anodes should each be connected to one of the segment drive lines, SEG013.
The LED Digit drive circuitry shares the same Current Sink transistors as the Lamp Column drives.
Thus, if the system is being driven in a 1/8 duty cycle to allow a 36V Lamp Supply, only Digit drive
lines DIG0-7 are active (or the board is a Pluto 5 128/16). In this case only 16 Seven Segment LED
digits may be driven from the controller.
6.12 Using the Multiplex Expansion Connector
The outputs on P11 are all CMOS signals swinging between GND and +12V. These signals may be
connected to Pluto 5 Multiplex Expansion Boards to increase the Lamp and/or LED drive capability of
the system.
See the PLUTO 5 MULTIPLEX EXPANSION BOARD USER MANUAL for details of connection and
operation.
6.13 Adding Video Capabilities
A Calypso 16 Video Card is available from Heber Ltd. which plugs directly onto the Pluto 5 board via
the 2 DIN41612 connectors P14 and P15.
See the CALYPSO 16 USER MANUAL for details.
The Calypso 16 Video Card supersedes the Pluto 5 CGA/VGA Video Card. For further information on
the Pluto 5 CGA/VGA Video Card refer to the PLUTO 5 CGA/VGA BOARD USER MANUAL.
Document No. 80-15151 Issue 6
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Page 24
7
SOFTWARE DEVELOPMENT
A number of options exist for the development and debug of software for use on Pluto 5.
Software will normally be generated using a Cross Assembler, Cross Compiler and Linker package. A
suitable package is included with the Pluto 5 Development Kit.
When software has been successfully compiled, assembled and linked, it may be tested and
debugged using the Background Debug Mode facility built in to the 68340 Processor.
For full details of debugging, refer to the PLUTO 5 DEVELOPMENT KIT QUICK START GUIDE and
other documentation supplied with the Development Kit.
Document No. 80-15151 Issue 6
HEBER LTD
Page 25
8 CONNECTOR TYPES AND PIN OUTS
8.1
Schedule of Connector Types
There are two types of Pluto 5 Board with either Ultrex or Box Header connectors, and 3 other families
of connectors:
•
•
Pluto 5 with Ultrex connectors is referred to as Pluto 5U
Pluto 5 with Box Header connectors is referred to as Pluto 5B
Pluto 5U uses the following 4 different families of connectors for connection to the cableform in the
machine:
•
•
•
•
AMPMTA-100. 2.54mm single in-line headers with friction lock and polarisation.
AMP MTA-156. 3.96mm single in-line headers with friction lock and polarisation.
AMP Ultrex. 2.54mm dual row headers.
25 way “D” Type
Pluto 5B uses the following 4 different families of connectors for connection to the cableform in the
machine:
•
•
•
•
AMPMTA-100. 2.54mm single in-line headers with friction lock and polarisation.
AMP MTA-156. 3.96mm single in-line headers with friction lock and polarisation.
Tyco Box Header 2.54mm dual row headers
25 way “D” Type
The actual part numbers of the board headers fitted to the Pluto 5 PCBs along with the part numbers
of suitable mating (cableform) parts are given in the following tables:
Table 16. AMP Ultrex Connector Part Numbers
Ident
P5
P7
P8
P9
Description
32W
50W
40W
34W
Ultrex
Ultrex
Ultrex
Ultrex
PCB Header
AMP Part No.
3-172870-2
5-172870-0
4-172870-0
3-172870-4
AMP IDC Connector Part Number
28-24 AWG Wire
3-172866-2
5-172866-0
4-172866-0
3-172866-4
Table 17. Tyco Box Header Connector Part Numbers
Ident
P5
P7
P8
P9
Description
34W
50W
40W
34W
Box Header
Box Header
Box Header
Box Header
Document No. 80-15151 Issue 6
PCB Header
Tyco Part No.
7-1437061-5
9-1437061-5
8-1437061-5
7-1437061-5
Tyco IDC Connector Part Number
28-24 AWG Wire
102387-8
102387-0
102387-9
102387-8
HEBER LTD
Page 26
Table 18. AMP MTA-100 Connector Part Numbers
Ident
P1
P4
P6
P10
P11
P12
P13
Description
PCB Header
AMP Part No.
6W MTA-100
18W MTA-100
16W MTA-100
5W MTA-100
7W MTA-100
8W MTA-100
4W MTA-100
AMP IDC Connector Part Number
2
2
24 AWG (0.22mm )
(Colour Natural)
22 AWG Wire(0.35mm )
(Colour Red)
640621-6
1-640621-8
1-640621-6
640621-5
640621-7
640621-8
640621-4
640620-6
1-640620-8
1-640620-6
640620-5
640620-7
640620-8
640620-4
640456-6
1-640456-8
1-640456-6
640456-5
640456-7
640456-8
640456-4
Table 19. AMP MTA-156 Connector Part Numbers
Ident
P3
Description
PCB Header
AMP Part No.
6W MTA-156
640388-6
AMP IDC Connector Part Number
2
2
24 AWG (0.22mm )
(Colour Natural)
20 AWG Wire(0.5mm )
(Colour Yellow)
640429-6
640427-6
The above MTA-100 and MTA-156 IDC Connector Part Numbers are for illustration and are of the
“Feed-Through Receptacle without Polarising Tabs” type. A number of alternatives exist that could
also be used, for example “Closed-End” types. Please consult the relevant AMP information for an
exhaustive list. If you have Internet Access, the information is also available on the AMP Web Site at
http://www.amp.com/.
Strain relief covers are also available.
8.2
P1 – RS232 Channel A
Reference:
Type:
Description:
P1
Header 6W AMP MTA-100
RS232 Channel A
1
2
3
4
5
6
Document No. 80-15151 Issue 6
GND
RXA
TXA
CTSA
RTSA
+12V
Input to Pluto 5
Output from Pluto 5
Input to Pluto 5
Output from Pluto 5
HEBER LTD
Page 27
8.3
P2 – Dataport (RS232 Channel B)
Reference:
Type:
Description:
8.4
P2
25W ‘D’ Socket
BACTA Dataport / RS232 Channel B
nc
1
RXB (Input to Pluto 5)
2
TXB (Output from Pluto 5)
3
CTSB (Input to Pluto5)
4
RTSB (Output from Pluto 5)
5
nc
6
GND
7
nc
8
nc
9
nc
10
-12V
11
nc
12
nc
13
14
nc
15
nc
16
nc
17
nc
18
GND
19
nc
20
nc
21
nc
22
nc
23
nc
24
nc
25
+12V
P3 – Power Input
Reference:
Type:
Description:
P3
Header 6W AMP MTA-156
Power
1
2
3
4
5
6
-12V
GND
GND
+12V
GND
Vmpx+
Document No. 80-15151 Issue 6
Neg supply for RS232 buffers
Ground
Ground
Main supply
Ground
Lamp MPX supply, +36V or +48V
HEBER LTD
Page 28
8.5
P4 – Multiplexed Lamp Sinks
Reference:
Type:
Description:
P4
Header 18W AMP MTA-100
Lamp Columns/Sinks
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
LC0
LC1
LC2
LC3
LC4
LC5
LC6
LC7
LC8*
LC9*
LC10*
LC11*
LC12*
LC13*
LC14*
LC15*
nc
nc
Lamp Column/Sink 0
Lamp Column/Sink 1
Lamp Column/Sink 2
Lamp Column/Sink 3
Lamp Column/Sink 4
Lamp Column/Sink 5
Lamp Column/Sink 6
Lamp Column/Sink 7
Lamp Column/Sink 8 (PLUTO 5 256/32 only)
Lamp Column/Sink 9 (PLUTO 5 256/32 only)
Lamp Column/Sink 10 (PLUTO 5 256/32 only)
Lamp Column/Sink 11 (PLUTO 5 256/32 only)
Lamp Column/Sink 12 (PLUTO 5 256/32 only)
Lamp Column/Sink 13 (PLUTO 5 256/32 only)
Lamp Column/Sink 14 (PLUTO 5 256/32 only)
Lamp Column/Sink 15 (PLUTO 5 256/32 only)
No Connection
No Connection
* Column Sinks LC8-15 are omitted on Pluto 5 128/16
8.6
P5 Ultrex – Multiplexed LEDs
Reference:
Type:
Description:
P5
Header 32W AMP Ultrex
LED - Drive for 16 or 32 seven-segment LED Digits.
Cathodes, Digit 0
Cathodes, Digit 2
Cathodes, Digit 4
Cathodes, Digit 6
Cathodes, Digit 8
Cathodes, Digit 10
Cathodes, Digit 12
Cathodes, Digit 14
Anodes, Segment 0
Anodes, Segment 2
Anodes, Segment 4
Anodes, Segment 6
Anodes, Segment 8
Anodes, Segment 10
Anodes, Segment 12
Anodes, Segment 14
DIG0
DIG2
DIG4
DIG6
DIG8
DIG10
DIG12
DIG14
SEG0
SEG2
SEG4
SEG6
SEG8*
SEG10*
SEG12*
SEG14*
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
DIG1
DIG3
DIG5
DIG7
DIG9
DIG11
DIG13
DIG15
SEG1
SEG3
SEG5
SEG7
SEG9*
SEG11*
SEG13*
SEG15*
Cathodes, Digit 1
Cathodes, Digit 3
Cathodes, Digit 5
Cathodes, Digit 7
Cathodes, Digit 9
Cathodes, Digit 11
Cathodes, Digit 13
Cathodes, Digit 15
Anodes, Segment 1
Anodes, Segment 3
Anodes, Segment 5
Anodes, Segment 7
Anodes, Segment 9
Anodes, Segment 11
Anodes, Segment 13
Anodes, Segment 15
* Common Cathode Drives DIG8-15 are omitted on Pluto 5 128/16
Document No. 80-15151 Issue 6
HEBER LTD
Page 29
8.7
P5 Box Header – Multiplexed LEDs
Reference:
Type:
Description:
P5
Header 34W Tyco Box Header
LED - Drive for 16 or 32 seven-segment LED Digits.
Not Used
Cathodes, Digit 0
Cathodes, Digit 2
Cathodes, Digit 4
Cathodes, Digit 6
Cathodes, Digit 8
Cathodes, Digit 10
Cathodes, Digit 12
Cathodes, Digit 14
Anodes, Segment 0
Anodes, Segment 2
Anodes, Segment 4
Anodes, Segment 6
Anodes, Segment 8
Anodes, Segment 10
Anodes, Segment 12
Anodes, Segment 14
DIG0
DIG2
DIG4
DIG6
DIG8
DIG10
DIG12
DIG14
SEG0
SEG2
SEG4
SEG6
SEG8*
SEG10*
SEG12*
SEG14*
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
Not Used
DIG1
DIG3
DIG5
DIG7
DIG9
DIG11
DIG13
DIG15
SEG1
SEG3
SEG5
SEG7
SEG9*
SEG11*
SEG13*
SEG15*
Cathodes, Digit 1
Cathodes, Digit 3
Cathodes, Digit 5
Cathodes, Digit 7
Cathodes, Digit 9
Cathodes, Digit 11
Cathodes, Digit 13
Cathodes, Digit 15
Anodes, Segment 1
Anodes, Segment 3
Anodes, Segment 5
Anodes, Segment 7
Anodes, Segment 9
Anodes, Segment 11
Anodes, Segment 13
Anodes, Segment 15
* Common Cathode Drives DIG8-15 are omitted on Pluto 5 128/16
8.8
P6 – Multiplexed Lamps Sources
Reference:
Type:
Description:
P6
Header 16W AMP MTA-100
Lamp Rows/Sources
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Document No. 80-15151 Issue 6
LR0
LR1
LR2
LR3
LR4
LR5
LR6
LR7
LR8
LR9
LR10
LR11
LR12
LR13
LR14
LR15
Lamp Row/Source 0
Lamp Row/Source 1
Lamp Row/Source 2
Lamp Row/Source 3
Lamp Row/Source 4
Lamp Row/Source 5
Lamp Row/Source 6
Lamp Row/Source 7
Lamp Row/Source 8
Lamp Row/Source 9
Lamp Row/Source 10
Lamp Row/Source 11
Lamp Row/Source 12
Lamp Row/Source 13
Lamp Row/Source 14
Lamp Row/Source 15
HEBER LTD
Page 30
8.9
P7 Ultrex – Reels
Reference:
Type:
Description:
P7
Header 50W AMP Ultrex
Reels - Connector for 6 Stepper Motor Reel Mechanisms
Lamp Column 0
Lamp Column 2
Lamp Column 4
Lamp Row 0
Lamp Row 2
Lamp Row 4
Open Drain Output 0
Open Drain Output 2
Open Drain Output 4
Open Drain Output 6
Open Drain Output 8
Open Drain Output 10
Open Drain Output 12
Open Drain Output 14
Open Drain Output 16
Open Drain Output 18
Open Drain Output 20
Open Drain Output 22
Input 0
Input 2
Input 4
Document No. 80-15151 Issue 6
LC0
LC2
LC4
LR0
LR2
LR4
GND
OP0
OP2
OP4
OP6
OP8
OP10
OP12
OP14
OP16
OP18
OP20
OP22
IP0
IP2
IP4
+12V
+12V
+12V
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
LC1
LC3
LC5
LR1
LR3
LR5
VCC
OP1
OP3
OP5
OP7
OP9
OP11
OP13
OP15
OP17
OP19
OP21
OP23
IP1
IP3
IP5
+12V
+12V
+12V
Lamp Column 1
Lamp Column 3
Lamp Column 5
Lamp Row 1
Lamp Row 3
Lamp Row 5
Open Drain Output 1
Open Drain Output 3
Open Drain Output 5
Open Drain Output 7
Open Drain Output 9
Open Drain Output 11
Open Drain Output 13
Open Drain Output 15
Open Drain Output 17
Open Drain Output 19
Open Drain Output 21
Open Drain Output 23
Input 1
Input 3
Input 5
HEBER LTD
Page 31
8.10 P7 Box Header – Reels
Reference:
Type:
Description:
P7
Header 50W Box Header
Reels - Connector for 6 Stepper Motor Reel Mechanisms
Lamp Column 0
Lamp Column 2
Lamp Column 4
Lamp Row 0
Lamp Row 2
Lamp Row 4
Open Drain Output 0
Open Drain Output 2
Open Drain Output 4
Open Drain Output 6
Open Drain Output 8
Open Drain Output 10
Open Drain Output 12
Open Drain Output 14
Open Drain Output 16
Open Drain Output 18
Open Drain Output 20
Open Drain Output 22
Input 0
Input 2
Input 4
Document No. 80-15151 Issue 6
LC0
LC2
LC4
LR0
LR2
LR4
GND
OP0
OP2
OP4
OP6
OP8
OP10
OP12
OP14
OP16
OP18
OP20
OP22
IP0
IP2
IP4
+12V
+12V
+12V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
LC1
LC3
LC5
LR1
LR3
LR5
VCC
OP1
OP3
OP5
OP7
OP9
OP11
OP13
OP15
OP17
OP19
OP21
OP23
IP1
IP3
IP5
+12V
+12V
+12V
Lamp Column 1
Lamp Column 3
Lamp Column 5
Lamp Row 1
Lamp Row 3
Lamp Row 5
Open Drain Output 1
Open Drain Output 3
Open Drain Output 5
Open Drain Output 7
Open Drain Output 9
Open Drain Output 11
Open Drain Output 13
Open Drain Output 15
Open Drain Output 17
Open Drain Output 19
Open Drain Output 21
Open Drain Output 23
Input 1
Input 3
Input 5
HEBER LTD
Page 32
8.11 P8 Ultrex – General I/O #1
Reference:
Type:
Description:
P8
Header 40W AMP Ultrex
General Purpose I/O #1
Open Drain Output 24
Open Drain Output 26
Open Drain Output 28
Open Drain Output 30
Open Drain Output 32
Open Drain Output 34
Open Drain Output 36
Open Drain Output 38
Open Drain Output 40
Open Drain Output 42
Open Drain Output 44
Open Drain Output 46
Input 20
Input 22
Input 24
Input 26
Input 28
Input 30
Document No. 80-15151 Issue 6
OP24
OP26
OP28
OP30
OP32
OP34
OP36
OP38
OP40
OP42
OP44
OP46
GND
IP20
IP22
IP24
IP26
IP28
IP30
+12V
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
OP25
OP27
OP29
OP31
OP33
OP35
OP37
OP39
OP41
OP43
OP45
OP47
GND
IP21
IP23
IP25
IP27
IP29
IP31
+12V
Open Drain Output 25
Open Drain Output 27
Open Drain Output 29
Open Drain Output 31
Open Drain Output 33
Open Drain Output 35
Open Drain Output 37
Open Drain Output 39
Open Drain Output 41
Open Drain Output 43
Open Drain Output 45
Open Drain Output 47
Input 21
Input 23
Input 25
Input 27
Input 29
Input 31
HEBER LTD
Page 33
8.12 P8 Box Header – General I/O #1
Reference:
Type:
Description:
P8
Header 40W Box Header
General Purpose I/O #1
Open Drain Output 24
Open Drain Output 26
Open Drain Output 28
Open Drain Output 30
Open Drain Output 32
Open Drain Output 34
Open Drain Output 36
Open Drain Output 38
Open Drain Output 40
Open Drain Output 42
Open Drain Output 44
Open Drain Output 46
Input 20
Input 22
Input 24
Input 26
Input 28
Input 30
Document No. 80-15151 Issue 6
OP24
OP26
OP28
OP30
OP32
OP34
OP36
OP38
OP40
OP42
OP44
OP46
GND
IP20
IP22
IP24
IP26
IP28
IP30
+12V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
OP25
OP27
OP29
OP31
OP33
OP35
OP37
OP39
OP41
OP43
OP45
OP47
GND
IP21
IP23
IP25
IP27
IP29
IP31
+12V
Open Drain Output 25
Open Drain Output 27
Open Drain Output 29
Open Drain Output 31
Open Drain Output 33
Open Drain Output 35
Open Drain Output 37
Open Drain Output 39
Open Drain Output 41
Open Drain Output 43
Open Drain Output 45
Open Drain Output 47
Input 21
Input 23
Input 25
Input 27
Input 29
Input 31
HEBER LTD
Page 34
8.13 P9 Ultrex – General I/O #2
Reference:
Type:
Description:
P9
Header 34W AMP Ultrex
General Purpose I/O #2
Open drain Output 48
Open drain Output 50
Open drain Output 52
Open drain Output 54
Open drain Output 56
Open drain Output 58
Open drain Output 60
Open drain Output 62
Input 6
Input 8
Input 10
Input 12
Input 14
Input 16
Input 18
OP48
OP50
OP52
OP54
OP56
OP58
OP60
OP62
GND
IP6
IP8
IP10
IP12
IP14
IP16
IP18
+12V
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
OP49
OP51
OP53
OP55
OP57
OP59
OP61
OP63
GND
IP7
IP9
IP11
IP13
IP15
IP17
IP19
Vmeter
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
OP49
OP51
OP53
OP55
OP57
OP59
OP61
OP63
GND
IP7
IP9
IP11
IP13
IP15
IP17
IP19
Vmeter
Open drain Output 49
Open drain Output 51
Open drain Output 53
Open drain Output 55
Open drain Output 57
Open drain Output 59
Open drain Output 61
Open drain Output 63
Input 7
Input 9
Input 11
Input 13
Input 15
Input 17
Input 19
Current Sensing +12V
8.14 P9 Box Header – General I/O #2
Reference:
Type:
Description:
P9
Header 34W Box Header
General Purpose I/O #2
Open drain Output 48
Open drain Output 50
Open drain Output 52
Open drain Output 54
Open drain Output 56
Open drain Output 58
Open drain Output 60
Open drain Output 62
Input 6
Input 8
Input 10
Input 12
Input 14
Input 16
Input 18
Document No. 80-15151 Issue 6
OP48
OP50
OP52
OP54
OP56
OP58
OP60
OP62
GND
IP6
IP8
IP10
IP12
IP14
IP16
IP18
+12V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
Open drain Output 49
Open drain Output 51
Open drain Output 53
Open drain Output 55
Open drain Output 57
Open drain Output 59
Open drain Output 61
Open drain Output 63
Input 7
Input 9
Input 11
Input 13
Input 15
Input 17
Input 19
Current Sensing +12V
HEBER LTD
Page 35
8.15 P10 – Loudspeakers
Reference:
Type:
Description:
P10
Header 5W AMP MTA-100
Loudspeakers
1
2
3
4
5
LS1+
LS1MIX
LS2+
LS2-
Loudspeaker, Channel 1
Loudspeaker, Channel 1
Channel 2 mixer input
Loudspeaker, Channel 2
Loudspeaker, Channel 2
WARNING: Loudspeaker outputs are bridge driven and must NOT be connected ground.
8.16 P11 – Multiplex Expansion
Reference:
Type:
Description:
P11
Header 7W AMP MTA-100
Multiplex Expansion
1
2
3
4
5
6
7
MPX1_DATA_A
MPX2_DATA_A
MPX_STR_A
MPX_STR_B
MPX_CLK
MPX_STR
MPX_OE
12V CMOS Output
12V CMOS Output
12V CMOS Output
12V CMOS Output
12V CMOS Output
12V CMOS Output
12V CMOS Output
8.17 P12 – Aux Outputs
Reference:
Type:
Description:
P12
Header 8W AMP MTA-100
Aux. Outputs
1
2
3
4
5
6
7
8
GND
AUX0
AUX1
AUX2
AUX3
AUX4
AUX5
+12V
Document No. 80-15151 Issue 6
Open drain output, 150mA, 1K pull-up to +5V
Open drain output, 150mA, 1K pull-up to +5V
Open drain output, 150mA, 1K pull-up to +5V
Open drain output, 150mA, 1K pull-up to +5V
Open drain output, 150mA, 1K pull-up to +5V
Open drain output, 150mA, 1K pull-up to +5V
HEBER LTD
Page 36
8.18 P13 – External I2C Bus
Reference:
Type:
Description:
P13
Header 4W AMP MTA-100
2
External I C Bus
1
2
3
4
GND
AUX7/SDA
AUX6/SCL
+5V
I2C SDA line, TTL Open Collector I/O, 1K Pull-up
I2C SCL line, TTL Open Collector I/O, 1K Pull-up
8.19 P14 – IO Expansion Card Connector
Reference:
Type:
Description:
P14
DIN41612, C/2 Vertical Plug
Connector for IO Expansion Boards
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
c
D8
D9
D10
D11
D12
D13
D14
D15
RXDA- (TTL)
TXDA- (TTL)
CTSA- (TTL)
RTSA- (TTL)
A0
A1
A2
A3
Document No. 80-15151 Issue 6
b
PORTA0
PORTA1
PORTA2
PORTA3
PORTA4
PORTA5
A22
ASDSR/WDSACK0DSACK1SIZ0
SIZ1
PB5
PB6
a
HALTCLKOUT
CS3RESETBERRA20
A23
A4
A5
A6
A7
+12V
VCC
VCC
GND
GND
HEBER LTD
Page 37
8.20 P15 – Memory Expansion Card Connector
Reference:
Type:
Description:
P15
DIN41612, C/2 Socket Vertical
Connector for Memory Expansion Boards
a
A4
VCC
VCC
A3
A2
A1
GND
GND
FPGA0
FPGA1
FPGA2
FPGA3
FPGA4
FPGA5
FPGA6
D0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
b
A5
A7
A9
A11
A13
A15
A17
A19
A21
D14
D12
D10
D8
D6
D1
D2
c
A6
A8
A10
A12
A14
A16
A18
A20*
D15
D13
D11
D9
D7
D5
D3
D4
* NB. - Pin c8, “A20” is in fact the connection to Pin 1 (ROM_P1) of the 2 on-board EPROMs, U1 &
U2, and is driven by the FPGA.
For all memory accesses, excluding those to the ROM/EPROM area mapped by CS0-, the FPGA
routes A20 to this pin.
For all memory accesses to the ROM/EPROM area mapped by CS0-, the FPGA routes either Vcc,
A19 or A20 to this pin, depending on the memory mode set in the FPGA.
See Section 5.6, “EPROM Sockets / EPROM Autoselect Feature” for details of operation.
8.21 P16 – Background Debug Mode Connector
Reference:
Type:
Description:
P16
10W Low Profile Header
Background Debug Mode Connector
Only fitted to Software Development Boards
DSGND
GND
RESETVCC
Document No. 80-15151 Issue 6
1
3
5
7
9
2
4
6
8
10
BERRBKPT
FREEZE
IFETCH
IPIPE
HEBER LTD
Page 38
Figure 1 - Schematic Sheet 1 - Root Sheet
SHT 6 - OPEN DRA IN OUTPUTS
RESETCS_OPD[0..15]
SHT 8 - +5V /CURRENT SENSE
A[0..23]
SHT 9 - CONNECTORS
RESETCS_OPOP[0..63]
D[0..15]
OP[0..63]
A [0..23]
IP[0..31]
15084_6
METER_SENSE
V REF
NMIMPX_REF2
MPX_REF1
PORTA [0..7]
SFX_CLK
SHT 2 - MC68340 CPU
R/WSIZ0
DSA CK0EXTA L
3.68MHZ
CS0CS1CS2CS3CLKOUT
DREQ1DREQ2-
D[0..15]
DSA CK1SIZ1
A [0..2 3]
METER_SENSE
NMI-
R/WSIZ0
DSACK0 EXTA L
3.68MHZ
CS0CS1CS2CS3CLKOUT
DREQ1DREQ2-
RESET
D[0 ..15]
HA LTBERR-
POP4
POP6
TOUT1
TOUT2
PORTA[0..7]
R/WSIZ0
DSACK0 EXTA L
3.68MHZ
CS0CS1CS2CS3CLKOUT
DREQ1DREQ2RESET
CS_OPCS_IPCS_TTLRA M_WLRA M_WURAM_OEROM_P12
ROM_OEROM_P1
CS_OPCS_IPCS_TTL-
FPGA[0..6]
SFX2_VCK
MPX_CLK
MPX_STR
MPX_OE
MPX1_DA TA_A
MPX2_DA TA_A
MPX_STR_DA TA_A
SFX2_D[0..3]
SFX1_D[0..3]
SFX1_VCK
SFX_CLK
SFX_CLK
SFX1_VCK
PORTA[0..7]
A SDSFC3
TGATE1TGATE2-
RAM_CSRAM_WLRAM_WURAM_OEROM_P12
ROM_OEROM_P1
SFX1_D[0..3]
SFX2_D[0..3]
SFX2_VCK
A[0..23]
D[0 ..15]
A [0..23]
CTSA RTSA CTSBRTSBRXDA
TXDA
RXDB
TXDB
RESETPB0
V REF
RAM_CSRESET
CS3CLKOUT
RXDA
TXDA
CTSA RTSA -
D[0..15]
RESET-
FPGA [0..6]
RESET-
FPGA [0..6]
SHT 13 - LED SEG DRIVES
MPX_CLK
MPX_STR
MPX_OE
MPX1_DA TA_A
MPX_STR_DA TA_A
MPX2_DA TA_A
SFX_CLK
SFX1_V CK
SFX1_D[0..3]
SFX2_D[0..3]
SFX2_V CK
CLK_12V
STR_12V
OE_12V
MPX1_A_12V
D[0 ..15]
A [0..2 3]
PORTA [0..7]
V REF
TGA TE1TGA TE2-
MPX1_C_12V
TGA TE1TGA TE2-
MPX1_B_12V
STR_A _12V
SEG[0..1 5]
SEG[0..15]
15084_D
CLK_12V
STR_12V
OE_12V
SEG[0..1 5]
STR_A _12V
LC[0..15]
MPX_REF1
MPX_REF2
RAM_CSRESET
D[0..15]
A[0..23]
PORTA [0..7]
MPX1_D_12V
SHT 11 - COL/DIG SINKS
PB5
PB6
PB5
PB6
BERRHA LT-
BERRHA LT-
LC[0..15]
MPX_REF1
MPX_REF2
LC[0..15]
15084_B
SHT 12 - LAMP ROW SOURCES
CLK_12V
STR_12V
OE_12V
PORTA [0..7]
PORTA[0..7]
A SDSFC3
TGATE1TGATE2-
IP[0..31]
CS_TTLASDSR/WDSA CK0DSA CK1SIZ0
SIZ1
MPX_CLK
MPX_STR
MPX_OE
MPX1_DA TA_ A
MPX2_DA TA_ A
MPX_STR_DA TA_A
15084_3
POP4
POP6
TOUT1
TOUT2
RA M_ CS-
15084_4
15084_5
SEL[0..2]
IP[0..3 1]
CS3CLKOUT
HA LTBERR-
CTSA RTSA CTSBRTSBRXDA
TXDA
RXDB
TXDB
RESETPB0
PB5
PB6
D[0..15]
SEL[0..2]
RXDA
TXDA
CTSA RTSA -
SHT 1 0 - RESET/BATT/RS232/I2C
CTSA RTSA CTSBRTSBRXDA
TXDA
RXDB
TXDB
RESETPB0
PB5
PB6
SEL[0..2]
SHT 4 - EPROM/RA M
SHT 5 - SOUND
POP4
POP6
TOUT1
TOUT2
D[0..15]
CS_IP-
SHT 3 - FPGA
A [0..2 3]
PORTA [0..7]
CS_IP-
CS_TTLA SDSR/WDSA CK0 DSA CK1 SIZ0
SIZ1
15084_7
D[0 ..15]
METER_SENSE
NMI-
SHT 7 - INPUTS/DIL SW
15084_8
DSACK1 SIZ1
A [0..2 3]
METER_SENSE
V REF
NMIMPX_REF2
MPX_REF1
PORTA [0..7]
SFX_CLK
OP[0..63]
SEL[0..2]
PORTA [0..7]
MPX1_A_12V
MPX1_B_12V
MPX1_C_12V
MPX1_D_12V
LR[0..15]
MPX1_B_12V
MPX1_C_12V
MPX1_D_12V
LR[0..15]
LR[0..15]
15084_C
15084_9
15084_A
15084_2
HEBER LTD.
Belvedere Mill
Chalfor d, Str oud
Gloucester shire GL6 8NT
Tel: 0453 886000 Fax: 0453 885013
Title
© HEBER LTD, 1996-20 02
Document No. 80-15151 Issue 6
PLUTO 5 - ROOT SHEET
Size
A3
Document Number
56- 15084
Date:
Monday, A ugust 11, 2003
Rev
11r 2
Sheet
1
of
13
HEBER LTD
Page 39
Figure 2 - Schematic Sheet 2 - CPU
N7
BACKGRO UND DEBUG
CONNECT OR
TCK
TMS
TDI
TDO
PP
PP
PP
PP
IEEE 11 49.1 ACCESS
TP9
PAD
A SDSR/WSIZ0
SIZ1
3,9 DSA CK09 DSA CK19
9
10
103
104
107
105
106
DSACK0 DSACK1 -
112
111
BERRHA LTRESET-
BERRHA LTRESET-
99
98
97
PP23
PP24
PP25
9,10
9,10
9,10
9,10
POP4
POP6
RXDB
TXDB
CTSBRTSB-
9
TOUT1
9
TGA TE2-
5
TOUT2
EXTA L
RXDA
TXDA
CTSA RTSA -
33
32
28
29
POP4
POP6
27
26
RXDB
TXDB
CTSBRTSB-
25
24
22
23
TOUT1
TOUT2
V CC
79
81
80
V CC
36
34
35
DONE1-
16
15
14
CLKOUT
16.77MH z
95
EXTA L
32.768K Hz
91
DREQ1-
DREQ1-
3,9 CLKOUT
1
TGA TE1-
5
TP11
PA D
3
RXDA
TXDA
CTSA RTSA -
10
10
10
10
87
2
3
4
5
8
9
10
CS0-
CS0-
5
5
100
101
102
108
BRBGBGACK-
PP
PP
PP
PB0
CS1CS2METER_SENSE
CS3PB5
PB6
PB7
10
PB0
3
CS13
CS28 METER_SENSE
3,9
CS3PB5
9
PB6
8
NMI3
69
70
71
72
A SDSR/WSIZ0
SIZ1
TP10
PAD
3
R103
680R
FC0
FC1
FC2
FC3
78
77
76
75
83
82
85
84
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
AS
DS
R/W
SIZ0
SIZ1
DSA CK0
DSA CK1
BERR
HA LT
RESET
BR
BG
BGACK
RMC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
MODCK/PB0
CS1/IRQ1/PB1
CS2/IRQ2/PB2
IRQ3/PB3
CS3/IRQ4/PB4
IRQ5/PB5
IRQ6/PB6
IRQ7/PB7
CS0/A V EC
RXDA
TXDA
CTSA
RTSA /OP0
RXRDYA /OP4
TXRDY A/OP6
RXDB
TXDB
CTSB
RTSB/OP1
A 24/PA0
A 25/PA1/IACK1
A 26/PA2/IACK2
A 27/PA3/IACK3
A 28/PA4/IACK4
A 29/PA5/IACK5
A 30/PA6/IACK6
A 31/PA7/IACK7
TGA TE1
TIN1
TOUT1
TGA TE2
TIN2
TOUT2
10
8
6
4
2
DREQ1
DA CK1
DONE1
DREQ2
DA CK2
DONE2
VCC
9
7
5
3
1
RESET-
GND
GND
DS-
144
143
142
141
138
137
136
135
134
133
132
131
128
126
125
124
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
113
37
38
39
42
43
44
45
46
47
48
51
52
53
55
56
57
60
61
62
63
64
65
66
A [0..23]
RESET-
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
A 18
A 19
A 20
A 21
A 22
A 23
123
122
121
120
117
116
115
114
DREQ2-
17
3.68MHZ
LD1
R44
RED
3K3
LD2
R45
GREEN
3K3
X1
C24
SCLK
12
SW3
PORTA 3
GND
N15
PORTA [0..7]
PORTA[0..7]
N11
2
3
4
5
6
7
8
9
PORTA 0
PORTA 1
PORTA 2
PORTA 3
PORTA 4
PORTA 5
PORTA 6
PORTA 7
1
A0
A1
A2
A3
A4
A5
A6
A7
V CC
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
3
DONE2-
N9
3.68MHZ 3
2
3
4
5
6
7
8
9
D8
D9
D10
D11
D12
D13
D14
D15
20
21
1
VCC
2
3
4
5
6
7
8
9
3K3*8 SIL
N10
3K3*8 SIL
DREQ2-
5,8,9,10
1
N16
V CC
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
2
3
4
5
6
7
8
9
GND
1
VCC
3K3*8 SIL
N17
V CC
1
A 16
A 17
A 18
A 19
A 20
A 21
A 22
A 23
2
3
4
5
6
7
8
9
1
VCC
3K3*8 SIL
PP5
3K3*8 SIL
2
GND
100n
GND
PP
HEBER LTD.
V CC
V CC
C25
100n
GND
Document No. 80-15151 Issue 6
ON-BOAR D
PUSHBUT TON
SW PUSHBUTTON
C23
100n
© HEBER LTD, 1996-20 02
SOFTWAR E
CONTROL LED
LED
V CC
MC68340PV
6
18
30
40
49
54
58
67
73
88
96
109
118
127
129
139
3
X2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
XTA L
V CCSYN
RESET L ED
3K3*8 SIL
EXTA L
93
V CC
A[0..23] 3,4,6,9
74HC14
PORTA 0
PORTA 1
PORTA 2
PORTA 3
PORTA 4
PORTA 5
PORTA 6
PORTA 7
13
12
11
13
V CC
3K3*8 SIL
V CC
U7F
PORTA 2
1
2
3
4
5
6
7
8
9
D[0..15] 3,4,6,7,9
CLKOUT
XFC
90
PB0
METER_SENSE
PB5
PB6
PB7
DONE1DONE2RESET-
3K3*8 SIL
TP13
PA D
89
V CC
D[0..15]
TP12
PA D
LC3
EMC FILTER
1
N8
1
2
3
4
5
6
7
8
9
LOW PROFILE HDR 10W
FITTED FOR DEV . ONLY
U5
BKPT
FREEZE
IPIPE
IFETCH
R102
680R
9
9
3,9
3,9
9
7
19
31
41
50
59
68
74
86
92
94
110
119
130
140
V CC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
V CC
ASR/WBERRBKPT
TCK
BRBGACKHA LT-
P16
IPIPE
IFETCH
FREEZE
BKPT
BERR-
V CC
TCK
TMS
TDI
TDO
PP1
PP2
PP3
PP4
V CC
C26
100n
GND
V CC
C27
100n
GND
V CC
C28
100n
GND
V CC
C29
100n
GND
V CC
C30
100n
GND
C31
100n
GND
Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0) 1453 885013
V CC
C32
100n
GND
Title
PLUTO 5 - CPU
Size
A3
Document Number
56- 15084
Date:
Tuesday , Aug ust 12, 2003
Rev
11r 2
Sheet
2
of
13
HEBER LTD
Page 40
Figure 3 - Schematic Sheet 3 - FPGA
2
R/W2,9 DSACK0 2
SIZ0
10
2
2
2
2
CS_OP- 6
CS_IP- 7
RESET
RA M_WL- 4
RA M_WU- 4
RA M_OE- 4
CS0CS1CS2CS3-
2,4,6,7,9 D[0..15]
ROM_OE- 4
ROM_P1 4
D[0..15]
D8
D9
D10
D11
D12
FPGA [0..6]
GND
V CC
U6
N14
FPGA 0
FPGA 1
FPGA 2
FPGA 3
FPGA 4
FPGA 5
FPGA 6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
D13
2
A [0..23]
A [0..2 3]
A0
A1
A2
A3
A4
A5
A6
A7
GND
GND
V CC
V CC
I/O
I/O
I/O
I/O
I/O
I/O
V CC
V CC
MODE
I/O
I/O(CLK)
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
FPGA 0
FPGA 1
FPGA 2
FPGA 3
1
4
V CC
3K3*8 SIL
V CC
V CC
GND
FPGA 4
FPGA 5
FPGA 6
GND
GND
SFX2_D[0..3]
SFX2_D0
SFX2_D1
SFX2_D2
SFX2_D3
SFX2_D[0..3]
SFX2_V CK
CS_TTL-
SFX2_V CK 5
CS_TTL- 9
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A19
A20
A21
A22
A23
D14
D15
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
2
3
4
5
6
7
8
9
FPGA [0..6]
FPGA
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
SFX1_D[0..3]
SFX1_D[0..3]
SFX1_D0
SFX1_D1
SFX1_D2
SFX1_D3
ROM_P12
GND
V CC
ROM_P12 4
5 SFX1_VCK
5,8 SFX_CLK
2
2
DREQ1DREQ2-
2
2
3.68MHZ
EXTA L
2
CLKOUT
MPX_OE 13
MPX_CLK 13
MPX_STR 13
MPX1_DA TA_A 13
MPX2_DA TA_A 13
MPX_STR_DA TA_A 13
R104
10M
X1
R105
HEBER LTD.
14.7456MHz
680R
C38
33p
GND
V CC
C37
33p
C33
100n
Document No. 80-15151 Issue 6
VCC
C34
100n
V CC
C35
100n
C36
100n
GND
GND
© HEBER LTD, 1996-20 02
V CC
GND
GND
GND
Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0) 1453 885013
Title
PLUTO 5 - FPGA
Size
A3
Document Number
56- 15084
Date:
Tuesday , August 12, 2003
Rev
11r 2
Sheet
3
of
13
HEBER LTD
Page 41
Figure 4 - Schematic Sheet 4 - Memory
VBATT
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
A 18
3
3
ROM_ P1
ROM_ OE-
ROM_P1
ROM_OE-
GND
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
31
1
24
22
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
A 18
D0
D1
D2
D3
D4
D5
D6
D7
13
14
15
17
18
19
20
21
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
A 18
V CC
C21
100n
GND
VCC
V PP
OE
CE
GND
32
V CC
16
GND
3
3
ROM_P1
ROM_ OE-
ROM_P1
ROM_OEGND
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
31
1
24
22
V BATT
U4
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
A 18
V CC
V PP
OE
CE
GND
13
14
15
17
18
19
20
21
D8
D9
D10
D11
D12
D13
D14
D15
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
V CC
C22
100n
10
9
8
7
6
5
4
3
25
24
21
23
2
26
1
GND
32
3 RA M_WL10 RA M_CSV CC
3 RA M_OE-
16
GND
27
20
22
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
WR
CE
OE
O0
O1
O2
O3
O4
O5
O6
O7
11
12
13
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
V BATT
C20
100n
GND
10
9
8
7
6
5
4
3
25
24
21
23
2
26
1
27
20
22
3 RA M_WU10 RA M_ CS3 RA M_ OE-
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
HM62256BLFP
O0
O1
O2
O3
O4
O5
O6
O7
11
12
13
15
16
17
18
19
D8
D9
D10
D11
D12
D13
D14
D15
V BATT
C19
100n
WR
CE
OE
GND
EPROM
U3
28
U1
VDD
U2
GND
ROM_ P12
14
ROM_P12
A [0..23]
28
3
D[0..15]
VDD
A [0..2 3]
GND
2
14
2,3,6,7,9 D[0..15]
GND
HM62256BLFP
GND
EPROM
EPROMS - 2*27C040 OR 2*27C801
U3/U4 - 32K*8 STATIC RAMS, SOP
PINS 1, 12 SET BY FPG A
CS0-
0
0
0
0
1
x
MODE
READ 1* 27C040
READ 2* 27C040
READ 1* 27C801
READ 2* 27C801
NON-ROM CYCLE
RESET
ROM_P1
ROM_P12
VCC
VCC
A19
A20
A20
1
A0
A19
A0
A19
A0/A19
1
------- ------------- ------------ --- MEMORY EX PANSION CONNE CTOR ------- ------------- ------------- -------
2
A [0..23]
A[0..23]
A4
V CC
A3
A2
A1
GND
FPGA 0
FPGA 1
FPGA 2
FPGA 3
FPGA 4
FPGA 5
FPGA 6
D0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
P15A
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
DIN41612-48W
TY PE "C/2" V ERT SKT
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
P15B
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
DIN41612-48W
TY PE "C/2" V ERT SKT
ROM_ P1
A6
A8
A10
A12
A14
A16
A18
(A20)
D15
D13
D11
D9
D7
D5
D3
D4
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
P15C
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
LINES F PGA0-6 HAVE T HE FOLLOWING DEFAULT FUNC TIONS
NAME
I/O
FPGA0
FPGA1
FPGA2
FPGA3
FPGA4
FPGA5
FPGA6
IN
OUT
OUT
OUT
OUT
OUT
OUT
FUNCTIO N
MEM_CAR D_PRESENTROM_MAP _1
ROM_MAP _2
WU- (WR ITE HIGH BYTE )
WL- (WR ITE LOW BYTE)
RAM_CS- (CS- FOR EXP ANSION RAM)
A22
DIN41612-48W
TY PE "C/2" V ERT SKT
D[0..15]
2,3,6,7,9 D[0 ..15]
3 FPGA[0..6]
A5
A7
A9
A 11
A 13
A 15
A 17
A 19
A 21
D14
D12
D10
D8
D6
D1
D2
FPGA [0..6]
HEBER LTD.
Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0) 1453 885013
Title
© HEBER LTD, 1996-20 02
Document No. 80-15151 Issue 6
PLUTO 5 - MEMORY
Size
A3
Document Number
56- 15084
Date:
Tuesday , August 12, 2003
Rev
11r 2
Sheet
4
of
13
HEBER LTD
Page 42
Figure 5 - Schematic Sheet 5 - Sound
SAMPLED SOUND CHANNEL #1
SAMPLED SOUND CHANNEL #2
V CC
V CC
C40
C39
GND
POP4
POP6
SFX1_S1
SFX1_S2
POP4
POP6
1
2
PORTA 0
3
15
SFX_CLK
SFX_CLK
16
17
S1
S2
T1
T2
T3
T4
DA O
12
13
3
8
PORTA [0..7]
2,8,9,10 PORTA [0..7]
PORTA 6
PORTA 7
11
4
5
6
7
SFX2_S1
SFX2_S2
1
2
PORTA 1
XT
A OUT
V CK
10
3
U39
18
SFX2_D0
SFX2_D1
SFX2_D2
SFX2_D3
GND
RESET
XT
100n
SFX_CLK
15
SFX_CLK
16
14
17
D0
D1
D2
D3
S1
S2
T1
T2
T3
T4
DA O
12
13
3
8
GND
11
RESET
XT
XT
A OUT
V CK
10
14
9
MSM6585
9
MSM6585
VDD
D0
D1
D2
D3
SFX2_D[0..3]
SFX2_D[0..3]
U8
18
PORTA [0..7]
4
5
6
7
VDD
SFX1_D0
SFX1_D1
SFX1_D2
SFX1_D3
2
2
GND
100n
GND
SFX1_D[0..3]
GND
SFX1_D[0..3]
R111
47K 2%
3 SFX1_V CK
R130
47K 2%
GND
SFX1_VCK
3 SFX2_V CK
GND
SFX2_V CK
C44
10n
R129
C49
22K
1/50
C51
10n
R112
22K
R131
22K
+12V
GND
C50
C43
GND
GND
GND
220/16
100n
4
U32
+
13
LS CONN ECTOR
P10
+
1
2
3
4
5
LS1+
LS1CH2_MIX
LS2+
LS2-
11
3
-
C47
PP6
1/50
R108
1
TOUT1 2
8
HDR 5W A MP MTA - 100
+
10
5
-
C45
1/50
C48
6
12
9
R109
3K3
3K3
PP7
1/50
PP
R110
7
TDA7057A Q
PP
TOUT2 2
C46
1/50
R113
3K3
3K3
GND
HEBER LTD.
Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0) 1453 885013
Title
© HEBER LTD, 1996-20 02
Document No. 80-15151 Issue 6
PLUTO 5 - SOUND
Size
A3
Document Number
56- 15084
Date:
Tuesday , August 12, 2003
Rev
11r 2
Sheet
5
of
13
HEBER LTD
Page 43
Figure 6 - Schematic Sheet 6 - Outputs
OP[0..63]
D0
18
SEL0
SEL1
SEL2
3
8
12
13
19
V CC
2
GND
9
U22
D
S0
S1
S2
G
CLR
V CC
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PGND
PGND
PGND
PGND
OP56
OP48
OP40
OP32
OP24
OP16
OP8
OP0
4
5
6
7
14
15
16
17
1
10
11
20
D4
OP[0..63] 9
18
SEL0
SEL1
SEL2
3
8
12
13
19
GND
GND
GND
GND
V CC
2
GND
9
TPIC6259
2
A[0..23]
A[0..23]
D1
18
U7A
A1
1
A2
3
2
SEL0
4
SEL1
SEL0
SEL1
SEL2
3
8
12
13
19
74HC14
U7B
74HC14
U7C
A3
5
6
74HC14
V CC
2
GND
9
S0
S1
S2
G
CLR
V CC
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PGND
PGND
PGND
PGND
OP57
OP49
OP41
OP33
OP25
OP17
OP9
OP1
4
5
6
7
14
15
16
17
1
10
11
20
D5
18
SEL0
SEL1
SEL2
3
8
12
13
19
GND
GND
GND
GND
V CC
2
GND
9
TPIC6259
SEL2
D2
18
SEL0
SEL1
SEL2
3
8
12
13
19
V CC
2
GND
9
S0
S1
S2
G
CLR
V CC
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PGND
PGND
PGND
PGND
4
5
6
7
14
15
16
17
1
10
11
20
OP58
OP50
OP42
OP34
OP26
OP18
OP10
OP2
18
D6
SEL0
SEL1
SEL2
3
8
12
13
19
GND
GND
GND
GND
V CC
2
GND
9
TPIC6259
18
D3
SEL0
SEL1
SEL2
3
10
3
8
12
13
19
CS_OPRESETV CC
2
GND
9
S0
S1
S2
G
CLR
V CC
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PGND
PGND
PGND
PGND
4
5
6
7
14
15
16
17
1
10
11
20
D7
OP59
OP51
OP43
OP35
OP27
OP19
OP11
OP3
18
3
8
12
SEL0
SEL1
SEL2
13
19
GND
GND
GND
GND
TPIC6259
2,3,4,7,9 D[0..15]
V CC
GND
PGND
PGND
PGND
PGND
4
5
6
7
14
15
16
17
1
10
11
20
OP60
OP52
OP44
OP36
OP28
OP20
OP12
OP4
GND
GND
GND
GND
U27
D
S0
S1
S2
G
CLR
V CC
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PGND
PGND
PGND
PGND
4
5
6
7
14
15
16
17
1
10
11
20
OP61
OP53
OP45
OP37
OP29
OP21
OP13
OP5
GND
GND
GND
GND
U28
D
S0
S1
S2
G
CLR
V CC
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PGND
PGND
PGND
PGND
OP62
OP54
OP46
OP38
OP30
OP22
OP14
OP6
4
5
6
7
14
15
16
17
1
10
11
20
GND
GND
GND
GND
TPIC6259
U25
D
G
CLR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
TPIC6259
U24
D
S0
S1
S2
TPIC6259
U23
D
U26
D
V CC
2
GND
9
U29
D
S0
S1
S2
G
CLR
V CC
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PGND
PGND
PGND
PGND
OP63
OP55
OP47
OP39
OP31
OP23
OP15
OP7
4
5
6
7
14
15
16
17
1
10
11
20
GND
GND
GND
GND
TPIC6259
D[0..15]
SEL[0..2]
SEL[0..2] 7
HEBER LTD.
V CC
V CC
C1
100n
GND
© HEBER LTD, 1996-20 02
Document No. 80-15151 Issue 6
V CC
C3
100n
GND
C2
100n
GND
Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0) 1453 885013
VCC
C4
100n
GND
Title
PLUTO 5 - OUTPUTS
Size
A3
Document Number
56- 15084
Date:
Tuesday , August 12, 2003
Rev
11r 2
Sheet
6
of
13
HEBER LTD
Page 44
Figure 7 - Schematic Sheet 7 - Inputs
IP[0..31]
IP[0..31]
9
D[0 ..15]
7
D3
9
1Y
2Y
V CC
1C0
1C1
1C2
1C3
2C0
2C1
2C2
2C3
A
B
1G
2G
C5
100n
GND
7
D4
9
D5
74HC253
U11
1Y
1C0
1C1
1C2
1C3
2Y
2C0
2C1
2C2
2C3
A
B
1G
2G
D6
7
D7
9
74HC253
U12
1Y
2Y
V CC
1C0
1C1
1C2
1C3
2C0
2C1
2C2
2C3
A
B
1G
2G
C6
100n
GND
14
2
1
15
47K 2%
R8
1
V CC
N12
3K3*8 SIL
2
3
4
5
6
7
8
9
R7
47K 2%
IP25
IP17
IP9
IP1
47K 2%
D8
7
D9
9
U14
1Y
1C0
1C1
1C2
1C3
2Y
2C0
2C1
2C2
2C3
47K 2%
N1
3K3*8 SIL
R10
R11
47K 2%
R13
47K 2%
R14
47K 2%
47K 2%
SEL0
SEL1
VCC
R12
47K 2%
R15
IP26
IP18
IP10
IP2
A
B
1G
2G
IP27
IP19
IP11
IP3
47K 2%
R16
6
5
4
3
1
2
3
4
5
6
7
8
10
11
12
13
14
2
1
15
47K 2%
R21
10
11
12
13
R18
GND
V CC
47K 2%
N13
3K3*8 SIL
R22
R20
47K 2%
R23
47K 2%
47K 2%
SEL0
SEL1
VCC
R19
47K 2%
47K 2%
IP28
IP20
IP12
IP4
IP29
IP21
IP13
IP5
47K 2%
R32
R24
R25
47K 2%
R28
10
11
12
13
47K 2%
R29
47K 2%
SEL0
SEL1
D10
7
D11
9
U13
1Y
1C0
1C1
1C2
1C3
2Y
2C0
2C1
2C2
2C3
A
B
1G
2G
47K 2%
N3
3K3*8 SIL
6
5
4
3
R26
VCC
R27
47K 2%
R30
47K 2%
6
5
4
3
1
2
3
4
5
6
7
8
10
11
12
13
14
2
1
15
SW2
16
15
14
13
12
11
10
9
8W DIL SW
SEL0
SEL1
GND
74HC253
IP30
IP22
IP14
IP6
IP31
IP23
IP15
IP7
47K 2%
R31
47K 2%
16
15
14
13
12
11
10
9
74HC253
47K 2%
R17
SW1
8W DIL SW
SEL0
SEL1
N2
3K3*8 SIL
6
5
4
3
14
2
1
15
47K 2%
47K 2%
R9
10
11
12
13
14
2
1
15
R6
SEL0
SEL1
6
5
4
3
14
2
1
15
R4
2
3
4
5
6
7
8
9
D2
74HC253
U10
R5
10
11
12
13
IP24
IP16
IP8
IP0
R3
47K 2%
1
A
B
1G
2G
R2
47K 2%
1
2C0
2C1
2C2
2C3
R1
6
5
4
3
1
2Y
1C0
1C1
1C2
1C3
1
9
1Y
9
8
7
6
5
4
3
2
D1
U9
9
8
7
6
5
4
3
2
7
9
8
7
6
5
4
3
2
D0
47K 2%
9
8
7
6
5
4
3
2
2,3,4,6,9 D[0 ..15]
N4
3K3*8 SIL
1
74HC253
3
6
VCC
CS_IP-
SEL[0..2]
SEL[0..2]
NOTE: S EL0-2 ARE INV ERTED A1-3
HEBER LTD.
Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0) 1453 885013
Title
© HEBER LTD, 1996-20 02
Document No. 80-15151 Issue 6
PLUTO 5 - INPUTS
Size
A3
Document Number
56- 15084
Date:
Tuesday , August 12, 2003
Rev
11r 2
Sheet
7
of
13
HEBER LTD
Page 45
Figure 8 - Schematic Sheet 8 - Power Supply
+12V
D1
UF4002
1
3
LC1
EMC FILTER
2
V METER+
+12V
METER DETECTION
R33
47R
POWER FAIL DETECTION
V CC
GND
R37
47K 2%
+12V
R38
47K 2%
R39
47K 2%
R40 revisions:
3k3 -> 10k Feb 1998
10k -> 4k7 Jul 2003
R40
4K7
2
1
NMI-
+
-
+
2
12
-
PP13
7
PP
6
V REF 10
R34
22K
LM339
U16A
3
METER_SENSE
2 METER_SENSE
R35
47K 2%
U16B
PP8
5
R36
4
PP9
GND
PP
LM339
47K 2%
PP10
PP
PP
GND
V CC
R124
47K 2%
PORTA[0..7]
2,5,9,10 PORTA [0..7]
U16C
+
14
-
PORTA 7
8
9
D21
1N4148
PP
R127
LM339
MPX_REF1
SFX_CLK 3
-
10
+
11
TP5
PA D
V CC
TP6
PA D
+12V
TP7
PA D
+12V _IN
TP8
PA D
22K
U16D
13
GND
MPX_REF1 11
R125
1K
Thresho ld 2 - Lamp s hort cct.
PORTA 6
SFX_CLK
PP11
PP12
MPX CURRENT
PP
SENSE
LM339
C9
47p
Thresho ld 1 - Lamp p resent
C10
47p
MPX_GND
GND
GND
V SS
R126
120R
GND
GND
MPX_REF2
MPX_REF2 11
VMOT+
+12V
LC2
EMC FILTER
1
U15
LM7805
3
VI
2
3.15A F 20*5MM
D20
SA 15
GND
F1
+12V _IN
VCC
VO
C7
1/50
-12V
C8
1/50
D2
SA 5
GND
REGULATED +5V
© HEBER LTD, 1996-20 02
Document No. 80-15151 Issue 6
P3
POWER IN
HDR 6W A MP MTA - 156
D3
SA15
GND
GND
1
2
3
4
5
6
-12V
GND
GND
+12V_IN
MPX_GND
V MPX+
HEBER LTD.
Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0) 1453 885013
Title
PLUTO 5 - POWER SUPPLY
Size
A3
Document Number
56- 15084
Date:
Tuesday , August 12, 2003
Rev
11r 2
Sheet
8
of
13
HEBER LTD
Page 46
Figure 9 - Schematic Sheet 9 – IO Connectors
Heber L td. 1999
I/O 1
IP20
IP22
IP24
IP26
IP28
IP30
+12V
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
OP25
OP27
OP29
OP31
OP33
OP35
OP37
OP39
OP41
OP43
OP45
OP47
V CC
1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
12 LR[0..15]
LR[0..15]
GND
IP21
IP23
IP25
IP27
IP29
IP31
11 LC[0..15]
LC[0..15]
3
+12V
LC0
LC2
LC4
I/O 2
OP48
OP50
OP52
OP54
OP56
OP58
OP60
OP62
GND
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
IP6
IP8
IP10
IP12
IP14
IP16
IP18
+12V
P9
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
LR0
LR2
LR4
OP49
OP51
OP53
OP55
OP57
OP59
OP61
OP63
IP7
IP9
IP11
IP13
IP15
IP17
IP19
GND
GND
OP0
OP2
OP4
OP6
OP8
OP10
OP12
OP14
OP16
OP18
OP20
OP22
IP0
IP2
IP4
VMOT+
VMOT+
VMOT+
HDR 34W
V METER+
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
A 18
A 19
A 20
A 21
A 22
A 23
A 24
A 25
P7
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
A 18
A 19
A 20
A 21
A 22
A 23
A 24
A 25
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
LC1
LC3
LC5
LR1
LR3
LR5
3
OP1
OP3
OP5
OP7
OP9
OP11
OP13
OP15
OP17
OP19
OP21
OP23
IP1
IP3
IP5
6
18
A0
A1
A2
3
8
12
13
19
V CC
2
GND
9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
1
2
3
4
5
6
7
8
S0
S1
S2
G
CLR
V CC
PGND
PGND
PGND
PGND
GND
4
5
6
7
14
15
16
17
1
10
11
20
+12V
P12
HDR 8W A MP MTA - 100
GND
GND
GND
GND
2
I C
V CC
V CC
1
SDA
SCL
LC5
EMC FILTER
3
GND
1
2
3
4
P13
HDR 4W A MP MTA - 100
GND
U7E
V MOT+
V MOT+
V MOT+
2
10
TGA TE2-
11
PP15
R107
22K
74HC14
PP14
PP
PP
U7D
OP[0..63]
OP[0..63]
U30
D
GND
IP[0..31]
IP[0..3 1]
TTL I/O
TPIC6B259
LC4
EMC FILTER
1
HDR 50W
7
D8
CS_TTLRESET-
CS_TTL-
REELS
HDR 40W
N20
1K0*8 SIL
2
3
4
5
6
7
8
9
P8
2
GND
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
A 17
A 18
A 19
A 20
2
OP24
OP26
OP28
OP30
OP32
OP34
OP36
OP38
OP40
OP42
OP44
OP46
2
8
TGA TE1PP17
PP
9
74HC14
R106
22K
PP16
PP
2,5,8,10 PORTA[0..7]
2,3,4,6,7 D[0 ..15]
PORTA [0..7]
D[0..15]
D8
D9
D10
D11
D12
D13
D14
D15
2,10
2
2,10
2
RXDA
TXDA
CTSA RTSA -
RXDA
TXDA
CTSA RTSA -
A0
A1
A2
A3
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
DIN41612-48W
TY PE "R/2" V ERT MALE
2
A [0..2 3]
A [0..2 3]
P14C
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
2
A S2
DS2
R/W2,3 DSA CK02 DSA CK12
SIZ0
2
SIZ1
2,10
PB5
2
PB6
PORTA 0
PORTA 1
PORTA 2
PORTA 3
PORTA 4
PORTA 5
A22
ASDSR/WDSA CK0DSA CK1SIZ0
SIZ1
PB5
PB6
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
P14B
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
2
2
2
10
2
HALTCLKOUT
CS3RESETBERR-
HA LTCLKOUT
CS3RESETBERRA 20
A 23
A4
A5
A6
A7
+12V
VCC
VCC
GND
GND
DIN41612-48W
TY PE "R/2" V ERT MALE
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
P14A
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
DIN41612-48W
TY PE "R/2" VERT MALE
I/O EXP.
HEBER LTD.
Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0) 1453 885013
Title
© HEBER LTD, 1996-20 02
Document No. 80-15151 Issue 6
PLUTO 5 - CONNECTORS
Size
A3
Document Number
56- 15084
Date:
Tuesday , August 12, 2003
Rev
11r 2
Sheet
9
of
13
HEBER LTD
Page 47
Figure 10 - Schematic Sheet 10 - Reset/Battery/RS232
BATTERY BACK-UP
SM
Q2
FMMT717
VBATT
R42
3K3
TP14
PA D
+12V
PP18
BT1
2.4V NiMH
PP
3K3
Q1
2N7002
C11
1/50
1
14
R132
TP15
PA D
-12 V
RA M_CS- 4
2,9
GND
RESET-
2
RTSA -
2
TXDB
2
2
TXDA
RTSB-
V CC
4
5
V CC
9
10
V CC
12
13
U33
GND
V-
R43
3K3
V+
TP16
PA D
A1
TXA
B1
B2
TXB
C1
C2
TXC
D1
D2
TXD
GND
V CC
3
6
+12V
1
2
3
4
5
6
P1
RS232
(PORT A )
HDR 6W A MP MTA - 100
8
11
7
1488
GND
C52
22p
RTC
X2
32Khz
1
2
3
4
GND
GND
U40
OSCI
OSCO
A0
GND
8
7
6
5
V DD
INT
SCL
SDA
V BATT
GND
PORTA5
V CC
120R
GND
14
U38
VCC
TST
SCL
SDA
8
7
6
5
V CC
GND
VCC
U37
A0
A1
A2
GND
2,5,8,9
120R
R161
EEPROM
1
2
3
4
PORTA [0..7]
PORTA4
PCF8583
GND
GND
V CC
GND
PORTA [0..7]
R160
SCL
SDA
R114
24C04/24C08
RXDA
2,9
CTSA -
2
RXDB
2
CTSB-
R115
3K3
3K3
3
6
8
11
A
RXA
B
RXB
C
RXC
D
RXD
1
-12V
4
10
+12V
13
P2
DATAPOR T
(PORT B )
25W D SOCKET
GND
INTERNA L I2C BUS
2,9
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
7
1489
GND
PP19
POWER-ON RESET
PP
VCC
V REF
U17
RESET
5
RESET
6
1
R41
3K3
C12
100n
RESET
RESET
REF
SENSE
RESIN
GND
3
RESET-
CT
7
2
RESIN-
PB0
2
3
TL7705
C13
100n
4
2,6,9 RESET-
VCC
8
8
C14
220/16
V CC
GND
C53
100n
GND
© HEBER LTD, 1996-20 02
Document No. 80-15151 Issue 6
HEBER LTD.
Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0) 1453 885013
Title
PLUTO 5 - RESET/BATTERY/RS232
Size
A3
Document Number
56- 15084
Date:
Tuesday , Aug ust 12, 2003
Rev
11r 2
Sheet
10
of
13
HEBER LTD
Page 48
Figure 11 - Schematic Sheet 11 - Lamp Column/LED Digit Drives
1
GND
LC[0..15]
2
3
4
5
6
7
8
9
N18
3K3*8 SIL
+12v
16
8
GND
U20
STR
D
CLK
OE
V DD
680R
R98
680R
9
10
QS
QS
GND
R95
680R
R99
680R
R96
R97
680R
R100
LC1
LC1
D4
UF4002
Q37
BUK552
680R
Q38
BUK552
*
N19
3K3*8 SIL
+12V
C17
100n
GND
C18
100n
GND
+12v
16
8
GND
V DD
GND
R116
*
4
5
6
7
14
13
12
11
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
LC3
DIG3
LC3
D7
UF4002
LC4
LC4
DIG4
D8
UF4002
680R
R120
LC5
DIG5
*
R117
680R
680R
R121
*
680R
R122
680R
680R
*
R119
*
680R
R123
UF4002
LC6
*
Q41
BUK552
*
Q42
BUK552
680R
LC6
DIG6
D10
UF4002
LC7
LC7
DIG7
D11
UF4002
LC8
LC8
DIG8
*
*
Q43
BUK552
4094
LC9
LC9
DIG9
*
Q44
BUK552
P5
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
LC10
DIG10
*
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
SEG1
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
SEG15
*
Q45
BUK552
DIG1
DIG3
DIG5
DIG7
DIG9
DIG11
DIG13
DIG15
D14
LC11
D15
LC12
LC12
DIG12
*
D16
UF4002
LC13
DIG13
LC13
*
*
Q48
BUK552
D17
D4-D19 Changed from 1N4005 to UF 4002
March, 2003
UF4002
LC14
LC14
LC15
LC15
DIG14
*
*
Q49
BUK552
HDR 32W AMP ULTREX
HDR 18W AMP MTA- 100
UF4002
*
Q47
BUK552
P4
DIG11
LC11
*
Q46
BUK552
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
LAMP CO LUMNS(SINKS)
UF4002
*
or HDR 34W BOX HEADER
(Pins 33/34 - no connection)
D13
UF4002
LC10
A1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
D12
UF4002
*
DIG0
DIG2
DIG4
DIG6
DIG8
DIG10
DIG12
DIG14
SEG0
SEG2
SEG4
SEG6
SEG8
SEG10
SEG12
SEG14
LC0
LC1
LC2
LC3
LC4
LC5
LC6
LC7
LC8
LC9
LC10
LC11
LC12
LC13
LC14
LC15
D9
Q40
BUK552
*
R118
*
9
10
QS
QS
DIG2
D6
Q39
BUK552
2
3
4
5
6
7
8
9
+12V
U21
STR
D
CLK
OE
LC2
UF4002
LC5
1
2
3
15
DIG1
D5
UF4002
LC2
680R
R101
LC[0..15] 9
DIG0
Q36
BUK552
680R
GND
4094
LC0
Q35
BUK552
R94
4
5
6
7
14
13
12
11
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
1
1
2
3
15
13 STR_12V
13 STR_A _12V
13 CLK_12V
13 OE_12V
LC0
D18
UF4002
DIG15
*
*
Q50
BUK552
D19
UF4002
DIG[0..15]
7 SEG L ED DRIVE (32 DIGIT)
OR 14 S EG LED DRIVE (16 DIGIT)
MPX_REF1
* -
THESE C OMPONENTS OMI TTED
ON PLUT O 5 128/16.
(DRIVE FOR LC8-15/D IG8-15)
MPX_REF2
13 SEG[0..1 5]
MPX_REF1
8
MPX_REF2
8
Rsense
24 mill iohms
Copper Track
SEG[0..15]
MPX_GND
HEBER LTD.
Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0) 1453 885013
Title
© HEBER LTD, 1996-20 02
Document No. 80-15151 Issue 6
PLUTO 5 - LA MP COLUMN/LED DIGIT DRIV ES
Size
A3
Document Number
56- 15084
Date:
Tuesday , August 12, 2003
Rev
11r 2
Sheet
11
of
13
HEBER LTD
Page 49
Figure 12 - Schematic Sheet 12 - Lamp Row Drives
1
V MPX+
2
3
4
5
6
7
8
9
N5
3K3*8 SIL
GND
1
2
3
15
13 STR_12V
13 MPX1_A _12V
13 CLK_12V
13 OE_12V
+12V
16
GND
8
U18
STR
D
CLK
OE
VDD
GND
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
QS
QS
R85
4
5
6
7
14
13
12
11
3K3
R81
3K3
R84
R83
3K3
R80
3K3
R79
3K3
3K3
9
10
R82
Q11
22K
R55
BC846
Q12
22K
R56
Q19
TIP126
GND
3K3
GND
BC846
Q13
4094
Q20
TIP126
22K
R58
Q21
TIP126
BC846
Q15
22K
R59
BC846
Q16
22K
R60
BC846
Q17
22K
R61
BC846
Q18
22K
Q22
TIP126
C15
100n
Q23
TIP126
LR5
V MPX+
Q24
TIP126
LR6
V MPX+
Q25
TIP126
GND
GND
LR4
V MPX+
GND
+12V
LR0
LR1
LR2
LR3
LR4
LR5
LR6
LR7
LR8
LR9
LR10
LR11
LR12
LR13
LR14
LR15
LR3
V MPX+
GND
13 MPX1_B_12V
LAMP RO WS(SOURCE)
LR2
V MPX+
22K
R57
BC846
Q14
LR1
V MPX+
GND
3K3
R78
LR0
V MPX+
R54
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
HDR 16W A MP MTA - 100
LR7
V MPX+
P6
Q26
TIP126
GND
1
V MPX+
BC846
PP22
PP
PP21
PP
N6
3K3*8 SIL
2
3
4
5
6
7
8
9
PP20
PP
1
2
3
15
13 MPX1_C_12V
+12V
GND
16
8
U19
STR
D
CLK
OE
VDD
GND
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
QS
QS
4
5
6
7
14
13
12
11
9
10
R93
3K3
R89
3K3
R92
3K3
R88
R91
R90
3K3
R87
3K3
3K3
3K3
R86
3K3
Q3
22K
R47
BC846
Q4
22K
R48
Q27
TIP126
BC846
Q5
22K
R49
BC846
Q6
22K
R50
BC846
Q7
22K
R51
BC846
Q8
22K
R52
BC846
Q9
22K
R53
BC846
Q10
22K
GND
4094
Q28
TIP126
Q29
TIP126
C16
100n
GND
GND
GND
LR11
V MPX+
Q30
TIP126
LR12
V MPX+
Q31
TIP126
LR13
V MPX+
Q32
TIP126
GND
+12V
LR10
V MPX+
GND
13 MPX1_D_12V
LR9
V MPX+
GND
GND
LR8
V MPX+
R46
GND
LR14
V MPX+
Q33
TIP126
LR15
V MPX+
LR[0..15]
LR[0..15] 9
Q34
TIP126
BC846
HEBER LTD.
Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0) 1453 885013
Title
© HEBER LTD, 1996-20 02
Document No. 80-15151 Issue 6
PLUTO 5 - LA MP ROW DRIVES
Size
A3
Document Number
56- 15084
Date:
Tuesday , August 12, 2003
Rev
11r 2
Sheet
12
of
13
HEBER LTD
Page 50
Figure 13 - Schematic Sheet 13 - LED Segment Drives
U34
3
5
7
9
11
14
3
MPX_OE
3 MPX_CLK
3 MPX_STR
3 MPX1_DA TA_A
3 MPX2_DA TA_A
3 MPX_STR_DATA_ A
VCC
13
VCC
1
AI
BI
CI
DI
EI
FI
AO
BO
CO
DO
EO
FO
MODE
V DD
V CC
GND
OE_12V
CLK_12V
STR_12V
MPX1_A _12V
MPX2_A _12V
STR_A _12V
2
4
6
10
12
15
16
+12V
8
GND
OE_12V 11,12
CLK_12V 11,12
STR_12V 11,12
MPX1_A _12V 12
R62
+12V
Q51
BC337
STR_A_12V 11
150R
R63
Q52
BC337
4504
1
2
3
15
12 MPX1_B_12V
+12V
16
GND
8
150R
R64
Q53
BC337
U35
STR
D
CLK
OE
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
V DD
QS
QS
GND
4
5
6
7
14
13
12
11
150R
R65
Q54
BC337
150R
R66
Q55
BC337
9
10
150R
R67
Q56
BC337
150R
R68
4094
Q57
BC337
12 MPX1_C_12V
150R
R69
+12V
Q58
BC337
C41
100n
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
150R
GND
R70
+12V
Q59
BC337
+12V
Q60
BC337
C42
100n
GND
1
2
3
15
12 MPX1_D_12V
+12V
16
GND
8
V DD
GND
150R
R72
Q61
BC337
U36
STR
D
CLK
OE
150R
R71
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
QS
QS
4
5
6
7
14
13
12
11
150R
R73
Q62
BC337
150R
R74
Q63
BC337
9
10
150R
R75
Q64
BC337
150R
R76
4094
Q65
BC337
150R
R77
Q66
BC337
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
150R
SEG[0..15]
SEG[0..15] 11
U31A
2
1
U31B
4069
MPX2_A_12V
3
3
LC6
GND
4
1
U31C
5
6
1
U31D
4069
9
U31E
STR_12V
11
8
1
3
LC9
GND
4069
10
3
LC8
2
CLK_12V
GND
2
STR_A _12V
3
LC7
GND
4069
2
1
2
MPX1_A_12V
1
3
GND
1
2
3
4
5
6
7
P11
MULTIPLEX EXPANSION
HEBER LTD.
Belvedere Mill
Chalfor d, Str oud, GL6 8NT
Tel: +44 (0) 1453 886000
Fax: +44 (0) 1453 885013
HDR 7W 0.1 KK
13
12
4069
© HEBER LTD, 1996-2 002
Document No. 80-15151 Issue 6
GND
LC10
2
U31F
1
GND
3
Title
LC11
2
OE_12V
4069
+12V
V DD
PLUTO 5 - LED SEGMENT DRIV ES
Size
A3
Document Number
56- 15084
Date:
Tuesday , Aug ust 12, 2003
Rev
11r 2
Sheet
13
of
13
HEBER LTD
Page 51
Figure 14 - Pluto 5 Component Ident
Document No. 80-15151 Issue 6
HEBER LTD
Page 52
Figure 15 - Photograph of Pluto 5 with Ultrex Connectors (Pluto 5U)
Document No. 80-15151 Issue 6
HEBER LTD