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NUC740 User Manual NUC740 Evaluation Board User Manual The information described in this document is the exclusive intellectual property of Nuvoton Electronics Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NUC740-based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. . For additional information or questions, please contact:Nuvoton Electronics Corp. . Publication Release Date: Apr, 2009 -1- Revision B NUC740 User Manual 1 REVISION HISTORY.....................................................................................3 2 GENERAL DESCRIPTION ..............................................................................4 3 FEATURES....................................................................................................4 4 THE FUNCTION BLOCKS ...............................................................................5 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 5 CPU: NUC740 .................................................................................................... 5 FLASH AND SDRAM .............................................................................................. 6 PCMCIA CONNECTOR ............................................................................................ 6 PHY, WAN PORT AND LAN PORT ............................................................................ 6 JTAG. ................................................................................................................ 6 UART, 2ND USB AND LED ...................................................................................... 6 USB................................................................................................................... 6 POWER ON SETTING............................................................................................... 6 RESET SCHEMATIC ................................................................................................. 7 POWER ............................................................................................................... 7 CIRCUIT BLOCK DESCRIPTION AND JUMPER SETTING ................................7 5.1 5.2 5.3 5.4 5.5 5.6 MCU .................................................................................................................. 8 POWER ............................................................................................................. 11 MEMORY BLOCK .................................................................................................. 12 PCMCIA FUNCTION BLOCK .................................................................................. 13 LAN & WAN FUNCTION BLOCKS ........................................................................... 14 USB AND UART FUNCTIONS ................................................................................. 19 6 BOM...........................................................................................................20 7 SCHEMATIC ...............................................................................................24 Publication Release Date: Apr, 2009 -2- Revision B NUC740 User Manual 1 Revision history version date page description A May 13, 2003 - Initial Issued A1 Sep 3,2008 - Update B Apr 6,2009 - Change part number to NUC740 Publication Release Date: Apr, 2009 -3- Revision B NUC740 User Manual 2 General Description The evaluation board is a test platform that is suitable for the sample of NUC740. The board include the powerful 16/32-bit ARM® based RISC micro-controller (NUC740), USB function, memory, PCMCIA function, power control system, LAN and WAN Ethernet port. This allows us to test and debug all NUC740CD function. This document shows the system-based hardware design. We would describe the jumper function, selectable function and how to connect with the NUC740 in detail. 3 Features • • • • • • • • • NUC740: 16/32-bit ARM7TDMI® RISC micro-controller Boot ROM and AP flash-- 2M*16 bits for expansion. SDRAM: One 512*4 banks*32 M bits SDRAM External I/O: PCMCIA application (Wireless LAN) General I/O: control signal, UART or 2nd USB, show status (LEDs) USB: USB function LAN and WAN 10/100M Ethernet interface Embedded ICETM Interface Expansion Function: one port WAN and 4 ports LAN. Publication Release Date: Apr, 2009 -4- Revision B NUC740 User Manual 4 The Function Blocks PCMCIA Wireless LAN Send Pattern LAN PC WAN port LAN Port RS232 PHY ICE JTAG Flash & SDRAM MII or RMII MAC 1 JTAG MII socket PHY MII or RMII PCMCIA connector NAT MAC 2 JATG USB signal EBI Console or Loop UART CPU Test Pin GPIO Timer Reset Circuit W90N740 Switch on/off Power Device USB Device USB USB 2nd USB Power on setting CLK USB Transceiver Power LED EVB Board Fig 1 The Function Block of Evaluation Board 4.1 CPU: NUC740 NUC740 is our protagonist. That is for her what we do every thing. The NUC740 is using ARM7TDMI® core inside. It is a low power, general-purpose integrated circuits. The NUC740 offers an 8K-byte Icache/SRAM, a 2K-byte D-cache/SRAM and two MACs of Ethernet controller that reduces total system cost. An NAT Accelerator is support to reduce the software loading for network address translation processing. We support 15MHZ frequency for CPU. In the PCBA, that would have test point for every one pin. The Publication Release Date: Apr, 2009 -5- Revision B NUC740 User Manual others that we do use power regulator support the power of the NUC740. 4.2 Flash and SDRAM We put boot room, flash and SDRAM on the evaluation board. The boot room sizes are 1 piece 256K*8 bits, PLCC package. They are using the ROM bank. We would put the other flash for application program. The sizes could be 2M*16 or 1M*16 bytes or 0.5M*16 bytes, TSOP package, which used the external I/O bank. The SDRAM has one piece and sizes are 2M*32 bytes. 4.3 PCMCIA connector We support one PCMCIA 16-bits PC Card socket. The main goal destination is which can connects with wireless LAN card. It is using the external memory interface of CPU. We would use bank two and high address, A23, to control I/O or attribute access. 4.4 PHY, WAN port and LAN port This is main function that do broadband gateway. We choose one port PHY IC of DM9161 of the DAVICOM. It supports MII mode and RMII mode. We made connect WAN port and LAN port on board or it can connect with an external wire. The function block would show some connect status LED. We have an extension function, one MII socket. That is for used the daughter board to extension 4 ports switch output. 4.5 JTAG. We used it to connect to CPU with ICE. It’s debug tool. 4.6 UART, 2nd USB and LED Those functions are creating by the programmable I/O ports of CPU. The UART and 2nd USB are optional functions. We used switch to select it. The UART can do console connection or RS232 full function connector. The 2nd USB needs a transceiver or external USB transceiver connects to USB device. The LED function is showing the power on or power off mode. 4.7 USB We have one USB host controller. It is USB 1.1 compliant specification. On the evaluation board, that we would have one power-switch IC. This IC can output current typically limited to 0.85A below the 5A safety requirement. 4.8 Power on setting After power on reset, there are four Power-On setting pins to configure NUC740 system configuration. We must set the next function: • • • • • D15 pin: Internal System Clock Select D14 pin: Big / Little Endian Mode Select D [13:12] : Boot ROM/FLASH Data Bus Width D [11:10] : Test Chip Configuration D [9:8] : Package Type Select Publication Release Date: Apr, 2009 -6- Revision B NUC740 User Manual We would have eight groups jumper setting to do it. On section 5.1 have more improve description. 4.9 Reset schematic We put one schematic on the board. It use reset IC schematic that make sure reset timer is fine. The other things that on board device-reset function would have two choices to do reset function. One is that device has reset schematic on itself side. The other one is which be control by the GPIO of the CPU. We use a keypad for system reset. The push bottom must functional when system is shutdown. 4.10 Power 5V, 3.3V and 1.8V are we needed power. We used external DC 5V adapter supply the board power and used linear regulator change from 5V voltage to the 3.3V voltage and change from 3.3V voltage to 1.8V voltage. We put the 5 linear regulators support CPU power, VDD18, VDD33, USBVDD, DVDD18, AVDD18, that destination is measure the CPU current. 5 Circuit Block Description and Jumper Setting The circuit block has 7 parts. 1. MCU 2. Power Block 3. Memory Block 4. PCMCIA Function Block 5. LAN Block 6. WAN Block 7. USB Function Block The Circuit blocks are shown in FIGURE 2. Publication Release Date: Apr, 2009 -7- Revision B NUC740 User Manual PCMCIA GP20/IRQ3# nWAIT# IRQ2# CS2# nWBE1/SDQM1# MEM_OE# LAN TX1_ERR RESET_LAN/WAN COL1 CRS1 MDIO1 MDC1 TX1_CLK TX1_EN TX1D[0..3] RX1D[0..3] RX1_CLK RX1_DV RX1_ERR TX1_ERR COL1 CRS1 MDIO1 MDC1 TX1_CLK TX1_EN TX1D[0..3] RX1D[0..3] RX1_CLK RX1_DV RX1_ERR COL1 CRS1 MDIO1 MDC1 TX1_CLK TX1_EN TX1D[0..3] RX1D[0..3] RX1_CLK RX1_DV RX1_ERR TX1_ERR VM/nCTS# TXD nTOE#/nDSR# FSE0/nDTR# VO_nCD# RCV/nRI# VP_nRTS# USB_MODE/RXD USB_SUSPND LAN VM/nCTS# TXD nTOE#/nDSR# FSE0/nDTR# VO/nCD# RCV/nRI# VP/nRTS# USB_MODE/RXD USB_SUSPND nWAIT# IRQ2# CS2# CS3# BTCS# MEM_OE# VPP_EN WP#_EN nWBE0/SDQM0# nWBE1/SDQM1# nWBE2/SDQM2# nWBE3/SDQM3# SD_RAS# SD_CAS# SD_MCLK SD_WE# SD_MCKE SD_CS0# SD_CS1# FLASH&SDRAM CS0# CS1# PC_RST PC_RST USB1_ON/OFF USB_SPEED USB_DN USB_DP IRQ1# USB USB_SUSPND USB_MODE/RXD VP/nRTS# RCV/nRI# VO/nCD# FSE0/nDTR# nTOE#/nDSR# TXD VM/nCTS# MEM_A[0..24] MEM_D[0..31] CS3# BTCS# MEM_OE# VPP_EN WP#_EN nWBE0/SDQM0# nWBE1/SDQM1# nWBE2/SDQM2# nWBE3/SDQM3# SD_RAS# SD_CAS# SD_MCLK SD_WE# SD_MCKE SD_CS0# SD_CS1# CS3# BTCS# MEM_OE# VPP_EN WP#_EN nWBE0/SDQM0# nWBE1/SDQM1# nWBE2/SDQM2# nWBE3/SDQM3# SD_RAS# SD_CAS# SD_MCLK SD_WE# SD_MCKE SD_CS0# SD_CS1# CPU USB PCMCIA MEMORY MEM_A[0..24] MEM_D[0..31] MEM_A[0..24] MEM_D[0..31] IRQ1# USB_DP USB_DN WAN COL0 CRS0 MDIO0 MDC0 TX0_CLK TX0_EN TX0D[0..3] RX0_CLK RX0_DV RX0_ERR RX0D[0..3] RESET_LAN/WAN TX0_ERR IRQ1# USB_DP USB_DN USB_SPEED USB1_ON/OFF TX0_ERR CPU COL0 CRS0 MDIO0 MDC0 TX0_CLK TX0_EN TX0D[0..3] RX0_CLK RX0_DV RX0_ERR RX0D[0..3] RESET_LAN/WAN COL0 CRS0 MDIO0 MDC0 TX0_CLK TX0_EN TX0D[0..3] RX0_CLK RX0_DV RX0_ERR RX0D[0..3] RESET_LAN/WAN TX0_ERR GP20/IRQ3# WAN GP20/IRQ3# nWAIT# IRQ2# PC_RST CS2# nWBE1/SDQM1# MEM_OE# MEM_A[0..24] MEM_D[0..31] POWER USB_SPEED USB1_ON/OFF POWER ETHERENT -WAN: MAC0 ONE PORT -LAN: MAC1 ONE POET -Expansion Function Connector USB PCMCIA Memory -USB1: Direct connect from CPU -BANK 3 -Flash: Boot ROM(64kX16) BTSC# & BANK 3 (2MX16) CS3#, -USB2 & UART: Switching function -A23: Attribute or I/O Select Power MCU NUC740 -Probe Header -Supply 1.8V, 3.3V and 5V Power -SDRAM: 2MX32 two pieces, two banks Title NUC740 EVB Size B Document Number NUC740 EVB Date: Monday , April 06, 2009 Rev A Sheet 1 of 8 FIGURE 2: Circuit Function Block 5.1 MCU The MCU Block consists of 8/16/32 bits RISC controller NUC740, clock generator, reset circuit, display LED, boot up setting and muti-ice connector. • The 8/16/32 bits CPU NUC740 is our production. We have connector that is the same pin with NUC740 for easy debugging. • The 15MHZ crystal is must mount on the board. RC22 1M YC1 15MHz CC1 20P CC2 20P FIGURE.3: Clock Generator Publication Release Date: Apr, 2009 -8- Revision B NUC740 User Manual • We used the MIC811 reset IC that make sure reset time more than 240ms. The function of the device is to assert a reset if either the power supply drops below a designated reset threshold level or MR# is forced low. This function take more ensure for system. The other thing is that have a buffer to make sure reset signal fan out is enough. We used a “and” gate to association reset signal come from JTAG and MIC811 (Reset IC). 5VD UC3 1 RESET# 2 GND 4 vcc U9 3 RESET# MR# 1 2 TOP SWITCH MIC811 FIGURE 4: Reset schematic We have expansion function is show the status by 7 LEDs that control by GPIO of the NUC740CD. They are GPIO0, GPIO1, GPIO2, GPIO3, GPIO15 and GPIO16. Function EBI Test GDMA Test Cache On/Off APB module MAC & NAT USB test GPIO GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 15 GPIO 16 Signal Name LMD0 LMD1 LMD2 LMD3 E0 E1 • 5VD RC101 1K RC103 1K RC104 1K RC105 1K RC106 1K RC107 1K DC2 LED GREEN E1 DC3 LED GREEN E0 DC4 LED GREEN LMD3 DC5 LED GREEN LMD2 DC7 LED GREEN LMD1 DC8 LED GREEN LMD0 FIGURE 5: Status LED • The power on setting that we follow next table. Power-On Setting Internal System Clock Select Little/Big Endian Mode Select Boot ROM/FLASH Data Bus Width Test Chip ConFiguration Package Type Select Pin D15 (JP8) D14 (JP7) D [13:12] (JP6, JP5) D [11:10] Fixed D [9:8] (JP2, JP1) Publication Release Date: Apr, 2009 -9- Revision B NUC740 User Manual 3V3 3V3 JP1 RC86 RC80 10K JP7 RC87 1 2 3 MEM_D8 3V3 1 2 3 MEM_D14 10K MEM_D11 10K HEADER 3 HEADER 3 3V3 JP2 RC88 3V3 MEM_D9 MEM_D12 RC89 HEADER 3 10K 3V3 3V3 JP5 1 2 3 1 2 3 4.7K JP8 RC90 1 2 3 MEM_D15 10K HEADER 3 HEADER 3 3V3 RC81 10K JP6 RC91 1 2 3 MEM_D13 MEM_D10 4.7K HEADER 3 JP8: JP8: JP7: JP7: LO--external clock from EXTAL pin is served as internal system clock HI-- PLL output clock is used as internal system clock HI--the external memory format is Little Endian mode LO--the external memory format is Big Endian mode JP6 JP5 BUS WIDTH JP2 JP1 PACKAGE LO LO 8 BITS LO LO RESERVED LO HI 16 BITS LO HI 128 PINS HI LO 32 BITS HI LO 160 PINS HI HI RESERVED HI HI 176 PINS FIGURE 6: Power on setting • JTAG interface: We put two kinds JTAG connector for ICE. In which one has 20 pins and the other has 14 pins. JP61 decide the JATG power is 3.3V or 5V. 3V3 JP61 POWER 5VD 1 2 3 HEADER 3 Publication Release Date: Apr, 2009 - 10 - Revision B NUC740 User Manual POWER RC35 SHORT JC2 2 4 6 8 10 12 14 16 18 20 1 3 5 7 9 11 13 15 17 19 nTRST# TDI TMS TCK TDO nSRST# 1 3 5 7 9 11 13 5VD RC46 SHORT CON20A JC1 2 4 6 8 10 12 14 RC44 0R POWER nTRST# TDI TMS TCK TDO RC85 10K 5VD 5VD nSRST# 10K TDI CON14A 5VD RC82 10K RC83 10K RC67 RC110 RC67 TMS RC84 10K 10K TCK nSRST# 0R NO ON Figure 8: JTAG Connector 5.2 Power We used 5V 3A adapter for the evaluation board. We planned use 2 pieces of 1A current regulator change voltage from 5V to 3.3V. One supports the peripheral power that are PHY and memory. The other one only support to NUC740. The CPU core power is come from 1.8V regulator. We used the inductor to separator the analog and digital power. We put the fuse on the voltage input side for measure the current of NUC740. We had put a switch on the power input line that can let the power shut down and did not DC 5V on the PCBA. If LAN port needs supply four ports. The 2.5V power would come from the other 2.5V regulator. The Power flow chart was show in FIGURE 8. Publication Release Date: Apr, 2009 - 11 - Revision B NUC740 User Manual PHY:3V3_VDD 3V3 _AVDD OSC 1. Power supply flow chart LED Flash & SDRAM 3.3V 1A regulator USB 3.3V On Daughter Board DC 5V 1.8V regulator 2.5V regulator Kendin 4 ports PHY CPU core 3.3V 1A regulator 1.8V regulator RS232 IC CPU PLL Digital Voltage CPU PLL Analog Voltage CPU I/O 3.3V— 3V3 FIGURE.8: Power flow chart 5.3 Memory Block The memory block includes three parts: 128k*8 boot ROM, 2M*16 bits for application program and 512*4*32 M bits SDRAM. The UF1 is 128k*8 boot ROM. The JP62 must short pin1 and pin 2. The JP63 must short pin1 and pin2 for UF2 that saved the application program. When the user uses the UF2 flash memory connects to boot rom bank that JP62 must open and JP63 must short pin 2,3. When you do this change that you must take care the boot room type. PVF RF16 10K JP62 BTCS# BOOTER_CE# CE# 1 2 JP63 CS3# BTCS# HEADER 2 CS3# FLASH_CE# CE# 1 2 3 HEADER 3 SDRAM size is 512*4 Banks*32 bits. We use the Nuvoton solution W986432DH. We connect with SDRAM follow rule of the FIGURE 8. Publication Release Date: Apr, 2009 - 12 - Revision B NUC740 User Manual A [ 1 0 :0 ] A [ 2 4 :0 ] A [ 1 0 :0 ] A 1 3 B S 0 A 1 4 B S 1 D [ 3 1 :0 ] D Q [ [ 3 1 :0 ] M C LK C LK C K E M C K E n S C S 0 n S C S [ 1 :0 ] n C S n S R A S n R A S n S C A S n C A S n S W E n W E n S D Q M [ 3 :0 ] n S D Q M [ 3 :0 ] D Q M [ 3 :0 ] S D R A M 6 4 M b 5 1 2 K x 4 x3 2 N U C 7 4 0 FIGURE 8: SDRAM Interface 5.4 PCMCIA Function Block The PCMCIA function is using one bank of the external memory that is the bank 2. We select I/O and attribute memory Read/Write by address A23. When A23 is ‘High’ state that memory is access I/O memory. If A23 is ‘Low’ state that memory is access attribute memory. The PCMCIA function block is used the external bank 2. The CS2# signal must connect with PCMCIA connector. The REG signal control by GPIO20/IRQ3#. The PCMCIA power depends on LI1, LI2, LI3 and LI4. If thePCBA are mounted the LI1 and LI2. The power is 5V. Otherwise, the PCBA are mounted the LI3 and LI4 that the power is 3.3V. RI2 GP20/IRQ3# REG 47 RI4 33R nECS2 20 CE# MEM_A23 19 UI2B EN 11 13 15 17 10 nOE 9 7 5 3 OE# WE# 74F244 RI6 33R 5VD 20 nWBE1 1 UI2A EN 18 16 14 12 IOWR# 5VD IORD# 14 2 4 6 8 74F244 MEM_A23 5 7 10 MEM_A23# UI1C 1 6 MEM_A23# 7404 MEM_A23 ==1 MEM_A23 ==0 I/O R/W Attribute R/W Publication Release Date: Apr, 2009 - 13 - Revision B NUC740 User Manual FIGURE 9: PCMCIA bank selector The PCMCIA signals “VS1, VS2” can select “HI” or “LOW” by the JP64 and JP65 VDD_3.3V JP64 RI8 10K 1 2 3 VS1 HEADER 3 VDD_3.3V JP65 RI9 10K 1 2 3 VS2 HEADER 3 Figure 10 VS1 and VS2 jump selector 5.5 LAN & WAN Function Blocks In LAN and WAN block that we used 10/100 physical layer IC DM9161 of the DAVICOM. It can support MII and RMII mode. We let reset signal come from two schematic. One connects to reset system. The other is local RC reset schematic. Which one used depends by system design. They (JP16, JP36) show on the FIGURE 11. 3V3_VDD JP16 RL2 100K 3 2 1 RESET_LAN/WAN RESET# HEADER 3 CL1 10uF . FIGURE 11: Reset Schematic The LAN clock is come from two kind parts too. They are crystal and OSC. The FIGURE 12 is their schematic. Publication Release Date: Apr, 2009 - 14 - Revision B NUC740 User Manual XT1 YL2 JP26 RL20 OUT XT1 1 2 3 8 33 25/50 MHz CL21 22pF HEADER 3 REF_CLK YL1 25 MHz XT2 RL25 XT2 0R CL22 22pF RX1_CLK FIGURE 12: LAN Clock generator In order to make sure that expand function work well. We control on/off MII signal with the switch—SW1, SW2, SW3 (LAN) and SW4, SW5, SW6 (WAN). We must turn off them, when we test Ethernet expansion function. That can make sure MII signals no influence with others. They show on FIGURE 13 SW2 COL CRS RX_CLK RXD0 RXD1 RXD2 RXD3 MDIO SW3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 COL1 CRS1 RX1_CLK RX1D0 RX1D1 RX1D2 RX1D3 MDIO1 MDC TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 TX_ERR 1 2 3 4 5 6 7 8 SW 1X8 16 15 14 13 12 11 10 9 MDC1 TX1_CLK TX1_EN TX1D0 TX1D1 TX1D2 TX1D3 TX1_ERR SW 1X8 SW4 SW1 RX_DV RX_ERR 1 2 3 4 8 7 6 5 RX1_DV RX1_ERR RX_DV RX_ERR 1 2 3 4 RX0_DV RX0_ERR 16 15 14 13 12 11 10 9 MDC0 TX0_CLK TX0_EN TX0D0 TX0D1 TX0D2 TX0D3 TX0_ERR DIP-4W DIP-4W SW5 COL CRS RX_CLK RXD0 RXD1 RXD2 RXD3 MDIO 8 7 6 5 SW6 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 COL0 CRS0 RX0_CLK RX0D0 RX0D1 RX0D2 RX0D3 MDIO0 MDC TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 TX_ERR 1 2 3 4 5 6 7 8 SW 1X8 SW 1X8 FIGURE 13: LAN and WAN MII Switch In LAN and WAN blocks that have some power on set functions must setting. They show on the next table and FIGURE 14. Publication Release Date: Apr, 2009 - 15 - Revision B NUC740 User Manual Setting Hi Phy address bit 0 1 Phy address bit 1 1 Phy address bit 2 1 Phy address bit 3 1 Phy address bit 3 1 Testmode Normal Option RMII RMII RPTR Repeater mode Scramble Enable Cable/Link Link Power down mode Power Down mode Note1: *:1 is LAN function block. *: 0 WAN Function Block Lo 0 0 0 0 0 Test Mode MII Node mode( default) Disable Without Link Normal mode Note RX*D01: RX*D1 RX*D2 RX*D3 CRS* Rx*_DV COL* RX*_ERR RX*_CLK CBLLNK PWRDWN OP2 OP1 OP0 Function Note 0 0 0 Dual speed 100/10 HDX OP0: COLLED*# OP1: SPDLED*# 0 0 1 Reserved OP2: ACTLED*# 0 1 0 Reversved 0 1 1 Manual select 10TX HDX 1 0 0 Manual select 10TX FDX 1 0 1 Manual select 100TX HDX 1 1 0 Manual select 100TX FDX 1 1 1 Auto negotiation enable with all capabilities The LAN setting headers are JP17, JP18, JP19, JP20, JP22, JP23, JP27, JP28, JP30, JP31, JP32, JP33, JP21 and JP29. The WAN setting headers are JP37, JP38, JP39, JP40, JP42, JP43, JP45, JP46, JP48, JP49, JP52 JP53, JP41 and JP47. 3V3_VDD JP21 RL34 1 2 3 CBLLNK 3V3_VDD RL35 1 2 3 PWRDWN HEADER 3 10K 10K HEADER 3 WAN_VDD WAN_VDD RW16 JP41 1 2 3 CBLLNK 10K JP29 RW35 1 2 3 PWRDWN HEADER 3 Publication Release Date: Apr, 2009 - 16 - JP47 10K HEADER 3 Revision B NUC740 User Manual WAN_VDD WAN_VDD JP37 PHY Address RXD0 PHYAD0 Pulled low normally RW12 1 2 3 10K JP38 Operating Mode Select RW13 COLLED# OP0 1 2 3 10K HEADER 3 HEADER 3 WAN_VDD WAN_VDD JP39 PHY Address RXD1 PHYAD1 Pulled low normally RW14 1 2 3 10K JP40 Operating Mode Select RW15 SPDLED# OP1 1 2 3 10K HEADER 3 HEADER 3 WAN_VDD WAN_VDD JP42 PHY Address RXD2 PHYAD2 Pulled low normally RW18 1 2 3 10K JP43 Operating Mode Select RW19 ACTLED# OP2 1 2 3 10K HEADER 3 HEADER 3 WAN_VDD WAN_VDD JP45 PHY Address RXD3 PHYAD3 Pulled low normally RW23 1 2 3 10K 0 = Disables Scrambing 1 = Enables Scrambing RW24 RX_CLK SCRAMBLE Pulled low normally 10K JP46 1 2 3 HEADER 3 HEADER 3 WAN_VDD JP48 PHY Address CRS PHYAD4 Pulled low normally RW28 1 2 3 10K WAN_VDD 0 = Node Mode 1 = Repeater Mode RX_ERR RPTR Pulled low normally JP49 RW29 1 2 3 10K HEADER 3 HEADER 3 WAN_VDD 0 = Normal Operation 1 = Enables Test Mode RW32 RX_DV TESTMODE Pulled low normally 10K WAN_VDD JP52 1 2 3 0 = MII 1 = RMII COL RMII Pulled low normally HEADER 3 Publication Release Date: Apr, 2009 - 17 - JP53 RW33 10K 1 2 3 HEADER 3 Revision B NUC740 User Manual 3V3_VDD 3V3_VDD JP17 PHY Address RXD0 PHYAD0 Pulled low normally RL12 1 2 3 10K JP18 Operating Mode Select RL13 COLLED# OP0 1 2 3 10K HEADER 3 HEADER 3 3V3_VDD 3V3_VDD JP19 PHY Address RXD1 PHYAD1 Pulled low normally RL14 1 2 3 10K JP20 Operating Mode Select RL15 SPDLED# OP1 1 2 3 10K HEADER 3 HEADER 3 3V3_VDD 3V3_VDD JP22 PHY Address RXD2 PHYAD2 Pulled low normally RL17 1 2 3 10K JP23 Operating Mode Select RL18 ACTLED# OP2 1 2 3 10K HEADER 3 HEADER 3 3V3_VDD 3V3_VDD JP27 PHY Address RXD3 PHYAD3 Pulled low normally RL22 1 2 3 10K 0 = Disables Scrambing 1 = Enables Scrambing RL23 RX_CLK SCRAMBLE Pulled low normally 10K JP28 1 2 3 HEADER 3 3V3_VDD PHY Address CRS PHYAD4 Pulled low normally RL27 JP30 1 2 3 10K HEADER 3 3V3_VDD 0 = Node Mode 1 = Repeater Mode RX_ERR RPTR Pulled low normally JP31 RL28 1 2 3 10K HEADER 3 HEADER 3 3V3_VDD 0 = Normal Operation 1 = Enables Test Mode RL31 RX_DV TESTMODE Pulled low normally 10K 3V3_VDD JP32 1 2 3 0 = MII 1 = RMII COL RMII Pulled low normally JP33 RL32 10K HEADER 3 1 2 3 HEADER 3 FIGURE 14: Ethernet Power on Setting Publication Release Date: Apr, 2009 - 18 - Revision B NUC740 User Manual 5.6 USB and UART Functions USB is a main function and difference with other broadband router. We have an independent USB port that connect to NUC740 USB function and a second USB port that is connect to GPIO. However, the second USB function is optional with UART function. Our USB is host controller that must supply the current to other device. Therefore, we have a power switch (UU8) to control the current. The 2nd USB is the same (UU6). In order to let 2nd USB and UART function cannot conflict that we used switch to separate the control signal. That is UU1 and UU5, FIGURE 15. UU1 is turn off the UART function. UU5 is turn off the 2nd USB function. You must turn off the switch 1 of the UU5 when use the console and UART function of the NUC740. UU1 UU5 MODE/RXD nTOE#/nDSR# RCV/nRI# VP/nRTS# VM/nCTS# VO/nCD# FSE0/nDTR# 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 TXD MODE/RXD VM/nCTS# nTOE#/nDSR# VO/nCD# RCV/nRI# TXD VP/nRTS# FSE0/nDTR# SW 1X8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SW 1X8 FIGURE 15: Switch devices for 2nd USB and UART The 2nd USB must have a transceiver to improve the function. The control signal is next. GPIO USB UART GP4 RCV nRI GP5 VP nRTS GP6 VM nCTS GP7 VO nCD GP8 FSE0 nTDR GP9 NTOE nDSR GP10 * TXD GP11 USB_Mode RXD GP13 Suspend * Note In order to control the USB power switch. That must select over current protect by GP18/NIRQ1 and control USB function on/off by GP12. Publication Release Date: Apr, 2009 - 19 - Revision B NUC740 User Manual 6 BOM NUC740 EVB Broad of NUC740 Bill Of Materials April 11,2003 15:07:17 Page1 Item Quantity Reference Part ______________________________________________ 1 2 2 78 3 20 4 10 5 6 1 7 7 12 8 9 10 11 12 13 14 15 4 4 2 2 3 1 3 11 16 17 18 19 20 1 2 2 1 1 CC1,CC2 20P CP1,CI1,CF1,CD1,CW2,CL2, 0.1uF CF2,CD2,CW3,CL3,CI3,CD3, CC3,CW4,CP4,CL4,CD4,CC4, CW5,CL5,CF5,CD5,CC5,CU6, CP6,CF6,CD6,CC6,CF7,CD7, CC7,CW8,CP8,CL8,CD8,CC8, CW9,CL9,CD9,CC9,CW10, CL10,CD10,CC10,CU11,CD11, CC11,CD12,CC12,CW13,CL13, CC13,CP14,CC14,CD15,CC15, CD16,CW17,CP17,CL17,CD17, CW18,CP18,CL18,CD18,CW19, CL19,CD19,CP20,CD20,CD21, CD22,CP23,CD23,CP24,CD24, CD25,CD26 CI2,CI4,CP5,CP7,CF8,CF10, 47U 16V CP13,CD13,CD14,CP15,CC16, CC17,CC18,CP19,CC19,CC20, CP21,CC21,CD27,CD28 CC22,CW23,CL23,CC24,CC25, 10P NO ON CC26,CC28,CC29,CC37,CC38 CC23 10P CU8,CU10,CF11,CW12,CL12, 0.01UF CW16,CL16 CW1,CL1,CU3,CU4,CU5,CU9, 10UF 16V CW14,CL14,CW15,CL15,CP16, CP22 CW6,CL6,CW7,CL7 0.1uF 2KV CW21,CL21,CW22,CL22 22pF CONU1,CONU2 USB CON CP3,CP2 100UF 16V CU1,CU7,CU12 33uF/16V CU2 1UF 16V DW1,DL1,DC1 RED DC2,DW3,DL3,DC3,DC4,DC5, GREEN DC7,DC8,DC9,DC10,DC11 DC6 3.0V ZENER DL2,DW2 YELLOW DL4,DW4 ORG JC1 CON14A JC2 CON20A Publication Release Date: Apr, 2009 - 20 - Revision B NUC740 User Manual 21 22 23 24 2 2 2 42 25 26 27 28 29 30 31 2 1 1 5 2 2 27 32 33 34 2 4 18 35 36 37 38 2 1 3 62 39 16 40 41 42 1 2 53 JC3,JC4 CON1 JL1,JW1 CON26A JL2,JW2 RJ-45L JP1,JP2,JP5,JP6,JP7,JP8, HEADER 3 JP16,JP17,JP18,JP19,JP20, JP21,JP22,JP23,JP26,JP27, JP28,JP29,JP30,JP31,JP32, JP33,JP36,JP37,JP38,JP39, JP40,JP41,JP42,JP43,JP44, JP45,JP46,JP47,JP48,JP49, JP52,JP53,JP61,JP63,JP64, JP65 JP14,JP12 HEADER 22X2 JP13 HEADER 16X2 JP15 HEADER 5X2 JP24,JP50,JP51,JP55,JP62 HEADER 2 J4,J5 HEADER 30 J7,J6 HEADER 30X2 LP1,LF1,LD1,LC1,LW2,LP2, FB LL2,LF2,LC2,LL3,LI3,LF3, LW4,LP4,LL4,LI4,LC4,LW5, LP5,LL5,LC5,LW6,LP6,LC6, LC7,LC8,LC9 LI1,LI2 NO USE LU1,LU2,LU3,LU4 FB1206 PR1,PR2,PR3,PR4,PR5,PR6, 33PR PR7,PR8,PR9,PR10,PR11, PR12,PR13,PR14,PR15,PR16, PR17,PR18 QF1,QF2 BC558 NO ON QF3 BC548B RC1,RI4,RI6 33R RI2,RC2,RI3,RC3,RC4,RI5, 47 RC5,RC6,RC7,RP8,RC8,RC9, RC10,RC11,RC12,RC13,RC14, RC15,RC16,RC17,RC18,RC19, RC23,RC24,RC25,RC26,RC27, RC28,RC29,RC30,RC33,RC34, RC36,RC37,RC40,RC41,RC42, RC43,RC45,RC47,RC48,RC49, RC52,RC53,RC54,RC55,RC58, RC59,RC60,RC61,RC62,RC63, RC64,RC65,RC66,RC69,RC70, RC71,RC72,RC73,RC78,RC79 RU3,RF8,RF10,RU12,RC20, 0R RC21,RL25,RW26,RC31,RC32, RC38,RC39,RC44,RC50,RC51, RC68 RC22 1M RC56,RC57 NO ON RU1,RI1,RU2,RP3,RI7,RI8, 10K RI9,RI10,RI11,RW12,RL12, Publication Release Date: Apr, 2009 - 21 - Revision B NUC740 User Manual 43 44 45 3 4 10 46 47 1 5 48 49 50 51 4 2 2 8 52 8 53 54 2 8 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 2 2 3 1 1 1 4 2 1 2 6 1 1 1 1 1 2 1 1 2 1 1 2 2 1 RI12,RW13,RL13,RI13,RW14, RL14,RI14,RW15,RL15,RW16, RL17,RW18,RL18,RW19,RL22, RW23,RL23,RW24,RL27,RW28, RL28,RW29,RL31,RW32,RL32, RW33,RL33,RW34,RL34,RW35, RL35,RC67,RC80,RC81,RC82, RC83,RC84,RC85,RC86,RC87, RC88,RC90 RW1,RL2,RC74 100K RF15,RC75,RC89,RC91 4.7K RU5,RP9,RF13,RC100,RC101, 1K RC103,RC104,RC105,RC106, RC107 RC102 10 RW36,RL36,RC108,RC109, 0R NO ON RC110 RF6,RF7,RF9,RF11 4.7K NO ON RF12,RF14 47K RL1,RW3 1.5K RW2,RL3,RW4,RL4,RW5,RL5, 50R 1% RW10,RL10 RW6,RL6,RW7,RL7,RW8,RL8, 75R 1% RW9,RL9 RL11,RW11 6.8K RL16,RW17,RL21,RW22,RL26, 300R RW27,RL30,RW31 RL20,RW21 33 RP6,RP1 2K RP2,RP5,RP7 1.2K RP4 560R RP10 560 RU4 100 RU6,RU7,RU8,RU9 15K RU10,RU11 27 SP1 POWER SW SW1,SW4 DIP-4W UU1,SW2,SW3,UU5,SW5,SW6 SW 1X8 UC1 NUC740 UC3 MIC811 UC4 7408 UC5 74HC04 UC6 TOP SWITCH UD2,UD1 512X4X32 64M UF1 W39L010 UF2 W28J160B/T 2MX16 UI1,UF4 7404 UI2 74F244 UI3 PCMCIA SOCKET UL1,UW1 PE-68515L UL2,UW2 DM9161 UP1 Power CON Publication Release Date: Apr, 2009 - 22 - Revision B NUC740 User Manual 80 81 82 83 84 85 86 87 88 89 2 1 1 1 1 1 8 1 2 2 UP2,UP4 MIC29152 UP3 MSOP-8 MIC3975 UU2 MAX241/SO UU6 AP1212H UU7 CONNECTOR DB9 Female UU8 PDIUSBP11A U1,U2,U4,U5,U6,U7,U8,U9 Nuvoton Logo YC1 15MHz YL1,YW1 25 MHz YL2,YW2 25/50 MHz Publication Release Date: Apr, 2009 - 23 - Revision B NUC740 User Manual 7 Schematic PCMCIA GP20/IRQ3# nWAIT# IRQ2# CS2# nWBE1/SDQM1# MEM_OE# LAN TX1_ERR RESET_LAN/WAN COL1 CRS1 MDIO1 MDC1 TX1_CLK TX1_EN TX1D[0..3] RX1D[0..3] RX1_CLK RX1_DV RX1_ERR TX1_ERR COL1 CRS1 MDIO1 MDC1 TX1_CLK TX1_EN TX1D[0..3] RX1D[0..3] RX1_CLK RX1_DV RX1_ERR COL1 CRS1 MDIO1 MDC1 TX1_CLK TX1_EN TX1D[0..3] RX1D[0..3] RX1_CLK RX1_DV RX1_ERR TX1_ERR VM/nCTS# TXD nTOE#/nDSR# FSE0/nDTR# VO_nCD# RCV/nRI# VP_nRTS# USB_MODE/RXD USB_SUSPND LAN VM/nCTS# TXD nTOE#/nDSR# FSE0/nDTR# VO/nCD# RCV/nRI# VP/nRTS# USB_MODE/RXD USB_SUSPND nWAIT# IRQ2# CS2# MEM_A[0..24] MEM_D[0..31] CS3# BTCS# MEM_OE# VPP_EN WP#_EN nWBE0/SDQM0# nWBE1/SDQM1# nWBE2/SDQM2# nWBE3/SDQM3# SD_RAS# SD_CAS# SD_MCLK SD_WE# SD_MCKE SD_CS0# SD_CS1# FLASH&SDRAM CS0# CS1# PC_RST PC_RST USB1_ON/OFF USB_SPEED USB_DN USB_DP IRQ1# USB USB_SUSPND USB_MODE/RXD VP/nRTS# RCV/nRI# VO/nCD# FSE0/nDTR# nTOE#/nDSR# TXD VM/nCTS# CS3# BTCS# MEM_OE# VPP_EN WP#_EN nWBE0/SDQM0# nWBE1/SDQM1# nWBE2/SDQM2# nWBE3/SDQM3# SD_RAS# SD_CAS# SD_MCLK SD_WE# SD_MCKE SD_CS0# SD_CS1# CS3# BTCS# MEM_OE# VPP_EN WP#_EN nWBE0/SDQM0# nWBE1/SDQM1# nWBE2/SDQM2# nWBE3/SDQM3# SD_RAS# SD_CAS# SD_MCLK SD_WE# SD_MCKE SD_CS0# SD_CS1# CPU USB PCMCIA MEMORY MEM_A[0..24] MEM_D[0..31] MEM_A[0..24] MEM_D[0..31] IRQ1# USB_DP USB_DN WAN COL0 CRS0 MDIO0 MDC0 TX0_CLK TX0_EN TX0D[0..3] RX0_CLK RX0_DV RX0_ERR RX0D[0..3] RESET_LAN/WAN TX0_ERR IRQ1# USB_DP USB_DN USB_SPEED USB1_ON/OFF TX0_ERR CPU COL0 CRS0 MDIO0 MDC0 TX0_CLK TX0_EN TX0D[0..3] RX0_CLK RX0_DV RX0_ERR RX0D[0..3] RESET_LAN/WAN COL0 CRS0 MDIO0 MDC0 TX0_CLK TX0_EN TX0D[0..3] RX0_CLK RX0_DV RX0_ERR RX0D[0..3] RESET_LAN/WAN TX0_ERR GP20/IRQ3# WAN GP20/IRQ3# nWAIT# IRQ2# PC_RST CS2# nWBE1/SDQM1# MEM_OE# MEM_A[0..24] MEM_D[0..31] POWER USB_SPEED USB1_ON/OFF POWER ETHERENT -WAN: MAC0 ONE PORT -LAN: MAC1 ONE POET -Expansion Function Connector USB PCMCIA Memory -USB1: Direct connect from CPU -BANK 3 -Flash: Boot ROM(64kX16) BTSC# & BANK 3 (2MX16) CS3#, -USB2 & UART: Switching function -A23: Attribute or I/O Select MCU NUC740 -Probe Header Power -Supply 1.8V, 3.3V and 5V Power -SDRAM: 2MX32 two pieces, two banks Title NUC740 EVB Publication Release Date: Apr, 2009 - 24 - Size B Document Number NUC740 EVB Date: Monday , April 06, 2009 Rev A Sheet 1 Revision B of 8 NUC740 User Manual RX0_ERR RX0_DV JW1 RX1_ER R RX1_CLK RX1_DV RC22 1M TXW_ER R TX1_ERR RC109 15MHz 0R NO ON CC1 20P CC2 20P CON26A JL1 Write Enable # JC3 CON1 JP61 0R JC4 1 2 3 CON1 HEADER 3 5VD UC6 1 RC69 RC70 RC71 RC72 RC73 10P SD_MCKE SD_WE# SD_RAS# SD_CAS# SD_MCLK 1 3V3 47 47 47 47 47 MCKE SWE# RAS# CAS# MCLK VDD33 LC2 VDD33 FB LC4 FB UC3 LC6 UC4A & 7 3 4 5 6 7 LC8 Q0 A3 A1 Q3 Q1 A4 A2 Q4 Q2 A5 GND Q5 MEM_D31 MEM_D30 MEM_D29 MEM_D28 5 6 7 8 MEM_D27 MEM_D26 MEM_D25 MEM_D24 5 6 7 8 MEM_D23 MEM_D22 MEM_D21 MEM_D20 5 6 7 8 MEM_D19 MEM_D18 MEM_D17 MEM_D16 5 6 7 8 AVDD18 FB AVDD18 DVDD18 FB DVDD18 33PR PR7 4 3 2 1 5 6 7 8 10K 5 6 7 8 MEM_D7 MEM_D6 MEM_D5 MEM_D4 5 6 7 8 MEM_D3 MEM_D2 MEM_D1 MEM_D0 3V3 PR4 RC1 33R 10K 3V3 10K MEM_D14 MEM_D11 10K GREEN LMD2 DC7 GREEN LMD1 DC8 GREEN 1K 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 LMD0 USBVCC DN GP9 GP7 D31 D29 D27 VSS33 VDD33 D23 VSS18 D21 D19 D17 D15 D13 VDD33 D11 D9 D7 D5 D3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 VSS33 VDD33 A23 A21 A19 A17 A15 VSS33 VDD33 A11 VSS18 A9 A7 A5 A3 A1 VSS33 VDD33 RAS# MCKE TACK DQM2 HEADER 3 3V3 3V3 JP5 1 2 3 MEM_D12 RC89 HEADER 3 1 2 3 4.7K RC81 JP8 RC90 1 2 3 MEM_D15 10K HEADER 3 PR6 JP6 RC91 10K MEM_D13 33PR 1 2 3 MEM_D10 33PR 33PR 4.7K HEADER 3 HEADER 30X2 J7 GP1 GP3 USB_PW TMS1 VDD18 TDO1 TRST# GP15 EMACK WAIT# OE# ESC0# ESC2# BT# SCS1# DQM1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 D0 D1 A24 A22 A20 A18 A16 A14 A13 A12 VDD18 A10 A8 A6 A4 A2 A0 MCLK CAS# SWE# TREQ DQM3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 HEADER 30X2 J4 J5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 HEADER 30 HEADER 30 TX0_CLK HEADER 22X2 10P NO ON CC24 JP8: LO--external clock from EXTAL pin is served as internal system clock JP8: HI-- PLL output clock is used as internal system clock JP7: HI--the external memory format is Little Endian mode JP7: LO--the external memory format is Big Endian mode JP2 MEM_A[0..24] MEM_A[0..24] RESET_LAN/WAN PC_RST 1 2 3 HEADER 3 MODE JP15 JP1 PACKAGE JP8 JP4 JP3 JP6 JP5 BUS WIDTH LO LO RESERVED LO LO LO CPU Core Test LO LO 8 BITS LO HI 128 PINS LO LO HI Internal SRAM Test LO HI 16 BITS HI LO 160 PINS LO HI LO DFT Test Mode HI LO 32 BITS HI HI 176 PINS * HI HI Nornal Mode HI HI RESERVED GP17 GP19 GP5 TXD_RS232 VDD33 1 3 5 7 9 2 4 6 8 10 GP18 GP20 GP6 RXD HEADER 5X2 VDD33 47 JP7 RC87 HEADER 3 9 RC79 RC80 JP2 RC76 REMOTE nRESET# 47 GREEN LMD3 DC5 HEADER 16X2 3V3 RC88 10 RC78 GREEN E0 DC4 JP13 MEM_D11 MEM_D10 MEM_D9 MEM_D8 3V3 MEM_D9 11 8 GREEN E1 DC3 HEADER 22X2 3V3 13 74HC04 DC2 1K GP0 GP2 USB_CTL USB_S TDI1 VSS18 TCK1 nRESET# GP16 EMREQ VDD33 VSS33 ESC1# ESC3# SCSO# DQM0 PR8 1 2 3 PR5 14 12 1K MEM_D15 MEM_D14 MEM_D13 MEM_D12 PR9 PR3 33PR 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 PR10 4 3 2 1 33PR VDD18 UC5 2 5 6 7 8 33PR MEM_D8 VDD18 LC7 VCC 4 3 2 1 PR11 4 3 2 1 4 3 2 1 3V3 3 7408 A0 33PR RC86 1 2 3 4 14 1 2 4.7K 1 33PR 4 3 2 1 PR13 4 3 2 1 PR12 33PR 33PR 1V8 MIC811 RC75 100K J6 RX1D[0..3] TX1D[0..3] JP14 MEM_A0 RC74 1K DP USBGND GP8 GP4 D30 D28 D26 D25 D24 VDD18 D22 D20 D18 D16 D14 VSS33 D12 D10 D8 D6 D4 D2 PR14 33PR 33PR JP1 DVSS18 FB FB AVSS18 3 1K RC105 10P NO ON CC25 JP12 USBPOW 1 2 3 4 RESET# MR# 1K RC104 FB nTOE#/nDSR# FSE0/nDTR# VO/nCD# RCV/nRI# 4 3 2 1 8 7 6 5 4 LC5 2 LC1 PR2 PR1 v cc RX1D[0..3] RC103 RC107 47 47 47 47 33PR 1 2 3 4 GND MEM_A1 MEM_A2 MEM_A3 1 USB_DP USB_DN CC23 2 TOP SWITCH RX1D3 RX1D2 RX1D1 RX1D0 RC106 0R 0R A0 A1 A2 5VD DQM2 DQM3 TACK TREQ 1 RC68 POWER NUC740 VDD33 3V3 USBVCC DP RC31 DN RC32 USBGND GP9 RC33 GP8 RC34 GP7 RC36 GP4 RC37 D31 D30 D29 D28 D27 D26 VSS33 D25 VDD33 D24 D23 VDD18 VSS18 D22 D21 D20 D19 D18 D17 D16 D15 D14 VSS33 D13 VDD33 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 nSRST# 8 7 6 5 10K nSRST# 0R NO ON 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 MEM_A24 RC67 MEM_A20 1 MEM_A21 2 MEM_A22 3 MEM_A23 4 CON14A 5VD 8 7 6 5 nTRST# TDI TMS TCK TDO 33PR 8 7 6 5 3.0V ZENER DC6 1 2 3 4 CON20A JC1 RX0D3 RX0D2 RX0D1 RX0D0 RC101 RX0_CLK 10P NO ON TX0D[0..3] RX0D[0..3] USBPOW RC102 10 USBVDD DP DN USBVSS GP9/nDSR# GP8/nDTR# GP7/nCD# GP4/nRI# D31 D30 D29 D28 D27 D26 VSS33 D25 VDD33 D24 D23 VDD18 VSS18 D22 D21 D20 D19 D18 D17 D16 D15 D14 VSS33 D13 VDD33 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 MEM_A12 MEM_A13 MEM_A14 MEM_A15 RC46 SHORT TXID0 TXID1 TXID2 TXID3 TXI_EN COL1 CRS1 MDIO1 VSS33 MDC1 TX1_CLK VDD33 GP0 GP1 GP2 GP3 GP12/nWDOG# GP13/TIMER0 GP14/TIMER1 TMS TDI VDD18 VSS18 TDO TCK nTRST# nRESET# GP15/nXDACK GP16/nXDREQ EMACK EMREQ nWAIT# VDD33 nOE VSS33 nECS0# nECS1# nECS2# nECS3# nBTCS# nSCS0# nSCS1# SDQM0 SDQM1 MEM_A168 MEM_A177 MEM_A186 MEM_A195 TDO nSRST# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1K 5VD 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 10P NO ON CC22 TXLD0 TXLD1 TXLD2 TXLD3 RX1_CLK CC26 TX0D[0..3] RX0D[0..3] PR17 8 7 6 5 PR15 1 TX1D0 2 TX1D1 3 TX1D2 4 TX1D3 DC1 47 8 7 6 5 nTRST# TDI TMS TCK RC110 TX1_CLK MEM_A8 MEM_A9 MEM_A10 MEM_A11 JC2 1 3 5 7 9 11 13 UC1 RC84 10K TCK RC100 PR18 1 2 3 4 33PR 8 7 6 5 TX0D3 TX0D2 TX0D1 TX0D0 TX1D[0..3] 5VD RED RC30 GP17 1 2 3 4 RC35 SHORT 2 4 6 8 10 12 14 RC83 10K TMS MEM_A4 MEM_A5 MEM_A6 MEM_A7 POWER 1 3 5 7 9 11 13 15 17 19 RC82 10K TDI TXLD0 TXLD1 TXLD2 TXLD3 TX1_EN 47 RC14 TXL_EN TX1_EN COL1 47 RC15 COL_L COL1 CRS1 47 RC16 CRS_L CRS1 MDIO1 47 RC17 MDIO_L MDIO1 VSS33 MDC1 47 RC18 MDC_L MDC1 TX1_CLK 47 RC19 TXL_CLK TX1_CLK VDD33 LMD0 RC20 0R GP0 VPP_EN LMD1 RC21 0R GP1 WP#_EN 0R GP2 LMD2 RC38 WATCHDOG LMD3 RC39 0R GP3 USB1 RC40 47 USB_CTL USB1_ON/OFF RC41 47 USB_PW USB_SUSPND RC42 47 USB_S USB_SPEED TMS RC43 47 TMS1 RC44 5VD TDI RC45 47 TDI1 0R VDD18 VSS18 TDO RC47 47 TDO1 47 TCK1 TCK RC48 nTRST# RC49 47 TRST# POWER RC85 nRESET# E0 RC50 0R GP15 0R E1 RC51 GP16 RC52 47 EMACK 10K RC53 47 EMREQ WAIT# RC54 47 nWAIT# VDD33 MEM_OE# RC55 47 OE# MEM_OE# VSS33 MEM_READ RC56 NO ONESC0# CS0# RC57 NO ONESC1# CS1# RC58 47 ESC2# CS2# RC59 47 ESC3# CS3# RC60 47 BT# BTCS# SCSO# RC61 47 SD_CS0# SCS1# RC62 47 SD_CS1# RC63 47 DQM0 nWBE0/SDQM0# RC64 47 DQM1 nWBE1/SDQM1# RC65 47 nWBE2/SDQM2# RC66 47 nWBE3/SDQM3# CON26A 2 4 6 8 10 12 14 16 18 20 5VD RXLD3 RXLD2 RXLD1 RXLD0 MEM_D[0..31] VDD33 5VD GND RXL_ERR RXLD0 RXLD1 RXLD3 TXLD0 TXLD2 TXL_EN CRS_L MDC_L TXL_ERR 2 4 6 8 10 12 14 16 18 20 22 24 26 DVSS18 DVDD18 AVSS18 AVDD18 RX1D3 RX1D2 RX1D1 RX1D0 RX1_DV RX1_CLK RX1_ERR VSS33 EXTAL XTAL VDD33 RX0_ERR RX0_DV RX0D3 RX0D2 RX0D1 VSS18 VDD18 RX0D0 RX0_CLK CRS0 COL0 TX0_CLK TX0D3 TX0D2 TX0D1 TX0D0 VSS33 TX0_EN MDIO0 MDC0 VDD33 GP11/RXD GP10/TXD GP6/nCTS# GP5/nRST# GP20/ nIRQ3# GP19/ nIRQ2# GP18/ nIRQ1# GP17/ nIRQ0# 1 3 5 7 9 11 13 15 17 19 21 23 25 IRQ1# USB1 OVERCUR_FLG PR16 8 7 6 5 33PR 1 2 3 4 RXWD3 RXWD2 RXWD1 RXWD0 USB_MODE/RXD TXD VM/nCTS# VP/nRTS# GP20/IRQ3# IRQ2# PCMCIA SDQM2 SDQM3 TACK TREQA MCKE nSWE# nSRAS# nSCAS# VDD33 MCLK VSS33 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 VSS18 VDD18 A12 VDD33 A13 VSS33 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 VDD33 D0 VSS33 D1 VDD33 5VD RXL_CLK GND RXL_DV RXLD2 GND TXLD1 TXLD3 COL_L MDIO_L GND TXL_CLK 33PR 1 2 3 4 MEM_D[0..31] Y C1 RC108 0R NO ON TXL_ERR TXWD3 TXWD2 TXWD1 TXWD0 A3 A4 A5 A6 A7 A8 A9 A10 A11 VSS18 VDD18 A12 VDD33 A13 VSS33 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 VDD33 D0 VSS33 D1 TX0_ERR RX0_ERR RX0_DV RX0_CLK CRS0 COL0 TX0_CLK TX0_EN MDIO0 MDC0 VSS33 MDIO_W TXW_EN TXWD1 TXWD3 CRS_W GND RXW_CLK GND RXWD0 RXWD2 RXW_ERR 5VD VDD33 2 4 6 8 10 12 14 16 18 20 22 24 26 DVSS18 DVDD18 AVSS18 AVDD18 RXLD3 RXLD2 RXLD1 RXLD0 RXL_DV 47 RC13 RX1_DV RC12 RX1_CLK RXL_CLK 47 RXL_ERR 47 RC11 RX1_ERR VSS33 EXTAL XTAL VDD33 RXW_ERR 47 RC10 RX0_ERR 47 RC9 RX0_DV RXW_DV RXWD3 RXWD2 RXWD1 VSS18 VDD18 RXWD0 RXW_CLK 47 RC8 RX0_CLK CRS_W 47 RC7 CRS0 COL_W 47 RC6 COL0 RC5 TX0_CLK TXW_CLK 47 TXWD3 TXWD2 TXWD1 TXWD0 VSS33 TXW_EN 47 RC4 TX0_EN MDIO_W 47 RC3 MDIO0 MDC_W 47 RC2 MDC0 VDD33 RXD 47 RC24 TXD_RS232 47 RC23 GP6 47 RC25 GP5 47 RC26 GP20 47 RC27 GP19 47 RC28 GP18 47 RC29 1 3 5 7 9 11 13 15 17 19 21 23 25 8 7 6 5 MDC_W TXWD0 TXWD2 COL_W GND TXW_CLK GND TXW_ERR RXWD1 RXWD3 RXW_DV 5VD VDD33 VDD18 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC10 CC11 CC12 CC13 CC14 CC15 CC16 CC17 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 47U 16V 47U 16V VSS18 VDD33 VDD33 CC18 CC19 CC20 CC21 47U 16V 47U 16V 47U 16V 47U 16V VSS33 LC9 FB Title NUC740 EVB Size Document Number CustomNUC740 EVB Date: Publication Release Date: Apr, 2009 - 25 - Monday , April 06, 2009 Rev A Sheet Revision B 2 of 8 NUC740 User Manual 3V3 MEM_A[0..24] MEM_D[0..31] FB nWBE0/SDQM0# PVF VF3.3 3D3 5 6 7 8 9 10 11 12 13 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 MEM_A18 MEM_A17 MEM_A7 MEM_A6 MEM_A5 MEM_A4 MEM_A3 MEM_A2 MEM_A1 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET# VPP WP# RY /BY # A18 A17 A7 A6 A5 A4 A3 A2 A1 A16 BY TE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 nWBE1/SDQM1# 29 28 27 26 25 24 23 22 21 MEM_A14 MEM_A13 MEM_A8 MEM_A9 MEM_A11 OE# MEM_A10 BOOTER_CE# MEM_D7 PVF RF16 10K JP62 DGND MEM_D15 MEM_D7 MEM_D14 MEM_D6 MEM_D13 MEM_D5 MEM_D12 MEM_D4 VF3.3 MEM_D11 MEM_D3 MEM_D10 MEM_D2 MEM_D9 MEM_D1 MEM_D8 MEM_D0 VPP_EN VPP Action BTCS# 1 2 HEADER 2 VF3.3 HI HI Full chip lock LO LO Full chip unlock RF7 RF8 0R 4.7K NO ON OE# DGND FLASH_CE# MEM_A0 VPP QF1 VPP_EN W28J160B/T 2MX16 BOOTER_CE# CE# MEM_A10 MEM_A9 MEM_A8 MEM_A7 MEM_A6 MEM_A5 MEM_A4 MEM_A3 MEM_A2 MEM_A1 MEM_A0 24 66 65 64 63 62 61 60 27 26 25 MEM_D31 MEM_D30 MEM_D29 MEM_D28 MEM_D27 MEM_D26 MEM_D25 MEM_D24 MEM_D23 MEM_D22 MEM_D21 MEM_D20 MEM_D19 MEM_D18 MEM_D17 MEM_D16 MEM_D15 MEM_D14 MEM_D13 MEM_D12 MEM_D11 MEM_D10 MEM_D9 MEM_D8 MEM_D7 MEM_D6 MEM_D5 MEM_D4 MEM_D3 MEM_D2 MEM_D1 MEM_D0 56 54 53 51 50 48 47 45 42 40 39 37 36 34 33 31 85 83 82 80 79 77 76 74 13 11 10 8 7 5 4 2 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RF9 BC558 NO ON BTCS# CS3# FLASH_CE# CE# 1 2 3 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD GND GND GND GND GND GND GND GND GND GND GND GND 23 22 19 18 17 20 59 28 71 16 68 67 MEM_A14 MEM_A13 RAS# CAS# SD_WE# SD_CS0# SDQM3# SDQM2# SDQM1# SDQM0# MCLK MCKE 14 21 30 57 69 70 73 SD_RAS# SD_CAS# SD_WE# SD_CS0# nWBE3/SDQM3# nWBE2/SDQM2# nWBE1/SDQM1# nWBE0/SDQM0# SD_MCLK SD_MCKE UD2 MEM_A11 3D3 1 3 9 15 29 35 41 43 49 55 75 81 6 12 32 38 44 46 52 58 72 78 84 86 512X4X32 64M JP63 CS3# N.C N.C N.C N.C N.C N.C N.C DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 4.7K NO ON DGND BA1 BA0 RAS CAS WE CS DQM3 DQM2 DQM1 DQM0 CLK CKE MEM_OE# MEM_A16 MEM_D1 MEM_D2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 14 15 16 17 18 19 20 W39L010 A12 A15 A16 NC VDD WE# NC UF1 MEM_A7 MEM_A6 MEM_A5 MEM_A4 MEM_A3 MEM_A2 MEM_A1 MEM_A0 MEM_D0 UD1 nWBE1/SDQM1# 4 3 2 1 32 31 30 FB MEM_A17 FB FB VF3.3 LD1 MEM_D31 MEM_D30 MEM_D29 MEM_D28 MEM_D27 MEM_D26 MEM_D25 MEM_D24 MEM_D23 MEM_D22 MEM_D21 MEM_D20 MEM_D19 MEM_D18 MEM_D17 MEM_D16 MEM_A12 MEM_A15 MEM_A16 LF3 LF1 UF2 MEM_A15 MEM_A14 MEM_A13 MEM_A12 MEM_A11 MEM_A10 MEM_A9 MEM_A8 MEM_A19 MEM_A20 nWBE1/SDQM1# RST VPP WP# nWBE0/SDQM0# 5VD 3V3 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 MEM_D15 MEM_D14 MEM_D13 MEM_D12 MEM_D11 MEM_D10 MEM_D9 MEM_D8 MEM_D7 MEM_D6 MEM_D5 MEM_D4 MEM_D3 MEM_D2 MEM_D1 MEM_D0 PVF LF2 MEM_D[0..31] MEM_D3 MEM_D4 MEM_D5 MEM_D6 MEM_A[0..24] MEM_A20 MEM_A19 MEM_A18 MEM_A17 MEM_A16 MEM_A15 MEM_A14 MEM_A13 MEM_A12 MEM_A11 MEM_A10 MEM_A9 MEM_A8 MEM_A7 MEM_A6 MEM_A5 MEM_A4 MEM_A3 MEM_A2 MEM_A1 MEM_A0 RF8,RF10 CHCNGE VALUE FROM 47K TO 0R VF3.3 HEADER 3 RF10 0R RF11 4.7K NO ON QF2 RF6 MEM_A10 MEM_A9 MEM_A8 MEM_A7 MEM_A6 MEM_A5 MEM_A4 MEM_A3 MEM_A2 MEM_A1 MEM_A0 24 66 65 64 63 62 61 60 27 26 25 MEM_D31 MEM_D30 MEM_D29 MEM_D28 MEM_D27 MEM_D26 MEM_D25 MEM_D24 MEM_D23 MEM_D22 MEM_D21 MEM_D20 MEM_D19 MEM_D18 MEM_D17 MEM_D16 MEM_D15 MEM_D14 MEM_D13 MEM_D12 MEM_D11 MEM_D10 MEM_D9 MEM_D8 MEM_D7 MEM_D6 MEM_D5 MEM_D4 MEM_D3 MEM_D2 MEM_D1 MEM_D0 56 54 53 51 50 48 47 45 42 40 39 37 36 34 33 31 85 83 82 80 79 77 76 74 13 11 10 8 7 5 4 2 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA1 BA0 RAS CAS WE CS DQM3 DQM2 DQM1 DQM0 CLK CKE N.C N.C N.C N.C N.C N.C N.C DQ31 DQ30 DQ29 DQ28 DQ27 DQ26 DQ25 DQ24 DQ23 DQ22 DQ21 DQ20 DQ19 DQ18 DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD GND GND GND GND GND GND GND GND GND GND GND GND 23 22 19 18 17 20 59 28 71 16 68 67 MEM_A14 MEM_A13 RAS# CAS# SD_WE# SD_CS1# SDQM3# SDQM2# SDQM1# SDQM0# MCLK MCKE 14 21 30 57 69 70 73 SD_RAS# SD_CAS# SD_WE# SD_CS1# nWBE3/SDQM3# nWBE2/SDQM2# nWBE1/SDQM1# nWBE0/SDQM0# SD_MCLK SD_MCKE MEM_A11 3D3 1 3 9 15 29 35 41 43 49 55 75 81 6 12 32 38 44 46 52 58 72 78 84 86 WP# 512X4X32 64M 3D3 BC558 NO ON WP#_EN 4.7K NO ON WP#_EN WP# Action HI HI Boot block unlock LO LO Boot block lock CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 CD11 CD12 CD13 CD14 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 47U 16V 47U 16V VF3.3 PVF CF5 CF6 CF7 CF8 CF10 CF1 CF2 0.1UF 0.1UF 0.1UF 47U 16V 47U 16V 0.1UF 0.1UF 3D3 5VD VCC RF12 47K RF13 1K 5VD CD15 CD16 CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25 CD26 CD27 CD28 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 47U 16V 47U 16V RF14 47K 14 RST RF15 UF4A 1 1 7 7404 CF11 0.01UF 2 4.7K QF3 BC548B Short 1,2 CPU reset Short 2,3 RC reset Title NUC740 EVB Publication Release Date: Apr, 2009 - 26 - Size C Document Number NUC740 EVB Date: Monday , April 06, 2009 Rev A Sheet Revision B 3 of 8 NUC740 User Manual 10/100 Mbps Fast Ethernet PHY 3V3_VDD MDIO JP16 RL3 100K Transformer HEADER 3 10 12 11 CT CT RX- RD- TX+ TD+ CT CT TX- TD- RL8 75R 1% 2KV CL3 0.1uF 50R 1% 2 RX- 16 TX+ 3V3_AVDD 14 15 RL5 3V3_AVDD 50R 1% CL4 0.1uF PE-68515L CL7 UL2 10UF 16V RL4 3 75R 1% 0.1uF 2KV LL4 2KV CL6 75R 1% 75R 1% RL9 RL10 CL5 0.1uF 50R 1% FB RX_DV RX_ERR 3V3_VDD RESET# 3V3_VDD XT2 XT1 DGND 37 38 39 40 41 42 43 44 45 46 47 48 AGND BGRESG TX- RL11 6.8K 1% RXDV/TESTMODE RXER/RXD[4]/RPTR DVDD RESET# DVDD XT2 XT1 DGND NC AGND BGRESG BGRES placed close to pins 47 & 48 as much as possible 0.1uF 2KV Chasis Ground Power-on Reset Settings Latched Inputs 3V3_VDD 1 2 3 10K 1 2 3 10K HEADER 3 3V3_VDD 1 2 3 10K COL CRS RX_CLK RXD0 RXD1 RXD2 RXD3 MDIO MDC 3V3_VDD TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 TX_ERR DGND CBLLNK ACTLED# 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 COL1 CRS1 RX1_CLK RX1D0 RX1D1 RX1D2 RX1D3 MDIO1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 3V3_VDD MDC1 TX1_CLK TX1_EN TX1D0 TX1D1 TX1D2 TX1D3 TX1_ERR TX1D0 RMII TX1D1 TX1_EN RX1D0 RX1D1 RX1_DV CRS_DV RX1_ERR MDC1 MDIO1 REF_CLK TX1_ERR SW 1X8 CL8 CL9 CL10 0.1uF 0.1uF 0.1uF JP20 Operating Mode Select RL15 SPDLED# OP1 3V3LAN 3V3_VDD 3V3_AVDD LL5 FB LL2 FB 3V3_AVDD CL18 CL19 0.1uF 0.1uF CL12 CL13 CL14 0.01UF 0.1uF 10UF 16V CL15 10UF 16V CL21 22pF 5VD RL19,RL24,RL29 REMOTE Y L1 25 MHz HEADER 3 3V3_VDD 1 2 3 3V3_VDD JP27 RL22 1 2 3 10K 0 = Disables Scrambing 1 = Enables Scrambing RL23 RX_CLK SCRAMBLE Pulled low normally 10K PHY Address CRS PHY AD4 Pulled low normally RL27 10K 3V3_VDD 0 = Node Mode 1 = Repeater Mode RX_ERR RPTR Pulled low normally JP31 RL28 1 2 3 10K 3V3_VDD JP32 1 2 3 HEADER 3 7 VCC OUT GND 25/50 MHz RL20 1 2 3 8 33 RL21 DL2 300R Y ELLOW JP24 1 2 HEADER 2 SPDLED# HEADER 3 RL36 LL3 3V3_VDD REF_CLK 0R NO ON RL25 CL23 0R HEADER 3 10K XT2 10P NO ON ACTLED# RL26 DL3 FB 300R JP29 RL35 1 2 3 PWRDWN HEADER 3 10K GREEN RX1_CLK HEADER 3 HEADER 3 3V3_VDD 0 = Normal Operation 1 = Enables Test Mode RL31 RX_DV TESTMODE Pulled low normally 10K 14 1 2 3 RED JP26 HEADER 3 JP30 1 2 3 5V YL2 JP28 HEADER 3 3V3_VDD 300R XT1 HEADER 3 3V3_VDD 3V3_VDD AGND 1 2 3 10K HEADER 3 3V3_AVDD DL1 COLLED# 3V3_VDD Operating Mode Select RL18 ACTLED# OP2 CL22 22pF 3V3_AVDD 1 2 3 RL16 JP23 DGND JP22 PHY Address RXD3 PHY AD3 Pulled low normally 0.1uF JP21 CBLLNK GND 3V3_VDD 10K CL17 0.01uF 3V3_VDD RL34 5V 3V3_VDD XT2 RL17 CL16 XT1 1 2 3 10K HEADER 3 PHY Address RXD2 PHY AD2 Pulled low normally RX1D[0..3] RX1D0 RX1D1 RX1D2 RX1D3 SW3 MDC TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 TX_ERR TX1_CLK TX1_EN TX1_ERR RX1_CLK CRS1 RX1_DV RX1_ERR COL1 MDC1 MDIO1 RX1D[0..3] SW 1X8 TX1D[0..3] 3V3_VDD JP19 RL14 TX1D[0..3] TX1D0 TX1D1 TX1D2 TX1D3 TX1_CLK TX1_EN TX1_ERR RX1_CLK CRS1 RX1_DV RX1_ERR COL1 MDC1 MDIO1 JP18 Operating Mode Select RL13 COLLED# OP0 HEADER 3 PHY Address RXD1 PHY AD1 Pulled low normally 24 23 22 21 20 19 18 17 16 15 14 13 MDC DVDD TXCLK/ISOLATE TXEN TXD[0] TXD[1] TXD[2] TXD[3] TXER/TXD[4] DGND CABLESTS/LINKSTS LINK/ACT LED#/OP2 3V3_AVDD 3V3_AVDD RX+ RXAGND AGND TX+ TX3V3_AVDD PWRDWN COLLED# SPDLED# JP17 RL12 MII RX1_DV RX1_ERR SW2 CC28 1 2 3 4 5 6 7 8 9 10 11 12 DM9161 3V3_VDD PHY Address RXD0 PHY AD0 Pulled low normally 8 7 6 5 DIP-4W 36 35 34 33 32 31 30 29 28 27 26 25 CL2 0.1uF 1 RL6 RL7 1 2 3 4 10P NO ON CL1 RD+ SW1 RX_DV RX_ERR TX_CLK COL/RMII CRS/PHYAD[4] RXCLK/SCRAMEN/10BTSER DGND MDINTR# RXEN DVDD RXD[0]/PHYAD[0] RXD[1]/PHYAD[1] RXD[2]/PHYAD[2] RXD[3]/PHYAD[3] MDIO 6 RX+ 3V3_VDD CC29 AVDD AVDD RX+ RXAGND AGND TX+ TXAVDD PWRDWN FDX/COL LED#/OP0 SPEED LED#/OP1 10 Solder 5 9 Solder NC NC RXNC NC RX+ TXTX+ 7 RJ-45L 8 7 6 5 4 3 2 1 1.5K 10P NO ON 50R 1% UL1 JL2 RESET# RL1 RX_CLK RESET_LAN/WAN 3 2 1 3V3_VDD 3V3_VDD RXD0 RXD1 RXD2 RXD3 MDIO RL2 COL CRS RX_CLK DGND RX+ Switching the external or on broad schematic 0 = MII 1 = RMII COL RMII Pulled low normally RL30 DL4 300R ORG CBLLNK JP33 RL32 10K 1 2 3 RL33 Title 10K Size B Document Number NUC740 EVB Date: Monday , April 06, 2009 HEADER 3 Publication Release Date: Apr, 2009 - 27 - NUC740 EVB Rev A Sheet 4 Revision B of 8 NUC740 User Manual MEM_A[0..24] 14 5VD MEM_A15 MEM_A16 MEM_A17 MEM_A18 MEM_A19 MEM_A20 MEM_A21 MEM_A22 UI1A nRESET 1 1 2 RESET 7 7404 RI10 10K 1 6 MEM_A23# 7 7404 RI2 GP20/IRQ3# RI4 33R 47 MEM_A23 19 EN 9 7 5 3 10 RI6 33R OE# WE# RI11 10K RI12 10K A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 D0 D1 D2 D3 D4 D5 D6 D7 SPKR STSCHG D8 D9 D10 D11 D12 D13 D14 D15 REG CE1 CE2 OE WE/PGM IORD IOWR INPACK IREQ IOIS16 GND GND GND GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CD1 CD2 VS2 VS1 WAIT VPP1 VPP2 RESET VCC VCC 30 31 32 2 3 4 5 6 MEM_D0 MEM_D1 MEM_D2 MEM_D3 MEM_D4 MEM_D5 MEM_D6 MEM_D7 29 28 27 26 25 24 23 22 12 11 8 10 21 13 14 MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 MEM_A14 36 67 57 43 59 RI3 RI5 VS2 VS1 nWAIT 47 47 VDD_3.3V RI1 10K nWAIT nWAIT# nRESET nWBE1 nOE GND GND PC_RST nWBE1/SDQM1# nECS2 RESET 5VD MEM_D[0..31] MEM_D31 MEM_D30 MEM_D29 MEM_D28 MEM_D27 MEM_D26 MEM_D25 MEM_D24 MEM_D23 MEM_D22 MEM_D21 MEM_D20 MEM_D19 MEM_D18 MEM_D17 MEM_D16 IRQ2# 18 52 58 51 17 MEM_A[0..24] MEM_D[0..31] MEM_D15 MEM_D14 MEM_D13 MEM_D12 MEM_D11 MEM_D10 MEM_D9 MEM_D8 MEM_D7 MEM_D6 MEM_D5 MEM_D4 MEM_D3 MEM_D2 MEM_D1 MEM_D0 MEM_OE# IREQ_PCM CS2# VDD_3.3V 5VD VDD_3.3V PCMCIA SOCKET LI1 20 1 61 7 42 9 15 44 45 60 16 33 68 35 34 1 74F244 5VD nWBE1 MEM_A23# OE# WE# IORD# IOWR# INPACK IREQ_PCM UI2B 11 13 15 17 nOE REG CE# CE# 20 nECS2 62 63 64 65 66 37 38 39 40 41 MEM_D8 MEM_D9 MEM_D10 MEM_D11 MEM_D12 MEM_D13 MEM_D14 MEM_D15 UI1C 5 20 19 46 47 48 49 50 53 54 55 56 MEM_A24 MEM_A25 14 5VD MEM_A23 MEM_A24 MEM_A23 MEM_A22 MEM_A21 MEM_A20 MEM_A19 MEM_A18 MEM_A17 MEM_A16 MEM_A15 MEM_A14 MEM_A13 MEM_A12 MEM_A11 MEM_A10 MEM_A9 MEM_A8 MEM_A7 MEM_A6 MEM_A5 MEM_A4 MEM_A3 MEM_A2 MEM_A1 MEM_A0 UI3 LI2 UI2A EN 2 4 6 8 VDD_3.3V 18 16 14 12 3V3 NO USE 3.3V NO USE IOWR# RI7 LI3 10K LI4 INPACK IORD# FB 10 FB MEM_A23 ==1 MEM_A23 ==0 GND 74F244 I/O R/W Attribute R/W VDD_3.3V CI1 0.1UF CI2 47U 16V GND CI3 0.1UF CI4 47U 16V VDD_3.3V JP64 RI8 10K RI9 10K RI13 10K RI14 10K 1 2 3 VS1 HEADER 3 VDD_3.3V JP65 VS2 1 2 3 HEADER 3 Title NUC740 EVB Publication Release Date: Apr, 2009 - 28 - Size B Document Number NUC740 EVB Date: Monday , April 06, 2009 Rev 0.1 Sheet 5 Revision B of 8 NUC740 User Manual 1V8 1.8V LP2 47 GREEN RP8 JP55 1 2 DC9 FB HEADER 2 5VD LP1 SP1 CP7 47U 16V GREEN RP9 1 FB GND POWER SW GND 1K CP6 0.1UF CP8 0.1UF 47U 16V IN DC10 CP3 CP2 CP1 0.1UF 2 Power CON 3 CP5 5V UP1 CP4 0.1UF 100UF 16V 100UF 16V LP5 3V3 FB 5VD 3V LP4 560 UP2 3V CP16 CP17 0.1UF EN OUT IN GND 2 3 1 ADJ GREEN RP10 4 RP1 5 DC11 FB 2K CP14 CP13 MIC29152 47U 16V 10UF 16V CP15 CP18 0.1UF 0.1UF 47U 16V RP2 RP3 10K 1.2K UP3 8 7 6 5 3V3LAN 5VD 3.3V LP6 UP4 1 1.8V MSOP-8 MIC3975 1.2K 2 CP22 10UF 16V CP23 0.1UF EN OUT IN GND RP5 RP4 EN GND IN GND ADJ GND OUTPUT GND 3 560R 1 2 3 4 ADJ 4 RP6 5 FB 2K CP19 MIC29152 47U 16V CP24 0.1UF CP20 0.1UF CP21 47U 16V RP7 1.2K Title NUC740 EVB Publication Release Date: Apr, 2009 - 29 - Size B Document Number NUC740 EVB Date: Monday , April 06, 2009 Rev 0.1 Sheet 6 of Revision B 8 NUC740 User Manual USB_DP USB_DN D1+ D1- UU1 MODE/RXD VM/nCTS# nTOE#/nDSR# VO/nCD# RCV/nRI# TXD VP/nRTS# FSE0/nDTR# USB HOST 5VD 5VD TXD CU1 RU1 5VD 33uF/16V UU6 LU1 10K USB1_ON/OFF IRQ1# USB_ON/OFF FLAG1 RU4 RU3 100 0R 1 2 3 4 CTL1 OUT1 FLG1 IN FLG2 GND CTL2 OUT2 8 7 6 5 CONU1 FB1206 1 CU6 CU7 CU8 0.1uF 33uF/16V 0.01uF D1D1+ 2 3 4 AP1212H RU5 RU2 CU2 16 15 14 13 12 11 10 9 1UF 16V SW 1X8 10K VBUS DD+ UU2 1 2 3 4 5 6 7 8 CU3 5VD CU5 10UF 16V 10UF 16V 8 5 26 22 19 7 6 20 21 24 25 12 14 13 11 GND RU6 RU7 15K 15K EN# SHUTDOWN C1+ C2+ C1C2V+ VVCC GND 9 4 27 23 18 2 3 1 28 15 16 17 10 1 CU12 CU10 33uF/16V 0.01uF FB1206 LU4 D2D2+ 2 3 4 RU8 RU9 15K UU8 UU5 USB_MODE/RXD nTOE#/nDSR# RCV/nRI# VP/nRTS# VM/nCTS# USB_SUSPND VO/nCD# FSE0/nDTR# MODE/RXD nTOE#/nDSR# RCV/nRI# VP/nRTS# VM/nCTS# VO/nCD# FSE0/nDTR# 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 MODE OE# RCV VP VM SUSPND VPO VMO 1 2 3 4 5 6 7 MODE VCC OE# VMO/FSEO RCV VPO VP D+ VM DSUSPND SPEED GND NC 10UF 16V CU9 CONNECTOR DB9 Female 5 9 4 8 3 7 2 6 1 RI DTR CTS TXD_R RTS RXD DSR DCD CONU2 FB1206 CU4 10UF 16V 1K LU2 RXD CTS DSR DCD RI TXD_R RTS DTR MAX241/SO USB CON FB1206 LU3 R1OUT R1IN R2OUT R2IN R3OUT R3IN R4OUT R4IN R5OUT R5IN T1IN T1OUT T2IN T2OUT T3IN T3OUT T4IN T4OUT VBUS DD+ UU7 GND Female USB CON 15K 3V3 14 13 12 11 10 9 8 3V3 VMO VPO RU10 RU11 SPEED 27 27 D2+ D2USB_SPEED 3V3 SW 1X8 RU12 PDIUSBP11A CU11 0R 0.1uF Title NUC740 EVB Publication Release Date: Apr, 2009 - 30 - Size B Document Number NUC740 EVB Date: Monday , April 06, 2009 Rev 0.1 Sheet 7 Revision B of 8 NUC740 User Manual WAN_VDD 10/100 Mbps Fast Ethernet PHY RW2 100K 50R 1% Transformer 6 10 12 11 RX+ RD+ CT CT RX- RD- TX+ TD+ CT CT TX- TD- 50R 1% 2 RX- 16 TX+ WAN_AVDD 14 15 RW9 PE-68515L RW10 75R 1% 0.1uF 2KV 2KV CW6 RW7 RW8 75R 1% 75R 1% 2KV CW7 RW5 WAN_AVDD 50R 1% CW4 0.1uF LW5 CW5 0.1uF 50R 1% FB TX- RX_DV RX_ERR WAN_VDD RESET# WAN_VDD XT2 XT1 DGND 37 38 39 40 41 42 43 44 45 46 47 48 AGND BGRESG RW11 6.8K 1% RXDV/TESTMODE RXER/RXD[4]/RPTR DVDD RESET# DVDD XT2 XT1 DGND NC AGND BGRESG BGRES placed close to pins 47 & 48 as much as possible 0.1uF 2KV Chasis Ground Power-on Reset Settings Latched Inputs WAN_VDD 1 2 3 10K JP38 Operating Mode Select RW13 COLLED# OP0 1 2 3 10K HEADER 3 HEADER 3 WAN_VDD RW14 1 2 3 10K RX0_DV RX0_ERR TX0D0 TX0D1 TX0D2 TX0D3 TX0_CLK TX0_EN TX0_ERR RX0_CLK CRS0 RX0_DV RX0_ERR COL0 MDC0 MDIO0 DIP-4W WAN_VDD 10P NO ON CC37 24 23 22 21 20 19 18 17 16 15 14 13 MDC DVDD TXCLK/ISOLATE TXEN TXD[0] TXD[1] TXD[2] TXD[3] TXER/TXD[4] DGND CABLESTS/LINKSTS LINK/ACT LED#/OP2 1 2 3 4 5 6 7 8 COL CRS RX_CLK RXD0 RXD1 RXD2 RXD3 MDIO MDC WAN_VDD TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 TX_ERR DGND CBLLNK ACTLED# 16 15 14 13 12 11 10 9 COL0 CRS0 RX0_CLK RX0D0 RX0D1 RX0D2 RX0D3 MDIO0 JP40 Operating Mode Select RW15 SPDLED# OP1 10K RX0D[0..3] SW6 MDC TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 TX_ERR 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 MDC0 TX0_CLK TX0_EN TX0D0 TX0D1 TX0D2 TX0D3 TX0_ERR TX0_ERR CW8 CW9 CW10 0.1uF 0.1uF 0.1uF 3V3LAN WAN_VDD LW6 LW4 FB FB CW18 CW19 0.1uF 0.1uF CW12 CW13 CW14 0.01UF 0.1uF 10UF 16V CW21 22pF 300R XT1 1 2 3 HEADER 3 WAN_VDD JP48 10K WAN_VDD 0 = Node Mode 1 = Repeater Mode RX_ERR RPTR Pulled low normally JP49 RW29 1 2 3 10K HEADER 3 0.1uF WAN_VDD JP52 1 2 3 HEADER 3 7 VCC OUT GND 25/50 MHz 1 2 3 JP44 RW21 1 2 3 8 33 RW22 DW2 WAN_VDD WAN_VDD SPDLED# JP47 RW35 300R HEADER 3 RW36 REF_CLK 0R NO ON CW23 10P NO ON RW26 ACTLED# HEADER 3 10K 1 2 3 PWRDWN YELLOW LW2 XT2 RW27 0R 300R GREEN DW3 WAN_VDD FB HEADER 3 JP51 10K JP50 1 2 1 2 HEADER 2 HEADER 2 RX0_CLK HEADER 3 WAN_VDD 0 = Normal Operation 1 = Enables Test Mode RW32 RX_DV TESTMODE Pulled low normally 10K 14 JP46 DGND 0 = Disables Scrambing 1 = Enables Scrambing RW24 RX_CLK SCRAMBLE Pulled low normally 10K HEADER 3 1 2 3 RED 5V HEADER 3 Y W2 1 2 3 DW1 COLLED# AGND CW22 22pF WAN_AVDD WAN3_VDD WAN_VDD 1 2 3 10K WAN_VDD JP45 RW28 CW17 0.01uF JP41 RW16 CBLLNK WAN_VDD WAN_AVDD Operating Mode Select RW19 ACTLED# OP2 WAN_VDD PHY Address CRS PHYAD4 Pulled low normally CW16 WAN_VDD 5V GND 1 2 3 10K CW15 10UF 16V 5VD RW20,RW25,RW30 REMOTE RW17 JP43 HEADER 3 RW23 WAN_AVDD WAN_AVDD WAN_VDD JP42 PHY Address RXD3 PHYAD3 Pulled low normally TX0D0 RMII TX0D1 TX0_EN RX0D0 RX0D1 RX0_DV CRS_DV RX0_ERR MDC0 MDIO0 REF_CLK SW 1X8 XT2 10K RX0D[0..3] RX0D0 RX0D1 RX0D2 RX0D3 SW 1X8 WAN_VDD Y W1 25 MHz HEADER 3 WAN_VDD RW18 TX0_CLK TX0_EN TX0_ERR RX0_CLK CRS0 RX0_DV RX0_ERR COL0 MDC0 MDIO0 XT1 1 2 3 HEADER 3 PHY Address RXD2 PHYAD2 Pulled low normally TX0D[0..3] WAN_VDD JP39 PHY Address RXD1 PHYAD1 Pulled low normally 8 7 6 5 SW5 WAN_AVDD WAN_AVDD RX+ RXAGND AGND TX+ TXWAN_AVDD PWRDWN COLLED# SPDLED# JP37 RW12 1.5K TX_CLK 1 2 3 4 5 6 7 8 9 10 11 12 DM9161 WAN_VDD PHY Address PHYAD0 RXD0 Pulled low normally RW3 36 35 34 33 32 31 30 29 28 27 26 25 RW4 3 RW6 75R 1% UW2 10UF 16V CW3 0.1uF 1 2 3 4 CC38 COL/RMII CRS/PHYAD[4] RXCLK/SCRAMEN/10BTSER DGND MDINTR# RXEN DVDD RXD[0]/PHYAD[0] RXD[1]/PHYAD[1] RXD[2]/PHYAD[2] RXD[3]/PHYAD[3] MDIO 5 TX0D[0..3] SW4 RX_DV RX_ERR 10P NO ON MDIO CW1 CW2 0.1uF 1 MII RX_CLK AVDD AVDD RX+ RXAGND AGND TX+ TXAVDD PWRDWN FDX/COL LED#/OP0 SPEED LED#/OP1 10 Solder RJ-45L 8 7 6 5 4 3 2 1 9 Solder NC NC RXNC NC RX+ TXTX+ 7 RESET# HEADER 3 UW1 JW2 RESET_LAN/WAN 3 2 1 WAN_VDD WAN_VDD RXD0 RXD1 RXD2 RXD3 MDIO JP36 RW1 COL CRS RX_CLK DGND RX+ Switching the external or on broad schematic 0 = MII 1 = RMII COL RMII Pulled low normally RW31 DW4 300R ORG CBLLNK JP53 RW33 10K 1 2 3 RW34 Title NUC740 EVB 10K HEADER 3 Publication Release Date: Apr, 2009 - 31 - Size B Document Number NUC740 EVB Date: Monday , April 06, 2009 Rev 0.1 Sheet 8 of Revision B 8 NUC740 User Manual Important Notice Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Nuvoton products are not intended for applications wherein failure of Nuvoton products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales. Publication Release Date: Apr, 2009 - 32 - Revision B