Download MPC755 RISC Microprocessor Hardware Specifications

2
Integer Unit 2
+
Integer Unit 1
+ × ÷
Reorder Buffer
(6-Entry)
Completion Unit
32-Bit
Reservation
Station
Reservation
Station
2 Instructions
• Time Base Counter/Decrementer
• Clock Multiplier
• JTAG/COP Interface
• Thermal/Power Management
• Performance Monitor
Additional Features
DTLB
SRs
(Original)
DBAT
Array
Data MMU
32-Bit
CR
System Register
Unit
Reservation
Station
Tags
PA
32-Kbyte
D Cache
17-Bit L2 Address Bus
64-Bit L2 Data Bus
Data Load Queue
L1 Castout Queue
Instruction Fetch Queue
32-Kbyte
I Cache
Reservation Station
Tags
L2CR
L2 Tags
Not in the MPC745
L2 Castout Queue
L2 Controller
FPSCR
FPSCR
+ × ÷
64-Bit Floating-Point
Unit
IBAT
Array
128-Bit
(4 Instructions)
L2 Bus Interface
Unit
Rename Buffers
(6)
FPR File
ITLB
SRs
(Shadow)
Instruction MMU
60x Bus Interface Unit
Store Queue
(EA Calculation)
+
Load/Store Unit 64-Bit
64-Bit
32-Bit
Reservation Station
(2-Entry)
32-Bit Address Bus
32-/64-Bit Data Bus
EA
CTR
LR
64-Bit
(2 Instructions)
BHT
BTIC
64-Entry
Branch Processing
Unit
Rename Buffers
(6)
GPR File
Dispatch Unit
Instruction Queue
(6-Word)
Fetcher
Instruction Unit
Overview
Figure 1. MPC755 Block Diagram
MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor