Download SERVICE MANUAL

CDX-C4840R/C4850R
SERVICE MANUAL
AEP Model
UK Model
Photo: CDX-C4850R
Model Name Using Similar Mechanism
CDX-C570R/C580R
CD Drive Mechanism Type
MG-363T-121
Optical Pick-up Name
KSS-521A
SPECIFICATIONS
Power amplifier section
CD player section
System
Signal-to-noise ratio
Frequency response
Wow and flutter
Compact disc digital audio
system
90 dB
10 – 20,000 Hz
Below measurable limit
Tuner section
Outputs
Speaker outputs
(sure seal connectors)
Speaker impedance
4 – 8 ohms
Maximum power output 40 W × 4 (at 4 ohms)
General
Outputs
FM
Tuning range
Aerial terminal
Intermediate frequency
Usable sensitivity
Selectivity
Signal-to-noise ratio
87.5 – 108.0 MHz
External aerial connector
10.7 MHz
12 dBf
75 dB at 400 kHz
65 dB (stereo),
68 dB (mono)
Harmonic distortion at 1 kHz
0.8% (stereo),
0.6% (mono)
Separation
35 dB at 1 kHz
Frequency response
30 – 15,000 Hz
Tone controls
Power requirements
Dimensions
Mounting dimension
MW/LW
Tuning range
MW: 531 – 1,602 kHz
LW: 153 – 281 kHz
Aerial terminal
External aerial connector
Intermediate frequency 10.7 MHz / 450 kHz
Sensitivity
MW: 30 µV
LW: 50 µV
Mass
Supplied accessories
Line outputs (2) (CDX-C4850R)
Line output (1) (CDX-C4840R)
Power aerial relay control
lead
Power amplifier control
lead
Telephone ATT control
lead (CDX-C4850R)
Bass ±8 dB at 100 Hz
Treble ±8 dB at 10 kHz
12 V DC car battery
(negative ground)
Approx. 178 × 50 × 185 mm
(w/h/d)
Approx. 182 × 53 × 162 mm
(w/h/d)
Approx. 1.2 kg
Parts for installation and
connections (1 set)
Front panel case (1)
Design and specifications are subject to change without
notice.
FM/MW/LW COMPACT DISC PLAYER
MICROFILM
–1–
SECTION 4
DIAGRAMS
4-1. IC PIN DESCRIPTION
• IC801 MB90574APMT-G-199-BND (SYSTEM CONTROL)
Pin No.
Pin Name
I/O
Pin Description
1
2
LD ON
FOK
O
I
Laser ON/OFF control output
Focus OK signal detection input
3
4
XLAT25
DATA25
O
O
CD signal processing latch output
CD signal serial data output
5
6
XRST
GFS
O
I
Reset output to CD signal processor IC.
GFS signal detection input
7
8
NIL
VCC
—
—
Not used. (Connect to ground in this set.)
Power supply pin (+5 V)
9 – 11
12
NIL
FLS SI/NOSE1
—
I
Not used. (Open)
Front panel attachment detection input
13
14
LCD SO/FLS SO
LCD CKO
O
O
LCD serial data output
LCD serial clock output
15
16
BEEP
NIL
O
—
BEEP output
Not used. (Open)
17
18
SQ SI
NIL
I
—
Sub Q data input
Not used. (Connect to ground in this set.)
19
20
SQ CKO
UNI SI
O
I
Sub Q read clock output
BUS system serial interface input
21
22
UNI SO
UNI CK
O
I/O
23
24
C IN
SIRCS
I
I
25
26
27
TXT SI
NIL
TXT CKO
I
—
O
CD-TEXT data input
Not used. (Connect to ground in this set.)
CD-TEXT data read clock output
28
29
CLOK25
SYSRST
O
O
CD signal processing serial clock output
System reset output
30
31
DEEMPH
AMP ATT
O
O
De-emphasis output
Power amplifier attenuator control output
32
33
MD ON
VSS
O
—
CD mechanism power control output
Ground
34
35
C
CD ON
—
O
Power stabilization capacitor pin
CD power control output
36
37
BUS ON
NIL
O
O
BUS ON control output
Power control output of A/D conversion.
38
39
DVCC
DVSS
—
—
VREF input of D/A converter.
Ground of D/A converter.
40
41
NIL
ANGLE
—
O
Not used. (Open)
LCD view angle alignment output (Not used in this set.)
42
43
AVCC
AVRH
—
—
Analog power supply pin (+5 V)
VREF + input of A/D converter.
44
45
AVRL
AVSS
—
—
VREF – input of A/D converter.
Analog ground
46 – 48
49
KEY IN0 – 2
RC IN0
I
I
50
51
QUALITY
NIL
I
—
52
53
MPDH
S-METER
I
I
54
55
VCC
NS MASK
—
O
BUS system serial interface output
BUS system serial clock input/output
Track jump No. count input
Remote commander input
Key input 0 – 2
Rotary commander input 0
Noise detection input
Not used. (Connect to ground in this set.)
Tuner multi path input
S-meter voltage detection input
Power supply pin (+5 V)
Noise detection output
– 22 –
Pin No.
56
Pin Name
AMP ON
I/O
O
57
58
TXT ON
VOL ATT
O
O
59
60
NIL
ATT
61
62
Pin Description
Power amplifier power control output
Pin No.
111
Pin Name
ANT REM
I/O
O
Pin Description
ANT REMOTE power control output
Reset output to CD-TEXT decoder IC.
Electric volume mute control output
112
113
NIL
CTL2
—
—
Not used. (Open)
Not used in this set.
—
O
Not used. (Open)
System attenuate control output
114
115
CD LD
CD EJ
O
O
Loading motor control output (Loading direction)
Loading motor control output (Eject direction)
RC IN1
TU ATT
I
O
Rotary commander shift key input 1
Tuner attenuate output
116
117
L SW
IN SW/(PH1)
I
I
Sled limit switch detection input
Disc insertion detection input
63
64
VSS
NIL
—
—
Ground
Not used. (Open)
118
119
D SW
VSS
I
—
DOWN switch detection input
Ground
65
66
SSTOP
TEST
I
I
IF counter result signal detection input of PLL.
Test mode initial setting detection input
120
SELF SW/(IN SW)
I
Disc self store detection input
67
68
DAVN
FM ON/AM ON
I
O
RDS IC data acquisition detection input
FM ON output
69
70
TU ON
SDA
O
I/O
71
72
SCL
NOSE2
O
I
I2C BUS serial clock output
Front panel OPEN detection input
73
74
X1A
X0A
O
I
Sub ceramic oscillator output (32 kHz)
Sub ceramic oscillator input (32 kHz)
75
76
SCOR
BU IN
I
I
SCOR signal detection input
Backup power detection input
77
78
DQSY
CD SENS
I
I
CD-TEXT data setting completion signal detection input
CD SENS signal detection input
79
80
81
NIL
TEL ATT
ST/MONO
I
I
I/O
82
83
SEEKOUT
SD IN
O
I
SEEK output
Signal detector input
84
85
WIDE
NARROW
O
O
WIDE select output (Not used in this set.)
NARROW select output (Not used in this set.)
86
87
HSTX
MD2
—
—
Hardware standby input (Connect to pin (º (RESET).)
Operation mode input (Connect to ground in this set.)
88, 89
90
MD1, 0
RESET
—
I
Operation mode input (Connect to VCC in this set.)
Reset input
91
92
VSS
X0
—
I
Ground
Main ceramic oscillator input (4.19 MHz)
93
94
X1
VCC
O
—
Main ceramic oscillator output (4.19 MHz)
Power supply pin (+5 V)
95
96
COM8V ON
NIL
O
—
COM 8V control output
Not used. (Open)
97
AREA1
I
98
AREA2
I
Tuner power control output
I2C BUS serial data input/output
Key input acknowledge
Telephone attenuate detection input
Tuner stereo signal detection input/forced monaural output
Destination select input 1 (Fixed at “L” in this set.)
Destination select input 2 (Fixed at “L” (AEP, UK model) or “H” (German model)
99
LOUD
I
in this set.)
Fixed at “L” in this set.
100
101
BAND
ACC IN
I
I
Fixed at “H” in this set.
Accessory power detection input
102, 103
104
PH3, 2
LCD CE
I
O
Disc insertion detection photo sensor input (Fixed at “H” in this set.)
LCD chip enable output
105
106, 107
FLS W
RE IN0, 1
I
I
Flash write input (Fixed at “H” in this set.)
Rotary encoder input
108
109
ILL ON
PW ON
O
O
Illumination power control output
System power control output
110
NIL
—
Not used. (Open)
– 23 –
– 24 –
CDX-C4840R/C4850R
(Page 41)
4-7. SCHEMATIC DIAGRAM — CD MECHANISM SECTION — • Refer to page 32 for Waveforms.
• Refer to page 51 for IC Block Diagrams.
Note:
• Voltage and waveforms are dc with respect to ground
under no-signal conditions.
no mark : CD PLAY
: Impossible to measure
∗
– 35 –
– 36 –
CDX-C4840R/C4850R
(Page 36)
4-9. SCHEMATIC DIAGRAM — MAIN SECTION (1/3) — • Refer to page 53 for IC Block Diagrams.
C4850R
(Page 44)
– 41 –
(Page 46)
– 42 –
Note:
• Voltage is dc with respect to ground under no-signal
(detuned) condition.
no mark : FM
(
) : MW
<
> : CD PLAY
CDX-C4840R/C4850R
4-10. SCHEMATIC DIAGRAM — MAIN SECTION (2/3) — • Refer to page 51 for IC Block Diagrams.
(Page 45)
(Page 41)
Note:
• Voltage is dc with respect to ground under no-signal
(detuned) condition.
no mark : FM
(
) : MW
<
> : CD PLAY
– 43 –
– 44 –
CDX-C4840R/C4850R
4-11. SCHEMATIC DIAGRAM — MAIN SECTION (3/3) — • Refer to page 53 for IC Block Diagrams.
(Page 44)
(Page 42)
(Page 47)
Note:
• Voltage is dc with respect to ground under no-signal
(detuned) condition.
no mark : FM
(
) : MW
<
> : CD PLAY
– 45 –
– 46 –
CDX-C4840R/C4850R
4-12. SCHEMATIC DIAGRAM — DISPLAY SECTION —
(Page 46)
Note:
• Voltage is dc with respect to ground under no-signal
(detuned) condition.
no mark : FM
– 47 –
– 48 –
• IC Block Diagrams
IC1 CXD2507AQ
SEIN
CLOK
XLAT
VDD
XLTO
DATO
CNIN
XLON
SPOD
SPOC
SPOB
SPOA
CLKO
IC602 SAA6588T-118
64 63 62 61 60 59 58 57 56 55 54 53 52
PSWN 11
MAD 12
1
MON
MDP
MDS
LOCK
TEST
2
3
4
5
6
FILO
7
FILI
PCO
VSS
AVSS
CLTV
AVDD
8
9
10
11
12
13
RF
BIAS
ASYI
ASYO
ASYE
14
15
16
17
18
SUB CODE
PROCESSOR
CPU
INTERFACE
14
51
50
49
48
47
46
45
44
43
42
41
40
5
DIGITAL
CLV
4
EFM
DEMODULATOR
DIGITAL
PLL
DATA
XRST
SENS
MUTE
SQCK
SQSO
EXCK
SBSO
SCOR
VSS
WFCK
EMPH
4
PAUSE
DETECTOR
AFIN 13
VDDA
VSSA
MPX
VREF
CLOCKED
COMPARATOR
14
15
16
17
4
SIGNAL
QUALITY
DETECTOR 5
RDS/RDBS
DEMODULATOR
POWER SUPPLY
AND RESET
LVIN 20
ASYMMETRY
CORRECTOR
D/A
INTERFACE
5
ERROR
CORRECTOR
16K
RAM
DIGITAL
OUT
39 DOUT
6
38
37
36
35
34
3
C4M
FSTT
XTSL
XTAO
XTAI
33 MNTO
WDCK 19
GTOP
XUGF
XPCK
VDD
GFS
RFCK
C2PO
XROF
MNT3
MNT1
LRCK
PCMD
BCLK
20 21 22 23 24 25 26 27 28 29 30 31 32
OP IN –
OP IN +
VREF
CH3
CH3-IN
CH2
CH2-IN
VCC
CH1
CH1-IN
CH1 +
CH1 –
CH2 +
CH2 –
IC3 BA6796FP-T1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LEVEL
SHIFT
VCC
LEVEL
SHIFT
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
LEVEL
SHIFT
THERMAL
SHUT
DOWN
3
4
5
6
7
8
9
CH4
CTL1
CTL2
FWD
REV
TRAY
GND
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
DRIVE
BUFFER
10
11
12
13
14
CH3 –
2
DRIVE
BUFFER
CH3 +
1
CH4-IN
REV
OPOUT
FWD
CH4 +
V/I
CTL2
COM
LOGIC
CTL1
CH5 –
LEVEL
SHIFT
– 51 –
10 SCL
9 SDA
INTERFACE
REGISTER
RDS/RDBS
DECODER
OSCILLATOR
AND CLOCK
57kHz
8th ORDER
BAND-PASS
SCOUT 18
CIN 19
3
CLOCK
GENERATOR
FOK
SERVO AUTO
SEQUENCER
IIC-BUS
SLAVE
TRANSCEIVER
8
7
6
5
4
DAVN
VDDD
VSSD
OSCI
OSC0
TEST
CONTROL
3 TCON
MULTI-PATH
DETECTOR
2 MPTH
1 MRO
PHD 1
PHD
LD
RF M
RF O
RF I
CP
CB
CC1
36
35
34
33
32
31
30
29
28
27 26 25
FOK
CC2
PHD 2
IC2 CXA1782BQ
LEVEL S
FOK
APC
MIRR
RF IV AMP1
IIL
24
SENS
TTL
23
C.OUT
22
XRST
21
DATA
20
XLT
19
CLK
18
VCC
17
ISET
16
SL O
15
SL M
14
SL P
13
TA O
DFCT
TTL
RF IV AMP2
TTL
FE BIAS 37
IIL DATA REGISTER
INPUT SHIFT REGISTER
FE AMP
ADDRESS DECODER
F
IIL
IIL
OUTPUT DECODER
38
TOG1-3
BAL1-3
F IV AMP
E
39
EI
40
FS1-4
TG1-2
TM1-7
PS1-4
FZC COMP
E IV AMP
BAL 3
BAL2
BAL1
TE AMP
HPF COMP
VEE
TRACKING
PHASE
COMPENSATION
LPF COMP
ISET
41
TM6
TED 42
TOG3
TOG2
TOG1
TG1
TM5
TM4
TEI
TZC
TM3
44
ATSC 45
46
FCS PHASE
COMPENSATION
TZC COMP
LPFI 43
TM2
DFCT
WINDOW COMP
FS1
TM1
TM7
FS2
ATSC
TDFCT 47
F SET
6
7
8 9
10
11
12
TG2
FSET
TA M
– 52 –
TGU
FDFCT
5
SRCH
FEI
4
FE O
3
FE M
2
FLB
1
FGD
FS4
48
FEO
VC
TG2
DFCT
IC401 TDA7462
28
27
26
25
24
23
INPUT
GAIN &
AUTO
ZERO
LOUDNESS
CONTROL
CIRCUIT
VOLUME
CONTROL
CIRCUIT
SOFT
MUTE
TREBLE/
BASS
CONTROL
CIRCUIT
VOICE BANDPASS
HP
FRONT
FADER
22 OUT FL
FRONT
FADER
21 OUT FR
REAR
FADER
20 OUT RL
REAR
FADER
19 OUT RR
LP
COMPANDER
REAR SIDE
SELECTOR
1
2
3
4
5
6
7
8
9
10
11
12
13
INPUT MULTIPLEXER &
MIXING STAGE
SE1L
SE1R
MD+
MD–
CDL+
CDL–
CDR–
CDR+
PDR
PDGND
PDL
SE2L
SE2R
FRONT SIDE
SELECTOR
PAUSE
DETECT
SE3L
SE3R
MUTE
SDA
SCL
PAUSE
LOUDNESS
CONTROL
CIRCUIT
INPUT
GAIN
SUBWOOFER
LP
BEEP
FADER
18 SUBOUT+
SUBWOOFER
OUT
17 SUBOUT–
SDA
IIC
BUS
DIGITAL CONTROL CIRCUIT
SCL
16 VDD
POWER
SUPPLY
CREF 14
IC702 PCM1717E-ST2
XTI
DGND
1
2
VDD
3
LRCIN 4
DIN
5
BCKIN
6
ZERO
7
IC901 BA4903
5.7V
20 XTO
19 CLKO
CLK
CONTROL
ON
18 ML/MUTE
INPUT
INTERFACE
MODE
CONT
ROL
DIGITAL
FILTER
ON
–
17 MC/DM1
+
+
16 MD/DM0
THERMAL
SHUT
DOWN
15 RSTB
14 MODE
NOISE SHAPER
5LEVE DAC
LOWPASS FILTER
D/C R
8
VOUTR 9
AGND 10
CMOS
AMP
5LEVEL DAC
CIRCUIT ON
1
AMP
ON
LOWPASS FILTER
CMOS
AMP
15 GND
13 D/C L
12 VOUTL
11 VCC
– 53 –
2
AMP
OUT
3
GND
–
REGULATOR
VREF
OVER
VOLTAGE
PROTECT
4
VCC
5
VDD
OUT
IC601 TDA7427AD1TR
28 LPOUT
VDD1
LP FM
1
LP HC
2
LP AM
3
V REF
4
LCL/DX
5
SEEK
6
NIL
7
MONO
8
SWITCH
LP1/LP2
CHARGE
PUMP
PHASE
COMP
SWITCH
SWM/DIR
INLOCK
DETECTOR
PORT
EXTENSION
27 VDD2
11 BIT PROG
COUNTER
6 BIT PROG
COUNTER
26 GND AM
SWITCH
SWM/DIR
PRE COUNTER
:32/33
25 AM IN
SWITCH
AM/FM
24 FM IN
TEST
LOGIC
23 NC
OSCIN 9
OSCOUT 10
REF
OSCILLATOR
SUPPLY
&
POWER ON
RESET
16 BIT PROG
COUNTER
22 GND D
21 VDD1
NC 11
SCL 12
SDA 13
20 ADDR
19 HFREF
I2C
BUS
INTERFACE
18 AMOSC
14 BIT PROG
COUNTER
IF AM 14
SWITCH
AM/FM
TIMER
SWITCH
OUT
CONTROL
17 DOUT/INLOCK
11-21 BIT PROG COUNTER
16 SSTOP
15 IF FM
IC703 LC89170M-T
IC803 BA8270F-E2
VDD
EXCK 1
CPU INTERFACE
32 WORD X 8 BIT
DUAL PORT RAM
CRC
CHECKER
WFCK 4
MCK 5
XMODE 6
BUS ON
SWITCH
RST 2
RESET
SWITCH
BATT 3
BATTERY
SWITCH
12 SRDT
11 SCLK
TIMING
&
SYNCHRONIZATION
SIGNAL
PROTECTION
14 VCC
14 VDD
13 DQSY
SBSO 2
SCOR 3
BUS ON 1
10 SW2
CLK 4
VREF 5
DATA 6
GND 7
9 SW1
GND 7
8 TEST
– 54 –
13
12
11
10
RST
BUS ON
CLK IN
BU IN
9 DATA IN
8 DATA OUT