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Transcript

MC-8
Controller
Service Manual
Harman Specialty Group 3 Oak Park, Bedford, MA, 01730-1413 USA
Customer Service: Telephone: 781-280-0300 | Service Fax: 781-280-0499 | www.lexicon.com
Part No. 070-17536 | Rev 0
DOCUMENT CONVENTIONS
This document contains general safety and service instructions for the MC-8. It is important to read this manual
before attempting service instructions. Pay particular attention to safety instructions.
The following symbols are used in this document:
Appears on the component to indicate the presence of uninsulated, dangerous voltage
inside the enclosure – voltage that may be sufficient to constitute a risk of shock.
Appears on the component to indicate important operating and maintenance instructions
in the accompanying literature.
WARNING
Calls attention to a procedure, practice, condition or the like that, if not correctly
performed or adhered to, could result in injury or death.
CAUTION
Calls attention to a procedure, practice, condition or the like that, if not correctly
performed or adhered to, could result in damage or destruction to part or all of the
product.
Note:
Calls attention to information that is essential to highlight.
IMPORTANT SAFETY INSTRUCTIONS
1. Read and keep these instructions.
2. Heed all warnings.
3. Follow all operation instructions.
4. Do not use this apparatus near water.
5. Clean only with a dry cloth.
6. Do not block any ventilation openings.
7. Install in accordance with the manufacturer’s instructions.
8. Do not install near any heat sources such as radiators, heat registers, stoves, or another apparatus
(including amplifiers) that produces heat.
9. Do not defeat the safety purpose of the polarized or grounding-type plug. A polarized plug has two blades
with one wider than the other. A grounding-type plug has two blades and a third grounding prong. The wide
blade or the third prong are provided for your safety. If the provided plug does not fit into your outlet, consult
an electrician for replacement of the obsolete outlet.
10. Protect the power cord from being walked on or pinched particularly at plugs, convenience receptacles, and
the point where they exit from the apparatus.
11. Only use attachments/accessories specified by the manufacturer.
12. Use only with the cart, stand, tripod, bracket, or table specified by the manufacturer, or sold with
the apparatus. When a cart is used, use caution when moving the cart/apparatus combination to
avoid injury from tip-over.
13. Unplug this apparatus during lightning storms or when unused for long periods of time.
14. Refer all servicing to qualified service personnel. Servicing is required when the apparatus has been
damaged in any way, such as when a power-supply cord or plug is damaged, liquid has been spilled or
objects have fallen into the apparatus, the apparatus has been exposed to rain or moisture, does not
operate normally, or has been dropped.
15. Refer to the operating instructions for power requirements. Be advised that different operating voltages may
require the use of different line cord and/or attachment plug.
16. Do not install the unit in an unventilated rack, or directly above heat-producing equipment such as power
amplifiers. Observe the maximum ambient operating temperature listed in the product specification.
17. Never attach audio power amplifier outputs directly to any of the unit’s connectors.
18. To reduce the risk of fire or electric shock, do not expose this apparatus to rain or moisture.
19. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to
Part 15 of FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses, and radiates radio frequency energy and, if not installed and used
in accordance with the instructions, may cause harmful interference to radio or television reception, which can
be determined by turning the equipment off and on. The user is encouraged to try to correct the interference by
one or more of the following measures:
•
Re-orient or relocate the receiving antenna.
•
Increase the separation between the equipment and the receiver.
•
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
•
Consult the dealer or an experienced radio/ television technician for help.
SAFETY SUMMARY
The following general safety precautions must be observed during all phases of operation, service, and repair of
this unit. Failure to comply with these precautions or with specific warnings elsewhere in these instructions
violates manufacturer safety standards and intended use of this unit. Harman Specialty Group assumes no
liability for failure to comply with these requirements.
GROUND THE INSTRUMENT
To minimize shock hazard, the unit chassis and cabinet must be connected to an electrical ground. The unit is
equipped with a three-wire grounding type plug. It will only fit into a grounding type power outlet. This is a safety
feature. If you are unable to insert the plug into the outlet, contact your electrician to replace your obsolete
outlet. Do not defeat the safety purpose of the grounding type plug.
DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE
Do not operate the unit in the presence of flammable gasses or fumes. Operation of any electrical instrument in
such an environment constitutes a definite safety hazard.
KEEP AWAY FROM LIVE CIRCUITS
Operating personnel must not remove unit covers. Qualified maintenance personnel must make component
replacements and internal adjustments. Do not replace components with the power cord connected. Under
certain conditions, dangerous voltages may exist even with the power cord removed. To avoid personal injuries,
always disconnect power and discharge circuits before touching them.
DO NOT SERVICE OR ADJUST ALONE
Do not attempt internal service or adjustment unless another person capable of rendering first-aid resuscitation
is present.
DO NOT SUBSTITUTE PARTS OR MODIFY INSTRUMENT
Because of the danger of introducing additional hazards, do not install substitute parts or perform any
unauthorized modification to the unit.
DANGEROUS PROCEDURE WARNINGS
Warnings such as the example shown below precede potentially dangerous procedures throughout this
document. Instructions contained in warnings must be followed.
WARNING
Dangerous voltages capable of causing death are present in this unit. Use extreme caution
when handling, testing, or adjusting.
CAUTION
ELECTROSTATIC DISCHARGE (ESD) PRECAUTIONS
The following practices minimize possible damage to circuit boards resulting from electrostatic
discharge or improper insertion.
•
Keep circuit boards in their original packaging until ready for use.
•
Avoid having plastic, vinyl, or Styrofoam in the work area.
•
Wear an anti-static wrist strap.
•
Discharge personal static before handling circuit boards.
•
Remove and insert circuit boards with care.
•
When removing circuit boards, handle only by non-conductive surfaces. Never touch open-edge
connectors except at a static-free workstation.
•
Minimize handling of circuit boards.
•
Handle each circuit board by its edges.
•
Do not slide circuit boards over any surface.
•
Insert circuit boards with the proper orientation.
•
Use static-shielded containers for storing and transporting circuit boards.
WARNING
3 Oak Park
Bedford, MA 01730-1413 USA
Telephone: 781-280-0300
Fax: 781-280-0490
www.lexicon.com
Customer Service
Telephone: 781-280-0300
Sales Fax: 781-280-0495
Service Fax: 781-280-0499
Product Shipments
16 Progress Road
Billerica, MA 01821-5730 USA
Part No. 070-17536 | Rev 0 | 08/05
These service instructions are only intended for use by
qualified personnel. Do not perform any servicing other than
that contained in these instructions unless qualified to do so.
Refer to the Safety Summary on the previous page prior to
performing any service.
“Lexicon” and the Lexicon logo are registered trademarks of
Harman International Industries, Incorporated.
U.S. patent numbers and other worldwide patents issued
and pending.
© 2005 Harman International Industries, Inc. All rights
reserved.
This document should not be construed as a commitment on
the part of Harman Specialty Group. The information it
contains is subject to change without notice. Harman
Specialty Group assumes no responsibility for errors that
may appear within this document.
TABLE OF CONTENTS
CHAPTER 1 – REFERENCE DOCUMENT & EQUIPMENT LISTS ........................1-1
CHAPTER 2 – GENERAL INFORMATION .............................................................2-1
CHAPTER 3 – SPECIFICATIONS ..........................................................................3-1
CHAPTER 4 – FUNCTIONAL VERIFICATION .......................................................4-1
Initial Inspection................................................................................................................. 4-1
Functional Audio I/O Tests ................................................................................................ 4-2
Audio Performance Verification ......................................................................................... 4-5
Video Input/Output Tests................................................................................................... 4-9
Lexicon Audio Precision ATE Summary.......................................................................... 4-11
CHAPTER 5 – TROUBLESHOOTING ....................................................................5-1
Diagnostic Categories ...................................................................................................... 5-1
Power On Modes ............................................................................................................... 5-1
Diagnostics User Interface ............................................................................................... 5-1
Diagnostic Reporting ......................................................................................................... 5-2
Power On Diagnostics ....................................................................................................... 5-8
Extended Diagnostics Tests ............................................................................................ 5-11
Repair Diagnostics Tests................................................................................................. 5-12
Functional Diagnostic Suite ............................................................................................. 5-14
Repair Diagnostic Suite ................................................................................................... 5-19
Audio I/O Tests ................................................................................................................ 5-20
Video I/O Tests ................................................................................................................ 5-21
CHAPTER 6 – THEORY OF OPERATION .............................................................6-1
Main Board Z180 Host Processor ..................................................................................... 6-1
FPGAs ............................................................................................................................... 6-3
Host Interface to Other Boards.......................................................................................... 6-6
Decoder Board................................................................................................................... 6-8
DSP Board....................................................................................................................... 6-10
Audio Routing .................................................................................................................. 6-13
VCO Board Overview..........................................................................................................6-16
MC-8 Analog Overview .......................................................................................................6-16
MC-8 Video System Circuit Overview.................................................................................6-20
CHAPTER 7 – PARTS LIST ........................................................................................ 7-1
Main Board Assembly ........................................................................................................... 7-1
Memory Board Assembly...................................................................................................... 7-4
Video RCA Board Assembly ................................................................................................. 7-5
Video Out Board Assembly................................................................................................... 7-5
DSP Board Assembly ........................................................................................................... 7-5
Decoder Board Assembly ..................................................................................................... 7-6
Switch/LED Board Assembly ................................................................................................ 7-6
Standby Board Assembly...................................................................................................... 7-6
XLR Board Assembly............................................................................................................ 7-7
IR/Encoder Board Assembly................................................................................................. 7-7
VCO Assembly...................................................................................................................... 7-7
Chassis Assembly................................................................................................................. 7-8
Mic Board Assembly ............................................................................................................. 7-9
Power Supply Assembly ....................................................................................................... 7-9
Fan Assembly ....................................................................................................................... 7-9
Switch/LED Board Assembly ................................................................................................ 7-9
Front Panel Mechanical Assembly ....................................................................................... 7-9
Video Mechanical Assembly ...............................................................................................7-10
Packaging/Miscellaneous ...................................................................................................7-10
Power Cord Options............................................................................................................7-10
Mounting Option..................................................................................................................7-10
MC8 to MC8B Upgrade Option ...........................................................................................7-10
ASSEMBLY DRAWINGS
080-14834
080-15461
080-15462
080-15463
080-15482
ASSY DWG,MECH,VCO,
ASSY DWG,SHIPMENT
ASSY DWG,CHASSIS, M
ASSY DWG,MECH,FP,M
ASSY DWG,ACCESS,MC
SCHEMATICS
060-13699
060-14849
060-15259
060-15279
060-15289
060-15299
060-15309
060-15319
060-14849
060-15329
060-15339
060-15349
060-15389
060-16139
SCHEM,IR/ENCODER BD
SCHEM,VCO BD
SCHEM,MAIN BD
SCHEM,VIDEO RCA BD
SCHEM,SWITCH/LED BD
SCHEM,MEMORY BD
SCHEM,DSP BD
SCHEM,DECODER BD
SCHEM,VCO BD
SCHEM,STANDBY BD
SCHEM,VIDEO OUT BD
SCHEM,XLR BD
SCHEM,MIC/DSP BD
SCHEM,MCLK VCO BD
Lexicon
CHAPTER 1 – REQUIRED EQUIPMENT
Reference Document
Refer to the MC-8 User Guide-Lexicon P/N 070-15481.
Required Equipment
The following is a minimum suggested equipment list required to perform the proof of
performance tests:
•
High quality amplifier with RCA and XLR input connectors and volume control capabilities
•
A pair of high quality speakers
•
High quality video monitor with composite (RCA), S-video and component (RCA and BNC) input
connections
•
CD disc for use as a test audio source
•
DVD disc for use as a test video source
•
DAT Recorder for testing the digital output of the MC-8
•
Variable AC power supply (2 amp minimum)
•
Digital multimeter (DMM) 3.5 digits 0.5% or better accuracy
•
Low Distortion Audio Oscillator with single-ended and balanced analog outputs, switchable 40kHz
low-pass filter or band-pass (20-20kHz) filter, and output THD+N < 0.001%
•
100 MHz oscilloscope
•
S/PDIF Digital Distortion Analyzer with coaxial and optical input
•
S/PDIF Digital Function Generator with coaxial and optical output
•
Low Distortion Audio Analyzer with switchable 30Hz high-pass filter or band-pass (20-20kHz) filter
capable of measuring THD+N <0.01%
•
DVD/CD player with RCA analog L/R outputs, digital coaxial outputs, optical outputs, and composite,
S-video and component outputs
•
(2) RS232 wrap around plugs (These are made by connecting pins 2 & 3 of a female DB9 connector)
•
MC-8 remote control.
Required Cables
•
Shielded audio cable with an RCA connector on one end and an appropriate connector on the
opposite end for connection to a Low Distortion Audio Oscillator
•
Shielded audio cable with an RCA connector on one end and an appropriate connector on the
opposite end for connection to a Low Distortion Audio Analyzer
•
Shielded (balanced) audio cable and a XLR female connector on one end and an appropriate
connector on the opposite end for connection to a Low Distortion Analyzer
•
(4) Shielded audio cables with RCA connectors on both ends
1-1
MC-8 Service Manual
•
(2) Shielded audio cables with a XLR male on one end and XLR female on the other
•
Digital S/PDIF audio cable with RCA connectors on both ends
•
Digital S/PDIF audio cable with optical connectors on both ends
•
(2) Video cables with RCA connectors on both ends
•
(2) Video cables with S-video connectors on both ends
•
(2) Video cables with 3-wire component RCA connectors on both ends
•
MC-8 AC power cord (see Chapter 7 for list of part numbers).
Required Tools
The following is a minimum suggested equipment list required for performing disassembly,
assembly and repairs:
•
Clean, antistatic, well-lit work area with grounding wrist strap
•
Number 1 Phillips tip screwdriver (magnetic tip preferred)
•
14mm socket nut driver
•
(2.5 mm) Hex Driver
•
3/16 Hollow nut driver
•
Magnification glasses and lamp
•
Surface Mount Technology (SMT) Soldering/Desoldering bench-top repair station.
1-2
Lexicon
CHAPTER 2 – GENERAL INFORMATION
Periodic Maintenance
Under normal conditions the MC-8 requires minimal maintenance. Use a soft, lint-free cloth slightly
dampened with warm water and a mild detergent to clean the exterior surfaces of the unit.
Do not use alcohol, benzene or acetone-based cleaners or any strong commercial cleaners. Avoid using
abrasive materials such as steel wool or metal polish. If the unit is exposed to a dusty environment, a
vacuum may be used to remove dust from the unit's exterior.
Ordering Parts
When ordering parts, identify each part by type, board assembly location, component location,
price and HSG/Lexicon Part Number.
Replacement parts can be ordered from:
Harman Specialty Group
3 Oak Park Drive
Bedford, MA 01730-1441
Telephone: 781-280-0300; Fax: 781-280-0499; email: [email protected]
ATTN: Customer Service
TU
UT
Returning Units to HSG/Lexicon for Service
Before returning a unit for warranty or non-warranty service, consult with HSG/Lexicon Customer Service
to determine the extent of the problem and to obtain Return Authorization. No equipment will be accepted
without Return Authorization from HSG/Lexicon.
If HSG/Lexicon recommends that a MC-8 be returned for repair and you choose to return the unit to
HSG/Lexicon for service, HSG/Lexicon assumes no responsibility for the unit in shipment from the
customer to the factory, whether the unit is in or out of warranty. All shipments must be well packed (using
the original packing materials if possible), properly insured and consigned, prepaid, to a reliable shipping
agent.
When returning a unit for service, please include the following information:
•
Name
•
Company Name
•
Street Address
•
City, State, Zip Code, Country
•
Telephone number (including area code and country code where applicable)
•
Serial Number of the unit
•
Description of the problem
•
Preferred method of return shipment
•
Return Authorization number (on both the inside and outside of the package).
2-1
MC-8 Service Manual
Please enclose a brief note describing any conversations with HSG/Lexicon personnel (indicate the name
of the person at HSG/Lexicon) and give the name and daytime telephone number of the person directly
responsible for maintaining the unit.
Do not include accessories such as manuals, cables, remote controls, etc. with the unit, unless
specifically requested to do so by HSG/Lexicon Customer Service personnel.
2-2
Lexicon
CHAPTER 3 – SPECIFICATIONS
Audio Input and Output Connectors
Analog Audio Inputs
8 stereo (RCA) or 5 stereo and one 5.1-channel or 2 stereo and two
5.1-channel connectors
Digital Audio Inputs
4 S/PDIF coaxial (RCA) and 4 S/PDIF optical connectors; coaxial and
optical input connectors conform to IEC-958, S/PDIF standards
Sample Rates
44.1, 48, 88.2, 96kHz
Accepts
16-24 bits PCM audio, Dolby Digital, DTS, DTS-ES discrete data formats
Main Audio Outputs
8 unbalanced (RCA) and 8 balanced (XLR, MC-8 balanced only)
connectors for Front L/R, Center, Sub, Side L/R and Rear L/R
Zone 2 Audio Outputs
1 unbalanced (RCA, variable output level) stereo connector, 1 balanced
(XLR, variable output level, MC-8 balanced only) stereo connector, 1
S/PDIF coaxial (RCA) connector
Main Zone Audio Performance
A/D Conversion
24-bit, 96kHz, dual-bit ∆Σ architecture
D/A Conversion
24-bit, 44.1 to 192kHz, multi-bit ∆Σ architecture
Frequency Response*
10Hz to 20kHz, +0.05dB/-0.1dB, -0.5dB at 40kHz, reference 1kHz
THD + Noise*
Below 0.008% at 1kHz, maximum output level
Dynamic Range*
108dB minimum, 22kHz bandwidth
Signal-to-Noise Ratio*
108dB minimum, 22kHz bandwidth
Input Sensitivity
200mVrms (2Vrms for maximum output level) at 0dB input gain
Input Impedance
100kΩ in parallel with 150pF
Output Level
150mVrms typical, 6Vrms maximum (RCA connectors) 300mVrms
typical, 12Vrms maximum (XLR connectors, MC-8 Balanced only)
Maximum value with full-scale input signal and volume at +12dB
Output Impedance
100Ω in parallel with 150pF (RCA connectors), 50Ω in parallel with
150pF (XLR connectors, MC-8 Balanced only)
3-1
MC-8 Service Manual
Zone 2 and Audio Performance
D/A Conversion
24-bit, 44.1 to 192kHz, multi-bit ∆Σ architecture
Frequency Response*
10Hz to 20kHz, +0.1dB/-0.25dB, -0.75dB at 40kHz, reference 1kHz
THD + Noise*
Below 0.005% at 1kHz, (maximum output level)
Dynamic Range*
103dB minimum, 108dB typical, 22kHz bandwidth
Signal-to-Noise Ratio*
103dB minimum, 108dB typical, 22kHz bandwidth
Input Sensitivity
200mVrms (4Vrms for maximum output level)
Input Impedance
100kΩ in parallel with 150pF
Output Level
200mVrms typical, 4Vrms maximum (RCA connectors), 400mVrms
typical, 8Vrms maximum (XLR connectors), MC-8 Balanced only;
maximum value with full-scale input signal and volume at 0dB
Output Impedance
100Ω in parallel with 150pF (RCA connectors), 50Ω in parallel with
150pF (XLR connectors, MC-8 Balanced only)
Video Input and Output Connectors
Video Inputs
5 composite (RCA), 5 S-video and 3 component video (RCA)
Video Outputs
2 composite (RCA), (1 monitor, 1 Zone 2), 2 S-video (1 monitor, 1
Zone2) and 1 component (BNC)
Composite and S-video Performance
Compatibility
NTSC, PAL and SECAM
Switching
Active
Output Level
1.0V peak-to-peak
Impedance
75Ω
Input Return Loss
>40dB
Differential Gain*
<0.5%
Differential Phase*
<0.5°
Bandwidth*
>25MHz
K Factor*
<0.3%
Gain*
±0.15dB
3-2
Lexicon
Signal-to-Noise Ratio*
>65dB
Frequency Response*
10Hz to 10MHz + 0.1/-0.3dB
Component Video Performance
Compatibility
3-Channel (Y/Pb/Pr), format-independent
Switching
Passive
Impedance
75Ω
Bandwidth
>150MHz
Insertion Loss*
<3dB
Microphone Input Connectors (For V2 and Higher Units)
Input
4 3.5 miniature phone jacks
Input Sensitivity
10mVrms (400mV maximum input level)
Input Impedance
20kΩ (accepts balanced or unbalanced input signals)
Other
Trigger Outputs
1 power on/off and 1 programmable connector on detachable screw
terminals (+12 VDC, 0.5 amps each)
RS-232 Serial Input/Output
2 9-pin D-sub connectors
Power Requirements
90-250 VAC, 50-60Hz, 60W (universal line input), detachable power cord
MC-8 Dimensions & Weight
Height (with feet): 3.81 inches (97mm)
Width: 17.3 inches (440mm)
Depth: 14.85 inches (377mm)
Weight: 17lb (7.6kg)
3-3
MC-8 Service Manual
MC-8 Balanced Dimensions & Weight
Height (with feet): 5.04 inches (128mm)
Width: 17.3 inches (440mm)
Depth: 14.85 inches (377mm)
Weight: 24lb (10.7kg)
Rack Mounting
Optional brackets are available for installation in a standard 19"
equipment rack (2 rack units required for MC-8; 3 rack units for MC-8
Balanced)
Environment
Operating Temp: 0° to 35°C (32° to 95°F)
Storage Temp: -30° to 75°C (-22° to 167°F)
Relative Humidity: 95% maximum without condensation
Remote Control
Hand-held, backlit infrared remote control unit, preprogrammed &
learning
Requires two AA batteries (alkaline batteries recommended)
*Specifications are subject to change without notice.
3-4
Lexicon
CHAPTER 4 – FUNCTIONAL VERIFICATION
PERFORMANCE VERIFICATION
This section describes a quick verification of the operation of the MC-8 and the integrity of its analog and
digital audio signal paths. Tests that are specifically included for the MC-8 Balanced version can be
omitted when testing an MC-8.
WARNING
Dangerous voltages capable of causing death are present in this unit. Use extreme
caution when handling, testing, or adjusting. Always power down all equipment before
breaking/making connections.
Initial Inspection
1. Inspect the MC-8 for obvious signs of physical abuse.
2. Verify that all switches operate smoothly.
3. With the power off for ten minutes and the AC cord disconnected, remove the MC-8 top cover using a
hex wrench (2.5mm). Remove the 13 screws on the top cover of the unit to remove the cover.
4. Verify that all socketed ICs are correctly seated.
5. Verify that all cables are correctly installed and are securely fastened.
6. Check for burnt or obviously damaged components.
7. Put the top cover back on.
8. Power on the MC-8 using the main power switch on the back of the unit, and verify that the MC-8
runs through its Power On Diagnostics.
9. Check each of the front panel switches for smooth mechanical operation, verify each LED turns on
and off when the associated switch is depressed, and that the display acknowledges each switch
function.
10. Press each button on the remote and verify that the MC-8 is responding to all the remote commands.
4-1
MC-8 Service Manual
FUNCTIONAL AUDIO I/O TESTS
The following tests verify the basic functions of the MC-8.
Power Supply Tests
The main power supply in the MC-8 has an operational range of 100-240VAC 50-60Hz, 60W. The
following test is for North American line voltage of 120VAC.
Lethal voltages capable of causing death are present in this unit. In this procedure,
testing will be performed with the top cover removed and the unit turned on. Due to risk
of shock, do not remove the cover with the unit powered on.
Test:
1. Set the variable AC supply to 120 volts.
2. Verify that the MC-8 is powered off at its rear panel power switch.
3. Connect the power cord between the supply and the MC-8.
4. Remove the top cover.
5. Check for power supply shorts to ground.
6. Turn on the MC-8 using the rear main power switch.
7. Power on the unit at 120VAC.
8. Verify the current draw on the Variac does not exceed 0.6 amps.
9. Using a DMM, measure all the power supply rails as stated in the tables below, being sure to use the
MC-8 chassis as ground.
10. Verify that all the voltages are within the tolerance range shown below.
Main Board
Supply Rail
Tolerance
Test Points
+5VD
4.75 - 5.25
Red wire at J45 behind front panel center at volume
knob left to ground
Battery
≥ 2.5
Right side to the Left of U69, measure the top of the
battery to ground
+15V
15.00 - 16.95
Yellow wire at J32 to ground
-15V
-14.25 - 15.75
Blue wire at J32 to ground
+5VAD
4.75 - 5.25
Red wire at J32 to ground
-5VA
-4.75 - 5.25
Gray wire at J32 to ground
4-2
Lexicon
Video Board
Supply Rail
Tolerance
Test Points
+5VAD
4.75 - 5.25
Red wire at J17 on Video board to ground
+5VA
4.75 - 5.25
Black wire at J17 on Video board to ground
-5VA
-4.75 - 5.25
Gray wire at J17 on Video board to ground
In order to properly test the MC-8 as described in this document, the MC-8 must be in Diagnostics mode.
Perform the following procedure to enter the Diagnostics mode.
To enter Diagnostics mode:
1. Connect the video monitor to the composite output. This will allow full viewing of the Diagnostics
menus of the MC-8.
2. Press and hold the front panel Main VCR and Zone 2 VCR buttons while powering up the MC-8 with
the main power switch on the back of the unit.
3. When “LEXICON” appears on the display, release the buttons on the front panel.
4. The display on the MC-8 front panel will read “DIAGS MENU FUNCTIONAL TESTS.” The full
Diagnostics Menu will be displayed on the monitor.
Analog Inputs To Main Zone Outputs Test
This test will verify the audio path between the RCA paired inputs labeled 1 to 8, to all analog outputs,
both RCA and XLR.
Test:
1. Connect the low distortion oscillator output to the left and right audio inputs labeled 1 on the rear
panel of the MC-8.
2. With the amplifier powered off, connect the RCA left and right front outputs of the MC-8 to the
amplifier left and right inputs. Connect the outputs of the amplifier to the pair of speakers.
3. Using the remote control Menu arrow, scroll through the Diagnostics Menu and select the Audio
I/O Tests.
4. In the Audio I/O Test menu, highlight Audio Input 1 Test, and then press the Menu arrow to
engage the test. The MC-8 is now set to route audio from the left and right RCA inputs labeled 1 to all
RCA analog outputs.
5. Power on the amplifier.
6. Slowly increase the volume on the amplifier to a comfortable listening level.
7. Sweep the oscillator from 20Hz to 20kHz.
8. Verify that clean, undistorted audio can be heard throughout the frequency sweep.
9. Power down the amplifier.
10. Repeat steps 5 through 7 for the remaining paired RCA outputs.
4-3
MC-8 Service Manual
11. If testing an MC-8 Balanced unit, repeat the above procedure using XLR cables to connect the
appropriate MC-8 XLR Main Zone outputs to the amplifier.
12. The above procedure should be repeated to test Analog inputs 2 through 8. To do this, repeat the
procedure, changing the Input Test selected in step 4 to the next appropriate Input. The oscillator
outputs will need to be moved to the appropriate MC-8 Input, corresponding to the Input selected in
the Audio I/O Test Menu.
Digital Inputs to Main Zone Outputs Test
This test will verify the audio path between the S/PDIF coaxial and optical digital inputs labeled (1 to 4), to
all analog outputs, both RCA and XLR.
Note:
This test requires the use of a DVD/CD player as a source. The tests to follow will be run using a PCM
signal at a 44.1kHz sample rate.
Test:
1. Connect the S/PDIF coaxial digital output of the DVD/CD player to the S/PDIF coaxial digital input 1
on the rear of the MC-8.
2. With the amplifier off, connect the RCA left and right front outputs of the MC-8 to the amplifier left and
right inputs. Connect the outputs of the amplifier to a pair of speakers.
3. Using the remote control Menu arrow, scroll through the Diagnostic Menu and select the Audio I/O
Tests.
4. In the Audio I/O Test Menu, highlight S/PDIF Input CX 1 Test then press the Menu arrow to
engage the test. The MC-8 is now set to route digital audio from the S/PDIF coaxial digital input 1 to
all the RCA analog outputs.
5. Insert a CD and press play on the player.
6. Power on the amplifier.
7. Slowly increase the volume on the amplifier to a comfortable listening level.
8. Verify that clean, undistorted audio can be heard.
9. Stop the DVD player and power down the amplifier.
10. Repeat steps 2 through 7 for the remaining paired RCA outputs.
11. If testing an MC-8 Balanced unit, repeat the above procedure using XLR cables to connect the
appropriate MC-8 XLR Main Zone Outputs to the amplifier.
12. The above procedure should be repeated to test digital S/PDIF Inputs 2 through 4, as well as optical
Inputs labeled 1 to 4. To do this repeat the procedure, changing the Input test selected in step 4 to
the next appropriate Input. The DVD output will need to be moved to the appropriate MC-8 Input,
corresponding to the Input selected in the Audio I/O Test Menu. When testing the optical inputs, be
sure to use the appropriate digital cable.
4-4
Lexicon
AUDIO PERFORMANCE VERIFICATION
Performing these tests assures that the audio signal paths in the MC-8 meet published specifications.
These tests will verify the performance specifications of the A/D and D/A circuitry: gain, frequency
response, THD+N, S/N ratio, and dynamic range (when applicable) of each channel.
Analog Audio Inputs To Main Zone RCA Output Tests
These tests will verify the specifications of the Main Zone RCA output channels.
Setup:
1. Connect an audio cable between the output of the Low Distortion Oscillator and the MC-8 left RCA
input 1.
2. Connect an audio cable between the left front RCA output of the MC-8 and the input of the Distortion
Analyzer.
3. Using the MC-8 Remote Control Menu arrow, scroll through the Diagnostic Menu and select the
Audio I/O Tests.
4. In the Audio I/O Test Menu, highlight Audio Input 1 Test, and then press the Menu arrow to
engage the test. The MC-8 is now set to route audio from the left and right RCA inputs labeled 1 to all
RCA analog outputs.
Gain Test (GAIN) Test:
1. Apply a 997Hz signal @ + 4Vrms to Analog input labeled 1.
2. Set the scale on the Distortion Analyzer to measure +8Vrms signal level.
3. Turn all the filters off on the Analyzer (Filter not required for Gain Test).
4. Verify that the output level measurement from the MC-8 is between the range of +6.60Vrms and
+8.90Vrms. Note this level.
Total Harmonic Distortion + Noise Test (THD+N):
1. Adjust the scale on the Distortion Analyzer to measure 0.001% THD+N and turn on the 40kHz low
pass or audio band pass filter.
2. Sweep the oscillator frequency from 20Hz to 2kHz, and 8kHz to 40kHz.
3. Verify that the THD+N measured on the Analyzer is less than 0.01% (20Hz to 2kHz), and 0.02%
(8kHz to 40kHz).
Frequency Response Test (FREQ):
1. Set the scale on the Distortion Analyzer to measure +4Vrms signal level.
2. Using the output level from step 4 of the Gain Test, set the Distortion Analyzer for a 0dB reference to
check Frequency Response for the MC-8.
3. Turn the filter on the analyzer off.
4. Sweep the oscillator frequency from 10Hz to 40kHz.
5. Verify the signal levels are +0.05dBr to –0.15dBr 10Hz-20kHz, and +0.05dBr to –0.50dBr 20kHz40kHz of reference level over the entire sweep.
4-5
MC-8 Service Manual
Signal to Noise Test (SNR):
1. Using the 0dBr from step 2 of the Frequency Response Test, turn off the oscillator and verify a noise
level measurement <-108dBr.
2. Swap cables from the left RCA input 1 to the right RCA input 1 and the left front RCA output to the
right front RCA output. Repeat the GAIN, THD+N, FREQ and SNR tests for the remaining Main Zone
RCA Outputs.
Digital Inputs to Main Zone RCA Output Tests
Having tested all analog-to-analog specifications in the previous tests, it is now necessary to verify that all
the digital inputs pass specifications. These tests will verify the specifications of all digital inputs to the
front left and right RCA outputs.
Setup:
1. Connect a digital audio cable from the output of the Digital Function Generator to S/PDIF coaxial
input 1 on the rear of the MC-8.
2. Connect an audio cable between the left front RCA output of the MC-8 and the input of the Analog
Distortion Analyzer.
3. Using the remote control Menu arrow, scroll through the Diagnostic Menu and select the Audio I/O
Tests.
4. In the Audio I/O Test Menu, highlight S/PDIF Input CX number 1 Test then press the Menu arrow
to engage the test. The MC-8 is now set to pass digital audio from the S/PDIF coaxial RCA input 1 to
the front left and right RCA output.
Gain Test (GAIN):
1. Apply a 997Hz signal @ + 0.00dBFS (1Vrms) to S/PDIF coaxial input labeled 1.
2. Set the scale on the Distortion Analyzer to measure +8Vrms signal level.
3. Turn all the filters off on the Analyzer (Filters not required for Gain Test).
4. Verify that the output level measurement from the MC-8 is between the range of +3.73Vrms and
+4.47Vrms. Note this level.
Total Harmonic Distortion + Noise Test (THD+N):
1. Adjust the scale on the Distortion Analyzer to measure 0.001% THD+N and turn on the 40kHz low
pass or audio band pass filter.
2. Sweep the oscillator frequency from 20Hz to 2kHz, and 8kHz to 40kHz.
3. Verify that the THD+N measured on the Analyzer is less than 0.005% (20Hz to 2kHz), and 0.0175%
(8kHz to 40kHz).
4-6
Lexicon
Frequency Response Test (FREQ):
1. Set the scale on the Distortion Analyzer to measure +8Vrms signal level.
2. Using the output level from step 4 of the Gain Test, set the Distortion Analyzer for a 0dB reference to
check Frequency Response for the MC-8.
3. Turn the filter on the analyzer off.
4. Sweep the oscillator frequency from 10Hz to 40kHz.
5. Verify the signal levels are +0.05dBr to –0.10dBr 10Hz-20kHz, and +0.05dBr to –0.50dBr 20kHz40kHz of reference level over the entire sweep. Note these levels.
Dynamic Range Test (DYNRNG):
Using steps 1-3 of the Gain Test, set the oscillator to -60dBFS and verify a THD+N level measurement
<-108dBr.
Test the remaining inputs:
Use the GAIN, THD, FREQ and DYNRNG tests described above to test the remaining digital inputs (three
coaxial and four optical). When testing the optical inputs, be sure to use the appropriate digital cable.
Digital Inputs to Main Zone XLR Outputs Test
Note:
This test is for MC-8 Balanced units only.
Setup:
1. Connect a digital audio cable from the output of the Digital Function Generator to S/PDIF coaxial
input 1 on the rear of the MC-8B.
2. Connect an audio cable between the left front XLR output of the MC-8B and the input of the Analog
Distortion Analyzer.
3. Using the MC-8B Remote Control Menu arrow, scroll through the Diagnostic Menu and select the
Audio I/O Tests.
4. In the Audio I/O Test Menu, highlight S/PDIF Input CX number 1 Test then press the Menu arrow
to engage the test. The MC-8B is now set to pass digital audio from the S/PDIF coaxial RCA input 1
to the front left and right XLR output.
Gain Test (GAIN):
1. Apply a 997Hz signal @ +0.00dBFS to S/PDIF coaxial input 1.
2. Set the scale on the Distortion Analyzer to measure +8Vrms signal level.
3. Turn all the filters off on the Analyzer (Filter not required for Gain Test).
4. Verify that the output level measurement from the MC-8B is between the range of +7.43Vrms and
+8.83Vrms. Note this level.
4-7
MC-8 Service Manual
Total Harmonic Distortion + Noise Test (THD+N):
1. Adjust the scale on the Distortion Analyzer to measure 0.001% THD+N and turn on the 40kHz low
pass or audio band pass filter.
2. Sweep the oscillator frequency from 20Hz to 1kHz, and 5kHz to 40kHz.
3. Verify that the THD+N measured on the Analyzer is less than 0.005% (20Hz to 1kHz), and 0.02%
(5kHz to 40kHz).
Frequency Response Test (FREQ):
1. Set the scale on the Distortion Analyzer to measure +8Vrms signal level.
2. Using the output level from step 4 of the Gain Test, set the Distortion Analyzer for a 0dB reference to
check Frequency Response for the MC-8B.
3. Turn the filter on the analyzer off.
4. Sweep the oscillator frequency from 10Hz to 40kHz.
5. Verify the signal levels are +0.10dBr to –0.25dBr 10Hz-20kHz, and +0.10dBr to –0.75dBr 20kHz40kHz of reference level over the entire sweep. Note these levels.
Dynamic Range (DYNRNG):
Using steps 1-3 of the Gain Test, set the oscillator to -60dBFS and verify a THD+N level measurement
<-108dBr.
Test the remaining inputs:
Use the GAIN, THD, FREQ and DYNRNG tests described above to test the remaining digital inputs (three
coaxial and four optical). When testing the optical inputs, be sure to use the appropriate digital cable.
4-8
Lexicon
VIDEO INPUT/OUTPUT TESTS
These tests will verify that all thirteen video inputs and five video outputs pass video. There are three
different video paths to be tested in the MC-8: composite, S-video, and component. Composite and
S-video paths each have five inputs and two outputs. Component paths have three inputs and one output.
The following tests will verify that the MC-8 is passing clear, undistorted video. It is not necessary to enter
the Extended Diagnostics as was done in the audio tests.
Composite Video Input to Composite Video Outputs Test
This test will verify the composite video switching function of the MC-8.
Setup:
1. Connect the composite video output from the DVD player to the MC-8’s composite video input 1.
2. Connect the main composite output of the MC-8 to the composite input of the video monitor.
3. Turn on the DVD player, monitor, and the MC-8.
4. The monitor should display a blue screen.
5. Press the remote DVD1 button to select DVD-1 as the input for testing the video paths.
6. Press the Menu arrow. The MC-8 Main Menu will be displayed.
7. With the Menu arrow, scroll down to SETUP, then select by pressing the Menu arrow.
8. The Setup Menu will appear and Inputs at the top will be highlighted.
9. Press the Menu arrow again.
10. The display will read DVD1 Input Setup.
11. Press the Menu arrow. The DVD1 Menu will now be displayed.
12. Using the Menu arrow, scroll down to the Video In parameter and select it by pressing the Menu arrow.
13. Using the Menu arrow scroll to the video input Composite-1.
14. Press the Menu arrow to select video input Composite-1. This will assign the Composite -1 Video
input to the main composite output of the MC-8.
15. Press the remote OSD button to turn off the onscreen video information from the MC-8 and allow
viewing of the video from the DVD player.
16. The video path is now set for testing.
Test:
1. Load a disc into the DVD player and press play.
2. Verify a clean undistorted picture appears on the monitor.
3. Pause the DVD player.
4. To test the second composite output, switch the composite monitor output cable on the rear of the
MC-8 to the composite Zone 2 video output then repeat the procedure.
5. The setup and test procedure should be repeated to test composite video inputs labeled 2 through 5.
To do this, repeat the procedure, changing the Input Test selected in step 14 to the appropriate Input.
4-9
MC-8 Service Manual
S-video Inputs to S-video Outputs Test
This test will verify the S-video switching function of the MC-8.
Setup:
1. Connect the S-video output from the DVD player to the MC-8 S-video input 1.
2. Connect the main S-video output of the MC-8 to the S-video input of the video monitor.
3. Turn on the DVD player, monitor, and the MC-8.
4. The monitor should display a blue screen.
5. Press the remote DVD1 button to select this as the input for testing the video paths.
6. Press the Menu arrow. The Main Menu should appear on the screen.
7. With the Menu arrow, scroll down to Setup, and then select it by pressing the menu arrow.
8. The Setup Menu will appear and the Inputs at the top will be highlighted.
9. Press the Menu arrow again.
10. The display will read Input Setup DVD1.
11. Press the Menu arrow. The display on the MC-8 will now be at the top on the DVD1 Menu.
12. Using the Menu arrow, scroll down to the Video In parameter and select it by pressing the Menu arrow.
13. Using the Menu arrow, scroll to the video input S-video-1.
14. Press the Menu arrow to select the S-video-1 input. This will assign the S-video-1 input jack to the
Main Zone S-video output jack of the MC-8.
15. Press the remote OSD button. This will turn off the onscreen video information from the MC-8 and
allow viewing of the video from the DVD player.
16. The video path is now set for testing.
Test:
1. Load a disc into the DVD player and press play.
2. Verify a clean undistorted picture appears on the monitor screen.
3. Pause the DVD player.
4. To test the Zone 2 S-video output, switch the S-video monitor output cable on the back of the MC-8 to
the Zone 2 S-video output then repeat the procedure.
5. The above procedure should be repeated to test S-video inputs labeled 2 through 5. To do this,
repeat the procedure, changing the input selected in step 14 to the appropriate input.
4-10
Lexicon
Component Video Input to Component Video Output Test
This test will verify the component video switching function of the MC-8.
Setup:
1. Connect the component video output from the DVD player to the MC-8 component video input 1.
2. Connect the main component output of the MC-8 to the component input of the video monitor.
3. Turn on the DVD player, monitor, and the MC-8.
4. The monitor should display a blue screen.
5. Press the remote DVD1 button to select this as the input for testing the video paths.
6. Press the Menu arrow. The Main Menu should appear on the display.
7. Using the Menu arrow, scroll down to Setup, then select by pressing the Menu arrow.
8. The Setup Menu will appear and the inputs at the top will be highlighted.
9. Press the Menu arrow again.
10. The display will read Input Setup DVD1.
11. Press the Menu arrow. The display on the MC-8 will now be at the top of the DVD1 Menu.
12. Using the Menu arrow, scroll down to the Component In parameter and select it by pressing the
Menu arrow.
13. Press the Menu arrow to select the Component1 input. This will assign the component 1 video
input jack to the main component video output jack of the MC-8.
14. Press the remote OSD button. This will turn off the on-screen video information from the MC-8 and
allow viewing of the video from the DVD player.
15. The video path is now set for testing.
Test:
1. Load a disc into the DVD player and press play.
2. Verify a clean undistorted picture appears on the monitor screen.
3. Pause the DVD player.
4. The above procedure should be repeated to test the remaining two component Video inputs. To do
this, repeat the procedure, changing the Input selected in step 14 to the appropriate Input.
LEXICON AUDIO PRECISION ATE SUMMARY
This chart, which begins on the next page, represents a summary of Audio Precision test settings and
parameters used by Lexicon in production testing of all MC-8 products. This chart as well as the MC-8
ATE summary is provided as a reference and supplement to bench test settings found in the rest of the
Performance Verification section.
4-11
D-D Tests
Test Name
Digital Generator
See
Note: Left
DIG_ZONE_COAX1_IN_96k_TO_DIG_ZONE_COAX_OUT
DIG_ZONE_COAX1_IN_96k_TO_DIG_ZONE_COAX_OUT_GAIN
DIG_ZONE_COAX1_IN_96k_TO_DIG_ZONE_COAX_OUT_THD
-1dBFS
-1dBFS
D-A Tests
Test Name
Freq (Hz)
-1dBFS
-1dBFS
997
10-40k
3
3
3
3
3
Switcher Module
M
MC-8/B Setup
Z-out
Bal/
Unbal
Gnd/
Float
Level
Measure
Typical
Reading
Upper
Limit
Lower
Limit
Filter
Imp.
Band.
A In
B In
A Out
B Out
Midiman
PGM #:
Clock
Source
Sample
Rate
Audio
Source
n/a
n/a
n/a
n/a
n/a
n/a
dBFS
dBFS
Level
THD+N
-0.999
-144.00
-0.90
-140.00
-1.10
-999.00
n/a
n/a
n/a
n/a
<10 - Fs/2
<10Hz->20kHz LP
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
11
11
External
External
96000
96000
Analog
Analog
Z-out
Bal/
Unbal
Gnd/
Float
Level
Measure
Typical
Reading
Upper
Limit
Lower
Limit
Filter
Imp.
Band.
Digital Generator
See
Note: Left
DIG_ZONE_COAX1_IN_96k_TO_ANLG_ZONE_OUT
DIG_ZONE_COAX1_IN_96k_TO_ANLG_ZONE_OUT_GAIN
DIG_ZONE_COAX1_IN_96k_TO_ANLG_ZONE_OUT_FREQ
DIG_ZONE_COAX1_IN_96k_TO_ANLG_ZONE_OUT_THD
DIG_ZONE_COAX1_IN_96k_TO_ANLG_ZONE_OUT_XTALK
DIG_ZONE_COAX1_IN_96k_TO_ANLG_ZONE_OUT_DYNRNG
DIG_ZONE_COAX1_IN_88k_TO_ANLG_ZONE_OUT
DIG_ZONE_COAX1_IN_88k_TO_ANLG_ZONE_OUT_GAIN
DIG_ZONE_COAX1_IN_88k_TO_ANLG_ZONE_OUT_THD
DIG_ZONE_COAX1_IN_88k_TO_ANLG_ZONE_OUT_DYNRNG
DIG_ZONE_COAX1_IN_48k_TO_ANLG_ZONE_OUT
DIG_ZONE_COAX1_IN_48k_TO_ANLG_ZONE_OUT_GAIN
DIG_ZONE_COAX1_IN_48k_TO_ANLG_ZONE_OUT_THD
DIG_ZONE_COAX1_IN_48k_TO_ANLG_ZONE_OUT_DYNRNG
DIG_ZONE_COAX1_IN_44k_TO_ANLG_ZONE_OUT
DIG_ZONE_COAX1_IN_44k_TO_ANLG_ZONE_OUT_GAIN
DIG_ZONE_COAX1_IN_44k_TO_ANLG_ZONE_OUT_THD
DIG_ZONE_COAX1_IN_44k_TO_ANLG_ZONE_OUT_DYNRNG
DIG_ZONE_COAX2_IN_96k_TO_ANLG_ZONE_OUT
DIG_ZONE_COAX2_IN_44k_TO_ANLG_ZONE_OUT_GAIN
DIG_ZONE_COAX2_IN_44k_TO_ANLG_ZONE_OUT_THD
DIG_ZONE_COAX2_IN_96k_TO_ANLG_ZONE_OUT_DYNRNG
DIG_ZONE_COAX3_IN_96k_TO_ANLG_ZONE_OUT
DIG_ZONE_COAX3_IN_44k_TO_ANLG_ZONE_OUT_GAIN
DIG_ZONE_COAX3_IN_44k_TO_ANLG_ZONE_OUT_THD
DIG_ZONE_COAX3_IN_96k_TO_ANLG_ZONE_OUT_DYNRNG
DIG_ZONE_COAX4_IN_96k_TO_ANLG_ZONE_OUT
DIG_ZONE_COAX4_IN_44k_TO_ANLG_ZONE_OUT_GAIN
DIG_ZONE_COAX4_IN_44k_TO_ANLG_ZONE_OUT_THD
DIG_ZONE_COAX4_IN_96k_TO_ANLG_ZONE_OUT_DYNRNG
DIG_ZONE_OPT1_IN_96k_TO_ANLG_ZONE_OUT
DIG_ZONE_OPT1_IN_96k_TO_ANLG_ZONE_OUT_GAIN
DIG_ZONE_OPT1_IN_96k_TO_ANLG_ZONE_OUT_THD
DIG_ZONE_OPT1_IN_96k_TO_ANLG_ZONE_OUT_DYNRNG
DIG_ZONE_OPT2_IN_96k_TO_ANLG_ZONE_OUT
DIG_ZONE_OPT2_IN_96k_TO_ANLG_ZONE_OUT_GAIN
DIG_ZONE_OPT2_IN_96k_TO_ANLG_ZONE_OUT_THD
DIG_ZONE_OPT2_IN_96k_TO_ANLG_ZONE_OUT_DYNRNG
DIG_ZONE_OPT3_IN_96k_TO_ANLG_ZONE_OUT
DIG_ZONE_OPT3_IN_96k_TO_ANLG_ZONE_OUT_GAIN
DIG_ZONE_OPT3_IN_96k_TO_ANLG_ZONE_OUT_THD
DIG_ZONE_OPT3_IN_96k_TO_ANLG_ZONE_OUT_DYNRNG
DIG_ZONE_OPT4_IN_96k_TO_ANLG_ZONE_OUT
DIG_ZONE_OPT4_IN_96k_TO_ANLG_ZONE_OUT_GAIN
DIG_ZONE_OPT4_IN_96k_TO_ANLG_ZONE_OUT_THD
DIG_ZONE_OPT4_IN_96k_TO_ANLG_ZONE_OUT_DYNRNG
DIG_ZONE_OPT4_IN_96k_TO_ANLG_ZONE_OUT_OUTLEVEL_MUTE
DIG_ZONE_OPT4_IN_96k_TO_ANLG_ZONE_OUT_OUTLEVEL_MUTE
DIG_ZONE_OPT4_IN_96k_TO_ANLG_ZONE_OUT_RELAY_MUTE
DIG_ZONE_OPT4_IN_96k_TO_ANLG_ZONE_OUT_RELAY_MUTE
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_OUT
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_OUT_GAIN
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_OUT_FREQ
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_OUT_THD
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_OUT_XTALK
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_OUT_DYNRNG
Digital Analyzer
Right
Analog Analyzer
Switcher Module
M
MC-8/B Setup
A In
B In
A Out
B Out
Midiman
PGM #:
Clock
Source
Sample
Rate
Audio
Source
<10 - >500k
<10 - >500k
<10 - >500k
<10 - 22k
<10 - 22k
9
9
9
9
9
10
10
10
10
10
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
11
11
11
11
11
External
External
External
External
External
96000
96000
96000
96000
96000
Digital
Digital
Digital
Digital
Digital
40kHz LP 100k
40kHz LP 100k
None
100k
<10 - >500k
<10 - >500k
<10 - 22k
9
9
9
10
10
10
n/a
n/a
n/a
n/a
n/a
n/a
11
11
11
External
External
External
88200
88200
88200
Digital
Digital
Digital
+3.73
.0002
-140.00
40kHz LP 100k
40kHz LP 100k
None
100k
<10 - >500k
<10 - >500k
<10 - 22k
9
9
9
10
10
10
n/a
n/a
n/a
n/a
n/a
n/a
11
11
11
External
External
External
48000
48000
Digital
Digital
Digital
+4.47
.005
-103.00
+3.73
.0002
-140.00
40kHz LP 100k
40kHz LP 100k
None
100k
<10 - >500k
<10 - >500k
<10 - 22k
9
9
9
10
10
10
n/a
n/a
n/a
n/a
n/a
n/a
11
11
11
External
External
External
44100
44100
44100
Digital
Digital
Digital
+4.10
<.003
>-108.00
+4.47
.005
-103.00
+3.73
.0002
-140.00
40kHz LP 100k
40kHz LP 100k
None
100k
<10 - >500k
<10 - >500k
<10 - 22k
9
9
9
10
10
10
n/a
n/a
n/a
n/a
n/a
n/a
12
12
12
External
External
External
96000
96000
96000
Digital
Digital
Digital
Level
THD+N
THD+N
+4.10
<.003
>-108.00
+4.47
.005
-103.00
+3.73
.0002
-140.00
40kHz LP 100k
40kHz LP 100k
None
100k
<10 - >500k
<10 - >500k
<10 - 22k
9
9
9
10
10
10
n/a
n/a
n/a
n/a
n/a
n/a
13
13
13
External
External
External
96000
96000
96000
Digital
Digital
Digital
Vrms
%
dBr
Level
THD+N
THD+N
+4.10
<.003
>-108.00
+4.47
.005
-103.00
+3.73
.0002
-140.00
40kHz LP 100k
40kHz LP 100k
None
100k
<10 - >500k
<10 - >500k
<10 - 22k
9
9
9
10
10
10
n/a
n/a
n/a
n/a
n/a
n/a
14
14
14
External
External
External
96000
96000
96000
Digital
Digital
Digital
n/a
n/a
n/a
Vrms
%
dBr
Level
THD+N
THD+N
+4.10
<.003
>-108.00
+4.47
.005
-103.00
+3.73
.0002
-140.00
40kHz LP 100k
40kHz LP 100k
None
100k
<10 - >500k
<10 - >500k
<10 - 22k
9
9
9
10
10
10
n/a
n/a
n/a
n/a
n/a
n/a
11
11
11
External
External
External
96000
96000
96000
Digital
Digital
Digital
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
%
dBr
Level
THD+N
THD+N
+4.10
<.003
>-108.00
+4.47
.005
-103.00
+3.73
.0002
-140.00
40kHz LP 100k
40kHz LP 100k
None
100k
<10 - >500k
<10 - >500k
<10 - 22k
9
9
9
10
10
10
n/a
n/a
n/a
n/a
n/a
n/a
12
12
12
External
External
External
96000
96000
96000
Digital
Digital
Digital
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
%
dBr
Level
THD+N
THD+N
+4.10
<.003
>-108.00
+4.47
.005
-103.00
+3.73
.0002
-140.00
40kHz LP 100k
40kHz LP 100k
None
100k
<10 - >500k
<10 - >500k
<10 - 22k
9
9
9
10
10
10
n/a
n/a
n/a
n/a
n/a
n/a
13
13
13
External
External
External
96000
96000
96000
Digital
Digital
Digital
997
997
997
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
%
dBr
Level
THD+N
THD+N
+4.10
<.003
>-108.00
+4.47
.005
-103.00
+3.73
.0002
-140.00
40kHz LP 100k
40kHz LP 100k
None
100k
<10 - >500k
<10 - >500k
<10 - 22k
9
9
9
10
10
10
n/a
n/a
n/a
n/a
n/a
n/a
14
14
14
External
External
External
96000
96000
96000
Digital
Digital
Digital
+0.00dBFS
997
n/a
n/a
n/a
Vrms
Level
-103.00
-99.00
-1001.00
40kHz LP 100k
<10 - >500k
9
10
n/a
n/a
14
External
96000
Digital
+0.00dBFS
997
n/a
n/a
n/a
Vrms
Level
-125.00
-120.00
-1001.00
40kHz LP 100k
<10 - >500k
9
10
n/a
n/a
14
External
96000
Digital
+0.00dBFS
-1.00dBFS
-1.00dBFS
-1.00dBFS
-60.00dBFS
997
10-20k/40k
20-2k/8k-40k
15k
997
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
THD+N
+8.10
<-0.07/-0.30
<.003/.010
>-90.00
>-110.00
+8.83
+0.05
.005/.0175
-80.00
-108.00
+7.43
-0.10/-0.50
.0002
-150.00
-140.00
40kHz LP
None
40kHz LP
None
40kHz LP
<10 - >500k
<10 - >500k
<10 - >500k
<10 - 22k
<10 - 22k
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
2, 4, 6, 8
2, 4, 6, 8
2, 4, 6, 8
2, 4, 6, 8
2, 4, 6, 8
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
11
11
11
11
11
External
External
External
External
External
96000
96000
96000
96000
96000
Digital
Digital
Digital
Digital
Digital
Right
Freq (Hz)
+0.00dBFS
-1.00dBFS
-1.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
-1.00dBFS
-1.00dBFS
-1.00dBFS
-60.00dBFS
997
10-20k/40k
20-2k/8k-40k
15k
997
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
THD+N
+4.10
<-0.07/-0.39
<.003/.0075
>-90.00
>-108.00
+4.47
+0.10
.005/.0175
-80.00
-103.00
+3.73
-0.25/-0.75
.0002
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
+0.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
-1.00dBFS
-60.00dBFS
997
997
997
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
%
dBr
Level
THD+N
THD+N
+4.10
<.003
>-108.00
+4.47
.005
-103.00
+3.73
.0002
-140.00
+0.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
-1.00dBFS
-60.00dBFS
997
997
997
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
%
dBr
Level
THD+N
THD+N
+4.10
<.003
>-106.00
+4.47
.005
-103.00
+0.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
-1.00dBFS
-60.00dBFS
997
997
997
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
%
dBr
Level
THD+N
THD+N
+4.10
<.003
>-106.00
+0.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
-1.00dBFS
-60.00dBFS
997
997
997
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
%
dBr
Level
THD+N
THD+N
+0.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
-1.00dBFS
-60.00dBFS
997
997
997
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
%
dBr
+0.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
-1.00dBFS
-60.00dBFS
997
997
997
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
+0.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
-1.00dBFS
-60.00dBFS
997
997
997
n/a
n/a
n/a
n/a
n/a
n/a
+0.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
-1.00dBFS
-60.00dBFS
997
997
997
n/a
n/a
n/a
+0.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
-1.00dBFS
-60.00dBFS
997
997
997
+0.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
+0.00dBFS
+0.00dBFS
-1.00dBFS
-1.00dBFS
-1.00dBFS
-60.00dBFS
100k
100k
100k
100k
100k
D-A Tests
Test Name
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_OUT_OUTLEVEL_MUTE
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_OUT_OUTLEVEL_MUTE
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_OUT_RELAY_MUTE
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_OUT_RELAY_MUTE
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_OUT_CLKRNG
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_OUT_CLKRNG
DIG_MAIN_COAX1_IN_88K_TO_ANLG_MAIN_OUT
DIG_MAIN_COAX1_IN_88K_TO_ANLG_MAIN_OUT_GAIN
DIG_MAIN_COAX1_IN_88K_TO_ANLG_MAIN_OUT_THD
DIG_MAIN_COAX1_IN_88K_TO_ANLG_MAIN_OUT_DYNRNG
DIG_MAIN_COAX1_IN_88K_TO_ANLG_MAIN_OUT_CLKRNG
DIG_MAIN_COAX1_IN_88K_TO_ANLG_MAIN_OUT_CLKRNG
DIG_MAIN_COAX1_IN_48K_TO_ANLG_MAIN_OUT
DIG_MAIN_COAX1_IN_48K_TO_ANLG_MAIN_OUT_GAIN
DIG_MAIN_COAX1_IN_48K_TO_ANLG_MAIN_OUT_THD
DIG_MAIN_COAX1_IN_48K_TO_ANLG_MAIN_OUT_DYNRNG
DIG_MAIN_COAX1_IN_44K_TO_ANLG_MAIN_OUT
DIG_MAIN_COAX1_IN_44K_TO_ANLG_MAIN_OUT_GAIN
DIG_MAIN_COAX1_IN_44K_TO_ANLG_MAIN_OUT_THD
DIG_MAIN_COAX1_IN_44K_TO_ANLG_MAIN_OUT_DYNRNG
Digital Generator
See
Note: Left
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_XLR_OUT
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_XLR_OUT_GAIN
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_XLR_OUT_FREQ
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_XLR_OUT_THD
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_XLR_OUT_XTALK
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_XLR_OUT_DYNRNG
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_XLR_OUT_600
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_XLR_OUT_GAIN_600
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_XLR_OUT_THD_600
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_XLR_OUT_RELAY_MUTE
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_XLR_OUT_RELAY_MUTE
A-A Tests
Test Name
ANLG_ZONE_IN1_96K_TO_ANLG_ZONE_DIR_OUT
ANLG_ZONE_IN1_96K_TO_ANLG_ZONE_DIR_OUT_GAIN
ANLG_ZONE_IN1_96K_TO_ANLG_ZONE_DIR_OUT_FREQ
ANLG_ZONE_IN1_96K_TO_ANLG_ZONE_DIR_OUT_THD
ANLG_ZONE_IN1_96K_TO_ANLG_ZONE_DIR_OUT_XTALK
ANLG_ZONE_IN1_96K_TO_ANLG_ZONE_DIR_OUT_SNR
ANLG_ZONE_IN2_96K_TO_ANLG_ZONE_DIR_OUT
ANLG_ZONE_IN2_96K_TO_ANLG_ZONE_DIR_OUT_GAIN
ANLG_ZONE_IN2_96K_TO_ANLG_ZONE_DIR_OUT_FREQ
ANLG_ZONE_IN2_96K_TO_ANLG_ZONE_DIR_OUT_THD
ANLG_ZONE_IN2_96K_TO_ANLG_ZONE_DIR_OUT_XTALK
ANLG_ZONE_IN2_96K_TO_ANLG_ZONE_DIR_OUT_SNR
Module
Switcher M
Analog Analyzer
Freq (Hz)
Z-out
Bal/
Unbal
Gnd/
Float
Level
Measure
Typical
Reading
Upper
Limit
Lower
Limit
Filter
Imp.
Band.
MC-8/B Setup
A In
B In
A Out
B Out
Midiman
PGM #:
Clock
Source
Sample
Rate
Audio
Source
3
+0.00dBFS
+0.00dBFS
997
n/a
n/a
n/a
Vrms
Level
-104.00
-100.00
1001.00
40kHz LP 100k
<10 - >500k
1, 3, 5, 7
2, 4, 6, 8
n/a
n/a
11
External
96000
Digital
3
+0.00dBFS
+0.00dBFS
997
n/a
n/a
n/a
Vrms
Level
-125.00
-120.00
1001.00
40kHz LP 100k
<10 - >500k
1, 3, 5, 7
2, 4, 6, 8
n/a
n/a
11
External
96000
Digital
4
-1.00dBFS
-1.00dBFS
997
n/a
n/a
n/a
%
THD+N
>-92.00
-82.00
-105.00
None
<10 - 22k
1
n/a
n/a
n/a
11
External
87.3K-89.1K
Digital
3
3
3
+0.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
-1.00dBFS
-60.00dBFS
997
997
997
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
%
dBr
Level
THD+N
THD+N
+8.10
<.003
>-110.00
+8.83
.005
-108.00
+7.43
.0002
-140.00
40kHz LP 100k
40kHz LP 100k
40kHz LP 100k
<10 - >500k
<10 - >500k
<10 - 22k
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
2, 4, 6, 8
2, 4, 6, 8
2, 4, 6, 8
n/a
n/a
n/a
n/a
n/a
n/a
11
11
11
External
External
External
88200
88200
88200
Digital
Digital
Digital
4
-1.00dBFS
-1.00dBFS
997
n/a
n/a
n/a
%
THD+N
>-92.00
-82.00
-105.00
None
<10 - 22k
1
n/a
n/a
n/a
11
External
97K-95K
Digital
3
3
3
+0.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
-1.00dBFS
-60.00dBFS
997
997
997
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
%
dBr
Level
THD+N
THD+N
+8.10
<.003
>-110.00
+8.83
.005
-108.00
+7.43
.0002
-140.00
40kHz LP 100k
40kHz LP 100k
40kHz LP 100k
<10 - >500k
<10 - >500k
<10 - 22k
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
2, 4, 6, 8
2, 4, 6, 8
2, 4, 6, 8
n/a
n/a
n/a
n/a
n/a
n/a
11
11
11
External
External
External
48000
48000
48000
Digital
Digital
Digital
3
3
3
+0.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
-1.00dBFS
-60.00dBFS
997
997
997
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
%
dBr
Level
THD+N
THD+N
+8.10
<.003
>-110.00
+8.83
.005
-108.00
+7.43
.0002
-140.00
40kHz LP 100k
40kHz LP 100k
40kHz LP 100k
<10 - >500k
<10 - >500k
<10 - 22k
1, 3, 5, 7
1, 3, 5, 7
1, 3, 5, 7
2, 4, 6, 8
2, 4, 6, 8
2, 4, 6, 8
n/a
n/a
n/a
n/a
n/a
n/a
11
11
11
External
External
External
44100
44100
44100
Digital
Digital
Digital
Z-out
Bal/
Unbal
Gnd/
Float
Level
Measure
Typical
Reading
Upper
Limit
Lower
Limit
Filter
Imp.
Band.
Digital Generator
D-A XLR Tests (MC-8B ONLY)
Test Name
DIG_ZONE_COAX1_IN_96K_TO_ANLG_ZONE_XLR_OUT
DIG_ZONE_COAX1_IN_96K_TO_ANLG_ZONE_XLR_OUT_GAIN
DIG_ZONE_COAX1_IN_96K_TO_ANLG_ZONE_XLR_OUT_FREQ
DIG_ZONE_COAX1_IN_96K_TO_ANLG_ZONE_XLR_OUT_THD
DIG_ZONE_COAX1_IN_96K_TO_ANLG_ZONE_XLR_OUT_XTALK
DIG_ZONE_COAX1_IN_96K_TO_ANLG_ZONE_XLR_OUT_DYNRNG
DIG_ZONE_COAX1_IN_96K_TO_ANLG_ZONE_XLR_OUT_600
DIG_ZONE_COAX1_IN_96K_TO_ANLG_ZONE_XLR_OUT_GAIN_600
DIG_ZONE_COAX1_IN_96K_TO_ANLG_ZONE_XLR_OUT_THD_600
DIG_ZONE_COAX1_IN_96K_TO_ANLG_ZONE_XLR_OUT_RELAY_MUTE
DIG_ZONE_COAX1_IN_96K_TO_ANLG_ZONE_XLR_OUT_RELAY_MUTE
Right
See
Note: Left
100k
100k
Module
Switcher M
Analog Analyzer
B In
A Out
B Out
Midiman
PGM #:
Clock
Source
Sample
Rate
Audio
Source
<10 - >500k
<10 - >500k
<10 - >500k
<10 - 22k
<10 - 22k
21
21
21
21
21
22
22
22
22
22
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
11
11
11
11
11
External
External
External
External
External
96000
96000
96000
96000
96000
Digital
Digital
Digital
Digital
Digital
40kHz LP 100k
40kHz LP 100k
<10 - >500k
<10 - >500k
21
21
22
22
n/a
n/a
n/a
n/a
11
11
External
External
96000
96000
Digital
Digital
-1001.00
40kHz LP 100k
<10 - >500k
21
22
n/a
n/a
11
External
96000
Digital
+17.60
+0.05
.005/.020
-80.00
-108.00
+14.80
-0.1/-0.5
.0002
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
<10 - >500k
<10 - >500k
<10 - >500k
<10 - 22k
<10 - 22k
13,15,17,19
13,15,17,19
13,15,17,19
13,15,17,19
13,15,17,19
14,16,18,20
14,16,18,20
14,16,18,20
14,16,18,20
14,16,18,20
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
11
11
11
11
11
External
External
External
External
External
96000
96000
96000
96000
96000
Digital
Digital
Digital
Digital
Digital
+9.65
<.003
+10.63
.005
+8.93
.0002
40kHz LP 100k
40kHz LP 100k
<10 - >500k
<10 - >500k
13,15,17,19
13,15,17,19
14,16,18,20
14,16,18,20
n/a
n/a
n/a
n/a
11
11
External
External
96000
96000
Digital
Digital
-140.00
-120.00
-1001.00
40kHz LP 100k
<10 - >500k
13,15,17,19
14,16,18,20
n/a
n/a
11
External
96000
Digital
Typical
Reading
Upper
Limit
Lower
Limit
Filter
Imp.
Band.
Freq (Hz)
+0.00dBFS
-1.00dBFS
-1.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
-1.00dBFS
-1.00dBFS
-1.00dBFS
-60.00dBFS
997
10-20k/40k
20-1k/5k-40k
15k
997
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
THD+N
+8.10
<-0.15/-0.60
<.003/.075
>-88.00
>-110.00
+8.83
+0.10
.005/.020
-80.00
-105.00
+7.43
-0.25/-0.75
.0002
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
+0.00dBFS
-1.00dBFS
+0.00dBFS
-1.00dBFS
997
100
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
%
Level
THD+N
+6.85
<.002
+7.50
.005
+6.30
.0002
+0.00dBFS
+0.00dBFS
997
n/a
n/a
n/a
Vrms
Level
-135.00
-120.00
3
3
3
3
3
+0.00dBFS
-1.00dBFS
-1.00dBFS
-1.00dBFS
-60.00dBFS
+0.00dBFS
-1.00dBFS
-1.00dBFS
-1.00dBFS
-60.00dBFS
997
10-20k/40k
20-1k/5k-40k
15k
997
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
THD+N
+16.10
<-0.05/-0.25
<.003/.010
>-83.00
>-110.00
3
3
-3.00dBFS
-3.00dBFS
-3.00dBFS
-3.00dBFS
997
100
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
%
Level
THD+N
3
+0.00dBFS
+0.00dBFS
997
n/a
n/a
n/a
Vrms
Level
Z-out
Bal/
Unbal
Gnd/
Float
Level
Measure
Analog Generator
See
Note: Left
MC-8/B Setup
A In
Right
Module
Switcher M
Analog Analyzer
Right
Freq (Hz)
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
997
10-40k
20-40k
15k
997
20
20
20
20
20
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
+4.00
<-0.10
<.010
>-115.00
-108.00
+4.30
+0.10
.015
-100.00
-95.00
+3.70
-0.25
.00005
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
997
10-40k
20-40k
15k
997
20
20
20
20
20
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
+4.00
<-0.10
<.010
>-115.00
-108.00
+4.30
+0.10
.015
-100.00
-95.00
+3.70
-0.25
.00005
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
MC-8/B Setup
A In
B In
A Out
B Out
Midiman
PGM #:
Clock
Source
Sample
Rate
Audio
Source
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
9
9
9
9
9
10
10
10
10
10
1
1
1
1
1
13
13
13
13
13
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
9
9
9
9
9
10
10
10
10
10
2
2
2
2
2
14
14
14
14
14
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
A-A Tests
Test Name
ANLG_ZONE_IN3_96K_TO_ANLG_ZONE_DIR_OUT
ANLG_ZONE_IN3_96K_TO_ANLG_ZONE_DIR_OUT_GAIN
ANLG_ZONE_IN3_96K_TO_ANLG_ZONE_DIR_OUT_FREQ
ANLG_ZONE_IN3_96K_TO_ANLG_ZONE_DIR_OUT_THD
ANLG_ZONE_IN3_96K_TO_ANLG_ZONE_DIR_OUT_XTALK
ANLG_ZONE_IN3_96K_TO_ANLG_ZONE_DIR_OUT_SNR
ANLG_ZONE_IN4_96K_TO_ANLG_ZONE_DIR_OUT
ANLG_ZONE_IN4_96K_TO_ANLG_ZONE_DIR_OUT_GAIN
ANLG_ZONE_IN4_96K_TO_ANLG_ZONE_DIR_OUT_FREQ
ANLG_ZONE_IN4_96K_TO_ANLG_ZONE_DIR_OUT_THD
ANLG_ZONE_IN4_96K_TO_ANLG_ZONE_DIR_OUT_XTALK
ANLG_ZONE_IN4_96K_TO_ANLG_ZONE_DIR_OUT_SNR
ANLG_ZONE_IN5_96K_TO_ANLG_ZONE_DIR_OUT
ANLG_ZONE_IN5_96K_TO_ANLG_ZONE_DIR_OUT_GAIN
ANLG_ZONE_IN5_96K_TO_ANLG_ZONE_DIR_OUT_FREQ
ANLG_ZONE_IN5_96K_TO_ANLG_ZONE_DIR_OUT_THD
ANLG_ZONE_IN5_96K_TO_ANLG_ZONE_DIR_OUT_XTALK
ANLG_ZONE_IN5_96K_TO_ANLG_ZONE_DIR_OUT_SNR
ANLG_ZONE_IN6_96K_TO_ANLG_ZONE_DIR_OUT
ANLG_ZONE_IN6_96K_TO_ANLG_ZONE_DIR_OUT_GAIN
ANLG_ZONE_IN6_96K_TO_ANLG_ZONE_DIR_OUT_FREQ
ANLG_ZONE_IN6_96K_TO_ANLG_ZONE_DIR_OUT_THD
ANLG_ZONE_IN6_96K_TO_ANLG_ZONE_DIR_OUT_XTALK
ANLG_ZONE_IN6_96K_TO_ANLG_ZONE_DIR_OUT_SNR
ANLG_ZONE_IN7_96K_TO_ANLG_ZONE_DIR_OUT
ANLG_ZONE_IN7_96K_TO_ANLG_ZONE_DIR_OUT_GAIN
ANLG_ZONE_IN7_96K_TO_ANLG_ZONE_DIR_OUT_FREQ
ANLG_ZONE_IN7_96K_TO_ANLG_ZONE_DIR_OUT_THD
ANLG_ZONE_IN7_96K_TO_ANLG_ZONE_DIR_OUT_XTALK
ANLG_ZONE_IN7_96K_TO_ANLG_ZONE_DIR_OUT_SNR
ANLG_ZONE_IN8_96K_TO_ANLG_ZONE_DIR_OUT
ANLG_ZONE_IN8_96K_TO_ANLG_ZONE_DIR_OUT_GAIN
ANLG_ZONE_IN8_96K_TO_ANLG_ZONE_DIR_OUT_FREQ
ANLG_ZONE_IN8_96K_TO_ANLG_ZONE_DIR_OUT_THD
ANLG_ZONE_IN8_96K_TO_ANLG_ZONE_DIR_OUT_XTALK
ANLG_ZONE_IN8_96K_TO_ANLG_ZONE_DIR_OUT_SNR
ANLG_MAIN_IN1_96K_TO_ANLG_MAIN_OUT
ANLG_MAIN_IN1_96K_TO_ANLG_MAIN_OUT_GAIN
ANLG_MAIN_IN1_96K_TO_ANLG_MAIN_OUT_FREQ
ANLG_MAIN_IN1_96K_TO_ANLG_MAIN_OUT_THD
ANLG_MAIN_IN1_96K_TO_ANLG_MAIN_OUT_XTALK
ANLG_MAIN_IN1_96K_TO_ANLG_MAIN_OUT_SNR
ANLG_MAIN_IN2_96K_TO_ANLG_MAIN_OUT
ANLG_MAIN_IN2_96K_TO_ANLG_MAIN_OUT_GAIN
ANLG_MAIN_IN2_96K_TO_ANLG_MAIN_OUT_FREQ
ANLG_MAIN_IN2_96K_TO_ANLG_MAIN_OUT_THD
ANLG_MAIN_IN2_96K_TO_ANLG_MAIN_OUT_XTALK
ANLG_MAIN_IN2_96K_TO_ANLG_MAIN_OUT_SNR
ANLG_MAIN_IN3_96K_TO_ANLG_MAIN_OUT
ANLG_MAIN_IN3_96K_TO_ANLG_MAIN_OUT_GAIN
ANLG_MAIN_IN3_96K_TO_ANLG_MAIN_OUT_FREQ
ANLG_MAIN_IN3_96K_TO_ANLG_MAIN_OUT_THD
ANLG_MAIN_IN3_96K_TO_ANLG_MAIN_OUT_XTALK
ANLG_MAIN_IN3_96K_TO_ANLG_MAIN_OUT_SNR
ANLG_MAIN_IN4_96K_TO_ANLG_MAIN_OUT
ANLG_MAIN_IN4_96K_TO_ANLG_MAIN_OUT_GAIN
ANLG_MAIN_IN4_96K_TO_ANLG_MAIN_OUT_FREQ
ANLG_MAIN_IN4_96K_TO_ANLG_MAIN_OUT_THD
ANLG_MAIN_IN4_96K_TO_ANLG_MAIN_OUT_XTALK
ANLG_MAIN_IN4_96K_TO_ANLG_MAIN_OUT_SNR
ANLG_MAIN_IN5_96K_TO_ANLG_MAIN_OUT
ANLG_MAIN_IN5_96K_TO_ANLG_MAIN_OUT_GAIN
ANLG_MAIN_IN5_96K_TO_ANLG_MAIN_OUT_FREQ
ANLG_MAIN_IN5_96K_TO_ANLG_MAIN_OUT_THD
ANLG_MAIN_IN5_96K_TO_ANLG_MAIN_OUT_XTALK
ANLG_MAIN_IN5_96K_TO_ANLG_MAIN_OUT_SNR
Analog Generator
Analog Analyzer
Switcher Module
M
Z-out
Bal/
Unbal
Gnd/
Float
Level
Measure
Typical
Reading
Upper
Limit
Lower
Limit
Filter
Imp.
Band.
997
10-40k
20-40k
15k
997
20
20
20
20
20
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
+4.00
<-0.10
<.010
>-115.00
-108.00
+4.30
+0.10
.015
-100.00
-95.00
+3.70
-0.25
.00005
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
997
10-40k
20-40k
15k
997
20
20
20
20
20
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
+4.00
<-0.10
<.010
>-115.00
-108.00
+4.30
+0.10
.015
-100.00
-95.00
+3.70
-0.25
.00005
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
997
10-40k
20-40k
15k
997
20
20
20
20
20
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
+4.00
<-0.10
<.010
>-115.00
-108.00
+4.30
+0.10
.015
-100.00
-95.00
+3.70
-0.25
.00005
-150.00
-140.00
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
997
10-40k
20-40k
15k
997
20
20
20
20
20
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
+4.00
<-0.10
<.010
>-115.00
-108.00
+4.30
+0.10
.015
-100.00
-95.00
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
997
10-40k
20-40k
15k
997
20
20
20
20
20
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
+4.00
<-0.10
<.010
>-115.00
-108.00
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
997
10-40k
20-40k
15k
997
20
20
20
20
20
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
3
3
3
3
3
4.0Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.0Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
997
10-20k/40k
20-2k/8k-40k
15k
997
20
20
20
20
20
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
3
3
3
3
3
4.0Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.0Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
997
10-20k/40k
20-2k/8k-40k
15k
997
20
20
20
20
20
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
3
3
3
3
3
4.0Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.0Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
997
10-20k/40k
20-2k/8k-40k
15k
997
20
20
20
20
20
Unbal
Unbal
Unbal
Unbal
Unbal
3
3
3
3
3
4.0Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.0Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
997
10-20k/40k
20-2k/8k-40k
15k
997
20
20
20
20
20
3
3
3
3
3
4.0Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.0Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
997
10-20k/40k
20-2k/8k-40k
15k
997
20
20
20
20
20
See
Note: Left
Right
Freq (Hz)
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
MC-8/B Setup
A In
B In
A Out
B Out
Midiman
PGM #:
Clock
Source
Sample
Rate
Audio
Source
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
9
9
9
9
9
10
10
10
10
10
3
3
3
3
3
15
15
15
15
15
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
100k
100k
100k
100k
100k
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
9
9
9
9
9
10
10
10
10
10
4
4
4
4
4
16
16
16
16
16
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
9
9
9
9
9
10
10
10
10
10
5
5
5
5
5
17
17
17
17
17
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
+3.70
-0.25
.00005
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
9
9
9
9
9
10
10
10
10
10
6
6
6
6
6
18
18
18
18
18
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
+4.30
+0.10
.015
-100.00
-95.00
+3.70
-0.25
.00005
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
9
9
9
9
9
10
10
10
10
10
7
7
7
7
7
19
19
19
19
19
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
+4.00
<-0.10
<.010
>-115.00
-108.00
+4.30
+0.10
.015
-100.00
-95.00
+3.70
-0.25
.00005
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
9
9
9
9
9
10
10
10
10
10
8
8
8
8
8
20
20
20
20
20
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
Level
Level
THD+N
Level
Level
+7.80
<-0.05/-0.25
<.005/.010
>-85.00
-99.00
+8.90
+0.05
.010/.020
-80.00
-97.00
+6.60
-0.15/-0.50
.00005
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
1
1
1
1
1
2
2
2
2
2
1
1
1
1
1
13
13
13
13
13
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
+7.80
<-0.05/-0.25
<.005/.010
>-85.00
-99.00
+8.90
+0.05
.010/.020
-80.00
-97.00
+6.60
-0.15/-0.50
.00005
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
14
14
14
14
14
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
+7.80
<-0.05/-0.25
<.005/.010
>-85.00
-99.00
+8.90
+0.05
.010/.020
-80.00
-97.00
+6.60
-0.15/-0.50
.00005
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
1
1
1
1
1
2
2
2
2
2
3
3
3
3
3
15
15
15
15
15
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
+7.80
<-0.05/-0.25
<.005/.010
>-85.00
-99.00
+8.90
+0.05
.010/.020
-80.00
-97.00
+6.60
-0.15/-0.50
.00005
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
1
1
1
1
1
2
2
2
2
2
4
4
4
4
4
16
16
16
16
16
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
+7.80
<-0.05/-0.25
<.005/.010
>-85.00
-99.00
+8.90
+0.05
.010/.020
-80.00
-97.00
+6.60
-0.15/-0.50
.00005
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
1
1
1
1
1
2
2
2
2
2
5
5
5
5
5
17
17
17
17
17
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
A-A Tests
Test Name
ANLG_MAIN_IN6_96K_TO_ANLG_MAIN_OUT
ANLG_MAIN_IN6_96K_TO_ANLG_MAIN_OUT_GAIN
ANLG_MAIN_IN6_96K_TO_ANLG_MAIN_OUT_FREQ
ANLG_MAIN_IN6_96K_TO_ANLG_MAIN_OUT_THD
ANLG_MAIN_IN6_96K_TO_ANLG_MAIN_OUT_XTALK
ANLG_MAIN_IN6_96K_TO_ANLG_MAIN_OUT_SNR
ANLG_MAIN_IN7_96K_TO_ANLG_MAIN_OUT
ANLG_MAIN_IN7_96K_TO_ANLG_MAIN_OUT_GAIN
ANLG_MAIN_IN7_96K_TO_ANLG_MAIN_OUT_FREQ
ANLG_MAIN_IN7_96K_TO_ANLG_MAIN_OUT_THD
ANLG_MAIN_IN7_96K_TO_ANLG_MAIN_OUT_XTALK
ANLG_MAIN_IN7_96K_TO_ANLG_MAIN_OUT_SNR
ANLG_MAIN_IN8_96K_TO_ANLG_MAIN_OUT
ANLG_MAIN_IN8_96K_TO_ANLG_MAIN_OUT_GAIN
ANLG_MAIN_IN8_96K_TO_ANLG_MAIN_OUT_FREQ
ANLG_MAIN_IN8_96K_TO_ANLG_MAIN_OUT_THD
ANLG_MAIN_IN8_96K_TO_ANLG_MAIN_OUT_XTALK
ANLG_MAIN_IN8_96K_TO_ANLG_MAIN_OUT_SNR
ANLG_MAIN_IN345_96K_TO_ANLG_MAIN_DIR_OUT
ANLG_MAIN_IN345_96K_TO_ANLG_MAIN_DIR_OUT_GAIN
ANLG_MAIN_IN345_96K_TO_ANLG_MAIN_DIR_OUT_FREQ
ANLG_MAIN_IN345_96K_TO_ANLG_MAIN_DIR_OUT_THD
ANLG_MAIN_IN345_96K_TO_ANLG_MAIN_DIR_OUT_XTALK
ANLG_MAIN_IN345_96K_TO_ANLG_MAIN_DIR_OUT_SNR
ANLG_MAIN_IN345_96K_TO_ANLG_MAIN_DIR_OUT_DADIRMUX
ANLG_MAIN_IN345_96K_TO_ANLG_MAIN_DIR_OUT_DADIRMUX
ANLG_MAIN_IN678_96K_TO_ANLG_MAIN_DIR_OUT
ANLG_MAIN_IN678_96K_TO_ANLG_MAIN_DIR_OUT_GAIN
ANLG_MAIN_IN678_96K_TO_ANLG_MAIN_DIR_OUT_FREQ
ANLG_MAIN_IN678_96K_TO_ANLG_MAIN_DIR_OUT_THD
ANLG_MAIN_IN678_96K_TO_ANLG_MAIN_DIR_OUT_XTALK
ANLG_MAIN_IN678_96K_TO_ANLG_MAIN_DIR_OUT_SNR
ANLG_MAIN_IN678_96K_TO_ANLG_MAIN_DIR_OUT_DADIRMUX
ANLG_MAIN_IN678_96K_TO_ANLG_MAIN_DIR_OUT_DADIRMUX
Analog Generator
See
Note: Left
Freq (Hz)
Level
Measure
Typical
Reading
Upper
Limit
Lower
Limit
Filter
Imp.
Band.
MC-8/B Setup
A In
B In
A Out
B Out
Midiman
PGM #:
Clock
Source
Sample
Rate
Audio
Source
997
10-20k/40k
20-2k/8k-40k
15k
997
20
20
20
20
20
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
+7.80
<-0.05/-0.25
<.005/.010
>-85.00
-99.00
+8.90
+0.05
.010/.020
-80.00
-97.00
+6.60
-0.15/-0.50
.00005
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
1
1
1
1
1
2
2
2
2
2
6
6
6
6
6
18
18
18
18
18
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
3
3
3
3
3
4.0Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.0Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
997
10-20k/40k
20-2k/8k-40k
15k
997
20
20
20
20
20
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
+7.80
<-0.05/-0.25
<.005/.010
>-85.00
-99.00
+8.90
+0.05
.010/.020
-80.00
-97.00
+6.60
-0.15/-0.50
.00005
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
1
1
1
1
1
2
2
2
2
2
7
7
7
7
7
19
19
19
19
19
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
3
3
3
3
3
4.0Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.0Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
997
10-20k/40k
20-2k/8k-40k
15k
997
20
20
20
20
20
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
+7.80
<-0.05/-0.25
<.005/.010
>-85.00
-99.00
+8.90
+0.05
.010/.020
-80.00
-97.00
+6.60
-0.15/-0.50
.00005
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
1
1
1
1
1
2
2
2
2
2
8
8
8
8
8
20
20
20
20
20
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
3
3
3
3
3
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
997
10-40k
20-5k/10k-40k
15k
997
20
20
20
20
20
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
+4.00
<-0.03
<.01/.015
>-104
-108.00
+4.15
+0.05
.010/.020
-95.00
-100.00
+3.85
-0.25
.00005
-150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
3,4,5,5
3,4,5,5
3,4,5,5
3,4,5,5
3,4,5,5
15,16,17,17
15,16,17,17
15,16,17,17
15,16,17,17
15,16,17,17
1,3,5,7
1,3,5,7
1,3,5,7
1,3,5,7
1,3,5,7
2,4,6,8
2,4,6,8
2,4,6,8
2,4,6,8
2,4,6,8
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
OFF
OFF
997
20
Unbal
Float
Vrms
Level
-80.00
-70.00
-140.00
40kHz LP 100k
<10 - >500k
3,4,5,5
15,16,17,17
1,3,5,7
2,4,6,8
n/a
Internal
96000
Analog
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
4.00 Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
997
10-40k
20-5k/10k-40k
15k
997
20
20
20
20
20
Unbal
Unbal
Unbal
Unbal
Unbal
Float
Float
Float
Float
Float
Vrms
dBr
%
dB
dBr
Level
Level
THD+N
Level
Level
+4.00
<-0.03
<.01/.015
>-104
-108.00
+4.15
+0.05
.010/.020
-95.00
-100.00
+3.85
-0.25
.00005
150.00
-140.00
40kHz LP
None
40kHz LP
None
None
100k
100k
100k
100k
100k
<10 - >500k
<10 - >500k
<10 - >500k
<10 - >22k
<10 - >22k
6,7,8,8
6,7,8,8
6,7,8,8
6,7,8,8
6,7,8,8
18,19,20,20
18,19,20,20
18,19,20,20
18,19,20,20
18,19,20,20
1,3,5,7
1,3,5,7
1,3,5,7
1,3,5,7
1,3,5,7
2,4,6,8
2,4,6,8
2,4,6,8
2,4,6,8
2,4,6,8
n/a
n/a
n/a
n/a
n/a
Internal
Internal
Internal
Internal
Internal
96000
96000
96000
96000
96000
Analog
Analog
Analog
Analog
Analog
OFF
OFF
997
20
Unbal
Float
Vrms
Level
-80.00
-70.00
-140.00
40kHz LP 100k
<10 - >500k
6,7,8,8
18,19,20,20
1,3,5,7
2,4,6,8
n/a
Internal
96000
Analog
2&3
3
3
3
3
3
2&3
Digital Generator
See
Note: Left
Right
Freq (Hz)
3&5
3&5
3&5
+0.00dBFS
-1.00dBFS
-60.00dBFS
997
997
997
+0.00dBFS
-1.00dBFS
-60.00dBFS
Switcher Module
M
Analog Analyzer
2. The Analog Main Direct Input paths are selected at the MUX while the Main D/A converters are being driven with a -1dBFS Digital Input from COAX1.
5. The DSP Tests are used to verify the operation of the Decoder and DSP Boards.
Gnd/
Float
4.0Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
Notes:
4. The CLKRNG Tests are used to verify the operation of the PLL circuitry.
Bal/
Unbal
4.0Vrms
2.00 Vrms
4.0Vrms
4.0Vrms
OFF
1. The Analog Zone Direct Input paths are selected at the MUX while the Zone D/A converter is being driven with a -1dBFS Digital Input from COAX1.
3. The Audio Precision Switcher channels are selected during the Audio ATE macro.
Z-out
3
3
3
3
3
D-A DSP Tests
Test Name
DIG_MAIN_OPT1_IN_96K_TO_ANLG_MAIN_OUT_DSP
DIG_MAIN_OPT1_IN_96K_TO_ANLG_MAIN_OUT_DSP_GAIN
DIG_MAIN_OPT1_IN_96K_TO_ANLG_MAIN_OUT_DSP_THD
DIG_MAIN_COAX1_IN_96K_TO_ANLG_MAIN_OUT_DSP_DYNRNG
Switcher Module
M
Analog Analyzer
Right
Z-out
Bal/
Unbal
Gnd/
Float
Level
Measure
Typical
Reading
Upper
Limit
Lower
Limit
Filter
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Vrms
%
dBr
Level
THD+N
THD+N
+8.10
<.002
>-110.00
+8.83
.005
-108.00
+7.43
.0002
-140.00
40kHz LP 100k
40kHz LP 100k
40kHz LP 100k
Imp.
Band.
<10 - >500k
<10 - >500k
<10 - 22k
MC-8/B Setup
A In
B In
A Out
B Out
Midiman
PGM #:
Clock
Source
Sample
Rate
Audio
Source
1,3,5,7
1,3,5,7
1, 3, 5, 7
2,4,6,8
2,4,6,8
2, 4, 6, 8
n/a
n/a
n/a
n/a
n/a
n/a
11
11
11
External
External
External
96000
96000
96000
Digital
Digital
Digital
Lexicon
CHAPTER 5 – TROUBLESHOOTING
This chapter contains a complete description of the diagnostic tests for the MC-8/MC-8 Balanced
(MC8/B). The diagnostics in the MC8/B are used to verify functionality of the unit and to aid in
troubleshooting defective units. Familiarity is assumed with the MC8/B BOM structure, all applicable
assembly drawings, FAT process, and Audio ATE processes.
Diagnostic Categories
There are two types of diagnostics in the MC8/B: power-on and extended. The extended diagnostics
contain the tests that are used by manufacturing personnel to verify functionality and by repair personnel
to aid in troubleshooting. The entire set of power-on diagnostics is executed every time a unit is powered
on using the rear panel power switch. The power-on diagnostic tests can be run individually in the
extended diagnostics. The extended diagnostics also contain additional tests used to verify all the front
panel controls, infrared communications, audio and video performance, etc. The troubleshooting or repair
diagnostics are used to troubleshoot an MC8/B if any test fails.
Power On Modes
There are two power-on modes available. Power on via the rear panel power switch, or by bringing the
unit out of standby mode. The power-on diagnostics are executed every time the rear panel power switch
is switched on. When an MC8/B is operating, if the front panel Standby button is pressed, the unit goes
into low power/Standby mode. Pressing any front panel button or any remote key will bring the MC8/B out
of Standby mode. No diagnostics are run when the unit is brought out of Standby.
Diagnostics User Interface
Various combinations of button pushes are used to control diagnostic activity. The table below
summarizes the options available, followed by more detailed descriptions.
Action
Buttons to be Held
Enter Diagnostics
MAIN VCR & ZONE2 VCR
Skip Power-On Diagnostics
MAIN AUX & ZONE2 AUX
Jump to Extended Diagnostics
MAIN OFF & ZONE2 OFF
Attempt to Run the Next Diagnostic Test
MAIN TV & ZONE2 TV
To Enter Extended Diagnostics:
Press and hold the front panel MAIN VCR and ZONE 2 VCR buttons when powering on a MC8/B.
To Enter Extended Diagnostics via Serial Debug Port:
Enter the debug program by typing “debug” when connected to the serial port. The debug program is
case sensitive.
In addition, the extended diagnostics can be entered by sending “ed”, (for extended diagnostics), to the
unit via the serial debug port during the first ten seconds after powering on the unit.
5-1
MC-8 Service Manual
To skip Power On Diagnostics:
Press and hold the front panel MAIN AUX and ZONE2 AUX buttons. This will cause the unit to skip the
power-on diagnostics and go immediately to the operating system. Immediately after sufficient testing is
performed to verify the system can boot, (the Z180 CPU, EPROM, Z80 SRAM, FPGAs loaded, VFD etc.),
the diagnostics check to see if MAIN AUX and the ZONE2 AUX buttons are being pressed together. If
they are, the unit will attempt to skip the rest of the power up diagnostic tests and jump to the operating
system.
To bridge to Extended Diagnostics after a failure occurs:
Press and hold the front panel MAIN OFF and ZONE2 OFF buttons. This will cause the unit to bridge to
the extended diagnostics. After a failure the unit will attempt to display, on the VFD, and the front panel
LEDs, the failed test number, and loop on the failing test. If the Z180 CPU and support circuitry is not
working the unit will not attempt to read any front panel switches.
To execute the next Diagnostic Test after a failure occurs:
Press and hold the front-panel MAIN TV and ZONE2 TV buttons. This will cause the MC8/B to attempt to
execute the next power on diagnostic step. If a failure occurs, the MC8/B attempts to enter a test loop to
keep the signal lines active as an aid in debugging the failure. At the end of each successive loop, the
diagnostics will check to see if the MAIN TV and ZONE 2 TV buttons are being held. Depending on the
length of the test, the amount of time required pressing and holding the buttons will vary.
DIAGNOSTIC REPORTING
All diagnostic functionality is reported to the Vacuum Fluorescent Display (VFD) and to the front panel
LEDs. They report on what test is being executed, and if the test passed or failed. The LEDs are used to
report diagnostic status in the event that the VFD is not functioning.
Diagnostic status and data is also available on an external PC or a terminal, via the serial debug port
located at the D9 connector labeled RS232 2 on the rear panel. The D9 connector labeled RS232 1 is
used for updating the flash memory. In the event a diagnostic failure occurs for those diagnostic tests that
report to the error log, additional failure information, such as data sent, data received, address location,
etc., is listed in the error log. For example, Sharc SRAM failures are not reported to the error log. The
error log can be viewed via the VFD, or it can be sent to the serial debug port.
Vacuum Fluorescent Display (VFD)
The VFD is the primary source of information during diagnostics. The exact display information will
depend on the test(s) being executed. When an individual diagnostic test is executed, the VFD will
display the name of that test. Groups of tests, such as the power-on diagnostics or the burn-in loop, have
a generic message on the top line of the VFD. For example, “DIAGNOSTIC TESTS” is on the VFD while
the power-on diagnostics is being run. An E followed by a number indicates a test failure message.
Front Panel LEDs
The top row of the front panel LEDs is also used to display diagnostic status. The LEDs are used in
binary format with the Zone 2 VCR LED as the LSB and the Main DVD 1 LED as the MSB. Running test
number 1 would illuminate the Zone 2 VCR LED only with all the others off. Running test number 2 would
illuminate the Zone 2 Sat LED only with all others off. Running test number 3 would illuminate the Zone 2
SAT and the Zone 2 VCR LEDs together with all others off, etc.
5-2
Lexicon
If a failure occurs, the MUTE LED is illuminated to indicate the test failure, and the LEDs indicating which
test was running when the failure occurred will also continue to be illuminated. The diagnostics will
attempt to continuously execute the failed test, a test loop, to keep the signal lines active as an aid in
debugging the failure.
Serial Debug Port
The Serial Debug Port is available to provide diagnostic status to be viewed on an external PC from the
D9 connector labeled RS232 2. Using a terminal or a PC running a terminal program connected to RS232
2 the progress of the diagnostics can be monitored and test failure information is reported. Also, there is
an error log can be dumped to the serial debug port while in extended diagnostics. The serial protocol is
19,200bps, 8, N, 1, (8 data bits, no parity and 1 stop bit).
Serial Debug Cable
The cable required to connect the RS232 2 serial debug port to the computer is a straight-through serial
interface cable. A null modem adapter or cable should not be used. The MC8/B RS232 connector on the
rear panel is a D9 female; so one end of the serial cable must be a D9 male. The other connector on the
cable depends upon the RS232 connector used on the computer. The computer may have a D9 or a D25
male connector. Typically computers have a D9 for COM 1 and a D25 for COM 2. However, some newer
computers use a D9 for both COM 1 and COM 2. The COM port used on the computer does not matter,
however you must ensure that the serial communications program being used has the correct computer
COM port selected.
Serial Debug Program
The serial debug program controls the communication from an MC8/B to a computer. The program allows
a user to view activity of the unit and to control the unit. The debug program is used extensively to
perform audio and video testing of a unit in the audio and video ATE programs. This section will
demonstrate an example of using debug to troubleshoot a SHARC SRAM failure.
The MC8/B has four SHARCS on the DSP board organized as pairs: pair 0 and pair 1. Each pair of
SHARCS has four SRAMs and one SDRAM. In the case of a SHARC SRAM failure, the debug program
can be used to determine which of the four SRAMs is defective. Power on the unit with the RS232 2 port
connected to the computer, while the computer is running a terminal program with the correct COM port
and protocol enabled. When the unit reports the SHARC SRAM failure and has entered a diagnostic loop
with the same error data continuously cycling on the monitor, power off the unit. The data will appear as
follows:
“SHARC Failed Test test num: 00000003
test phase: 00000000
sharc address: 02FE000E
sharc byte written: AAAAAAAA
sharc byte read: AAAAAA8A
Sharc Error Code: 0318
sharcpair0_ps2 sram
sharcpair0_ps2 sram test failed, Error code: 0318
*DIAG FAIL:ShSRAM_02 E:0318*”
Compare the data from the sharc byte written to the sharc byte read. If the failure is a defective SRAM the
typical failure mode is to be off by one bit and the byte comparison will determine which IC is at fault. In
the above example:
5-3
MC-8 Service Manual
byte written: AAAAAAAA = 1010 1010 1010 1010 1010 1010 1010 1010
byte read: AAAAAA8A = 1010 1010 1010 1010 1010 1010 1000 1010
Since data bit 5 is the one that is not correct, checking the schematics for the SRAM used for pair 0,
DSPA and DSPB, that has data bit 5 on it will show which SRAM is associated with the failure. See the
chart below for further reference.
SHARC SRAM PIN ASSIGNMENTS:
SHARC PAIR 0
SHARC PAIR 1
DSPA/PS1 & DSPB/PS2
DSPC/PS1 & DSPD/PS2
Data Bits:
U20
U19
U18
U17
U12
U11
U10
U9
D0 = Pin 6
D24
D16
D8
D0
D24
D16
D8
D0
D1 = Pin 7
D25
D17
D9
D1
D25
D17
D9
D1
D2 = Pin 10
D26
D18
D10
D2
D26
D18
D10
D2
D3 = Pin 11
D27
D19
D11
D3
D27
D19
D11
D3
D4 = Pin 22
D28
D20
D12
D4
D28
D20
D12
D4
D5 = Pin 23
D29
D21
D13
D5
D29
D21
D13
D5
D6 = Pin 26
D30
D22
D14
D6
D30
D22
D14
D6
D7 = Pin 27
D31
D23
D15
D7
D31
D23
D15
D7
P/N 350-12456 ICSM,SRAM,128KX8,12NS,3.3V,SOJ
Note:
The reference designators are from MC8 DSP board revision 1, Lexicon P/N 710-15300.
Error Log
An error log, or ring buffer, containing a log of the last 20 (13h) failures is available. If the error quantity
exceeds 20, additional error messages are stored at the first location in the buffer (FIFO). The error log is
stored in the non-volatile section of SRAM, and is not able to display all diagnostic errors. For example,
SHARC SRAM failures are not reported to the error log. Every failure stored in the error log has six parts:
“#NN E## tXX aYYYYYY
wZZZZZZ rQQQQQQ”
#NN: Error Log Number
The error log location number (in hexadecimal). It goes from 00 to 13. Turning the encoder knob
clockwise allows one to scroll through all twenty error log locations.
E##: Failure Number
The E stands for error and the hexadecimal after the E indicates test number from the list on the next
page.
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tXX: Error Code List
NO_ERROR
0x0
ADDR_FAILURE
0x1
DATA_FAILURE
0x2
TIMEOUT_FAILURE
0x3
COUNTER_FAILURE
0x4
NON_VOL_DATA_FAILURE
0x5
OPCODE_FAILURE
0x6
IO_FPGA_ID_NO_MATCH
0x7
DAR_FPGA_ID_NO_MATCH (only for MC12)
0x8
AUDIO_FPGA_ID_NO_MATCH
0x9
ANALOG_FPGA_ID_NO_MATCH (only for MC12)
0xA
VFD_TIME_OUT
0xB
VFD_RAM_ERROR
0xC
TEST_INCOMPLETE
0xD
RS232_WRAP_FAILURE
0xE
SRAM_PREBURNIN_FAILURE
0x13
SRAM_BURN_IN_FAILURE
0x14
EPROM_CHKSUM_FROM_FLASH
0x15
SRAM_FAILURE
0x16
FIFO_ERROR_OVERRUN
0x17
PIC_SN_INVALID
0x18
FLASH_BURN_FAIL
0x19
FLASH_BURN_NO_ROOM_LEFT
0x1A
FLASH_BURN_NOT_FLASH_PART
0x1B
SHARC_TIMEOUT_REBOOT
0x1C
DSP_FPGA_ID_NO_MATCH
0x1D
DEC_FPGA_ID_NO_MATCH
0x1E
DIAG_TEST_NOT_EXIST
0x20
THERMOSTAT_FAILURE
0x21
ERROR_ID_BAD_VALUE
0x40
ERROR_PARAM_SEMA_CREATE
0x60
CS49400_NO_BOOT_START_MESSAGE
0x100
CS49400_NO_BOOT_SUCCESS_MESSAGE
0x101
CS49400_INIT_ERROR
0x102
CS49400_ERR_WRITE_TIMEOUT
0x103
CS49400_ERR_READ_TIMEOUT
0x104
CS49400_INTREQ_TIMEOUT
0x105
CS49400_AUTO_BOOT_FAILURE
0x106
CS49400_ENQ_MSG_FAILURE
0x107
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CS49400_DEQ_MSG_FAILURE
0x108
CS49400_FINTREQ_TIMEOUT
0x109
CS49400_NO_APP_START_MESSAGE
0x110
CS49400_AB_SPI_TIMEOUT
0x111
CS49400_C_SPI_TIMEOUT
0x112
CS49400_HOST_BOOT_FAILURE
0x113
CS49400_FLASH_WRITE_TIMEOUT
0x114
CS49400_BAD_FLASH_DATA
0x115
CS49400_BAD_RESP_OPCODE
0x116
CS49400_FLASH_READ_TIMEOUT
0x117
CS49400_MASTER_BOOT_FAILURE
0x118
CS49400_BAD_FLASH_VERSION
0x119
CS49400_ERASED_FLASH
0x11A
CS49400_CHECKSUM_FAIL
0x11B
The sharc error codes use from 0x0300 through 0x03FF
SHARC_WCLK_FAILURE
0x3F9
SHARC_SRAM_FAILURE
0x3FA
SHARC_SDRAM_FAILURE
0x3FB
SHARC_GPIO_FAILURE
0x3FC
SHARC_RX_TIMEOUT
0x3FD
SHARC_TX_TIMEOUT
0x3FE
SHARC_BAD_OPCODE
0x3FF
The following codes are used to interpret the results from the SHARC GPIO, SRAM, SDRAM, and Word
Clock Tests available from the Extended Diagnostic Repair Menu. The Error code is 16-bits with the most
significant byte always being 0x03.
The least significant byte is broken into bits as shown:
”(MSBit) B7 B6 B5 B4 B3 B2 B1 B 0 (LSBit)”
•
B7 - Semaphore indicator, 1 failed, 0, passed.
•
B6 - GPIO LED failure, 1 indicates that neither LED lit up from the test.
•
B5 – Read Back Reg Fail, 1 indicates the Readback register failed.
•
B4 - Test Fail, 1 indicates the test failed, 0 success.
•
B3 - SHARC Test Completed. 1 indicates that the sharc was able to finish executing the test.
•
B2 - READ Timeout, 1 means that Z180 could not read back from the SHARC. 1 indicated timeout.
•
B1 - WRITE Timeout, 1 means there was a timeout.
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•
B0 - SHARC write timeout id 0 is for PS1, 1 is for PS2.
•
If there is a WRITE TIMEOUT, then check B0 to see which SHARC in the pair caused the fault.
•
B3 shows if the SHARC was able to run the code, and determine whether there was success or
failure. Success or failure can be determined by either the GPIO LEDs, green success, red failure, or
by the return code in the register readback, 0xAA for success and 0x55 for failure.
•
If B4 is 0, then make sure that B3 is 1 before deciding whether the SHARC test passed.
•
If the GPIO LED failure bit indicates a failure, then check the circuitry surrounding the LED. An LED
failure occurs when the number of LEDs lit is NOT 1. If 2 are lit, then there is probably a short
between them. If 0 are lit, then parts may be missing, or a short exists.
•
Bits B2, B1 and B0 are read together. If a time out occurs then B2 or B1 will indicate what operation
caused the fault. B0 will indicate which processor failed, Processor A or B.
•
Bit B3 is used to indicate whether the SHARC was able to run the code. If this bit is zero, the code
was not able to run, a 1 indicates the SHARC was able to run.
•
Bit B4 indicates whether the test passed or failed. This bit is only valid if B3 is a 1.
•
Bit B5 indicates that the read back register failed. There is a fault in the read back register circuitry if
this bit is a 1.
•
Bit B6 indicates whether the circuitry around the SHARC LEDs failed. A 1 indicates a failure.
When the SHARC passes these tests, it will return a value of 0x0300.
aYYYYYY: Failing address location
The address (in hexadecimal) where the failure occurred.
wZZ: Value Written
The target value (in hexadecimal) that was written to the address where the failure occurred.
rQQ: Value Read
The actual value (in hexadecimal) that was read from the address where the failure occurred.
The error log is available as a menu item in the extended diagnostics under Repair Tests. In addition, the
error log can be viewed on an external PC or terminal via the D9 connector labeled RS232 2 on the rear
panel of the MC8/B. The error log is sent to RS232 2 when the VIEW ERRORLOG selection is made.
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Power On Diagnostics
As described earlier, there are two power-on modes in the MC8/B. Power on via the rear panel power
switch and by coming out of standby mode. Power-on diagnostics are executed every time the rear panel
power switch is switched on. Diagnostics are not run when the unit is brought out of Standby mode.
Power-on diagnostics take approximately forty seconds to complete. The power-on diagnostics are
intended to verify basic hardware functionality of an MC8/B. Additional diagnostic tests are available for
manufacturing and customer service to completely test the hardware, and for debugging failures.
Initially, an attempt is made to illuminate the VFD and front panel LEDs for approximately five seconds.
However during the first six tests the VFD will not be considered functional due to it not being tested.
During these tests, Trap Op Code, EPROM, FLASH Checksum, Z80 SRAM, program FPGAs, and VFD
RAM, the unit will attempt to use the STANDBY LED to indicate if a failure occurs. As soon as these are
completed the VFD will display:
“DIAGNOSTIC TESTS
…
…”
The dots increment in number from both sides simultaneously, as the rest of the power-on diagnostic
tests are completed. This communicates that the unit is still functioning. The audio outputs (digital and
analog) will be muted during this sequence.
The following sections list the test explanations. The front panel display is shown only for the first test that
can use the VFD. The reference designators used are for the MC8 Revision 3 Main Board 710-15250
used on BOM 023-15428, and revision 0 memory board used on BOM 023-15429. The schematic for the
main board is 060-15259, and the memory board is schematic 060-15299.
Trap Opcode
The Trap Opcode error occurs if during the initial boot sequence an undefined Opcode is fetched. The
INT/TRAP Control register can be used to determine the starting address of the undefined instruction. If
the trap error occurs an attempt will be made to blink the STANDBY LED using a rate of a single blink per
several seconds, and the test will attempt to enter a loop to exercise signal lines to aid in debugging.
EPROM Checksum Test
The EPROM Checksum test verifies the 2 Meg 27C020 EPROM, U3 on the Memory Board, has the
correct program by adding up all the values in each bank of the EPROM. The test verifies the separate
banks and the bank switching of the MC8/B. The checksum of each bank is reported to the Serial Debug
Port. The test verifies that the calculated checksum in each bank matches the checksum value stored in
the EPROM. If an error occurs an attempt will be made to blink the STANDBY LED using a rate of two
blinks per several seconds, and the test will attempt to enter a loop to exercise signal lines to aid in
debugging.
Z180 SRAM Test
The Z180 SRAM test performs non-destructive testing on the 256k SRAM, U90 on the Main board, on
page 2 of the main board schematics. The non-destructive test first saves the data in the location being
tested. Then that location is tested by writing and reading patterns 0x00, 0xFF, 0x55, 0xAA, 0x01, 0x02,
0x04, 0x08, 0x10, 0x20, 0x40, and 0x80. The original data is then returned to the SRAM and the next
location tested. Once each location in the SRAM is verified, a counting-memory check is done throughout
the SRAM to test buss integrity. First, each byte in a special 32-byte section is written with a count. Then,
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starting from the beginning of the block, and incrementing through it, the count is verified to be correct. If
so, this area will be used to store the contents of the rest of SRAM as it under goes the count check in
32-byte blocks. If an error occurs, an attempt will be made to blink the STANDBY LED using a rate of
three blinks per several seconds, and the test will attempt to enter a loop to exercise signal lines to aid in
debugging. In order for the test to pass the Z180 and the CPLD, U84 and U83 respectively on the main
board and page 1 of the schematics, and associated support circuitry must be functioning.
Flash Checksum Test
The Flash checksum test verifies the data in the 16 Meg flash memory, either U1 or U2 on the memory
board. For all banks the checksum test adds up all the data in each bank except for the bank number and
stored checksum locations (stored in the last three locations of each bank). The added value is then
verified against stored values. If an error occurs, an attempt will be made to blink the STANDBY LED
using a rate of four blinks per several seconds and the test will attempt to enter a loop to exercise signal
lines to aid in debugging.
DISPLAY FOR THE REMAINING TESTS
If any of the following tests fail the VFD display and LED matrix will display the test and error fault, if one
occurs, as previously discussed. The VFD will display the test number and the error code. In the event
that the VFD is not operable, the same information will be written to the LED matrix. The test number will
be read out as in the top row. The error number can be read out in the second row (Most Significant Byte)
and third row (Least Significant Byte).
Vacuum Fluorescent Display (VFD) Test
The VFD performs a busy test and a memory test. The busy test sends information to the VFD and
verifies that the VFD asserts then de-asserts its busy status. The VFD memory test consists of writing
55h, AAh, a walking 1 and finally a 0 to the character generator memory and display memory space of the
VFD and reading them back. After the MC8/B has passed the VFD Test, for the rest of the power on
diagnostics, the VFD displays:
”DIAGNOSTIC TESTS
…
…”
The dots increment in number from both sides simultaneously, as the rest of the power-on diagnostic
tests are completed. This keeps a user informed as to the functioning of a MC8/B.
If a failure occurs, the test will attempt to write an entry into the error log and enter a loop to exercise
signal lines to aid in debugging. The error log is stored in the non-volatile section of the SRAM so that it is
not destroyed during the power on diagnostics. A single error log entry is made each time the MC8/B is
powered up, a diagnostic test is executed, and a failure encountered.
I/O FPGA Test
The I/O FPGA test loads and verifies the programming of the XCS05-VQ100, U67 on the main board, on
page 2 of the schematics. The I/O FPGA is used to program the other DAR FPGA, the Audio FPGA, and
the Analog FPGA. If a failure occurs, the test will attempt to write an entry into the error log, write the test
number and the error number to the VFD and LED matrix.
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DSP FPGA Test
The DSP FPGA test loads and verifies the programming of the XCS05-VQ100, U7 on the DSP board
revision 1 and page 8 of the schematics. The Audio FPGA must be functioning since it is used to program
the DSP FPGA. If a failure occurs, the test will attempt to write an entry into the error log, write the test
number and the error number to the VFD and LED matrix.
Decoder FPGA Test
The Decoder FPGA test loads and verifies the programming of the XCS05XL-VQ100, U4 on the decoder
board and page 2 of the schematics. The Audio FPGA must be functioning since it is used to program the
Decoder FPGA. If a failure occurs, the test will attempt to write an entry into the error log, write the test
number and the error number to the VFD and LED matrix.
Crystal 49400 Test
This test verifies that the Crystal 49400, U2 on the decoder board and page 3 of the schematics, can
communicate with the Host Z180 processor through the Audio FPGA. If a failure occurs, the test will
attempt to write an entry into the error log, write the test number and the error number to the VFD and
LED matrix.
SHARC SDRAM Test
This test verifies that the SDRAM for each SHARC that has this test enabled on the DSP board is
operational and can be written to and read from. The SDRAM test is run using SHARC Pair 0 Processor
A and the SDRAM is U14 on the DSP board and page 4 of the schematics. The SDRAM test is also run
using SHARC Pair 1 Processor C, which is U4 on the DSP board and page 7 of the schematics. If a
failure occurs, the test will attempt to write an entry into the error log, write the test number and the error
number to the VFD and LED matrix.
The test writes the test patterns of 0x55555555, 0xAAAAAAAA, a walking 1 and 0x00000000 are written
to each location and read back. Once each location is verified, a counting test is applied to verify the
address buss.
SHARC SRAM Test
This test verifies that the SRAM for each SHARC that has this test enabled on the DSP board is
operational and can be written to and read from. The SRAM test is run using SHARC Pair 0 Processor B,
and the SRAMs are U17-U20 on the DSP board and page 4 of the schematics. The SRAM test is also run
using SHARC Pair 1 Processor D and the SRAMs are U9-U12 on the DSP board and page 7 of the
schematics. If a failure occurs, the test will attempt to write an entry into the error log, write the test
number and the error number to the VFD and LED matrix.
The test writes the test patterns of 0x55555555, 0xAAAAAAAA, a walking 1 and 0x00000000 are written
to each location and read back. Once each location is verified, a counting test is applied to verify the
address buss.
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Power On Diagnostics Completed
After the power-on diagnostics are completed the VFD will display the appropriate power up message:
“MANUFACTURER MODEL
(c) 200X
OPTIONS”
VX.XX
At this point the operating system takes over the functioning of the MC8/B.
EXTENDED DIAGNOSTIC TESTS
As described earlier, the extended diagnostic tests are accessible by pressing and holding the MAIN VCR
and ZONE 2 VCR front panel buttons when powering on a MC8/B. The audio outputs (analog and digital)
are muted. When the VFD displays “LEXICON,” the front panel buttons can be released. After the model
banner is briefly displayed on the VFD, the display will indicate:
“DIAGS MENU
FUNCTIONAL TESTS”
The extended diagnostics can also be entered via the serial debug port by first entering the debug
program. Type “debug” when connected to the RS232 2 serial port to access the debug program. The
debug program is case sensitive. Once in debug, type “x 2e” and the unit will go into extended
diagnostics. In addition the extended diagnostics can be entered through the RS232 2 serial port by
sending “ed” which stands for extended diagnostics, to the unit via the serial debug port during the first
ten seconds after powering on the unit.
After extended diagnostics are entered, use the front panel encoder, Mode and Mode buttons to
navigate through the diagnostics. The front panel encoder is rotated to display the desired tests. Press
the Mode button to move down through the menu selections and to execute the desired diagnostic
test. Use the Mode button to back up through the menu selections similar to an escape (ESC) button
on a computer keyboard.
Types of Tests
The extended diagnostic tests fall into two categories: functional and repair. The functional diagnostic
tests are required to functionally verify an MC8/B and are performed on every unit. The repair, or
troubleshooting, category is for troubleshooting defective units. The repair tests are used only if there is a
failure. The repair tests can be used to help isolate the source of failures so that units can be cost
effectively fixed.
Two groups of functional tests are executed on every MC8/B: Loop Tests and the Functional Test Suite.
These tests comprise the automated set of diagnostic tests used to verify functional operation of every
unit. All of the diagnostic tests in the loop tests and in the functional test suite are run in sequence. If
there is a failure the failing test will loop to allow the electrical signals to be active for troubleshooting. The
operator can optionally continue the diagnostic tests to see what other diagnostic tests might be failing.
User Interface
The user interface consists of a set of menus. The top menu is the "DIAGS MENU" and is shown in the
top line of the VFD display. To view the available menu items turn the encoder knob in either direction
and the menu choices will appear in the second row. The available choices are Functional Tests, Repair
Tests, Loop Tests, Audio I/O Tests, Video I/O Tests, and Normal Operation. When the desired menu item
is shown, press the Mode button. This selects the menu item. If the item is another menu, the menu's
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title now appears in the top line of the VFD and its menu items are in the second row. If a test is selected,
the test name will appear in the top line and the results or information to run the test will be on the second
row. Once a test is finished, or to get out of a menu press the Mode button. Pressing and holding the
Mode button returns you to the top-level diagnostic menu.
There are groups of diagnostic tests in which if a test passes, the diagnostics automatically execute the
next test. Group tests are the Power-On Diagnostics, in the Manufacturing suite, the Pre Burn-In test, and
the Burn-In Loop. For the Burn-In Loop, upon successful completion of the group tests, the VFD will
briefly display either "Pass" or "Fail", and continuously loops until power is removed from the unit.
If a test fails, the VFD and front panel LEDs, will attempt to indicate the failed test. The test will attempt to
loop to keep the signal lines active for debugging purposes. If an individual test is selected, it will
continuously run and report if it passes every time it successfully completes the test. In addition, test
progress and failure information is available via the serial debug port. Specific failure information will
depend on the test being executed.
REPAIR DIAGNOSTICS SUITE
The Repair Diagnostics suite allows you to individually execute every diagnostic test on a unit. The
Functional suite uses the same tests as the Repair Diagnostic suite, but automates how the tests are run.
The following tests are available in the Repair Diagnostics:
•
Z180 EPROM checksum
•
Z180 FLASH checksum
•
Z180 SRAM
•
I/O FPGA Verify
•
RS232 Wrap Test
•
SHARC Tests
Sharc GPIO (x12)
PAIR 0 PROC A
PAIR 0 PROC B
PAIR 1 PROC A
PAIR 1 PROC B
Sharc SRAM (x12)
PAIR 0 PROC A
PAIR 0 PROC B
PAIR 1 PROC A
PAIR 1 PROC B
Sharc SDRAM (x12)
PAIR 0 PROC A
PAIR 0 PROC B
PAIR 1 PROC A
PAIR 1 PROC B
Sharc WCLK(x12)
SEL 44 WORD CLK
SEL 48 WORD CLK
SEL 88 WORD CLK
SEL 96 WORD CLK
SEL 44-48 PLL WCLK
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SEL 88-96 PLL WCLK
SEL DRCVR WCLK
PAIR 0 PROC A
PAIR 0 PROC B
PAIR 1 PROC A
PAIR 1 PROC B
Sharc Boot (x2)
PAIR 0
PAIR 1
DSP FPGA Verify
CS49400 Boot Test
FPGA ID Test
Boot Test
Show Flash Version
Flash Checksum Test
Load Flash
IR Remote
VFD Memory Test
VFD CHAR Test
VFD BLOCK Test
OSD CHAR Test
SWITCH Test
LED Test
ENCODER Test
VIEW ERRORLOG
Clear NON-VOL SRAM
Set Triggers (x3)
TRIGGER 0
TRIGGER 1
Expand Output MUTE
MIC DSP CONN Test
Set FAN Test
Show Serial NUM
PIC SN Validity
Flash Burn Test
Thermostat Test
Set Constant Cycle
Normal Operation
The extended diagnostic tests that are the same as in the power-on tests are not described here.
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FUNCTIONAL DIAGNOSTIC SUITE
The manufacturing suite is available from the top level DIAGS MENU and the FUNCTIONAL TESTS item
is selected.
1. When you select the menu item, the VFD will display:
“FUNCTIONAL TESTS
START ALL TESTS”
There is only one menu item in this menu, and selecting it will start the sweep through the whole
repair suite. As long as there are no errors, the test will continue until the tests requiring an operator
response are encountered. If there is a failure, the offending test will cycle and the error code will be
displayed on the second line. For example, if the DEC FPGA verify fails the VFD will display:
“DIAGNOSTIC TESTS
DEC FPGA
E:001E”
2. To continue, hit the MODE button.
Some tests require you to help with the test by pressing the MODE key, or by turning the encoder
to iterate through the test.
3. Upon completion of all of the tests, the second row of the VFD displays “Pass” or “Errors.”
RS232 Wrap Test
This test verifies the RS232 ports are working by comparing the transmitted signal (at pin 2s of J5) to the
received signal (at pin 3s of J5). If the signals are the same, the test passed. In order to test this circuit,
(2) RS232 Wraparound plugs are needed and must be installed at the female D9 connectors (J4 & 5) on
the rear panel of the MC8/B labeled “RS232.” Once these plugs are installed, the test can be executed.
1. When you select the test, the display will read:
“EXTENDED DIAGNOSTICS
RS232 Test”
All buttons except for the Mode will be inactive. The encoder knob is active to select another test.
2. Press the Mode button to execute the test. The display will read the following if both ports pass:
“SERIAL PORT A PASSED
SERIAL PORT B PASSED”
If Serial Port A Failed, the display will read:
“SERIAL PORT A Failed
SERIAL PORT B PASSED”
If Serial Port B Failed, the display will read:
“SERIAL PORT A PASSED
SERIAL PORT B Failed”
If both Serial Ports Failed, the display will read:
“SERIAL PORT A Failed
SERIAL PORT B Failed”
To troubleshoot this type of failure, use the front panel Mode button. Each time the button is
pressed, a message is sent out the RS232 port at pin2 of J4. This will activate the COM0_TX0 signal
coming from the Z180 pin 48. In the situation where the test passes, the COM0_RX signal is present
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at Z180 pin 49 as long as the wraparound plug is connected. Another way to test this circuit is to
verify the IR Receiver (green) LED lights briefly when the button is pressed. This approach can be
helpful when troubleshooting intermittent failures.
Note:
If the unit is attached to a debugging PC, then serial port A will fail. However, if the PC's terminal software
is showing results and the user is able to type in commands or run debug scripts, then the port is working.
Thermostat Test
The thermostat test verifies the temperature sensor installed at U66 on the main board. To verify the IC’s
functionality, a shorting jumper is installed at W1. This shorting jumper changes the resistance presented
at pin 2 of the temperature sensor. The temperature sensor sets the temperature it detects via a resistor
divider network. Grounding pin 2 will cause the diagnostic test to verify the TEMP signal lines have
changed state.
1. Upon entering the test the VFD will indicate:
“THERMOSTAT TEST
Insert
Jumpers”
2. If the test passed when the MODE button is pressed the VFD will indicate:
“THERMOSTAT TEST
Test:
PASSED”
The diagnostic test will then prompt for the jumper to be removed.
“THERMOSTAT TEST
Remove:
jumpers”
If the jumpers are not removed the test will prompt a second time to have the jumpers removed.
“THERMOSTAT TEST
Jumpers not removed!”
Fan Test
The fan test verifies operation of the fan.
1. When you select the test, the VFD will indicate:
“SET FAN
FAN:
OFF”
2. Rotate the encoder knob clockwise and the VFD will indicate:
“SET FAN
FAN:
ON”
The fan will be spinning.
3. Rotate the encoder knob counter-clockwise and the VFD will indicate:
“SET FAN
FAN:
OFF”
The fan will stop spinning.
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IR Remote
This test verifies the functionality of the IR Remote by pressing on the remote and verifying that the VFD
displays which IR remote button was pressed. The VFD displays (in hexadecimal) the code received
when a remote key is pressed. The hex display on the VFD remains unchanged until another remote key
is pressed. While the remote key is being pressed the IR acknowledge LED will flash and the VFD
displays the message "IR", (without the quotes), next to the hex value. When you have successfully
exited the test the VFD will display an arrow on the left side pointing to the word REMOTE.
1. When you select the test, the display will read:
“IR REMOTE
Remote Test:”
All buttons except for Mode will be inactive.
2. When you hold down a remote button, such as the DVD 1 button, the display will read:
“IR REMOTE
Remote Test: 20IR”
The 20 is the hex code for the DVD 1 button, IR is displayed to indicate the remote is currently
transmitting a signal, and the amber IR acknowledge LED will be flashing. As different buttons are
held down, the hex code will change indicating which is being pressed.
VFD Character Test
The combination of the Character Test and the Block Test verifies that all display segments are
functioning. The Character Test places the same character on all VFD segments. The ENCODER knob is
then used to change the character. The test has sufficient variation of characters to verify complete
functionality of the VFD. All characters present in the VFD can be observed.
1. When you select the test, the VFD will display all “As” as shown below:
“AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA”
2. Rotate the encoder knob to view other characters. To exit the test, press the Mode button.
VFD Block Test
Note:
When rotating the encoder knob sometimes pixels on the VFD will randomly flicker very briefly. This is
normal operation.
The Block Test illuminates all pixels on a single segment of the VFD. The encoder knob is then used to
move the block to each segment.
Press the EFFECT DOWN button to execute the test. The display will read:
“g”
Rotate the encoder knob clockwise to move the block through all VFD locations. At the end of the line,
the block will wrap to the next line. In the case of second line the block will return to the starting point on
the first line.
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Switch Test
This test will verify all twenty-two front panel switches are working. Each button on the front panel is
pressed and the VFD will indicate which front panel button has been pressed.
Example: Switch Test: MODE_DN in the second line on the VFD.
If the button has an LED associated with it, the LED will illuminate. When all switches have been tested,
the bottom half of the display will indicate completion.
Encoder Test
The Encoder Test verifies the operation of the encoder knob including direction and the twenty-four
positions. It is designed so that if there was a bad position on the encoder knob, the display will never
indicate a "Passed" message. This is achieved by having the accumulator value reset to 0 if a switch
position was bad or if the encoder was turned in the opposite direction during the test. Therefore, the
accumulator will never see the expected value of 24 so the program would not be able to perform the next
task (i.e. instruct the user to perform the counter-clockwise test or display "Passed"). When the encoder is
being tested, the bottom right half of the display will indicate the direction and position value. The test
requires the clockwise direction to be tested first.
1. When you turn the encoder knob clockwise, the display will read:
“EXTENDED DIAGNOSTICS
Encoder Test CW 05”
In this example, the encoder knob was turned five positions clockwise.
2. After the encoder knob is turned one (1) revolution clockwise (covering all twenty-four positions) the
display will read:
“EXTENDED DIAGNOSTICS
Encoder Test CCW 24”
The bottom half of the display (CCW 24) indicates the counter-clockwise test is ready to be executed.
3. After you turn the encoder knob one complete revolution counter-clockwise (covering all positions),
the display will read:
“ENCODER TEST
Encoder test passed”
LED Test
The LED test illuminates each LED by turning the encoder knob clockwise or counter-clockwise. As the
encoder knob is turned each individual LED is illuminated.
5-17
MC-8 Service Manual
Expand Output MUTE Test
The Expand output MUTE test verifies that the MUTE signal going to the XLR board is functioning.
1. When you select the test, the VFD display will indicate:
“EXPAND OUTPUT MUTE
EXPOUT:
Low”
On the main board the red LED D23 will be lit when the VFD indicates that the EXPOUT signal is low.
2. Rotate the encoder knob clockwise and the VFD will indicate:
“EXPAND OUTPUT MUTE
EXPOUT:
High”
And the red LED at D23 will be off. If the unit being tested is a MC-8 Balanced, the relay on the XLR
board can also be heard. Turn the encoder knob counter-clockwise to set the expand-and mute
signal low.
Trigger Test
This test will verify the trigger circuits of the MC-8. For this test you will need the MC-8 remote control and
a Digital Multimeter (DMM).
Test:
1. Power on the MC-8.
2. Turn on the DMM and set it to read DC voltage for a 12V level.
3. Using the remote control Menu arrow, select SETUP form the Main Menu.
4. Scroll down through the SETUP menu and select TRIGGERS.
5. Scroll to DVD1 and change the trigger from OFF to ON.
6. Ress the remote control MAIN button, then press the remote control DVD1 button to select DVD1 as
the input for the Main Zone.
7. On the MC-8 rear panel, locate the Trigger Outputs block.
8. Connect the DMM’s red probe to positive (+) and connect the black probe to negative (-). Measure
the PWR +/- and the #1 +/- trigger outputs for 12 volts DC.
PIC Software ID Test
The functional diagnostics will now automatically perform the PIC S/N test, which verifies that the
software ID programmed into the PIC microcontroller is within the range allowed per the Lexicon
specification sheet.
5-18
Lexicon
REPAIR DIAGNOSTICS SUITE
View Error Log
This is not a test but it enables you to view the contents of the error log. Turning the encoder knob
allows you to view the error log contents.
Clear Non-Volatile RAM
This is not a test, but allows you to clear out the error log contents and other areas of RAM that are not
cleared on a power up.
1. When you select this menu item, the display will show:
“CLEAR NON-VOL SRAM
Confirm - Press MUTE”
2. When MUTE is pressed, the second line will display:
Initializing RAM for a second, then it will display:
“TEST COMPLETED”
LOOP TEST SUITE
The Loop, (burn-in) suite is available from the top level DIAGS MENU when the LOOP TESTS item is
selected.
1. When you select LOOP TESTS, the VFD will display:
“LOOP TESTS
NON_VOL RAM SETUP”
The NON_VOL RAM setup initializes the non-volatile section of the SRAM with a byte pattern that is
verified by the loop tests. As the unit is in burn-in, this byte is continuously verified ensuring that the
register section of the SRAM continues to hold data. This will also set a flag for programming the
decoder and video flash memories at the beginning of the burn-in loop the first time the test is run.
2. Rotating the encoder knob will display the following on the VFD:
“START ALL TESTS”
When the Start All Tests menu option is selected, the Loop tests are run continuously. The first time
the burn-in loop is run the decoder flash and the video flash will be programmed. They will each take
about 3.5 minutes to complete. This flash programming is only performed one time. All subsequent
looping of the burn-in loop will not program the flash.
These are the tests available in the Loop Test Suite:
•
Z180 Burn-In SRAM
•
Z180 EPROM checksum
•
Z180 FLASH checksum
•
VFD Memory
5-19
MC-8 Service Manual
•
I/O FPGA Verify ID
•
DSP FPGA Verify ID
•
Decoder FPGA
•
Crystal 49400 Boot
•
Sharc Internal GPIO (x4)
•
Sharc SRAM (x4)
•
Sharc SDRAM (x4)
•
Sharc Boot (x2)
•
Trigger 0 ON
•
Trigger 1 ON
•
Trigger 0 OFF
•
Trigger 1 OFF
There is only one item in this menu and selecting it will start the sweep through the whole suite of loop
tests. As long as there are no errors the test will continue to run. If there is a failure, the entire bottom row
of eight LEDs on the front panel will light. These are the TV, CD, TUNER, and AUX LEDs for the Main
and Zone2 sections. Depending upon the failure, the failing test will cycle and the error code will be
displayed on the second line of the VFD. For example, if the Decoder FPGA verify fails the VFD will
indicate:
DEC FPGA TEST
Fail:
E 001E
To continue, press the MODE switch.
Upon completion of all of the tests, the second row of the VFD will briefly indicate “Pass” or “Errors”.
Loop SRAM Test
The Burn-In SRAM Test reads a bit-pattern from a known location by the NON_VOL RAM SETUP.
AUDIO I/O TESTS
The Audio I/O tests contain the following tests:
•
Audio Input 1 Test
•
Audio Input 2 Test
•
Audio Input 3 Test
•
Audio Input 4 Test
•
Audio Input 5 Test
•
Audio Input 6 Test
•
Audio Input 7 Test
•
Audio Input 8 Test
5-20
Lexicon
•
SPDIF Input CX1 Test
•
SPDIF Input CX2 Test
•
SPDIF Input CX3 Test
•
SPDIF Input CX4 Test
•
SPDIF Input OP1 Test
•
SPDIF Input OP2 Test
•
SPDIF Input OP3 Test
•
SPDIF Input OP4 Test
These tests put the unit into a state to pass audio through the path that is contained in the test name for
troubleshooting. For instance the Audio Input 1 Test would pass analog audio from analog input 1 to all
the outputs.
VIDEO I/O TESTS
The Video I/O tests contain the following tests:
•
INIT INT SYNC
•
INIT EXT SYNC
•
Select PAL
•
Select SECAM
•
Load Font
•
Color Bars
•
Show CHARS
The video I/O tests initialize the video circuitry to put the unit into a known state for troubleshooting. The
menu items select a few of the basic setups that can be used for troubleshooting. These selections will
instruct the On Screen Display, OSD, IC in the unit to output a video signal that can be used to verify the
video circuit from the OSD to the monitor outputs of the unit.
5-21
Lexicon
CHAPTER 6 – THEORY OF OPERATION
Main Board Z180 Host Processor
The Z180 is responsible for all systems control in the unit. It runs off the 29.491mHz crystal oscillator. It is
reset by the main PWR_RST/ signal. ZCLK is a buffered synchronous clock output that is used to
synchronize signals in the Memory CPLD and the I/O FPGA.
29.491 MHZ
CRYSTAL
RS-232
RCV
RS 232 XMT
INTERRUPTS
ZWAIT/
ZA(7:0)
ZD(7:0)
Z180
HOST
PROCESSOR
SRAM
CONTROL
Z CTRL
Z180
HOST
INTERFACE
MEMORY
BOARD
CONTROL
SRAM
I/O FPGA
PROGRAM
RESETS
STANDBY BUTTON
MEMORY
EPROM
ENCODER INTERFACE
MEMORY CPLD
FLASH
ROM
HOST PROCESSOR
BLOCK
MEMORY
BOARD
Memory CPLD
The Memory CPLD is programmed at the factory like an EPROM. It can be programmed before or after it
is soldered to the PC board. It provides the following functionality:
•
Host data, address and control interface – provides all memory space address decoding, plus a small
section of I/O space that is occupied by the Memory CPLD internal control and status registers
•
SRAM read/write signals and bank address bit
•
Flash ROM and EPROM control signals and bank address bits, RA(22:15)
•
The I/O FPGA programming bits
•
Reset lines under host control to the analog circuitry, I/O FPGA, Video Board, and Front Panel Board
•
The Standby LED
•
The Standby button
•
The Front Panel Encoder interface.
6-1
MC-8 Service Manual
Host Processor Memory
There are three devices located in the Z180’s memory space; the SRAM, which is on the Main Board,
and the FLASH ROM and EPROM, which are located on the Memory Board. The 32kx8, 70ns SRAM is
powered by the battery backup, BAT_VCC, so that user and factory default settings are preserved when
the unit is powered down.
The Z180 boots from the 256kx8 70ns EPROM at power up. Once the EPROM, SRAM and FLASH
diagnostics have passed the Z180 sets a bit in the Memory CPLD that allows the Z180 to run out of the
FLASH ROM. The 2Mx8 FLASH ROM is programmable from the RS-232 serial port.
Host Processor I/O
All peripheral devices and boards live in the Z180 I/O address space. The I/O FPGA handles all address
decoding. Due to the size of the Main Board, the Z180 data bus is buffered through two 74VHCT245s,
creating the IODX and IODY data buses. All data and address buses going to other boards are also
buffered.
RS-232 Serial Interface
The 29.491mHz crystal oscillator is divided down to provide the 19.2K Serial Baud Rate of the MC-8. The
TX0, RX0, TX1 and RX1 ports on the Z180 are connected to the Max202E Transceiver that drives the
two female DB9 connectors RS-232 1 and 2.
6-2
Lexicon
FPGAs
Host Programming of FPGAs
All FPGAs are programmed by the Host processor as part of the boot process when the unit is powered
on from the rear panel. The I/O FPGA is programmed by the host through the Memory CPLD. The Audio
FPGA is programmed by the host through the I/O FPGA. Any FPGAs residing on daughter boards are
programmed through the Audio FPGA. It is important to understand that until the FPGAs have been
programmed, most of the unit, including the front panel and on screen display are in reset. There are
LEDs that light to indicate when the programming for each FPGA is complete.
Z180 ADDRESS
Z180 DATA
MEMORY CPLD
Z180
HOST
INTERFACE
I/O FPGA
PROGRAM
IO FPGA
Z180
HOST
INTERFACE
PROGRAM
PINS
AUDIO
FPGA
PROGRAM
AUDIO FPGA
DAUGHTER
BOARD 0
Z180
HOST
INTERFACE
PROGRAM
PINS
FPGA PROGRAMMING
DAUGHTER
BOARDS
FPGA
PROGRAM
DAUGHTER
BOARD 1
DAUGHTER
BOARD 2
6-3
MC-8 Service Manual
I/O FPGA
The I/O FPGA has a byte wide data path for the host interface. It provides the following functions:
•
Handles the entire I/O space memory map for the system
•
Generates the chip selects for all peripheral devices that the host communicates with over the I/O
data bus
•
Automatically generates wait states to the Host for devices that require longer access times.
•
Outputs the bits that are used to program the Audio FPGA
•
Receives Video Board status
•
Receives temperature sensor status
•
Generates 4mHz clock used for serial control interfaces
•
Allows the host to choose between the crystal oscillators for analog audio, the master clock output of
the Digital Receivers or the output of the Phase Lock Loop (PLL) as the master clock source for each
zone.
•
Digital control signals for the PLL
•
Control bits and sample-rate detection clocks to the Main and Zone Digital Receivers.
Z180
HOST
INTERFACE
CHIP
SELECTS
HOST
WAIT
STATES
CONTROL/
STATUS
CHIP
SELECTS
VIDEO
BOARD
STATUS
BITS
AUDIO
FPGA
PROGRAM
TEMPERATURE
STATUS
MAIN
DRCVR
CONTROL
& NRZ
AUDIO
DATA
ZONE
DRCVR
CONTROL
& NRZ
AUDIO
DATA
XTAL OSC
AUDIO
MASTER
CLOCKS
4 MHZ
SERIAL
CLOCK
PLL I/O & CONTROL
MAIN MASTER CLOCK I/O
ZONE MASTER CLOCK I/O
I/O FPGA
6-4
Lexicon
Audio FPGA
The Audio FPGA is the central audio routing block for the system. It has a byte-wide data path to the host
and seven host address lines. It performs the following functions:
•
Generates word and bit clocks for each zone from the master clocks and distributes them to all audio
devices and interfaces on the main board
•
Allows the host to select which digital audio connector is connected to the Main and Zone Digital
Receivers
•
Receives status bits from the Main and Zone Digital Receivers
•
Host Serial Control Interface to the to the Video Board and On Screen Display. Consists of the chip
select, serial clock and data. The FPGA converts the host parallel data to a serial data stream
•
Serial control of the Main and Zone DACs and Volume Controls
•
The 1mHz clock signal used by the 16C54 PIC IR Receiver
•
Routes all I2S audio data in the system
•
Packs and unpacks I2S audio into octal streams for the Sharc DSPs
•
Provides interrupts to the Z180 Host processor
•
Provides twelve programmable tie lines each to the DSP board connector and the three daughter
board connectors.
HOST
INTERRUPTS
HOST
INTERFACE
VIDEO
SERIAL
CONTROL
ANALOG
DAC &
VOLUME
CONTROL
SERIAL
INTERFACE
MAIN DRCVR
STATUS
ZONE
DRCVR
STATUS
ANALOG
CONTROL
REGISTER
CHIP
SELECTS
COAX/OPTO
INPUTS
S/PDIF NRZ
DATA OUT
text
MAIN AUDIO CLOCKS & DATA
ZONE 2 AUDIO CLOCKS & DATA
DSP BOARD INTERFACE
DAUGHTER BD 0 INTERFACE
(DECODER)
DAUGHTER BD 1 INTERFACE
DAUGHTER BD 2 INTERFACE
SPARES
AUDIO FPGA BLOCK
6-5
MC-8 Service Manual
HOST INTERFACE TO OTHER BOARDS
Front Panel, IR/Encoder, and VFD
The interface to all of the front panel boards (with the exception of the standby board) is a single ribbon
connector. All signals are connected to the Switch/LED Board. It then passes signals as required to the
IR/Encoder Board and the VF Display.
The signals used by the Switch LED Board are as follows:
•
FP_RST – this prevents the LEDs from lighting when the unit is first powered up, until the host is
initialized
•
SWRD_LEDWR/ - when this signal is high, the MUX generates the enable for reading the Switch
Buffer. When it is low, it generates write strobes to the LED Registers and the Switch Column
register. In order to read the switches, the host must first select a column
•
Front Panel data – bi-directional
•
Front Panel address – used by the MUX.
Signals used by the VF Display are as follows:
•
VFD_EN_BUF – chip select to the display
•
Data – byte-wide
•
Address – two address bits. Address determines whether an access is a read or a write.
Signals used by the IR/Encoder Board are as follows:
•
IR auxiliary data from the rear panel connector. This is optically coupled with the incoming IR signal at
the IR receiver
•
The IR acknowledge LED bit. This comes from the PIC and is used to indicate that the unit is
detecting an infrared signal
•
System_On and Overload LED bits
•
Encoder 0:1 – these are the output of the front panel encoder knob. They are read and interpreted on
the main board.
VFD ENABLE
HOST IO DATA
BUFFER
HOST ADDRESS
BUFFER
VFD ENABLE
FRONT
PANEL DATA
DATA
FRONT
PANEL ADDR
ADDR
VFD
MUX
SWITCH READ/LED WRITE
RESET
VFD DATA
ADDR (0:1)
BUT
TON
REG
DISPLAY
LED
REG
LED'S
IR AUX DATA
IR AUX DATA
IR ACK LED
IR ACK LED
IR DATA
IR
RECEIVER
IR DATA
ENCODER (0:1)
ENCODER (0:1)
FRONT PANEL
CONNECTOR
FRONT PANEL,
I/R ENCODER & OSD
6-6
ENCODER
SWITCH/LED BOARD
IR ENCODER
BOARD
Lexicon
Video Board & OSD
The control interface to the Video Board consists of:
•
Serial control data
•
The serial control bit clock
•
OSD chip select – enables the serial control port of the On Screen Display chip
•
Video Register chip select – enables the serial to parallel registers that generate the control bits used
on the video board
•
The video reset line.
SERIAL CTRL DATA
SERIAL CTRL CLOCK
BUFFER
(3V->5V)
VIDEO DETECT
OSD CHIP SELECT
VIDEO REG CHIP SELECT
RESET
VIDEO BOARD INTERFACE
VIDEO BOARD
CONNECTOR
DSP and Daughter Board Connectors
The DSP and daughter board connectors have the following interface:
•
Host I/O data bus
•
Host I/O address bus
•
Host I/O control – RD, WR and CS
•
Reset
•
4 MHz clock used on the analog board to derive serial control clocks
•
12 programmable tie lines to the Audio FPGA which can be used as needed for audio clocks and
data or control
•
1 programmable tie line to the I/O FPGA.
HOST IO DATA
BUFFER
HOST ADDRESS
DBA DATA
DBA ADDR
BUFFER
IO_RD
IO_WR
RD
WR
DAUGHTER BOARD CHIP SELECT
4 MHZ SERIAL CONTROL CLK
12 TIE LINES
RESET
DAUGHTER
BOARD
INTERFACE
DAUGHTER
BOARD
CONNECTOR
6-7
MC-8 Service Manual
DECODER BOARD
The Decoder board is installed in the Daughter Board 0 slot.
Decoder FPGA
The Decoder FPGA has a byte wide data path for the host interface with 5 bits of addressing. It provides
the following functions:
•
Provides ABOOT/IRQ and HINBUSY/ lines for control of the Cirrus 49400
•
Converts Host parallel data for serial control of the 49400 DSP AB and C
•
Uses the MCKI daughter board audio clock inputs DB_MCKI and DB_FSI to create the input and
output frame sync and SCLKs required by the 49400 audio interface. This includes running the input
and output sides of the CS49400 at different rates for DTS 96/24 decoding
•
Uses the Decoder GPIO pins to enable the correct Decoder
•
Flash write signals and addresses
•
Routes audio data to and from the CS 49400. The input is a single I2S 2-channel PCM data line. The
output of the chip consists of four I2S 2-channel PCM data lines.
HOST
INTERFACE
DSP AB CONTROL
DSP C CONTROL
AUDIO CLOCKS
AUDIO DATA
FLASH ROM INTERFACE
DECODER FPGA BLOCK
6-8
Lexicon
CIRRUS CS49400 DSP Audio Decoder
The CIRRUS DSP is responsible for detecting and decoding all compressed audio data formats, Dolby
AC-3 and DTS. It is a 2.5-Volt part. Its processor clock is a 12.288 MHz crystal oscillator. The internal
speed at which the chip runs is selected by DEC_CLK_SEL. The chip actually consists of two linked
processors, which are referred to as DSP AB and DSP C. In the following section, (x) refers to AB or C.
To boot the chip, the Host processor sets the DEC_(x)_ABOOT/IRQ pin low and sets the ECODER_RST/
pin high. The chip then boots from the external Flash Rom. Processor C boots first, followed by processor
AB. The host, through the CS49400, can program the Flash ROM. During run time, the host
communicates with the Crystal Decoder through a serial control interface that consists of the following
signals:
•
DEC_(x)_SCDIN – host serial control data generated in the DAR FPGA
•
DEC_(x) SCDOUT – CS49400 Decoder status data output to the host
•
DEC_(x)_SCCLK – serial data bit clock
•
DEC_(x)_CS/ - serial port chip select
•
DEC_(x)_ABOOT/IRQ/ - CS49400 interrupt to the host.
The Main Zone input, analog or digital, is always routed through the Crystal decoder except during audio
diagnostics. The serial audio interface consists of:
•
DEC_SDI – 2 channel PCM audio stream input from either the Main Digital Receiver or the Main
Analog ADC
•
DEC_SDO(3:0) – four 2-channel PCM audio stream outputs that are routed down to the Audio FPGA
on the main board where they are converted into octal data streams that are then sent to the Sharc
DSPs
•
DEC_IN_FSI – Input side word clock audio framing signal, 1 x input sample rate
•
DEC_IN_SCKI – Input side audio bit clock, 64 x input sample rate
•
DEC_OUT_FSI – Output side word clock audio framing signal, 1 x output sample rate
•
DEC_OUT_SCKI – Output side audio bit clock, 64 x output sample rate.
It is possible for the input side of the CS49400 to run at half the sample rate of the output side. This is
required for DTS 96/24 decoding.
EPROM DATA
DATA
FLASH
ROM
DSP AB SERIAL
CONTROL CLOCKS
ADDRESSES
DSP AB SERIAL
CONTROL DATA
DEC AB ABOOT/IRQ
DSP C SERIAL
CONTROL CLOCKS
CRYSTA
L
49326
DSP C SERIAL
CONTROL DATA
DEC C ABOOT/IRQ
AUDIO DATA
& CLOCKS IN
4x2 CHANNEL PCM AUDIO DATA OUT
CIRRUS CS49400 DSP BLOCK
6-9
MC-8 Service Manual
DSP BOARD
The principle DSP in the system consists of two pairs of Analog Device 21065 SHARC DSP engines,
which reside on a daughter board. Each pair shares four 128kx8 12ns SRAMs and one 2Mx32 SDRAM.
The SHARCs communicate with this external memory and each other over a 32-bit wide data bus. All
necessary chip selects are generated by the SHARCs, including the clocking required for the
Synchronous DRAM. The SHARCs master clock is provided by a 30MHz crystal oscillator that is
distributed through a 74LCX14 inverter used as a buffer.
30
MHZ
SHARC A
HOST
DATA
DSP
COMMAND
REGISTER
(DSP FPGA)
SRAM
X4
SHARC C
SHARC
DSP
A/B
SHARC B
ADDRESS & DATA
SDRAM
ADDRESS & DATA
DSP
STATUS
REGISTER
(DSP FPGA)
HOST
DATA
SHARC D
SHARC
DSP
BLOCK
HOST
DATA
6-10
DSP
COMMAND
REGISTER
(DSP FPGA)
SRAM
X4
SDRAM
DSP
STATUS
REGISTER
(DSP FPGA)
SHARC
DSP
C/D
HOST
DATA
Lexicon
DSP Board FPGA
The DSP FPGA has a byte wide data path for the host interface with five-bits of addressing. It provides
the following functions:
•
Host communication with DSPs A, B, C and D. This includes resets, wait lines, status/control bits,
data registers, and interrupts
•
One GPIO bit from each DSP and one Flag bit common to all four
•
Uses the FS/ and MCKI signals from the Audio FPGA on the main board to derive the necessary
audio clocks – FS/ which is used as the sample interrupt, 4FS/ which is the octal frame sync and
256FS, the serial bit clock for the octal data stream.
HOST
INTERFACE
DSP AB CONTROL & DATA
DSP CD CONTROL & DATA
AUDIO CLOCKS
AUDIO DATA
DSP FPGA BLOCK
Host Communication with the SHARC DSPs
The lowest byte of the SHARC external data bus is also connected to the Host to DSP Command
Register and the DSP to Host Status Register in the DSP FPGA. There are three modes of
communication between the Host and the DSPs. The first occurs at boot time. When it comes out of
reset, the A or C SHARC asserts DSP_BMS/ and DSP_RD/. These are combined by the DSP FPGA to
create SP_CMD_RD/. This signal is used to generate the DSP_WAIT/ signal, which is re-clocked by the
DSP_30MHZ to synchronize it to the SHARCs. It is then sent to the SHARC as DSP_AB_ACK where it
keeps the SHARC in a wait state until the Z180 has written the data to the DSP Command Register.
DSP_ACK/
DSP_ACK/
SHARC
DSP'S
A/B
HOST
DATA
DSP
CMD
REG
(FPGA)
DSP_BMS/
DSP_RD/
DSP
FPGA
DSP
DATA
CMD_REG_FULL
TO
HOST
DSP_COMMAND_WR/
DSP_CMD_RD/
DSP_C0MMAND_RD/
DSP_COMMAND_WR/
HOST LOADS SHARC AFTER RESET: BOOT MODE
6-11
MC-8 Service Manual
Host Writes Data to a SHARC DSP
This is how the host transmits data to the SHARCs during run-time. The Host writes a byte to the DSP
Command Register. The write strobe, DSP_COMMAND_WR/ also interrupts the SHARC to let it know
that a byte is waiting. The SHARC then retrieves the byte by asserting DSP_HOST_CS/ and DSP_RD/.
This also clears a status bit in the DSP FPGA, informing the host that the command register is empty and
can be written to again.
DSP_COMMAND_WR/
HOST
DATA
DSP
CMD
REG
(FPGA)
SHARC
DSP'S
A/B
DSP_HOST_CS/
CMD_REG_FULL
DSP
FPGA
DSP_RD/
TO
HOST
DSP_COMMAND_WR/
DSP
DATA
DSP_CMD_RD/
DSP_C0MMAND_RD/
DSP_COMMAND_WR/
HOST WRITES DATA TO SHARC
SHARC DSP writes Data to the Host
The SHARC writes a byte into the DSP to Host Status Register in the DSP FPGA by asserting
DSP_HOST_CS/ and DSP_WR/. This sets a bit in the DSP FPGA that informs the host that that register
is full and waiting to be read. When the host reads the byte, the DSP_STATUS_FULL line to the SHARC
is cleared so the SHARC knows that the register is empty and can be written to again.
DSP_STATUS_FULL
DSP_STATUS_FULL
DSP_HOST_CS/
DSP_WR/
I/O
FPGA
STAT_REG_FULL
TO
HOST
DSP_STATUS_RD/
SHARC
DSP'S
A/B
DSP_STATUS_WR/
DSP
DATA
DSP
STATUS
REG
(FPGA)
HOST
DATA
DSP_STATUS_RD/
DSP_STATUS_WR/
SHARC DSP WRITES DATA TO HOST
6-12
HOST-DSP
COMUNICATIONS
BLOCK
Lexicon
AUDIO ROUTING
Digital Audio Input Path
Digital Audio can be either PCM 2-channel data or one of the compressed data formats. It enters the unit
on one of the digital input connectors that are connected to the Audio FPGA. The FPGA functions as a
mux and routes the output NRZ, (Non Return to Zero) data of the connector selected by the user to the
two Digital Receivers, Main and Zone. These receivers lock to the incoming signal and extract a
2-channel PCM audio signal that is returned to the Audio FPGA.
Main Audio Data Path
The Main Audio Data Path is as follows:
1. Output of the Main Digital Receiver and the Main ADC to the Audio FPGA
2. Output of the Audio FPGA to the Crystal 49400 Decoder on the Decoder Board, Daughter Board 0
3. Four 2-channel outputs from the Crystal 49400 Decoder back to the Audio FPGA
4. The four 2-channel streams are packed into a single octal data stream in the Audio FPGA
5. The output of the octal packer is sent to SHARC A on the DSP Board
6. The octal output of SHARC B is sent to the input of Sharc C
7. Two octal outputs of SHARC D are sent back to the Audio FPGA on the Main board
8. The two octal outputs from SHARC D (not all slots are used) are unpacked into four 2-channel PCM
streams in the Audio FPGA
9. These four 2-channel streams are sent to the Analog board as MAIN_DAC(0:4)_SDI.
MAIN_DRCVR_SDO
MAIN_ADC_SDO
DECODER_SDO(0:3)
CRYSTAL DECOER CS49400
AUDIO CLOCKS & DATA
DECODER_SDI
CRYSTAL
49400
DECODER
4 STEREO IN TO 1 OCTAL OUT
DECODER BOARD
SHARC DSP A/B AUDIO DATA IN
DSPA_OA_SDI
SHARC
DSP
AB
DSPB_SDI
SHARC DSP C/D AUDIO DATA I/O
SHARC
DSP
C/D
DSP BOARD
DSP D Serial Audio Out
1 OCTAL IN TO 4 STEREO OUT
MAIN_DAC(0:5)_SDI
MAIN AUDIO PATH
AUDIO FPGA BLOCK
TO
ANALOG
SECTION
6-13
MC-8 Service Manual
Main Audio Clock Path
There are two possible sources of master clock for the Main Audio Path. The 24.576 oscillator that can
provide either a 48kHz or 96kHz sample rate, or the master clock output of the main digital receiver. In
practice, the unit runs off the crystal at 96kHz when the input is analog. When the input is digital, the
master clock output of the digital receiver is used. This master clock is de-jittered by the PLL that is
controlled by the I/O FPGA using signals derived from MAIN_DRCVR_MCKO.
Depending on the input selected, the appropriate master clock is routed from the I/O FPGA to the Audio
FPGA. Here it drives a clock tree that divides down the master clock, which is 256 times the sample rate,
256FS, to create the other clock rates required.
•
The SHARC DSPs receive a word clock, or framing signal, FS and a bit clock of 256FS
•
The Digital Receiver, ADCs and DACs use a word clock, FS/and bit clock, 64FS/
•
The DSP and Decoder Boards receive a 256FS Master Clock and a word clock, FS/. These are used
on each individual board to derive the audio clock signals required by that particular board.
PLL_MCKO
PLL
CONTROL
24.576 MHZ
MAIN DRCVR
PLL
4896_MCK
MAIN_DRCVR_MCKO
IO FPGA
MAIN_MCKO
MAIN
DRCVR
MAIN_DRCVR_FSI
MAIN_DRCVR_SCKI
MAIN
ANALOG
MAIN_ANLG_FSI
MAIN_ANLG_SCKI
MAIN_ANLG_MCKI
DSP BOARD
DBx_FSI
DBx_MCKI
DAUGHTER
BOARDS
0,1,2
MAIN AUDIO CLOCKS
6-14
AUDIO FPGA
DBx_FSI
DBx_MCKI
PLLMCKO
Lexicon
Zone Audio Clock and Data Paths
The Zone Audio Data Path is as follows:
•
Output of the Zone Digital Receiver to the Audio FPGA
•
A 2-channel stream is sent to the Analog section as ZONE_DAC_SDI. This stream is either the
output of the Zone Digital Receiver or a 2-channel down-mix of the Main Audio content.
There are three possible sources of master clock for the Zone Audio Path. The 22.5792mHz crystal
oscillator that provides either a 44.1kHz or 88.2kHz sample rate, the 24.576 oscillator that provides either
a 48kHz or 96kHz sample rate, or the master clock output of the Zone digital receiver. In practice, the unit
runs off the crystal at 96kHz when the input is analog. When the input is digital, the master clock output of
the digital receiver is used. Depending on the input selected, the appropriate master clock is routed from
the DAR FPGA to the Audio FPGA. Here it drives a clock tree that divides down the master clock, which
is 256 times the sample rate, 256FS, to create the other clock rates required.
•
The Digital Receiver uses a word clock, FS, and bit clock, 64FS
•
The Analog Board receives a 256FS Master Clock and a word clock, FS. These are used on the
analog board to derive the audio clock signals required by the devices on that board.
24.576 MHZ
4896_MCK
ZONE
DRCVR
ZONE_DRCVR_MCKO
IO FPGA
ZONE_DRCVR_SDO
ZONE_MCKO
ZONE
DRCVR
CLOCK
ZONE
ANALOG
CLOCKS
ZONE AUDIOCLOCKS
ANALOG
CONNECTORS
ZONE
DRCVR
ZONE_DRCVR_FSI
ZONE_DRCVR_SCKI
ZONE_ANLG_FSI
ZONE_ANLG_MCKI
TO
ANALOG
SECTION
AUDIO FPGA
INPUT
MUX
ZONE_DRCVR_SDO
ZONE_SDO
DSP BOARD
TO
DIGITAL
RCVR
DAC
OUTPUT
MUX
OUTPUT
CONNECTOR
DOWNMIX
ZONE AUDIO DATA
AUDIO
FPGA
6-15
MC-8 Service Manual
VCO BOARD OVERVIEW
The MC-8 VCO board is an isolated Voltage-Controlled Oscillator module that forms part of an overall
PLL for generating master clocks for digital audio in the MC-8 system. The board is housed in a shielded
enclosure and mounts to the main board through a 5-pin in-line header J1, which carries control-voltage
input, oscillator output, and 5-volt power and ground. The VCO assembly is soldered to the MC-8 main
board, which incorporates the phase-detector and error amplifier to form the complete PLL.
MC-8 ANALOG OVERVIEW
The analog section of the MC-8 encompasses all of the analog audio inputs and outputs, level controls
and A/D and D/A converters. This section is located near the rear panel connections on the MC-8 Main
Board. There are two separate signal paths: Main and Zone 2. Each of the eight analog stereo inputs or
eight digital inputs can be routed to any of the two paths. The Main path digitizes the analog signal (if
selected) and passes it to the DSP. Refer to the Main Audio Path 2-Channel Input block diagram in the
next column. The DSP creates eight different output signals from the 2-channel input. D/A converter ICs
convert each of the eight signals from the DSP to analog. The signals pass through level controls to their
respective RCA connectors. A direct analog path is also provided which passes a 2-channel analog input
signal directly to the Left and Right Front outputs via the level controls, bypassing the DSP and
converters.
The MC-8 Balanced version offers additional Balanced Main and Zone 2 analog outputs using XLR
connectors. In this version, an internal 34-pin ribbon cable routes the post level control signals from the
Analog board to the XLR board. The XLR board incorporates active balanced output drivers for each of
the ten outputs.
In addition, two 5.1-channel sources can be selected for the Main audio path. There are two possible
methods of getting a 5.1-source into the box. Refer to the Main Audio Path 5.1-Channel Input block
diagram above.
1. An S/PDIF signal may be encoded in Dolby Digital or DTS format and pass through a decoder that
outputs the 5.1 channels. These channels are then passed along to the DSP.
2. Two sets of three separate analog input pairs can be routed directly to the outputs, bypassing the
DSP and converters. This mode is available for DVD-Audio and multi-channel SACD players with 5.1
analog outputs. In the first case, Input 3 would pass to the Left and Right Front outputs; Input 4 would
pass to the Center and Subwoofer outputs. Input 5 would pass to the Left and Right Side and Rear
outputs. A duplicate set uses inputs 6, 7, and 8 in a similar manner.
Any of the eight analog or eight digital audio inputs can be selected as the source for the Zone 2 Audio
Path as shown in the Zone 2 Audio Paths block diagram below. An analog source can be passed directly
to the analog outputs. Likewise, a digital source can be passed directly to the digital outputs and be
routed to a D/A converter for the analog outputs. In addition, a 5.1 Dolby Digital or DTS encoded 5.1
digital source may also be selected and passed through a decoder which will output a 2-channel downmix
for the Zone 2 outputs. One S/PDIF RCA (coaxial) output port is available.
6-16
Lexicon
Analog Audio Inputs
The Left input jacks and associated circuitry are on the first sheet. See the second sheet for the Right
input jacks and circuitry. Each input pair is buffered by a dual TL072 op amp. Each buffer connects to two
DG408 8x1 CMOS switches. There are separate switches for the Main and Zone 2 analog source
selection with independent switches for left and right channels, for a total of four DG408s.
The outputs of the Main source selectors feed the Main Input Level control. Two dual op amps are used
for the direct analog path to the Front L/R outputs and the Zone 2 outputs and buffer a 6dB voltage
divider that feeds the level control.
At the bottom right-hand corner of sheets one and two are two op amps. These amplifiers are used when
routing a 5.1-analog source. One buffers the Center and Subwoofer signals from Inputs 4 or 7 while the
other buffers the Surround L/R signals from Input 5 or 8.
Microphone Inputs and Main A/D Converter
Two microphone inputs are provided for use with an optional daughter card with 1/8-inch microphone
connectors and preamplifiers. A DG411 analog switch can select Mic inputs 1 and 2 to be passed to the
Main Input level control and A/D converter. When the Mic input is selected, the Analog inputs are disabled
by bringing MAIN_ANLG_EN low.
The Main Input level control is the PGA2311, which has a range from +31.5 to –95.5 dB in 0.5 dB steps.
The PGA2311 operates on ±5 volt rails and cannot handle signal levels greater than 7.5 Vpp.
Two dual op amps provide the left and right differential audio signals to the A/D converter. The op amp
circuits bias the signals at 2.5 V and attenuate it by 7dB. This means a 2 Vrms signal at the output of the
level control will be equivalent to 0 dBFS after the A/D conversion.
The AK5383 stereo A/D converter incorporates a dual-bit deltasigma architecture. It outputs 24 bits at a
96kHz sample rate under normal operation. The serial audio data from the A/D converter goes directly to
the digital part of the Main board. The A/D also provides a signal to mute the Main analog inputs
(MAININ_VC_MUTE/) when it is going through calibration during power up or sample rate changes.
Control signals are used for reset (MAIN_ADC_RST/) and to place the converter in 88.2k or 96k sample
rate mode (MAIN_ADC_96K_EN). The Audio FPGA (sheet 4) provides three clocks: MAIN_ADC_MCKI/,
which is 256xFS for 44.1k and 48k sample rates, 128xFS for 88.2k and 96k sample rates;
MAIN_ADC_SCKI/, which is 64xFS; and MAIN_ADC_FSI/ which is 1xFS (where FS = sample rate).
Zone 2 D/A converter
The AK4395 24-bit delta-sigma stereo D/A converter operates up to 192 kHz. The DAC is configured
through its serial control port (pins 8,10,11) with a separate Reset pin.
The output of the DAC passes through a second order low-pass filter with its –3dB frequency at 83kHz.
The filter is flat out to 20kHz. It has an overall gain of 7.4dB when measured at the test points. This
means a 0 dBFS signal at the D/A converter will be 4Vrms going into the analog switches.
ADG451 analog switches select either the output of the respective DAC or the analog input source
directly. The selected signal goes to the PGA2310 output level control and driver. These are special
volume controls that run from +/-15 volt supplies and have a built-in op-amp driver. Zone 2 analog output
has a maximum output level of 4 Vrms. The signal passes through a muting relay on the way to the
output jacks. The relays are controlled by the ZONEOUT_MUTE/ signal.
6-17
MC-8 Service Manual
Main D/A Converters
There are eight outputs for the Main Audio Path. The D/A circuitry is shown for two outputs on each
sheet. The circuitry is identical for all eight outputs.
The AK4395 is the same 24-bit D/A converter that operates Zone 2.
The Analog FPGA (sheet 4) is the source for the clocks and data for the D/A converters. The MCLK is at
256 times the sample rate (FS). Each converter gets MCLK through a separate source resistor. The
SCLK (64xFS) and LRCK (1xFS) are distributed to two sets of two DACs via separate source resistors.
All of the D/A converters operate in I2S mode.
The AK4395 DACs are configured through their serial ports (pins 8,10,11). FRONT_DAC_RST/ puts the
Front L/R pair of DACs into reset, while all other DACs share the same reset line (MAIN_DAC_RST/).
A second order low-pass filter follows the DACs. The filter amplifies the 1.7Vrms differential signal to
8Vrms (+13.5 dB) and converts it to single-ended for the level controls. Note these values assume a 0
dBFS digital input signal to the DAC. ADG451 analog switches are used to select either the DAC output
or analog input for the respective output. These direct analog signal paths have been designed to support
two modes:
•
2-channel analog direct or bypass mode. Any analog input can be routed directly to the L/R Front
outputs
•
5.1-channel analog direct or bypass mode. When this mode is enabled, specific analog input signals
are routed to specific analog outputs according to the table below.
Two different pairs of control bits are used to select the DSP/DAC signals or analog input signals for the
Main outputs. FRONT_DACOUT_SEL/ selects the Front L/R DAC outputs for the Left and Right Front
outputs when low. FRONT_DIRECT_SEL/ selects the analog input for the Front outputs.
MAIN_DACOUT_SEL/ selects the respective DAC outputs for all of the other Main outputs (Center, Sub,
L/R Side, L/R Rear) whereas MAIN_DIRECT_SEL/ selects the 5.1 analog inputs directly.
The output from the analog switch goes to a PGA2310 output level control and driver. This level control
operates from +/-15V rails with a gain range from +31.5dB to –95.5dB in 0.5dB steps. Each PGA2310
controls a signal pair.
The outputs from the level control pass through DC-blocking caps and relays before going to the RCA
connectors. The relays mute the Main outputs during a power cycle and whenever the unit is in Standby
or Off. The relays are controlled by the MAINOUTS_MUTE/ signal.
The PGA2310 outputs also go to a 34-pin connector. This connector is used for routing the audio to the
XLR board in MC-8 Balanced models.
6-18
Lexicon
Control Registers and XLR Board Connector
A 34-pin dual row ribbon connector routes the audio signals to the XLR board for MC-8 Balanced models.
Five discrete 74HC273 control registers are located on the board. The Z180 writes to them via the 8-bit
data bus (IODX_D[7:0]).
Control Register 0 provides the following:
•
Mute relay control for the Main RCA outputs (MAINOUTS_MUTE/)
•
Mute relay control for the Main XLR outputs (EXPOUTS_MUTE/)
•
Mute relay control for the Zone RCA & XLR outputs (ZONEOUT_MUTE/)
•
Mic selection
•
5.1 direct mux selection.
Control Register 1 provides the following:
•
Analog source selection for the Main audio path (MAIN_ANLG_SEL[2:0]; MAIN_ANLG_EN)
•
Main A/D calibration and 96kHz sample-rate enable (MAIN_AD_RST/; MAIN_AD_96K_EN).
Control Register 3 provides the following:
•
Analog source selection for the Zone audio path (ZONE_ANLG_SEL[2:0]; ZONE_ANLG_EN)
•
Zone DAC reset control (ZONE_DAC_RST/)
•
Zone output selection – DSP or analog direct path (ZONE_DACOUT_SEL/; ZONE_DIRECT_SEL/)
•
Mute for Zone output level control (ZONEOUT_VC_MUTE/).
Control Register 4 provides the following:
•
Independent Zero crossing enable for each Main output level control (FRONT_VC_ZCEN, etc.)
•
Zero crossing enable for the Zone output level control (ZONE_VC_ZCEN).
Control Register 6 provides the following:
•
Main DACs reset control (MAIN_DAC_RST/)
•
Main outputs selection – DSP or analog direct path (MAIN_DACOUT_SEL/; MAIN_DIRECT_SEL/)
•
Mute for Main output level controls (MAINOUT_VC_MUTE/)
•
Front Main DACs reset control (FRONT_DAC_RST/)
•
Front Main output selection – DSP or analog direct path
FRONT_DACOUT_SEL/;FRONT_DIRECT_SEL/)
•
Mute for Front Main output level control (FRONT_VC_MUTE/).
6-19
MC-8 Service Manual
Power Supply Connections and Regulators
There is a separate feed from the 60W switching power supply to the Analog section of the Main board.
The Video board gets its power from the analog section. The Analog board has a 6-pin connector that
accepts ±15 volts, ±5 volts and two ground connections to the supply. A 4-pin connector supplies the
video board with +5VD, +5VA and –5VA.
A 7805 voltage regulator creates the +5VA supply from the +15V rail. Heat is dissipated by a heatsink.
+5VA is an alternative "clean" 5-volt supply used by the A/D and D/A converters. +5VR is created in a
similar way to provide a stable reference for the D/A converters.
MC-8 VIDEO SYSTEM CIRCUIT OVERVIEW
The MC-8 video section consists of two major functional blocks: video switcher and on-screen display
(OSD) generator.
The video assembly consists of three boards, the Video RCA Board (schematic 060-15279), the Video
Out Board (schematic 060-15339), and the Video Board (schematic 060-15269).
The RCA input and output boards connect to the main board via flexible ribbon connectors, with most of
the active circuitry contained on the Video Board. Video input and output connectors are mounted directly
on the boards, which attach to the rear panel of the MC-8. Separate cables supply power and control
signals to the video assembly. Control from the main board is implemented via a serial interface.
Composite video inputs
Specific references are to input 1; other inputs are similar. Standard video levels applied to RCA jack J5
develop 1Vp-p is across 75-ohm termination resistor R15. Emitter-follower Q5 is located close to the
connector and buffers the input with a gain slightly less than unity. Transistor bias is supplied through
R13. Buffered video is fed to pin 10 of ribbon cable J6 through low-value series resistor R14, which
reduces high-frequency peaking in the transmission path to the video board.
Composite video outputs
Composite video outputs originating on the video board are fed through individual pins of J3 to the
corresponding output RCA jacks. The on-board traces are controlled-impedance and form part of a
75-ohm wideband transmission system, and output level is 1Vp-p when terminated in 75 ohms (2Vp-p
open-circuit).
S-video inputs
Specific references are to input 1; other inputs are similar. S-video luminance inputs (pin 4 of the mini-din
jacks) are terminated and buffered the same as composite inputs. AC-coupling is applied after buffering;
C45 couples S-video #1 luminance. Chrominance input #1 (pin 3 of mini-din jack J13) is first ac-coupled
by C42, and then buffered by emitter follower Q10. The dc-level at the chroma input pin is direct-coupled
to subsequent sense circuitry through R80.
6-20
Lexicon
Main (Monitor) Composite / S-video
Composite and S-video luminance connect to multiplexers U17 and U18. S-video chrominance connects
to U16. The composite multiplexer is addressed by the MVID_SELn bits, and the S-video multiplexers are
addressed by the MSVID_SELn bits. When MCVID_EN/ is asserted low, U18 is enabled, and all
MSVID_SELn bits are forced to 0 (U20, sheet 7). Composite multiplexer U18 selects one composite
source. With MSVID_SELn set to 0, the S-video path is disabled because U17 is selecting a
disconnected input, and U16 is selecting a grounded input to feed the chrominance channel. When
MCVID_EN/ is high, U18 is disabled, disconnecting the composite inputs, and U20 passes addresses to
the MSVID_SELn bits, allowing U17 and U16 to select one of the S-video sources.
The composite/luminance (MY) signal from U17/U18 is amplified by non-inverting stage U29. R164
makes the gain slightly greater than the desired factor of two in order to make up for slight losses in other
stages. The signal from U29-1 is fed through R121 to the sync-stripper and dc-restorer. The dc-correction
signal BPCOR returns through R166 to close the dc-feedback loop and maintain the video back-porch
near 0Vdc. The signal OSD_Y_IN is distributed to output amplifiers U26 and U28, and also feeds the
on-screen display.
Chroma selected by U16 (MC) is ac-coupled by C137 and amplified by U29, also with gain slightly greater
than two. With a composite source selected, U16 is forced to input 0, grounding the chroma channel. The
signal OSD_C_IN is distributed to output amplifiers U27 and U28, and also feeds the on-screen display.
The dc-level on the chroma channel of the selected source is fed to the base of Q15 through multiplexer
U19 and the associated 100k series resistor. R132 raises the threshold for sensing a high level. The
dc-amplifier formed by Q15 and Q14 is disabled when MORPHEN/ is high. When enabled, a high dc-level
on the chroma input will drive base current into Q15. Q15 saturates and turns on Q14, which applies a
high dc-level to the filter formed by R31 and C112. With low dc-level input, both transistors remain off,
and no dc is fed to the filter. This circuit discriminates a low or high dc voltage on the selected chroma
input and forms a 0 or 5V level accordingly. The sensing threshold is around 3V.
Main S-video at J2 is driven by gain-of-one amplifiers U26 (luma) and U27 (chroma). Internal multiplexers
in these amplifiers determine whether the S-video is taken from the OSD path (MSTHRU/=hi) or straight
through from the input amplifiers (MSTHRU/=low). MSTHRU/ follows MTHRU/ unless MSVID_OFF is
asserted allowing main S-video luminance to be shut off when a composite source is in use. Amplifier
outputs are fed through 75-ohm series resistors (R148, R151), forming a matched transmission- line
driver system. R150 and R152 compensate for slight impedance errors due to the resistance of the onboard connecting traces. The chroma output is ac-coupled by C130, with a dc-level introduced through
R3. When MORPHEN1/ is asserted low, switch U1 permits the main chroma output to follow the
dc-sensing circuit.
Main composite video CVID_MAIN is driven by U28. Luma and chroma from the input amplifiers are
summed by R162 and R159, scaled by 1/2. The result is amplified by U28, which has a gain of slightly
more than two. With composite input, there is no chroma, and the result is simply the composite video.
With S-video input, the result is the composite version of the S-video, the sum of Y+C. The internal U28
multiplexer selects whether the OSD is in the path or whether the input is fed straight through, controlled
by MTHRU/. Output impedance is structured as with the main luma output.
Standard 1Vp-p video input levels produce 1Vp-p output on the composite and luminance channels when
terminated in 75 ohms, or 2Vp-p open circuit. The composite main output is fed to the output RCA jack on
the Video Out board via ribbon cable J16.
6-21
MC-8 Service Manual
Zone Composite / S-video
Zone video circuitry is structured similarly to main video, but without OSD capability. Refer to the previous
section for additional description. Multiplexers U11 and U10/U9 are addressed by the ZVID_SELn and
ZSVID_SELn bits respectively to select an independent record source, but otherwise operate like their
counterparts in the main path. There is no dc-restorer in the zone path, so back-porch dc-level varies with
average picture level due to input ac-coupling. The multiplexer internal to output amplifier U13 allows the
zone S-video luminance to be shut off when a composite source is in use. The zone composite output is
fed to its RCA jack on the Video Out board via ribbon cable J16.
Component Video Switcher
Component video switching is performed by means of relays to maximize signal fidelity and format
compatibility. There is no active circuitry in the component video path.
Three sets of component input RCA jacks (component inputs 1,2,3) feed a 3-wide, two-tier tree of doublethrow relays. Each tier is comprised of a pair of dpdt relays. The tree selects one of the input sets and
presents it to the bank of final output relays. The final tier of relays (RY3,RY1) connects the output RCA
jacks to either the selected component source or to the OSD. One transistor driver is associated with
each pair of relays. Relays are actuated when the associated PSELn bit is asserted high, switching from
the normally closed to the normally open circuits.
Component OSD luminance (Y) is taken from the normal analog luminance output of the OSD chip.
Color-difference signals (Pr, Pb) are derived from logic-level signals from the RGB port of the chip.
U5 buffers the logic levels and provides inverted versions of R and B. A resistor array forms a weighted
sum of the RGB levels along with appropriate dc-offset and scaling to implement the standard color
difference matrix: =
•
Y= .587G+.299R+.114B
•
Pr = .713 (R-Y)
•
Pb =.564 (B-Y).
U6 serves as buffer/filter/output driver for the Pr and Pb and drives the outputs through series-terminating
resistors R27, and R34.
One normally closed pole of RY5 grounds OSD_PY_OUT in order to effectively disable component
output.
The signals generated by the MC-12 OSD are compatible only with the 480i component format. When
incompatible formats are in use, the component OSD is inapplicable, and is not accessed by the
operating system software.
6-22
Lexicon
On-Screen Display Signals
OSD chip U32 produces a character-based video display that can be overlaid on program video or that
can occupy a full-screen, based on an independent internal video generator. OSD modes and parameters
are controlled by an extensive set of internal registers, accessed via serial interface.
The character strings to be displayed are loaded serially into the screen memory within the chip. The
bitmapped patterns that define the shapes of individual characters are stored in external font memory,
interfaced through the A[15:0] and D[7:0] buses (see below). Character dot-clock is fixed at about 15
MHz, based on the external LC circuit formed by L1/C108/C109. Oscillator U33 (PAL) or U34 (NTSC)
supplies a crystal clock. The active oscillator is determined by a high level on either NTSC_EN or
PAL_EN, enabling the respective oscillator.
In overlay mode, composite or S-video luminance from the input amplifier is applied to YIN, and similarly,
S-video chrominance (if applicable) is applied to CIN. The video applied to YIN is shifted to have a backporch dc-level of about 1.57Vdc by U23 and associated circuitry. C101/C102 passively couple the accontent of the luminance signal, with the op-amp providing the dc response. The chroma channel is
biased to the same 1.57V level by R129/R130. The OSD video is related to program video by the
separate H and V syncs (GMHSYN/, VSYNC/) derived by the sync stripper.
The full-screen mode is independent of video and sync inputs. Raster generation is based on the
appropriate crystal clock.
The OSD luminance output is dc-shifted back to 0V back-porch level by U23 and associated circuitry.
C98/C99 passively couple the ac-content, with the op-amp providing the dc response. Chroma is simply
ac-coupled by C117/C125. The shifted OSD video is buffered and filtered by U24 to produce
OSD_SY_OUT and OSD_SC_OUT. OSD_PY_OUT is buffered separately by U25 to drive the component
osd luminance output. Switch U35 permits the S-video luminance to be turned off when MSVID_YOFF is
asserted high. OSD_Y+C_OUT is formed as half the sum of the buffer outputs. These OSD output signals
feed the output amplifiers as described earlier.
In order to produce usable overlays in the SECAM system, the OSD switching action is bypassed at high
frequency through U35 and R146, preserving an attenuated version of the fm color carriers.
On-Screen Display Serial Control
The internal registers of the OSD are programmed serially from the main board in multiple 8-bit packets
on VIDEO_DATA, accompanied by VIDEO_SCLK, operating at 1 MHz. During routine OSD updating,
OSD_CS/ is fed through U35 as the OSD chip-select. Each logical transfer to the OSD chip consists of a
pair of single byte transfers.
Sync Stripper / DC Restorer
Video from input amplifier U29 is fed through R121 to U2, which drives sync stripper U3 and the dcrestorer formed by switch U1 and op amp U2.
Sync stripper U3 accepts analog video and extracts vertical and horizontal sync, producing logic level
VSYNC-OUT and AFC-OUT pulses respectively. A phase-locked loop based on ceramic resonator Y1
provides robust horizontal sync extraction even from noisy video sources. Pull-down resistors on the
outputs improve the pulse waveshapes. Sections of U4 buffer and shape the pulses from U3. AFC-OUT
is stretched by R15/C18 before buffering in order to meet the minimum width necessary for the OSD chip.
Sections of U4 and the network formed by R9, R10, D2 and C12 form pulses that are aligned with video
back porch. These pulses switch U1, which in combination with integrator U2, forms a sample-and-hold
circuit that closes the feedback loop around the input video amplifier during back-porch time. This acts to
6-23
MC-8 Service Manual
maintain the back-porch level at 0V. D1 limits the negative-going output of U2 in order to minimize the
undesirable effects of unusual sync patterns inherent in the macrovision video copy-protection scheme.
Additional logic within U3 detects the presence of a valid video input. SYNC_DETECT is fed to the main
board for use in OSD management. With video input absent, AFC_OUT free-runs at around 15kHz.
Video Control Registers
Control registers are implemented using shift registers as serial-to-parallel converters. U36, 37, and 38
are 8-bit shift registers which are cascaded to receive a 24-bit serial word. Each chip contains internal
shift stages plus a set of output latches. The shift clock and data are VIDEO_SCLK and VIDEO_DATA,
shared in common with the OSD. All VIDEO_DATA gets accumulated in the shift stages, but the 24
output latches are only updated on the rising edge of VIDEO_REG/, which acts as a chip-select for the
control registers. All control bits are initialized to 0 at power-up by VIDEO_RST/.
Font Flash Programming Interface
Three additional shift registers are dedicated to the in-system programming of flash memory U31, which
holds the bitmapped OSD font pattern. U22 is interfaced to the memory D[7:0] bus, and U21/U30 are
interfaced to the A[15:0] bus.
The shift stages of U22, 21, and 30 receive VIDEO_SCLK and VIDEO_DATA, in common with the OSD
and the video control register chips, and their serial-to-parallel transfers are clocked by OSD_CS/, in
common with the OSD chip U32. However, in normal operation, the tri-state outputs of these chips are
disabled so they do not drive the buses, and the only bus activity is the fetching of font patterns from U31
over the A[15:0], D[7:0] buses under the control of OSD U32. When necessary, the host processor on the
main board manages the programming of the font flash memory by means of control-register bits
OSD_TSC/ and VROM_WR/. In normal operation both bits are de-asserted (set high).
When OSD_TSC/ is asserted low, the bus interface of OSD U32 is disabled, and the bus interface of the
three shift registers is enabled. U35 disconnects OSD_CS/ from U32, and the OSD chip select remains
high due to internal pullup, so the OSD chip will be isolated from subsequent serial transfers involving
OSD_CS/.
The host loads the shift registers with memory address and data patterns, which are transferred to the
parallel holding registers on the rising edge of OSD_CS/. With the tri-state outputs enabled, address and
data are driven onto the memory buses. Data is written to the flash rom when the host asserts
VROM_WR/.
Digital Audio Input Ports
The Video board incorporates two optical S/PDIF connectors (CP1,CP2) and four coaxial S/PDIF
connectors (J14,J15), with associated amplifiers (U7,U8). S/PDIF signals are fed to the main board via
J19.
Power and Control Interface
J19 is the control and status interface to the host. J17 supplies power from a connector on the main
board. The main video +5-volt rail is +5VV, a filtered version of system +5VD, which also supplies relay
coils through FB1. The negative rail is -5VV, derived from the main board -5VA. The sync stripper U3 is
specially powered from a well-regulated rail, +5VAS, derived from the main board +5VA.
6-24
CHAPTER 7 – PARTS LIST
PART NO
U
DESCRIPTION
QTY
EFFECT.
INACT.
REFERENCE
Main Board Assembly
022-14458
202-09794
PL,MECH ASSY,VCO,MC12/B
RESSM,RO,0 OHM,0805
1.000
31.000
202-09795
202-09871
RESSM,RO,5%,1/10W,2.2K OHM
RESSM,RO,5%,1/10W,1K OHM
2.000
43.000
202-09872
RESSM,RO,5%,1/10W,33 OHM
31.000
202-09873
RESSM,RO,5%,1/10W,10K OHM
29.000
202-09874
202-09897
202-09899
202-10557
RESSM,RO,5%,1/10W,2.2M OHM
RESSM,RO,5%,1/10W,470 0HM
RESSM,RO,5%,1/10W,47 OHM
RESSM,RO,5%,1/10W,4.7K OHM
2.000
3.000
1.000
10.000
202-10558
RESSM,RO,5%,1/10W,47K OHM
6.000
202-10559
RESSM,RO,5%,1/10W,100 OHM
59.000
202-10569
202-10571
RESSM,RO,5%,1/10W,10 OHM
RESSM,RO,5%,1/10W,100K OHM
7.000
25.000
202-10585
202-10586
RESSM,RO,5%,1/4W,51 OHM
RESSM,RO,5%,1/4W,100 OHM
4.000
26.000
202-10598
202-10836
RESSM,RO,5%,1/10W,330 OHM
RESSM,RO,5%,1/4W,1K OHM
2.000
6.000
202-10890
RESSM,RO,5%,1/10W,220 OHM
18.000
202-10946
202-10948
202-10949
202-11041
202-11071
202-12836
202-14792
RESSM,RO,5%,1/10W,3.3K OHM
RESSM,RO,5%,1/10W,390 OHM
RESSM,RO,5%,1/10W,1.2K OHM
RESSM,RO,5%,1/10W,680 OHM
RESSM,RO,5%,1/4W,75 OHM
RESSM,RO,5%,1/10W,2.7K OHM
RESSM,RO,5%,1/10W,56 OHM
1.000
1.000
4.000
1.000
1.000
2.000
23.000
203-10424
203-10583
203-10896
203-11083
RESSM,RO,1%,1/10W,4.99K OHM
RESSM,RO,1%,1/10W,10.0K OHM
RESSM,RO,1%,1/10W,1.00K OHM
RESSM,RO,1%,1/10W,49.9K OHM
2.000
3.000
4.000
8.000
203-11737
RESSM,RO,1%,1/10W,5.76K OHM
8.000
203-11741
203-11993
203-11996
RESSM,RO,1%,1/10W,18.2K OHM
RESSM,RO,1%,1/10W,357 OHM
RESSM,RO,1%,1/10W,6.49K OHM
1.000
4.000
8.000
203-11997
203-12167
203-12363
203-12370
RESSM,RO,1%,1/10W,13.7K OHM
RESSM,RO,1%,1/10W,374 OHM
RESSM,RO,1%,1/10W,90.9 OHM
RESSM,RO,1%,1/10W,280 OHM
1.000
1.000
1.000
16.000
203-12371
RESSM,THIN,1%,1/10W,2.74K OHM
4.000
J31
R102,108,113,118,123
R181,183,185,186,192
R194,196,197,202,313
R314,320-324,343,362
R365,383-388,410
R179,434
R180,220-248,278
R280,284,290,294
R305,308,381,409
R414,431,432,437
R328-333,335-341
R356-361,363,364
R368-377
R3,5,7,9,11,13,15,17
R19,21,319,326,342
R378,392-401,408
R415,416,430,435
R252,254
R309,311,412
R204
R159-162,318,327
R379,380,433,436
R52,53,205,258
R259,438
R23-42,264,269-276
R279,281-283,285-289
R291-293,295-304,306
R307,352-355,417,418
R47-51,191,251
R128,129,132,133,136
R137,140,141,144,145
R148,149,152,153,156
R157,182,184,189,190
R193,195,200,201,440
R208,209,214,215
R2,4,6,8,10,12,14,16
R18,20,127,130,131
R134,135,138,139,142
R143,146,147,150,151
R154,155,158
R249,250
R166,167,170,171
R174,175
R43,44,382,389-391
R413,419-429
R407
R22
R255,256,261,316
R1
R277
R45,46
R163,164,260,265-268
R310,312,325,334
R344-351,366,367
R402,404
R262,263
R206,207,317
R168,172,176,439
R64,68,74,78,84
R88,94,98
R66,71,76,81,86
R91,96,101
R253
R55,57,59,60
R62,63,72,73
R82,83,92,93
R315
R178
R177
R65,67,69,70,75,77
R79,80,85,87,89,90
R95,97,99,100
R54,56,58,61
7-1
PART NO
DESCRIPTION
203-12719
203-12722
203-13131
203-13133
203-13134
203-13537
203-13638
203-15479
RESSM,THIN,1%,1/10W,2.00K OHM
RESSM,THIN,1%,1/10W,49.9K OHM
RESSM,RO,1%,1/10W,8.45K OHM
RESSM,THIN,1%,1/10W,1.15K OHM
RESSM,THIN,1%,1/10W,1.00K OHM
RESSM,THIN,1%,1/10W,5.62K OHM
RESSM,THIN,1%,1/10W,2.49K OHM
RESSM,THIN,1%,1/10W,1.21K OHM
4.000
1.000
3.000
4.000
4.000
2.000
2.000
16.000
240-09367
CAPSM,ELEC,10uF,25V,NONPOL,20%
16.000
240-09786
240-10758
240-11111
240-12330
CAP,ELEC,100uF,25V,RAD,LOW ESR
CAPSM,ELEC,1uF,50V,20%,5.5mmH
CAPSM,ELEC,47uF,6V,NONPOL,20%
CAPSM,ELEC,2.2uF,35V,20%
5.000
2.000
2.000
11.000
240-13216
240-13217
240-13642
CAPSM,ELEC,22uF,16V,20%
CAPSM,ELEC,47uF,16V,20%
CAP,ELEC,47uF,25V,RAD,NPOL,6D
3.000
4.000
10.000
240-13803
240-15668
CAP,ELEC,560uF,35V,RAD,LOW ESR
CAPSM,ELEC,330uF,6.3V,20%,105C
1.000
21.000
241-09798
CAPSM,TANT,10uF,10V,20%
6.000
241-11799
CAPSM,TANT,4.7uF,6.3V,20%
27.000
244-10423
CAP,MYL,.22uF,50V,RAD,5%,BOX
9.000
244-11589
245-09291
245-09876
245-10544
CAP,MYL,.068uF,63V,RAD,5%,BOX
CAPSM,CER,470pF,50V,COG,5%
CAPSM,CER,.01uF,50V,Z5U,20%
CAPSM,CER,220pF,50V,COG,5%
2.000
1.000
2.000
16.000
245-10561
245-10562
CAPSM,CER,100pF,50V,COG,5%
CAPSM,CER,150pF,50V,COG,10%
4.000
42.000
245-10588
245-11592
245-11594
245-11645
245-11949
CAPSM,CER,33pF,50V,COG,10%
CAPSM,CER,680pF,50V,COG,5%
CAPSM,CER,2200pF,50V,COG,5%
CAPSM,CER,.47UF,50V,Z5U,20%
CAPSM,CER,1500pF,50V,COG,5%
1.000
4.000
4.000
3.000
8.000
245-12485
CAPSM,CER,.1uF,25V,Z5U,20%
U
7-2
QTY
203.000
EFFECT.
INACT.
REFERENCE
R212,213,218,219
R257
R165,169,173
R103-106
R187,188,198,199
R210,216
R211,217
R107,109-112
R114-117,119-122
R124-126
C166,167,172,173
C178,179,184,185
C190,191,196,197
C202,203,208,209
C310,311,316,317,410
C302,385
C56,59
C12,15,18,21,24,27
C30,33,36,39,415
C222,224,226
C248,249,301,303
C11,14,17,20,23,26
C29,32,35,38
C402
C98-113,119,129
C139,149,159
C244,247,276,293
C329,403
C42,45,48,51,54,116
C121,123,126,131,133
C136,141,143,146,151
C153,156,161,163,250
C263,266,270,271
C336,341
C309,312,314,318,321
C323,325,327,409
C338,343
C414
C411,412
C69-71,73,77-79,81
C85-87,89,93-95,97
C278,279,282,283
C1-10,164,165,170
C171,176,177,182,183
C188,189,194,195,200
C201,206,207,212-215
C221,223,225,308,313
C315,319,320,322,324
C326,408
C228
C61-63,65
C114,115,267,274
C229-231
C124,125,134,135
C144,145,154,155
C13,16,19,22,25,28
C31,34,37,40,41,43
C44,46,47,49,50,52
C53,55,57,58,60,64
C66-68,72,74-76,80
C82-84,88,90-92,96
C117,118,120,122,127
C128,130,132,137,138
C140,142,147,148,150
C152,157,158,160,162
C168,169,174,175,180
C181,186,187,192,193
C198,199,204,205,210
C211,216-220,227
C232-243,245,246
C251-262,264,265,268
C269,272,273,275,277
C280,281,284-292
C294-300,304-307,328
C330,334,335,337,339
C340,342,344-384
C386-391,394-401
C404,413
PART NO
DESCRIPTION
270-00779
270-06671
270-09799
270-11545
FERRITE,BEAD
FERRITE CHOKE,2.5 TURN
FERRITESM,CHIP,600 OHM,1206
FERRITESM,CHIP,600 OHM,0805
14.000
4.000
6.000
9.000
270-13802
300-10509
300-10563
300-10564
300-11599
INDUCTORSM,24uH,20%,2.74A
DIODESM,1N914,SOT23
DIODESM,DUAL,SERIES,GP,SOT23
DIODESM,SCHOTTKY,LOW VF,SOT23
DIODESM,GP,1N4002,MELF
1.000
5.000
18.000
5.000
11.000
300-14286
310-10510
310-10565
310-10566
310-15016
330-09889
330-10523
330-12452
DIODESM,SCHOTTKY,1A,SMB
TRANSISTORSM,2N3904,SOT23
TRANSISTORSM,2N3906,SOT23
TRANSISTORSM,2N4401,SOT23
TRANSISTOR,MOSFET,30V,TO220
ICSM,DIGITAL,74ACT04,SOIC
IC,HEX INVERTER,74HCU04,SOP
ICSM,DIGITAL,74VHCT244,SOIC
2.000
2.000
3.000
3.000
1.000
1.000
1.000
10.000
330-13865
330-13876
330-14247
ICSM,DIGITAL,74VHC04,SOIC
ICSM,DIGITAL,74VHC273,SOIC
ICSM,DIGITAL,74VHCT245,SOIC
3.000
7.000
7.000
330-14534
330-15084
340-00742
340-09244
340-10502
340-10552
340-10567
340-11575
340-11597
340-12936
340-13137
340-14535
340-15492
340-15493
340-15740
345-13138
345-13140
346-10549
346-14583
350-13676
350-13854
350-13863
350-14540
355-13829
355-14761
365-13861
365-14683
390-13885
390-14544
410-11639
430-10419
430-10420
ICSM,DIGITAL,74VHCT541,SOIC
ICSM,DIGITAL,74LVC14A,SOIC
IC,LINEAR,7805 (LM 340 T-5)
ICSM,LINEAR,78LS05,5V REG,SOIC
ICSM,LIN,LF353,DUAL OPAMP,SOIC
ICSM,LIN,MC33078,DU OPAMP,SOIC
ICSM,LIN,MC34164,+5V MON,SOIC
ICSM,LIN,7805,+5V REG,TO263
ICSM,LIN,TL072,DUAL OPAMP,SOIC
ICSM,LIN,OPA2134,DU OP AMP,SO8
IC,LINEAR,LM2941CT,ADJ,TO-220
IC,LIN,1585A,3.3V REG,TO220
ICSM,LIN,PGA2310,VOL,15V,SOIC
ICSM,LIN,PGA2311,VOL,5V,SOIC
ICSM,LIN,LM56C,THERMO,LP,SOIC
ICSM,INTER,CS8414,RCVR,SOIC
ICSM,INTER,RS232 XCVR,+5V,SOIC
ICSM,SS SWITCH,DG408,SOIC
ICSM,SS SW,ADG451QUAD,1P1T,SOI
ICSM,CPLD,MC12,MEM,V1.00
ICSM,FPGA,XCS05XL-4,10X10,VQFP
ICSM,SRAM,32KX8,70NS,SOIC,20uA
ICSM,FPGA,XCS20XL-4,20X20,PQFP
ICSM,ADC,AKM5383,24b,96kHz,SOP
ICSM,DAC,AK4395,24BIT,VSOP
ICSM,uPROC,Z8S180,33MHz,PQFP
ICSM,uPROC,PIC16C54,MC12,V1.00
CRYSTAL OSCSM,29.491MHz,TRI
CRYSTAL OSCSM,24.576MHz,TRI,3V
RELAY,2P2T,DIP,5V,HI SENS
LEDSM,INNER LENS,RED
LEDSM,INNER LENS,YEL
1.000
1.000
1.000
1.000
9.000
6.000
1.000
1.000
9.000
5.000
3.000
1.000
5.000
1.000
1.000
2.000
1.000
4.000
7.000
1.000
1.000
1.000
1.000
1.000
5.000
1.000
1.000
1.000
1.000
5.000
3.000
7.000
430-10421
LEDSM,INNER LENS,GRN
8.000
460-04598
500-03620
500-13643
510-03922
510-10546
510-10745
510-12319
510-13146
510-13149
510-13538
510-13877
510-13887
510-14079
510-14080
510-14890
640-01701
704-06165
704-14452
710-15250
BATTERY,LITH,3V@160mAH,HORIZ
CONN,EURO,C,ROW a+c,FEM
CONN,EURO,C,48P,abc,RECP,VERT
CONN,POST,100X025,HDR,6MCG
CONN,POST,079,HDR,4MC
CONN,POST,100X025,HDR,2MC,POL
CONN,D-SUB,9FCX2,STACKED,PCRA
CONN,HDR,.200,4MC,PCRA
CONN,RCA,PCRA,1FCGX2V,WH/RED,G
CONN,RCA,PCRA,1FCG,BLK,GND
CONN,POST,.100,HDR,2X5MCG,LP
CONN,POST,.100,HDR,2X13MCG,POL
CONN,POST,156X045,HDR,4MC,LOK
CONN,POST,156X045,HDR,6MC,LOK
CONN,POST,.100,HDR,2X17MCG,LK
SCRW,4-40X1/4,PNH,PH,ZN
HEATSINK,TO220,.75X.5X.5,TAB
HEATSINK,TO220,MTTAB,NUT,1.45H
PC BD,MAIN,MC8
U
QTY
1.000
4.000
1.000
1.000
1.000
2.000
1.000
1.000
13.000
1.000
1.000
1.000
2.000
1.000
2.000
2.000
3.000
2.000
1.000
EFFECT.
INACT.
REFERENCE
FB1-10,20-22,24
FB29-32
FB11-15,23
FB16-19,25,26,28
FB33,34
L1
D29,33,42,46,60
D3-20
D28,30-32,61
D1,2,24-27,36-38
D47,48
D34,35
Q7,9
Q4,6,8
Q1,2,5
Q3
U55
U57
U62,67,68,70,71
U76,77,81,82,91
U44,58,88
U48-52,93,94
U61,69,74,75,80
U95,97
U92
U53
U63
U54
02/19/03
U21-28,56
U30,34,39,43,46,47
U98
U60
02/19/03 U21-28,56
U11-15
U36-38
U96
U1-5
U35
U66
U64,65
U29
U32,33,41,42
U6-10,31,40
U83
U72
U90
U87
U45
U16-20
U84
U89
U85
U73
RY1-5
D23,43,45
D21,49,51,52,54
D56,58
D22,41,44,50,53
D55,57,59
BAT1
J34,36-38
J48
J35
J43
J18,42
J14
J15
J1-13
J17
J19
J46
J29,45
J32
J28,30
H/S 704-14452
U36-38
U63,96
01/17/03 PICK REV 4 PC BOARD
7-3
PART NO
DESCRIPTION
QTY
EFFECT.
710-15250
PC BD,MAIN,MC8
1.000
01/17/03
U
INACT.
REFERENCE
PICK REV 5 PC BOARD
Memory Board Assembly
202-09873
245-12485
RESSM,RO,5%,1/10W,10K OHM
CAPSM,CER,.1uF,25V,Z5U,20%
1.000
3.000
350-15741
ICSM,FLASH,16M,MC8,V1.00
1.000
350-15742
500-13644
520-04999
710-15290
IC,ROM,27C020,MC8,MEM,V1.00
CONN,EURO,C,48P,abc,PLUG,RA
IC SCKT,32 PIN,MACH,TIN
PC BD,MEM,MC8
1.000
1.000
1.000
1.000
R1
C5; C1,2 (IF U1 POP);
C3,4 (IF U2 POP)
U1 (TSOP pkg);
(or U2 for SOIC pkg)
U3
J1
U3
PICK REV 0 PC BOARD
Video Board Assembly
202-09795
202-09871
RESSM,RO,5%,1/10W,2.2K OHM
RESSM,RO,5%,1/10W,1K OHM
4.000
16.000
202-09873
RESSM,RO,5%,1/10W,10K OHM
9.000
202-09874
202-10426
RESSM,RO,5%,1/10W,2.2M OHM
RESSM,RO,5%,1/10W,15K OHM
1.000
13.000
202-10558
202-10571
RESSM,RO,5%,1/10W,47K OHM
RESSM,RO,5%,1/10W,100K OHM
4.000
12.000
202-10573
RESSM,RO,5%,1/10W,470K OHM
11.000
202-10943
202-10944
202-10945
202-10947
202-10948
202-11042
202-11071
202-12369
202-13579
RESSM,RO,5%,1/10W,22K OHM
RESSM,RO,5%,1/10W,33K OHM
RESSM,RO,5%,1/10W,1.5K OHM
RESSM,RO,5%,1/10W,680K OHM
RESSM,RO,5%,1/10W,390 OHM
RESSM,RO,5%,1/10W,6.8K OHM
RESSM,RO,5%,1/4W,75 OHM
RESSM,RO,5%,1/10W,36K OHM
RESSM,RO,5%,1/10W,22 OHM
3.000
1.000
1.000
1.000
1.000
2.000
4.000
4.000
10.000
203-10560
RESSM,RO,1%,1/10W,75.0 OHM
19.000
203-10583
203-10837
203-10840
RESSM,RO,1%,1/10W,10.0K OHM
RESSM,RO,1%,1/10W,475 OHM
RESSM,RO,1%,1/10W,750 OHM
4.000
5.000
14.000
203-10895
203-11080
RESSM,RO,1%,1/10W,681 OHM
RESSM,RO,1%,1/10W,1.15K OHM
2.000
8.000
203-11082
203-11723
203-11726
203-11730
203-12198
203-12298
203-12838
203-12897
203-14789
203-14790
240-09786
240-10758
240-11111
RESSM,RO,1%,1/10W,15.0K OHM
RESSM,RO,1%,1/10W,4.75K OHM
RESSM,RO,1%,1/10W,301 OHM
RESSM,RO,1%,1/10W,1.37K OHM
RESSM,RO,1%,1/10W,2.15K OHM
RESSM,RO,1%,1/10W,30.1K OHM
RESSM,RO,1%,1/10W,29.4K OHM
RESSM,RO,1%,1/10W,976 OHM
RESSM,RO,1%,1/10W,61.9K OHM
RESSM,RO,1%,1/10W,11.8K OHM
CAP,ELEC,100uF,25V,RAD,LOW ESR
CAPSM,ELEC,1uF,50V,20%,5.5mmH
CAPSM,ELEC,47uF,6V,NONPOL,20%
240-11827
CAPSM,ELEC,10uF,16V,20%
8.000
240-13217
245-09876
245-09895
245-10416
245-10544
245-10561
245-10588
245-10972
245-10975
CAPSM,ELEC,47uF,16V,20%
CAPSM,CER,.01uF,50V,Z5U,20%
CAPSM,CER,10pF,50V,COG,10%
CAPSM,CER,1000pF,50V,COG,5%
CAPSM,CER,220pF,50V,COG,5%
CAPSM,CER,100pF,50V,COG,5%
CAPSM,CER,33pF,50V,COG,10%
CAPSM,CER,.068uF,50V,X7R,20%
CAPSM,CER,3300pF,50V,X7R,10%
3.000
5.000
1.000
3.000
2.000
2.000
4.000
1.000
1.000
7-4
1.000
5.000
2.000
2.000
5.000
1.000
1.000
4.000
1.000
1.000
3.000
1.000
10.000
R88,91,94,97
R1,15,43-45,50,51
R58,59,66,67,74,75
R82,83,131
R3,7,10,12,16,117
R133,134,172
R2
R18,35-42,106,150
R152,153
R89,90,95,96
R11,48,56,64,72,80
R112,116,119,140
R161,166
R53,61,69,77,85
R118,167-171
R6,13,14
R132
R5
R4
R8
R98,102
R86,87,92,93
R109,114,158,164
R49,52,57,60,65
R68,73,76,81,84
R27,34,46,47,54,55
R62,63,70,71,78,79
R99,100,105,147,148
R151,155
R19,24,25,32
R9,101,121,146,149
R29,31,104,107,110
R111,113,115,138
R143,157,160,163,165
R135,141
R103,108,137,139
R144,145,159,162
R20
R120,122,125,128,130
R154,156
R26,33
R123,124,126,127,129
R17
R21
R28,30,136,142
R22
R23
C87-89
C6
C29,33,37,41,45
C140-144
C17,83-85,99,106
C125,139
C66,86,101
C50,51,55,56,100
C109
C14,15,137
C10,12
C8,9
C48,49,53,54
C7
C11
PART NO
DESCRIPTION
245-10976
245-10977
245-11625
245-12070
245-12485
CAPSM,CER,47pF,50V,COG,5%
CAPSM,CER,330pF,50V,COG,5%
CAPSM,CER,33pF,50V,COG,5%
CAPSM,CER,15pF,50V,COG,10%
CAPSM,CER,.1uF,25V,Z5U,20%
3.000
1.000
1.000
1.000
90.000
245-12524
245-14762
245-14763
245-14764
270-00779
270-11289
300-10509
300-10563
300-11599
310-10510
310-10565
310-10566
330-09797
330-10505
330-10506
330-10523
330-10524
330-15667
340-10502
340-11495
340-13856
340-14791
340-15683
345-10503
346-10507
346-10508
350-15672
365-13288
390-10516
390-13857
390-13858
410-11639
510-13128
510-13148
510-13840
510-14079
510-15471
510-15472
510-15473
680-15469
710-15260
CAPSM,CER,68pF,50V,COG,5%
CAPSM,CER,6.8pF,50V,COG,5%
CAPSM,CER,12pF,50V,COG,5%
CAPSM,CER,82pF,50V,COG,5%
FERRITE,BEAD
INDUCTORSM,10uH,10%
DIODESM,1N914,SOT23
DIODESM,DUAL,SERIES,GP,SOT23
DIODESM,GP,1N4002,MELF
TRANSISTORSM,2N3904,SOT23
TRANSISTORSM,2N3906,SOT23
TRANSISTORSM,2N4401,SOT23
ICSM,DIGITAL,74AC04,SOIC
ICSM,DIGITAL,74HC02,SOIC
ICSM,DIGITAL,74HC595,SOIC
IC,HEX INVERTER,74HCU04,SOP
ICSM,DIGITAL,74HC08,SOIC
ICSM,DIGITAL,74HCT594,SOIC
ICSM,LIN,LF353,DUAL OPAMP,SOIC
ICSM,LIN,LT1229,VID OPAMP,SOIC
ICSM,LIN,EL4421C,VIDAMP,W/MUX
ICSM,LIN,EL4422C,VIDAMP,W/MUX
ICSM,LIN,AD8072,VIDAMPX2,SOIC
ICSM,INTER,NJM2229,SYNSEP,SOIC
ISCM,SS SWITCH,74HC4051,SOIC
ICSM,SS SWITCH,74HC4053,SOIC
ICSM,FLASH,128KX8,5V,90NS,PLCC
ICSM,uPROC,MB90092,OSDC,PQFP
RESONATOR,CER,503KHz
CRYSTAL,OSCSM,14.31818MHz,TRI
CRYSTAL,OSCSM,17.73448MHz,TRI
RELAY,2P2T,DIP,5V,HI SENS
CONN,MINIDIN,4FC,PCRA,GND
CONN,RCA,PCRA,1FCGX2V,BLK,GND
CONN,OPTO,PCRA,TORX173,6Mbps
CONN,POST,156X045,HDR,4MC,LOK
CONN,RCA,PCRA,1FCGX2V,GRN,GND
CONN,RCA,PCRA,1FCGX2V,RED,GND
CONN,RCA,PCRA,1FCGX2V,BLU,GND
CABLE,100,PLUG/SCKT,2X17C,2"L
PC BD,VIDEO,MC8
1.000
1.000
4.000
1.000
4.000
1.000
1.000
5.000
3.000
11.000
1.000
3.000
1.000
1.000
3.000
2.000
2.000
3.000
2.000
2.000
3.000
1.000
4.000
1.000
7.000
2.000
1.000
1.000
1.000
1.000
1.000
6.000
7.000
2.000
2.000
1.000
2.000
2.000
2.000
1.000
1.000
C20,25,115
C18
C122
C108
C1-5,13,16,21-23
C26-28,30-32,34-36
C38-40,42-44,46,47
C52,57-65,67-82
C90-98,102-105,107
C110-113,117-119,124
C126-132,134-136,138
C145-148
C123
C120
C19,24,114,116
C121
FB1-4
L1
D2
D1,6-9
D3-5
Q1-10,15
Q14
Q11-13
U5
U4
U21,22,30
U7,8
U12,20
U36-38
U2,23
U24,29
U13,26,27
U28
U6,14,15,25
U3
U9-11,16-19
U1,35
U31
U32
Y1
U34
U33
RY1-6
J1,2,9-13
J14,15
CP1,2
J17
J5,8
J4,7
J3,6
J19
PICK REV 3 PC BOARD
5.000
5.000
5.000
2.000
12.000
5.000
5.000
2.000
1.000
1.000
R1,4,7,10,13
R2,5,8,11,14
R3,6,9,12,15
C13,14
C1-12
Q1-5
J1-5
CP1,2
J6
PICK REV 2 PC BOARD
2.000
1.000
1.000
J1,2
J3
PICK REV 1 PC BOARD
U
QTY
EFFECT.
INACT.
REFERENCE
Video RCA Board Assembly
202-09871
202-13579
203-10560
240-11827
245-12485
310-10510
510-13147
510-13840
680-15475
710-15270
RESSM,RO,5%,1/10W,1K OHM
RESSM,RO,5%,1/10W,22 OHM
RESSM,RO,1%,1/10W,75.0 OHM
CAPSM,ELEC,10uF,16V,20%
CAPSM,CER,.1uF,25V,Z5U,20%
TRANSISTORSM,2N3904,SOT23
CONN,RCA,PCRA,1FCG,YEL,GND
CONN,OPTO,PCRA,TORX173,6Mbps
CABLE,FFC,20CX.1,CRMP,ST/RA,3"
PC BD,VIDEO RCA,MC8
Video Out Board Assembly
510-13147
680-15474
710-15330
CONN,RCA,PCRA,1FCG,YEL,GND
CABLE,FFC,4CX.1,CRMP,ST/RA,3"
PC BD,VIDEO OUT,MC8
DSP Board Assembly
202-09794
202-09872
202-09873
RESSM,RO,0 OHM,0805
RESSM,RO,5%,1/10W,33 OHM
RESSM,RO,5%,1/10W,10K OHM
13.000
12.000
2.000
R4,18,19,21-24,43-48
R6-17
R3,36
7-5
PART NO
DESCRIPTION
202-10557
202-11073
202-11496
245-12485
270-11545
310-10510
330-13866
330-13882
350-12456
350-13854
350-13879
365-13860
390-13886
430-10419
430-10421
500-03619
710-15300
RESSM,RO,5%,1/10W,4.7K OHM
RESSM,RO,5%,1/4W,270 OHM
RESSM,RO,0 OHM,1206
CAPSM,CER,.1uF,25V,Z5U,20%
FERRITESM,CHIP,600 OHM,0805
TRANSISTORSM,2N3904,SOT23
ICSM,DIGITAL,74VHC244,SOIC
ICSM,DIGITAL,74LCX14,SOIC
ICSM,SRAM,128KX8,12NS,3.3V,SOJ
ICSM,FPGA,XCS05XL-4,10X10,VQFP
ICSM,SDRAM,512KX32X4,3.3V,TSOP
ICSM,uPROC,ADSP21065,60MHz,PQF
CRYSTAL OSCSM,30.0MHz,TRI,3.3V
LEDSM,INNER LENS,RED
LEDSM,INNER LENS,GRN
CONN,EURO,R,96P,a+c,PLUG,VERT
PC BD,DSP,MC8
U
QTY
EFFECT.
INACT.
REFERENCE
2.000
9.000
7.000
96.000
4.000
1.000
1.000
1.000
8.000
1.000
2.000
4.000
1.000
4.000
5.000
1.000
1.000
R39,41
R25-32,40
R20,33-35,37,38,42
C3-98
FB2-5
Q1
U8
U3
U9-12,17-20
U7
U4,14
U5,6,15,16
U2
D3,4,7,8
D1,2,5,6,9
J1
PICK REV 2 PC BOARD
1.000
2.000
2.000
1.000
1.000
1.000
4.000
2.000
1.000
1.000
24.000
1.000
1.000
1.000
1.000
1.000
1.000
1.000
1.000
1.000
1.000
1.000
1.000
1.000
1.000
R5
R2,3
R7,8
R1
R6
R4
RP1,2,5,6
RP3,4
C27
C12
C1-11,13,14,17-26,28
C15
C16
FB1
D3
D1
Q1
U6
U4
U1
U2
U3
D2
J1
PICK REV 2 PC BOARD
8.000
2.000
2.000
9.000
8.000
1.000
6.000
3.000
1.000
4.000
1.000
1.000
8.000
2.000
9.000
21.000
2.000
.000
1.000
R17-23,29
R24,25
R26,27
R1-4,9-12,28
R5-8,13-16
C1
C2-7
D17-19
Q1
U2-5
U1
U6
D5-8,13-16
D20,21
D1-4,9-12,22
SW1-21
J1,2
J3
PICK REV 1 PC BOARD
1.000
1.000
1.000
1.000
D1
SW1
J1
PICK REV 0 PC BOARD
Decoder Board Assembly
202-09872
202-09873
202-10557
202-10599
202-11073
202-11496
205-14586
205-15737
241-09798
241-11799
245-12485
245-12524
245-13810
270-11545
300-11599
300-14286
310-10510
340-13883
350-13854
350-15491
365-15490
390-12076
430-10421
500-04557
710-15310
RESSM,RO,5%,1/10W,33 OHM
RESSM,RO,5%,1/10W,10K OHM
RESSM,RO,5%,1/10W,4.7K OHM
RESSM,RO,5%,1/10W,3K OHM
RESSM,RO,5%,1/4W,270 OHM
RESSM,RO,0 OHM,1206
RESSM,NET,5%,ISOL,10KX4
RESSM,NET,5%,ISOL,3.3KX4
CAPSM,TANT,10uF,10V,20%
CAPSM,TANT,4.7uF,6.3V,20%
CAPSM,CER,.1uF,25V,Z5U,20%
CAPSM,CER,68pF,50V,COG,5%
CAPSM,CER,1200pF,50V,COG,5%,08
FERRITESM,CHIP,600 OHM,0805
DIODESM,GP,1N4002,MELF
DIODESM,SCHOTTKY,1A,SMB
TRANSISTORSM,2N3904,SOT23
ICSM,LIN,LM2937,2.5V REG,TO263
ICSM,FPGA,XCS05XL-4,10X10,VQFP
ICSM,FLASH,512KX8,3V,200NS,TSO
ICSM,uPROC,DSP,CS49400,LQFP
CRYSTAL OSCSM,12.288MHz
LEDSM,INNER LENS,GRN
CONN,EURO,C,ROW a+c,MALE,RA
PC BD,DECODER,MC8/MC12
Switch/LED Board Assembly
202-09795
202-10597
202-10599
202-10945
202-10948
240-09786
245-12485
300-10509
310-10510
330-10372
330-10537
330-14244
430-13639
430-13888
430-14527
453-13899
510-13145
680-14083
710-15280
RESSM,RO,5%,1/10W,2.2K OHM
RESSM,RO,5%,1/10W,180 OHM
RESSM,RO,5%,1/10W,3K OHM
RESSM,RO,5%,1/10W,1.5K OHM
RESSM,RO,5%,1/10W,390 OHM
CAP,ELEC,100uF,25V,RAD,LOW ESR
CAPSM,CER,.1uF,25V,Z5U,20%
DIODESM,1N914,SOT23
TRANSISTORSM,2N3904,SOT23
ICSM,DIGITAL,74HC574,SOIC
ICSM,DIGITAL,74HC541,SOIC
ICSM,DIGITAL,74VHCT138,SOIC
LEDSM,BLU,30MCB,AX,ZBEND,2.5MM
LEDSM,RED,60MCD,AX,ZBEND,2.5MM
LEDSM,SYEL,250MCD,AX,ZBEND,2.5
SWSM,PBM,1P1T,6.2MMSQ,200GF
CONN,POST,.100,HDR,2X7MCG,LP
CABLE,100,PLUG/SCKT,2X13C,2"L
PC BD,SW/LED,MC8
Standby Board Assembly
430-13888
453-13899
510-10546
710-15320
7-6
LEDSM,RED,60MCD,AX,ZBEND,2.5MM
SWSM,PBM,1P1T,6.2MMSQ,200GF
CONN,POST,079,HDR,4MC
PC BD,STANDBY,MC8
PART NO
U
DESCRIPTION
QTY
EFFECT.
INACT.
REFERENCE
XLR Board Assembly
202-10585
RESSM,RO,5%,1/4W,51 OHM
20.000
202-10943
RESSM,RO,5%,1/10W,22K OHM
20.000
202-10948
203-12720
RESSM,RO,5%,1/10W,390 OHM
RESSM,THIN,1%,1/10W,2.94K OHM
2.000
20.000
203-13132
RESSM,THIN,1%,1/10W,3.01K OHM
40.000
240-13642
CAP,ELEC,47uF,25V,RAD,NPOL,6D
20.000
240-13803
245-10562
245-10587
CAP,ELEC,560uF,35V,RAD,LOW ESR
CAPSM,CER,150pF,50V,COG,10%
CAPSM,CER,18pF,50V,COG,10%
2.000
20.000
30.000
245-12485
CAPSM,CER,.1uF,25V,Z5U,20%
20.000
270-00779
270-06671
300-11599
310-10566
340-12936
410-11639
510-10881
510-14890
620-12428
710-15340
FERRITE,BEAD
FERRITE CHOKE,2.5 TURN
DIODESM,GP,1N4002,MELF
TRANSISTORSM,2N4401,SOT23
ICSM,LIN,OPA2134,DU OP AMP,SO8
RELAY,2P2T,DIP,5V,HI SENS
CONN,XLR,3MC,PCRA,SMALL
CONN,POST,.100,HDR,2X17MCG,LK
LUG,#4,INT STAR,XLR GND
PC BD,XLR,MC8B
20.000
2.000
2.000
2.000
10.000
10.000
10.000
1.000
10.000
1.000
R7,10,17,20,27
R30,37,40,47,50
R57,60,67,70,77
R80,87,90,97,100
R3,4,13,14,23,24
R33,34,43,44,53
R54,63,64,73,74
R83,84,93,94
R1,2
R5,6,15,16,25,26
R35,36,45,46,55
R56,65,66,75,76
R85,86,95,96
R8,9,11,12,18,19,21
R22,28,29,31,32,38
R39,41,42,48,49,51
R52,58,59,61,62,68
R69,71,72,78,79,81
R82,88,89,91,92,98
R99,101,102
C21,22,28,29,35,36
C42,43,49,50,56,57
C63,64,70,71,77,78
C84,85
C91,92
C1-20
C24-26,31-33,38-40
C45-47,52-54,59-61
C66-68,73-75,80-82
C87-89
C23,27,30,34,37
C41,44,48,51,55
C58,62,65,69,72
C76,79,83,86,90
FB1-20
FB21,22
D1,2
Q1,2
U1-10
RY1-10
J1-10
J11
J1-10
PICK REV 0 PC BOARD
IR/Encoder Board Assembly
202-00528
202-00530
202-00531
245-03609
345-14780
430-10594
430-14487
RES,CF,5%,1/4W,820 OHM
RES,CF,5%,1/4W,1.2K OHM
RES,CF,5%,1/4W,1.5K OHM
CAP,CER,.1uF,50V,Z5U,AX,80/20%
IC,INTER,GP1U28,38kHz,IR DET
LED,T1-3/4,IR
LED,T1,BLU,430NM
1.000
1.000
1.000
2.000
1.000
1.000
1.000
430-14787
LED,T1,RED,700NM
1.000
430-14788
LED,T1,YEL,585NM
1.000
452-13640
630-14778
680-14082
SW,RTY,ENC,24POS,INC B,25L,VRT
SPCR,LED,T1,.375"H
CABLE,100,PLUG/SCKT,2X7C,3"L
1.000
3.000
1.000
710-13690
PC BD,IR/ENC,MC12
1.000
R1
R2
R3
C1,2
U1B
D1
SYSTEM ON
D4
OVERLOAD
D2
IR ACK
D3
SW1
D2-4
IR/ENC BD
(J1) TO SW/LED BD
PICK REV 2 PC BOARD
1.000
1.000
1.000
1.000
4.000
1.000
1.000
1.000
R1
C3
C1,2,4,5
FB1
L1
D1
VCO Assembly
700-14838
700-14839
202-09899
245-09895
245-12485
270-11545
270-14359
300-13881
HOUSING,VCO,MC12
COVER,VCO,MC12
RESSM,RO,5%,1/10W,47 OHM
CAPSM,CER,10pF,50V,COG,10%
CAPSM,CER,.1uF,25V,Z5U,20%
FERRITESM,CHIP,600 OHM,0805
COILSM,VAR,1uH,5%,5.6X6.2X6MM
DIODESM,VARACTOR,BB132
7-7
PART NO
DESCRIPTION
QTY
340-14528
ICSM,LIN,MC100EL1648,VCO,SOIC
1.000
U1
1.000
1.000
1.000
U1
J1
PICK REV 0 PC BOARD
1.000
PICK REV 0 PC BOARD
DSUB JSCKT
REAR PANEL
DCONN TO R.PANEL
U
EFFECT.
INACT.
REFERENCE
– or –
340-16132 ICSM,LIN,MC100EL1648,VCO,TSSOP
510-14836
CONN,POST,100X025,HDR,5MC,RA
710-14840
PC BD,VCO,MC12
– or –
710-16130 PC BD,VCO,MCLK
Chassis Assembly
Note: * items are on MC-8 only; ^ items are on MC-8B only
120-09621
490-13144
527-12974
540-02472^
541-15458*
635-13637
635-14779
ADHESIVE,THRDLOCK,GP
CONN,PLUG,.200,4FC,RA,12-30G
CONN,DSUB,JSCKT,4-40,.187X.25
PLUG,HOLE,3/8",BLK
FOOT,1.97X.43H,ABS,BLK
SPCR,M3X34MM,M/F,6MM HEX
SPCR,M3X14MM,6MM HEX
0.003
1.000
4.000
4.000
4.000
2.000
2.000
635-15468
640-10467
640-10467
SPCR,M3X16MM,M/F,6MM HEX
SCRW,M3X6MM,FH,PH,BZ
SCRW,M3X6MM,FH,PH,BZ
4.000
2.000
2.000
640-10498
640-10498
640-10498
640-10498
640-10498
640-10498
640-10498
SCRW,M3X6MM,PNH,PH,BZ
SCRW,M3X6MM,PNH,PH,BZ
SCRW,M3X6MM,PNH,PH,BZ
SCRW,M3X6MM,PNH,PH,BZ
SCRW,M3X6MM,PNH,PH,BZ
SCRW,M3X6MM,PNH,PH,BZ
SCRW,M3X6MM,PNH,PH,BZ
2.000
4.000
3.000
4.000
5.000
2.000
2.000
640-10498
640-10499^
640-13645
640-15476
640-15476^
640-15476^
640-15477*
641-01703*
641-10989
641-11466
641-14898^
680-14494^
680-14539
680-15470
SCRW,M3X6MM,PNH,PH,BZ
SCRW,M3X8MM,PNH,PH,BZ
SCRW,M4X10MM,FH,SCKT,BZ
SCRW,M4X8MM,PNH,PH,ZN
SCRW,M4X8MM,PNH,PH,ZN
SCRW,M4X8MM,PNH,PH,ZN
SCRW,M4X12MM,PNH,PH,ZN
SCRW,TAP,AB,4X1/4,PNH,PH,ZN
SCRW,TAP,AB,4X3/8,PNH,PH,BZ
SCRW,TAP,#4X3/8,PNH,PH,BZ,TRI
SCRW,TAP,#4X1/4,PNH,PH,BZ,TRI
CABLE,.10,SCKTX2-180,2X17C,6"
CABLE,HSG/HSG,4C,4"
CABLE ASSY,3.5mmJACK/HSG,2C,3"
4.000
2.000
13.000
2.000
3.000
4.000
4.000
2.000
6.000
14.000
20.000
1.000
1.000
1.000
700-15447
700-15448
700-15450^
702-15444
702-14454^
702-14495*
702-15457
720-13632^
720-15256
740-14888
CHASSIS,2U,MC8
COVER,2U,MC8
CHASSIS,1U,MC8B
PANEL,REAR,MC8
PANEL,FRONT,1U,MC12B
PANEL,ACCESS,MC12
PANEL,OPTION,BLANK,MC8
PAD,FOOT,1.438DIA
TAPE,COPPER,1/2"W,EMBOSSED,PSA
LABEL,LIC/PAT/WARN,MC12
1.000
1.000
1.000
1.000
1.000
1.000
2.000
4.000
16.500
1.000
7-8
CHASSIS
VIDEO BD TO MAIN BD
MEM BD TO CHASSIS;
DECODER TO CHASSIS
DSP BD TO MAIN BD
PS SPT TO CHASSIS
MEM BD TO CHASSIS;
DECODER TO CHASSIS
PS SPT TO CHASSIS
MAIN BD TO CHASSIS
F.PANEL TO CHASSIS
DSP BD TO MAIN BD
VIDEO ASSY TO R.PNL
VIDEO ASSY TO MAINBD
MEM BD TO CHASSIS;
DECODER TO CHASSIS
OPT PANELS TO REAR
XLR BD TO 1U CHASSIS
COVER TO CHASSIS
F.PANEL TO CHASSIS
1U FP TO 1U CHASSIS
1U CHAS TO 2U CHAS
FEET TO CHASSIS
ACCESS PANEL TO CHAS
R.PANEL TO CHASSIS
RCA CONN TO R.PANEL
XLR BD TO 1U CHASSIS
XLR (J11) TO MN (J28)
MN(J29) TO VID(J17)
IR CONN TO MAIN BD
(J18); DRESS NUT
SUPPLIED W/JACK
CHASSIS BOTTOM
REAR PANEL
1U CHASSIS BOTTOM
APPLY TO R.PNL TOP
MC8: 2U CHASSIS
BOTTOM; MC8B: 1U
CHASSIS BOTTOM
PART NO
U
DESCRIPTION
QTY
EFFECT.
INACT.
REFERENCE
Mic Board Assembly
202-09795
RESSM,RO,5%,1/10W,2.2K OHM
8.00
202-09871
202-10426
202-10598
202-11073
203-11077
203-11980
RESSM,RO,5%,1/10W,1K OHM
RESSM,RO,5%,1/10W,15K OHM
RESSM,RO,5%,1/10W,330 OHM
RESSM,RO,5%,1/4W,270 OHM
RESSM,RO,1%,1/10W,237 OHM
RESSM,THIN,1%,1/10W,10.0K OHM
1.00
4.00
4.00
4.00
1.00
16.00
203-12481
203-12719
203-12723
240-09367
240-11827
RESSM,RO,1%,1/10W,1.50K OHM
RESSM,THIN,1%,1/10W,2.00K OHM
RESSM,THIN,1%,1/10W,102 OHM
CAPSM,ELEC,10uF,25V,NONPOL,20%
CAPSM,ELEC,10uF,16V,20%
1.00
4.00
4.00
4.00
12.00
240-13216
245-10562
CAPSM,ELEC,22uF,16V,20%
CAPSM,CER,150pF,50V,COG,10%
45-10976
245-12485
CAPSM,CER,47pF,50V,COG,5%
CAPSM,CER,.1uF,25V,Z5U,20%
270-11545
300-11599
340-10552
340-11559
346-14583
500-04557
510-10595
640-10498
680-15743
701-15738
701-15739
710-15380
740-11287
FERRITESM,CHIP,600 OHM,0805
DIODESM,GP,1N4002,MELF
ICSM,LIN,MC33078,DU OPAMP,SOIC
ICSM,LIN,LM317M,+ADJ REG,DPAK
ICSM,SS SW,ADG451QUAD,1P1T,SOI
CONN,EURO,C,ROW a+c,MALE,RA
PHONE JACK,3.5MM,PCRA,3C,STER
SCRW,M3X6MM,PNH,PH,BZ
CABLE,100,PLUG/SCKT,2X5C,2.5"L
BRACKET,MTG,MIC/DSP BD,MC8
BRACKET,MTG,OPT BD
PC BD,MIC/DSP,MC8
LABEL,S/N,PCB,PRIN
1.00
8.00
12.00
13.00
9.00
2.00
4.00
1.00
1.00
1.00
4.00
4.00
1.00
1.00
1.00
1.00
1.00
R41,50,52
R14,16,28,30,39
R17
R27,38,49,60
R15,29,40,51
R26,37,48,59
R20
R18,19,21,22,31-3
R42-45,53-56
R23
R25,36,47,58
R24,35,46,57
C8,14,20,28
C11-13,17-19,23-2
C31-33
C7
C34,35,41,42,46,4
C51,52
C38-40,43-45,48-5
C9,10,15,16,21,22
C30,36,37,56-58
FB3-10,13
D9,10
U18-20,26
U12
U25
J3
J5-8
2 PER BRKT
J4
PHONE JACKS
PICK REV 1 PC BOARD
Power Supply Assembly
454-13850
490-11462
530-02488
SW,ROCKER,2P1T,5A/80A@250,TV5
CONN,AC,3MC,SNAP,04TH,IEC,10A
TIE,CABLE,NYL,.14"X5-5/8"
1.000
1.000
2.000
640-10467
640-10498
640-12534
643-10492
644-01737
644-02716
644-10494
680-11461
680-14536
680-14537
680-15465
SCRW,M3X6MM,FH,PH,BZ
SCRW,M3X6MM,PNH,PH,BZ
SCRW,M3X20MM,PNH,PH,BZ
NUT,M4X.7MM,KEP,ZN
WSHR,LOCK,SPLIT,#4
WSHR,FL,#4CLX.312ODX.03THK
WSHR,FL,M4CLX9ODX.8MM THK
WIRE,18G,G/Y,2.5",187QDC/LUG#8
CABLE,PWR,.187/.110QDC,SLV,4.5
CABLE,PWR,HSG/.110QDC,2C,5"
CABLE,HSG/HSG,8C,SLV,16/17"
2.000
2.000
4.000
1.000
2.000
2.000
1.000
1.000
1.000
1.000
1.000
700-15449
720-14852
740-08556
740-15745
750-15466
SUPPORT,PS,MC8
GASKET,FAN,1.5D/1.7SQ,BLK
LABEL,GROUND SYMBOL,0.5"DIA
LABEL,FUSE,CAUTION,2.5A/250V
PWR SUP,+-5V/+-15V,60W
1.000
1.000
1.000
1.000
1.000
FAN TO PS SPT
PS SUPPORT
PS SUPPORT
1.000
2.000
1.000
CRIMP CONN TO WIRES
FERRITE SLEEVE TO
PS SPT
PWR SW TO PS SPT
PWR SUP TO PS SPT
FAN TO PS SPT
CHASSIS GND
PWR SUP TO PS SPT
PWR SUP TO PS SPT
CHASSIS GND
AC CONN TO CHAS GND
AC CONN TO PWR SW
PWR SW TO PWR SUP
PWR SUP TO
MAIN BD (J32 & J45)
Fan Assembly
410-14851
525-12536
527-12537
FAN,40X40X10MM,12VDC,3.43CFM
CONN,CONT,CRIMP,22-26AWG,AMP
CONN,HSG,CRIMP,.100X2,POL,LK
Front Panel Mechanical Assembly
550-15459
702-15440
023-14068
023-15437
023-15438
430-13143
530-09382
550-13633
550-13634
KNOB,1.75X.91H,6MM,ALUM,PEWTER
PANEL,FRONT,MC8
PL,IR/ENC BD ASSY,MC12/B
PL,SW/LED BD ASSY,MC8/B
PL,STANDBY BD ASSY,MC8/B
DISPLAY,VF,20X2 CHAR,5X8DOT
CLIP,WIRE HRNS,.15DIA,ADH BAK
BUTTON,.276X.572,BLK
BUTTON,.276X.572,BLK,W/LTPIPE
1.000
1.000
1.000
1.000
1.000
1.000
1.000
2.000
20.000
ENCODER
FP SHIELD,CENTER
7-9
PART NO
DESCRIPTION
QTY
635-14526
640-01841
640-10495
640-10498
640-10498
640-10498
640-15476
680-14693
SPCR,M3CLX6MM,6MMRD
SCRW,2-56X1/4,PNH,PH,ZN
SCRW,M3X12MM,PNH,PH,ZN
SCRW,M3X6MM,PNH,PH,BZ
SCRW,M3X6MM,PNH,PH,BZ
SCRW,M3X6MM,PNH,PH,BZ
SCRW,M4X8MM,PNH,PH,ZN
CABLE,100,PLUG/SCKT,2X7C,10.5"
1.000
4.000
1.000
9.000
6.000
2.000
2.000
1.000
680-14854
CABLE,079,SCKT/SCKT,4C,4",CMP
1.000
701-15454
701-15456
703-14098
BRACKET,SUPPORT,COVER,MC8
SHIELD,6.5X1.8X.4"H
LENS,6.36X1.55,MC12
1.000
1.000
1.000
U
EFFECT.
INACT.
REFERENCE
IR/ENC BD
DISPLAY TO FP
IR/ENC BD
SHIELD TO FP
SW/LED BD TO FP
STANDBY BD TO FP
SPT BRKT TO FP
DSPLY TO SW/LED(J1).
SOLDER TO DSPLY.
STANDBY BD (J1) TO
MAIN BD (J43)
Video Mechanical Assembly
023-15431
023-15432
023-15433
635-15716
640-01701
640-10498
641-13116
701-15455
PL,VIDEO BD ASSY,MC8/B
PL,VIDEO RCA BD ASSY,MC8/B
PL,VIDEO OUT BD ASSY,MC8/B
SPCR,M3X17MM,6MM HEX
SCRW,4-40X1/4,PNH,PH,ZN
SCRW,M3X6MM,PNH,PH,BZ
SCRW,TAP,AB,4X3/8,FH,PH,BZ
BRACKET,VIDEO BD,MC8
1.000
1.000
1.000
1.000
3.000
2.000
15.000
1.000
VID RCA TO VIDEO
VIDEO BD TO BRKT
VID RCA TO VIDEO
VIDEO BD TO BRKT
Packaging/Miscellaneous
022-15306
070-15039
070-15481
460-08345
730-11459
730-15286
730-15484
730-15486
730-14896
730-15487
730-15488
730-15483
750-15480
PL,KIT,ACCESS PKG,MC8/B
NOTES,RELEASE/ERRATA,MC8
GUIDE,USER,MC8/B
BAT,ALK,AA
BOX,21X5X19,LEXICON
BOX,17.75X12.125X2.5"
BOX,21-3/4X19X9-3/4,LEXICON
BOX,22-1/2X19-3/4X11,BLANK
INSERT,FOAM,ENDCAP,1U,MC12B
INSERT,FOAM,BASE,2&3UX15
INSERT,FOAM,TOP,2&3UX15
TRAY,ACCESSORY,MC8/B
REMOTE CONTROL,MC8
1.000
1.000
1.000
2.000
1.000
1.000
1.000
1.000
2.000
1.000
2.000
1.000
1.000
SHIPMENT
INNER BOX
OUTER BOX
Power Cord Options
680-09149
680-08830
680-10093
680-10094
680-10095
680-10096
680-10097
CORD,POWER,IEC,10A,2M,NA,SVT
CORD,POWER,IEC,6A,2M,EURO
CORD,POWER,IEC,5A,2M,UK
CORD,POWER,IEC,6A,2M,ITALY
CORD,POWER,IEC,6A,2M,SWISS
CORD,POWER,IEC,6A,2M,AUSTRALIA
CORD,POWER,IEC,6A,2M,JAPAN
1.000
1.000
1.000
1.000
1.000
1.000
1.000
N.AMER
Mounting Option
630-08670
640-08671
640-14680
701-15453
WSHR,FIN,#10,NYL,BLK
SCRW,10-32X3/4,FH,PH,BLK
SCRW,M4X14MM,FH,SCKT,SS
BRACKET,MTG,RACK,2U,MC8
4.000
4.000
6.000
2.000
MC-8 to MC-8B Upgrade Option
023-15439
540-02472
640-10499
640-15476
640-15476
641-14898
680-14494
700-15450
702-14454
720-13632
7-10
PL,XLR BD ASSY,MC8B
PLUG,HOLE,3/8",BLK
SCRW,M3X8MM,PNH,PH,BZ
SCRW,M4X8MM,PNH,PH,ZN
SCRW,M4X8MM,PNH,PH,ZN
SCRW,TAP,#4X1/4,PNH,PH,BZ,TRI
CABLE,.10,SCKTX2-180,2X17C,6"
CHASSIS,1U,MC8B
PANEL,FRONT,1U,MC12B
PAD,FOOT,1.438DIA
1.000
4.000
2.000
3.000
4.000
20.000
1.000
1.000
1.000
4.000
XLR BD TO 1U CHASSIS
1U FP TO 1U CHAS
XLR BD TO 1U CHASSIS
XLR BD (J11)
1U CHASSIS BOTTOM
2/10/05
RELEASED COPY
2/10/05
RELEASED COPY
MAY 6 2004
RELEASED COPY
MAY 6 2004
RELEASED COPY
8
7
6
5
4
2
3
1
REVISIONS
REV
D
DESCRIPTION
1
CHANGED PER DCR 000327-00
2
CHANGED PER DCR 000925-01
3
CHANGED R3 FROM 2.4K TO 1.5K PER ECO
010130-00
DRAFTER
CHECKER
RWH
3/27/00
KB
4/10/00
RWH
10/13/00
KB
10/20/00
CW
1/30/01
KB
1/30/01
Q.C.
AUTH.
CW
4/28/00
KB
4/10/00
CW
10/23/00
KB
10/20/00
ECM
1/30/01
KB
1/30/01
D
+5VD
IRM-8755-H2 3
VCC
1
OUT
SEE NOTE 4
GND
U1C
2
+5VD
GPIU281 2
VCC
1
OUT
SEE NOTE 4
U1B
IR FLASHER
SHIELD GND
5
4
+5VD
3
J1
2
GPIU5
VCC
1
OUT
SEE NOTE 4
U1A
IR_DATA
SHIELD GND
6
5
4
OVERLOAD
IR ACK
+5VD
+5VD
+5VD
+5VD
C
SYSTEM ON
C2
C1
3
.1/50
.1/50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D1
IR
D4
D2
BLU
RED
R3
IR_AUXRET
IR_AUXIN
1.5K
1/4W
5%
D3
C
YEL
R2
R1
1.2K
820
1/4W
5%
1/4W
5%
SYSTEM_ON_LED
OVLD_LED
IR_ACK_LED
ENCODER
NOTES
1 UNLESS OTHERWISE INDICATED, CAPACITORS ARE UF/V
A
B
C
ENCODER_A
ENCODER_B
2
DIGITAL
GROUND
ANALOG
GROUND
CHASSIS
GROUND
POWER
GROUND
3 LAST REFERENCE DESIGNATORS USED: C2, D4, J1, R3, SW1, U1
4 INSTALL ONE ONLY OF U1A, B, C.
SW1
B
B
exicon
CONTRACT
NO.
APPROVALS
DRAWN
CHECKED
Q.C.
ISSUED
8
7
6
5
4
3
2
DATE
CW
10/27/99
KB
10/27/99
RWH
10/27/99
KB
10/27/99
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,IR/ENC BD,MC12
SIZE
B
CODE
NUMBER
060-13699
REV
3
FILE NAME
13699-3 . 1
SHEET
1
1 OF 1
1-30-2001_15:17
A
8
7
6
5
4
3
2
1
REVISIONS
REV
DRAFTER
CHECKER
DESCRIPTION
Q.C.
AUTH.
D
D
FB1
C5
C
+5VD
.1/25
C
C4
.1/25
D1
BB132
2
1
L1
1UH
3
C3
OUT
10PF
8
C2
.1/25
MC1648
VCC VCCO
TANK
VREF
AGC
GND1 GND2
6
7
4
5
R1
OSC
47
VCO_V
C1
U1
.1/25
5
4
3
2
1
NOTES
1 UNLESS OTHERWISE INDICATED, RESISTORS ARE 1/10W
J1
2 UNLESS OTHERWISE INDICATED, RESISTORS ARE 5%
3 UNLESS OTHERWISE INDICATED, CAPACITORS ARE UF/V
4
DIGITAL
GROUND
ANALOG
GROUND
CHASSIS
GROUND
POWER
GROUND
5 LAST REFERENCE DESIGNATORS USED: C5, D1, FB1, J1, L1, R1, U1.
B
B
exicon
CONTRACT
NO.
APPROVALS
DRAWN
8
7
6
5
4
3
DATE
RWH
10/25/00
CHECKED
ECM
11/7/00
Q.C.
CW
11/7/00
ISSUED
KB
11/7/00
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM, VCO BD, MC12
SIZE
B
CODE
NUMBER
060-14849
REV
0
FILE NAME
14849-0 . 1
SHEET
1
1 OF 1
11-8-2000_9:31
A
7
6
5
4
3
+5VD
2
ZD[7:0]
[2/D6,3/D7,5/A7,6/B6,7/A6,8/A6]
+5VD
R401
10K
1
4
VDD
IN
C413
.1/25
29.491MHZ
R402
3
OUT
2
ZXTAL
56
+5VD
GND
D
32
U85
ZD0
ZD1
ZD2
ZD3
ZD4
ZD5
ZD6
ZD7
FB35
R406
*
*
6
1
CLK_IN
NC 2
NC
R405
4 SS%
7 FS1
8 FS2
C392
VDD
5
CLK_OUT
W181-01
GND
3
*
.1/25
*
C393
10/10
*
R403
*
*
56
+5VD
10K
[1/C1,4/D4]
[1/C1,4/D4]
[1/C1,4/D4]
C
[2/D1,2/D3]
[11/A4]
[11/A4]
10K
R400
10K
ZINT0/
ZINT1/
ZINT2/
BUSREQ/
ZINT0/
ZINT1/
ZINT2/
NMI/
ZWAIT/
COM0_RX
COM1_RX
R394
10K
[2/C6]
R399
R393
10K
R392
10K
R395
10K
R396
10K
R397
10K
76
EXTAL
74
XTAL
35
36
37
38
39
40
41
44
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
U86
R398
NC
2
3
14
22
23
30
42
43
51
62
63
75
79
D0
D1
D2
D3
D4
D5
D6
D7
VCC
ZWAIT/
77
80
DREQ1/
59
R404
71
ZCLK
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
TOUT, A18
A19
33MHZ
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
BUSREQ
MREQ
IORQ
RD
WR
M1
ST
RFSH
BUSACK
HALT
E
WAIT
RST
DREQ1
TEND1
COM0_RX
CKA0
DCD0/
CTS0/
49
RXA0
50
CKA0,DREQ0/
47
DCD0
46
CTS0
RTS0
COM1_RX
CKA1
54
RXA1
55
CKA1,TEND0/
TXA1
RXS
CKS
57
RXS,CTS1/
58
CKS
TXA0
TXS
TEST
GNDGNDGNDGND
12 34 72 73
8
9
10
11
13
15
16
17
18
19
20
21
24
25
26
27
28
29
31
33
ZA0
ZA1
ZA2
ZA3
ZA4
ZA5
ZA6
ZA7
ZA8
ZA9
ZA10
ZA11
ZA12
ZA13
ZA14
ZA15
NC
NC
NC
NC
66
65
70
69
68
7
64
78
61
ZMREQ/
ZA[15:0]
COM0_TX
45
NC
52
COM1_TX
56
NC
53
NC
ZCLK
[11/B7]
[11/A7]
U84
9
ZD0
ZD1
ZD2
ZD3
ZD4
ZD5
ZD6
ZD7
52
7
2
3
11
5
13
18
ZA15
ZA14
ZA13
ZA12
ZA7
ZA6
ZA5
ZA4
ZA3
ZA2
ZA1
ZA0
84
65
33
77
55
45
76
15
39
56
14
37
10
BSY/RDY
ZMREQ/
ZIORQ/
ZRD/
ZWR/
PWR_RST/
PWR_RST/
23
12
67
54
74
38
VCC
D0
D1
D2
D3
D4
D5
D6
D7
A15
A14
A13
A12
A7
A6
A5
A4
A3
A2
A1
A0
BSY/RDY
ZMREQ
ZIORQ
ZRD
ZWR
RESET
30
TCK
59
TDO
28
TDI
29
TMS
58
ENCODER_A
ENCODER_B
44
ENC_A
53
ENC_B
51
CHARGE
24
T_RUN
NOTE: XC9572 I/O HAS INTERNAL 10K PULLUPS
DURING POWER UP AND PROGRAMMING
CHANGED SHEETS 10, 13, 14 PER ECO
5
CHANGED SHEET 22 PER ECO 031111-00
6
UPDATED FOR MC4 PER DCR 040922-00
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
02/20/03
KB
02/20/03
CW
5/25/04
KAB
5/26/04
CW
10/14/04
AT
9/27/04
D
RELEASED COPY
S_SW
83
SA_14
50
SRAM_RD
66
SRAM_WR
68
RA22
70
RA21
81
RA20
80
RA19
79
RA18
75
RA17
72
RA16
71
RA15
MEM_RD
EPROM
FLASH0
MEM_SPARE
FLASH_WR
FLASH_RST
BSY/RDY_RD
41
63
69
82
46
34
20
25
IO_PROGRAM
47
IO_CCLK
17
IO_DIN
[1/C1,2/C5]
SA_14
SRAM_RD/
SRAM_WR/
RA22
RA21
RA20
RA19
RA18
RA17
RA16
RA15
[2/B8]
MEM_RD/
EPROM/
FLASH0/
MEM_SPARE
FLASH_WR/
FLASH_RST/
ZD4
R383
R385
R384
1K
R386
R387
VIDEO_RST/
DBA_RST/
FP_RST
IO_RST/
*
1
2
3
4
J41
R389
R391
R390
220
RED
RED
D43
D45
R382
220
*
D42
TRIGGER
SHEET
REVISION
TITLE
HOST & MEMORY CPLD
1 OF 23
6
2 OF 23
4
MEMORY CONN, RAM, I/O CPLD
STATUS & CTL REGISTERS, IR RCVR
3 OF 23
4
AUDIO FPGA
4 OF 23
4
DSP BOARD CONNECTOR
5 OF 23
4
OPTION BD 0 CONNECTOR
6 OF 23
4
OPTION BD 1 CONNECTOR
7 OF 23
4
OPTION BD 2 CONNECTOR
8 OF 23
4
DIGITAL AUDIO RECEIVERS & ZONE DIGITAL OUTPUT
9 OF 23
4
PHASE LOCK LOOP
10 OF 23
5
REMOTE POWER & RS232 PORTS
11 OF 23
4
FRONT PANEL,STANDBY,VIDEO CONN
12 OF 23
4
13 OF 23
LEFT ANALOG INPUT MUXES
5
RIGHT ANALOG INPUT MUXES
14 OF 23
5
MIC INPUTS & MAIN A/D CONVERTER
15 OF 23
4
ZONE2 DAC
16 OF 23
4
L/R FRONT DACS
17 OF 23
4
CENTER/SUB DACS
18 OF 23
4
L/R SIDE DACS
19 OF 23
4
L/R REAR DACS
20 OF 23
4
XLR BD CONN,CONTROL REG
21 OF 23
4
POWER SUPPLY
22 OF 23
5
BYPASS CAPACITORS
23 OF 23
4
+5VD
R381
1K
R379
4.7K
CHARGE/
GRN
D44
D41
Q4
2N3906
3
R378
10K
R380
4.7K
© 2004 Lexicon, Inc.
CONTRACT
NO.
exicon
1N914
GRN
ARE NOT INSTALLED.
DOCUMENT CONTROL BLOCK: #060-15259
[12/C5]
+5VD
*
B
[2/D6]
[2/D4]
[2/D4]
[2/A3]
[4/A4]
STANDBY_LED
POWER
GROUND
8 COMPONENTS MARKED WITH § ARE NOT INSTALLED ON MC4.
J40
ZD5
ZD6
CHASSIS
GROUND
J48, L1, Q9, R440, RY5, U98, W3.
7 COMPONENTS MARKED WITH
[12/D5]
[21/A7]
[12/B7]
[2/C5,3/B8,4/C8]
MEM_IO
MEM_AUDIO
ANALOG
GROUND
6 LAST REFERENCE DESIGNATORS USED: BAT1, C415, D61, E34, FB35,
1
2
3
ZD7
DIGITAL
GROUND
5 [XX/XX] DENOTES [SHEET NUMBER/SECTOR]
[2/B8]
[2/C8]
[2/B8]
[2/B8]
[2/B8]
[2/C8]
IO_PROGRAM/
IO_CCLK
IO_DIN
R308
220
NOTES
1 UNLESS OTHERWISE INDICATED, RESISTORS ARE 1/10W
4
RA[22:15]
1/50
4
ZINT0/
ZINT1/
ZINT2/
3 UNLESS OTHERWISE INDICATED, CAPACITORS ARE UF/V
26
TEST_LED0
36
TEST_LED1
43
TEST_LED2
40
TEST_LED3
U83
C
2 UNLESS OTHERWISE INDICATED, RESISTORS ARE 5%
57
MEM_IO
62
MEM_AUDIO
6
MEM_DAR
48
S_LED
61
S_SW_RD
4
E0
1
E1
21
TRIGGER
[2/C8]
[2/C8]
[2/C8]
C385
5
ENCODER_A
ENCODER_B
ZINT0/
ZINT1/
ZINT2/
32
VIDEO_RST
31
DBA_RST
35
FP_RST
19
IO_RST
GNDGNDGNDGNDGNDGND
8 16 27 42 49 60
ZCLK
ZMREQ/
ZIORQ/
ZRD/
ZWR/
ZM1/
ZCLK
ZMREQ/
ZIORQ/
ZRD/
ZWR/
ZM1/
64
VCCIO
22
VCCIO
A
6
4
78
VCC
220
7
CHANGED PER DCR 020827-00
ENC_A
ENC_B
MEM CPLD
XC9572
J35
CHARGE/
T_RUN/
73
VCC
ZCLK
STANDBY_SWITCH/
8
3
+5VD
1
2
3
4
5
6
[1/C1,12/B2]
[1/C1,12/B2]
CHANGED PER DCR 020731-00
MEMORY CPLD
+5VD
[12/C3]
2
[1/C1,2/C5]
[1/C1,2/C5]
ZM1/
B
[3/A5]
CHANGED PER DCR 020430-00
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
02/19/03
CBV
02/19/03
RWH
3/2/04
GAP
5/18/04
RWH
9/24/04
AT
9/27/04
TEST POINTS
ZIORQ/
ZRD/
NC
48
1
OCT 27 2004
NC
NC
NC
NC
NC
60
[2/D8,4/D7,5/C7,6/C6,7/C6,8/C6,12/A6]
DESCRIPTION
030213-00
ZWR/
67
REV
[1/C1,2/D5]
56
Z8S180-33
4
INT0
5
INT1
6
INT2
1
NMI
PWR_RST/
PHI
1
REVISIONS
T_RUN/
APPROVALS
DRAWN
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
HOST & MEMORY CPLD
SIZE
B
CODE
NUMBER
060-15259
REV
6
FILE NAME
15259-6 . 1
SHEET
1
1 OF 23
10-19-2004_8:58
8
8
7
6
5
4
3
2
1
REVISIONS
[1/D3,3/D7,5/A7,6/B6,7/A6,8/A6]
REV
ZD[7:0]
[1/B3]
[1/B3]
[1/D4,4/D7,5/C7,6/C6,7/C6,8/C6,12/A6]
ZA[15:0]
+3.3VD
[1/C3]
[3/B5]
[1/C3]
SEE NOTES
1&2
12
25
37
51
63
75
89
100
BAT_VCC
R319
ZA0
ZA1
ZA2
ZA3
ZA4
ZA5
ZA6
ZA7
ZA8
ZA9
ZA10
ZA11
ZA12
ZA13
SA_14
SRAM_WR/
SRAM_EN/
SRAM_RD/
10
9
8
7
6
5
4
3
25
24
21
23
2
26
1
43256
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
28
VCC
11
12
13
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
[1/B3]
IO_PROGRAM/
R320
10K
ZCLK
[1/D3,1/C1]
ZD0
ZD1
ZD2
ZD3
ZD4
ZD5
ZD6
ZD7
ZD0
ZD1
ZD2
ZD3
ZD4
ZD5
ZD6
ZD7
ZA15
ZA14
ZA13
32KX8
70NS
27
WE
20
CE
22
OE
14
GND
ZA7
ZA6
ZA5
ZA4
ZA3
ZA2
ZA1
ZA0
C
[1/C3,1/C1]
[1/B5,1/C1]
[1/C3,1/C1]
[1/B3,3/B8,4/C8]
BSY/RDY
EURO48-F
EPROM/
FLASH_RST/
FLASH_WR/
FLASH0/
MEM_SPARE
MEM_RD/
EURO48-F
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
ZA0
ZA1
ZA2
ZA3
ZA4
ZA5
B
RA15
RA16
RA17
RA18
RA19
ZD0
ZD1
ZD2
ZD3
ZA6
ZA7
ZA8
ZA9
ZA10
ZA11
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
J48
[1/B3]
22
M1
26
NC2
52
U90
[1/B3]
[1/B3]
[1/B3]
[1/B3]
[1/B3]
[1/B3]
NC
NC
2
90
91
92
93
94
95
96
97
VCC
XCS05-VQ100
PROGRAM
ZCLK
D0
D1
D2
D3
D4
D5
D6
D7
IO FPGA
A7
A6
A5
A4
A3
A2
A1
A0
ZIORQ/
ZRD/
ZM1/
98
Z1ORQ
99
ZRD
3
ZM1
IO_RST/
87
ZD4
ZD5
ZD6
ZD7
ZA12
ZA13
ZA14
86
ZWAIT
85
IORD
84
IOWR
83
RD/WR
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
66
DSP_IO
32
DB0_IO
54
DB1_IO
79
DB2_IO
+3.3VD
[2/D1,9/D4]
[4/D1,10/B2]
MAIN_DRCVR_MCKO
PLL_MCKO
4896_MCK
1
IN
OUT
J48
J48
ZONE_DRCVR_MCKO
39
ZONE_DRCVR_MCKO
ZONE_MCKO
56
[12/D3]
[12/D3]
[12/D3]
[12/D3]
4896_MCK
GND
U73
4896
[12/C6]
[12/C6]
8
7
*
ZWAIT/
IO_RD/
IO_WR/
RD/WR
NC
GND
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
D
U79
[1/C8,2/D1]
[2/D1,4/D8,5/C7,6/C7,7/C6,8/B6]
[2/D1,4/C8,5/B7,6/B7,7/B6,8/B6]
[2/D1,3/D7,3/C7,5/A7,6/A7,7/A6,8/A6,12/A7]
VFD_EN
SWRD_LEDWR/
FRONT_PANEL/
AUDIO_FPGA/
PIC_CONFIG
IODX_EN/
IODY_EN/
DSP_CS/
DB0_CS/
DB1_CS/
DB2_CS/
TEST POINTS
[12/B7]
[12/B7]
[12/A7]
[4/C8]
[3/C8]
[3/D7]
[3/C7]
[5/B4]
[6/B4]
[7/B4]
[8/B4]
CONTROL_2/
CONTROL_3/
STATUS_4/
ZWAIT/
IO_RD/
IO_WR/
RD/WR
MAIN_DRCVR_MCKO
ZONE_DRCVR_MCKO
AUDIO_4MHZ
ZWAIT/
IO_RD/
IO_WR/
RD/WR
MAIN_DRCVR_MCKO
ZONE_DRCVR_MCKO
4MHZ
[3/D5]
[3/C5]
[3/B8]
AUDIO_PROGRAM/
AUDIO_CCLK
AUDIO_DIN
C
6
[4/D8]
[4/D4]
[4/D4]
DSP_IO
DB0_IO
DB1_IO
DB2_IO
[5/D7]
[6/D7]
[7/D6]
[8/D6]
20
NOTES
1 M1,M0 HAVE WEAK PULLUPS
M1,M0 = 1,1 SLAVE SERIAL MODE
M1,M0 = 1,0 MASTER SERIAL MODE
2 JUMPER W2 TO GND TO USE CONFIGURATION ROM.
[10/B8]
[10/B8]
[10/B8]
MAIN_MCKO
[4/D1,4/C8]
[9/C7]
[9/D7]
[9/D7]
ZONE_MCKO
B
[4/C1,4/B8]
ZONE_DRCVR_RST
ZONE_ERR/STATUS
ZONE_CS12/FCK
[9/B7]
[9/C7]
[9/B7]
AUDIO_4MHZ
[2/D1,4/C8]
MEM_IO
IO_AUDIO
[1/B3]
[4/A4]
1
2
3
4
R314
R313
J33
*
U72
1
11
23
38
49
64
77
88
A
E31
4
IO_SP0
5
IO_SP1
34
TEMP1
43
TEMP2
33
VIDEO_0 (TDI)
60
VIDEO_1 (TCK)
61
VIDEO_2
62
VIDEO_3
VIDEO_0
VIDEO_1
VIDEO_2
SYNC_DETECT
GND
2
35
80 R388
MEM_IO
57 R322
IO_AUDIO
R325
CE
OE DATA
CLK CEO
MAIN_DRCVR_RST
MAIN_ERR/STATUS
MAIN_CS12/FCK
40
ZONE_DRCVR_RST
41
ZONE_DRCVR_ERR/STATUS
42
ZONE_DRCVR_CS12/FCK
3
VPP
VCC
47
MAIN_DRCVR_RST
46
MAIN_DRCVR_ERR/STATUS
45
MAIN_DRDVRCS12/FCK
+3.3VD
10K
W2
PLL_PUMP_UP
PLL_PUMP_DOWN/
PLL_LOCK_DOWN/
4_MHZ
.1/25
XC17S05XL
4.7K
28
PLL_PUMP_UP
29
PLL_PUMP_DOWN
30
PLL_LOCK_DOWN
44
MAIN_MCKO
48
MAIN_DRCVR_MCK0
27
PLL_MCKO
21
4896_MCK
MEMORY BOARD CONNECTOR
4
24.576MHZ
VDD
3.3V
2
RESET
67 R323
AUDIO_PROGRAM
68 R324
AUDIO_CCLK
55 R321
TMS_AUDIO_DIN
[2/D1,9/B4]
R326
71
69
70
56
76
58
59
65
31
53
78
CHANGED PER DCR 020430-00
+3.3VD
R318
*
1
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
[1/B8]
RA[22:15]
C357
24
50
36
74
72
73
81
CTRL2
82
CTRL3
6
(TMS) STATUS4
EURO48-F
+5VD
A1
RA20
RA21
RA22
M0
DONE
INIT
CCLK
IO_DIN
IO_DOUT
VFD_EN
SWRD_LEDWR/
FRONT_PANEL
AUDIO_FPGA
PIC_CONFIG (TDO)
IODX_EN
IODY_EN
DSP_CS
DB0_CS
DB1_CS
DB2_CS
7
A15
8
A14
9
A13
10
13
14
15
16
17
18
19
[12/B7]
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
exicon
CONTRACT
NO.
APPROVALS
DRAWN
TEMP1
TEMP2
5
4
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
MEMORY CONN, RAM, I/O FPGA
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 2
SHEET
1
2 OF 23
10-19-2004_8:58
[1/C3]
E30
IO_DONE
+3.3VD
+3.3VD
D
[3/B5]
IO_CCLK
IO_DIN
DESCRIPTION
8
7
6
5
4
3
2
1
REVISIONS
[21/B6]
[4/D7,12/A6]
IODX[7:0]
REV
IODY[7:0]
1
CHANGED PER DCR 020430-00
2
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
ZD[7:0]
[1/D3,2/D6,5/A7,6/B6,7/A6,8/A6]
D
ZD0
ZD1
ZD2
ZD3
ZD4
ZD5
ZD6
ZD7
IODX_EN/
RD/WR
[2/C3]
[2/D1,2/D3,3/C7,5/A7,6/A7,7/A6,8/A6,12/A7]
2
3
4
5
6
7
8
9
19
1
ZD0
ZD1
ZD2
ZD3
ZD4
ZD5
ZD6
ZD7
IODY_EN/
RD/WR
[2/C3]
[2/D1,2/D3,3/D7,5/A7,6/A7,7/A6,8/A6,12/A7]
C
DESCRIPTION
+3.3VD
+3.3VD
2
3
4
5
6
7
8
9
19
1
74VHCT245
A1
A2
A3
A4
A5
A6
A7
A8
G
DIR
B1
B2
B3
B4
B5
B6
B7
B8
100
100
100
100
100
100
100
100
IODX0
IODX1
IODX2
IODX3
IODX4
IODX5
IODX6
IODX7
[2/C3]
CONTROL_2/
IODY0
IODY1
IODY2
IODY3
IODY4
IODY5
IODY6
IODY7
B1
B2
B3
B4
B5
B6
B7
B8
74VHC273-3.3V
3
4
7
8
13
14
17
18
11
1
1D
2D
3D
4D
5D
6D
7D
8D
CLK
CLR
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
2
5
6
9
12
15
16
19
DB0_RST/
DB1_RST/
DB2_RST/
DSP_RST/
PIC_RST/
REMOTE_PWREN0/
REMOTE_PWREN1/
FAN_ON
[6/A7]
[7/B4]
[8/B4]
[5/A7]
[3/C8]
[11/C7]
[11/D7]
[12/D8]
18
17
16
15
14
13
12
11
IODY0
IODY1
IODY2
IODY3
IODY4
IODY5
IODY6
IODY7
[2/C3]
CONTROL_3/
IODY0
IODY1
IODY2
IODY3
IODY4
IODY5
IODY6
IODY7
74VHC273-3.3V
3
4
7
8
13
14
17
18
11
1
1D
2D
3D
4D
5D
6D
7D
8D
CLK
CLR
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
2
5
6
9
12
15
16
19
R422
220
U93
YEL
U95
D52
R423
220
GRN
D53
R424
220
YEL
D54
R425
220
GRN
D55
R426
220
R427
220
R428
220
GRN
YEL
D56
D57
R429
220
1
2
3
4
5
6
7
8
9
J47
+5VD
GRN
YEL
D59
74VHC04-5V
3
D58
1MHZ
PIC_RST/
[4/B1,4/C4]
[3/D3]
R409
IR_DATA
[12/B2]
1K
TIMER INT
PIC_CONFIG
[2/C3]
NC
74VHC04-5V
11
[2/C3]
OS2
OS1
MCLR
RA0
RA1
RA2
RA3
RTCC
VSS
VDD
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
10
14
6
7
8
9
10
11
12
13
6
C
NC
U88
R408
74VHC04-5V
74VHCT541
10K
2
3
4
5
6
7
8
9
STATUS_4/ 1
19
U89
U88
IO_RST/
[1/B3,2/C5,4/C8]
15
16
4
17
18
1
2
3
5
NC
74VHC04-5V
5
16C54
NC
4
U88
IR RECEIVER
1N914
D
SPARES
+3.3VD
D46
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
U94
U61
74VHCT245
A1
A2
A3
A4
A5
A6
A7
A8
G
DIR
R269
R270
R271
R272
R273
R274
R275
R276
18
17
16
15
14
13
12
11
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
A1
A2
A3
A4
A5
A6
A7
A8
1G
2G
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
1
IODY0
IODY1
IODY2
IODY3
IODY4
IODY5
IODY6
IODY7
18
17
16
15
14
13
12
11
2
NC
U88
74VHC04-5V
9
NC
8
U88
74VHC04-5V
12 NC
13
U88
U92
STATUS_4/
IR_ACK_PIC
[12/A7]
B
B
+5VD
Q8
RESET / BATTERY BACKUP
R439
D60
R440
2.2/35
IN
RESET
1
2N3906
GND
4
R434
2.2K
R435
10K
1N914
Q6
C415
1.00K
1% 2
MC34164
U98
R430
10K
C414
1K
.1/25
R437 D61
4.7K
47K
A
[2/C8]
V_BAT
470PF
R438
[2/D8]
C396
Q9
+5VD
R433
PWR_RST/
SRAM_EN/
2N3904
R436
4.7K
BAT_VCC
R432
1K
+5VD
100K
R431
2N3904
1K
+
Q7
-
BAR35
BAT1
exicon
CONTRACT
NO.
3V
PWR_RST/
[1/B8]
APPROVALS
DRAWN
8
7
6
5
4
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
STATUS & CTL REGISTERS, IR RCVR
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 3
SHEET
1
3 OF 23
10-19-2004_8:58
+5VD
2N3906
+5V MONITOR +5VD
7
6
5
4
+3.3VD
+3.3VD
[2/C3]
[3/D6,12/A6]
AUDIO_PROGRAM/
IODY[7:0]
D
[1/D4,2/D8,5/C7,6/C6,7/C6,8/C6,12/A6]
[2/D1,2/D3,5/C7,6/C7,7/C6,8/B6]
[2/D1,2/D3,5/B7,6/B7,7/B6,8/B6]
[2/C3]
[1/B3,2/C5,3/B8]
[2/D1,2/B3]
[12/D3]
[12/C3]
R342
10K
R343
ZA[15:0]
106
IODY0
IODY1
IODY2
IODY3
IODY4
IODY5
IODY6
IODY7
186
185
184
181
180
179
178
177
ZA0
ZA1
ZA2
ZA3
ZA4
ZA5
ZA6
194
193
191
190
189
188
187
AUDIO_4MHZ
OPTO[4:1]
D0
D1
D2
D3
D4
D5
D6
D7
M0
NC
M1
DONE
IO_INIT
CCLK
IO_DIN
IO_DOUT
VCC
55
AUDIO FPGA
COAX1
COAX2
COAX3
COAX4
OPTO1
OPTO2
OPTO3
OPTO4
56
57
58
59
60
61
62
63
4_MHZ
COAX1
COAX2
COAX3
COAX4
OPTO1
OPTO2
OPTO3
OPTO4
[2/B3,4/C1]
[4/C1,9/B4]
[9/B4]
[9/B4]
[9/B4]
[9/B4]
[9/B4]
[9/B4]
[9/B4]
[4/B4,5/D6]
MAIN_MCKO
MAIN_ADC_SDO
MAIN_DRCVR_SDO
MAIN_C0/
MAIN_CA
MAIN_CB
MAIN_CC
MAIN_CD
MAIN_CE
MAIN_ERF
2
74
5
6
7
8
9
10
11
15
ZONE_MCKO
ZONE_DRCVR_SDO
ZONE_C0/
ZONE_CA
ZONE_CB
ZONE_CC
ZONE_CD
ZONE_CE
ZONE_ERF
49
46
45
44
43
42
41
40
36
100
100
100
100
100
1K
FRONT_VC_CS/
CENTER_VC_CS/
SIDE_VC_CS/
REAR_VC_CS/
MAINOUT_VC_CLK
MAINOUT_VC_DATA
95
FRONT_DAC_CS
96
MAIN_DAC_CS
97
TDI_MAIN_DAC_CCLK
98
MAIN_DAC_CDATA
R293
R292
R291
R290
100
100
100
1K
FRONT_DAC_CS/
MAIN_DAC_CS/
MAIN_DAC_CCLK
MAIN_DAC_CDATA
R283
R285
R284
R282
R281
R280
100
100
1K
100
100
1K
ZONE_VC_CS/
ZONE_VC_CLK
ZONE_VC_DATA
ZONE_DAC_CCLK
ZONE_DAC_CDATA
ZONE_DAC_CS/
196
64
67
68
69
R361
R355
R354
R353
R352
33
100
100
100
100
1MHZ
OSD/
VIDEO_REG/
VIDEO_SCLK
VIDEO_DATA
3
4
14
70
73
72
99
100
101
107
108
109
110
R377
R376
R373
R351
R350
R349
33
33
33
56
56
56
R344
R289
R288
R287
R286
56
100
100
100
100
MAIN_DRCVR_FSI
MAIN_DRCVR_SCKI
MAIN_DRCVR_NRZI
MAIN_ADC_FSI/
MAIN_ADC_SCKI/
MAIN_ADC_MCKI/
MAIN_DAC_FSI/
MAIN_DAC_SCKI/
MAIN_DAC_MCKI/
FRONT_DAC_SDI
CENTER_DAC_SDI
SIDE_DAC_SDI
REAR_DAC_SDI
R335
R328
R368
R366
R367
R334
R279
33
33
33
56
56
56
100
DSP_AUDIO[10:0]
B
[5/C7]
[4/B4,6/D6]
[6/C7]
[4/B4,7/D5]
[7/C6]
[4/A4,8/D6]
[8/C6]
DSP_AUDIO_SP0
DB0_AUDIO[10:0]
DB0_AUDIO_SP0
DB1_AUDIO[10:0]
DB1_AUDIO_SP0
DB2_AUDIO[10:0]
DB2_AUDIO_SP0
DSP_AUDIO2
DSP_AUDIO6
DSP_AUDIO7
DSP_AUDIO8
DSP_AUDIO9
DSP_AUDIO10
136
132
129
128
126
125
124
DB0_AUDIO2
DB0_AUDIO6
DB0_AUDIO7
DB0_AUDIO8
DB0_AUDIO9
DB0_AUDIO10
19
23
24
27
29
30
31
DB1_AUDIO2
DB1_AUDIO6
DB1_AUDIO7
DB1_AUDIO8
DB1_AUDIO9
DB1_AUDIO10
102
148
147
146
142
141
139
DB2_AUDIO2
DB2_AUDIO6
DB2_AUDIO7
DB2_AUDIO8
DB2_AUDIO9
DB2_AUDIO10
160
167
166
164
162
161
159
ZONE_DRCVR_FSI
ZONE_DRCVR_SCKI
ZONE_DRCVR_NRZI
ZONE_DAC_FSI
ZONE_DAC_SCKI
ZONE_DAC_MCKI
ZONE_DAC_SDI
ZONE_NRZO
DSP_AUDIO2
DSP_AUDIO6
DSP_AUDIO7
DSP_AUDIO8
DSP_AUDIO9
DSP_AUDIO10
DSP_AUDIO_SP0
DSP_AUDIO0
DSP_AUDIO1
DSP_AUDIO3
DSP_AUDIO4
DSP_AUDIO5
DSP_AUDIO_4MHZ
DB0_AUDIO2
DB0_AUDIO6
DB0_AUDIO7
DB0_AUDIO8
DB0_AUDIO9
DB0_AUDIO10
DB0_AUDIO_SP0
DB0_AUDIO0
DB0_AUDIO1
DB0_AUDIO3
DB0_AUDIO4
DB0_AUDIO5
DB0_AUDIO_4MHZ
DB1_AUDIO2
DB1_AUDIO6
DB1_AUDIO7
DB1_AUDIO8
DB1_AUDIO9
DB1_AUDIO10
DB1_AUDIO_SP0
DB1_AUDIO0
DB1_AUDIO1
DB1_AUDIO3
DB1_AUDIO4
DB1_AUDIO5
DB1_AUDIO_4MHZ
DB2_AUDIO2
DB2_AUDIO6
DB2_AUDIO7
DB2_AUDIO8
DB2_AUDIO9
DB2_AUDIO10
DB2_AUDIO_SP0
DB2_AUDIO0
DB2_AUDIO1
DB2_AUDIO3
DB2_AUDIO4
DB2_AUDIO5
DB2_AUDIO_4MHZ
ANLG_0
ANLG_1
ANLG_3
ANLG_4
ANLG_6
A
NC
144
165
202
203
J39
GND
§
§
§
§
§
§
§
§
§
§
§
§
§
ZONE_DRCVR_FSI
ZONE_DRCVR_SCKI
ZONE_DRCVR_NRZI
ZONE_DAC_FSI/
ZONE_DAC_SCKI/
ZONE_DAC_MCKI
ZONE_DAC_SDI
ZONE_NRZO
138
137
135
134
133
127
R331
R338
R330
R337
R329
R336
33
33
33
33
33
33
DSP_AUDIO0
DSP_AUDIO1
DSP_AUDIO3
DSP_AUDIO4
DSP_AUDIO5
16
17
20
21
22
28
R375
R372
R371
R374
R370
R369
33
33
33
33
33
33
DB0_AUDIO0
DB0_AUDIO1
DB0_AUDIO3
DB0_AUDIO4
DB0_AUDIO5
R356
R341
R333
R340
R332
R339
33
33
33
33
33
33
DB1_AUDIO0
DB1_AUDIO1
DB1_AUDIO3
DB1_AUDIO4
DB1_AUDIO5
157
152
151
150
149
145
174
172
171
169
168
163
81
82
83
84
85
200
MEM_AUDIO
201
IO_AUDIO
§
§
§
§
§
§
§
§
§
§
§
§
R360
R364
R359
R363
R358
R357
33
33
33
33
33
33
R304
R303
R302
R301
R300
100
100
100
100
100
R362
R365
DB2_AUDIO0
DB2_AUDIO1
DB2_AUDIO3
DB2_AUDIO4
DB2_AUDIO5
DSP_AUDIO[10:0]
VPP
VCC
8
7
6
CE
OE DATA
CLK CEO
1
6
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
DESCRIPTION
1
CHANGED PER DCR 020430-00
2
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
NC
GND
*
[1/C1,1/C8]
[1/C1,1/C8]
[1/C1,1/C8]
REV
U78
[15/B8]
[15/B8]
[15/B8]
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
DSP_AUDIO_4MHZ
DB0_AUDIO[10:0]
TEST POINTS
MAIN PATH
[17/C8]
[18/C8,19/C8,20/C8]
[17/C8,18/C8,19/C8,20/C8]
[17/C8,18/C8,19/C8,20/C8]
MDRX_FSI
MDRX_SCKI
MDRX_SDO
[3/C8,4/B1]
[4/C1,12/D5]
[4/C1,12/D5]
[4/B1,12/D5]
[4/B1,12/D5]
MDAC_FSI
MDAC_FCKI
MDAC_MCKI
FDAC_SDI
CDAC_SDI
SDAC_SDI
RDAC_SDI
[4/D1,9/D7]
[4/D1,9/D7]
[9/D7]
[15/B2]
[15/B2]
[15/B2]
74VHC04-3.3V
5
[4/C1,17/C8]
[4/C1,18/C8]
[4/C1,19/C8]
[4/C1,20/C8]
[4/C1,9/B7]
[4/C1,9/B7]
[9/B7]
[4/C1,16/C8]
[4/C1,16/C8]
[4/C1,16/D8]
[4/C1,16/C8]
[9/A7]
[4/B7,5/D6]
6
R348
56
MAIN_DAC_FSI0/
R347
56
MAIN_DAC_FSI1/
R346
56
MAIN_DAC_SCKI0/
R345
56
MAIN_DAC_SCKI1/
R267
56
FRONT_DAC_MCKI
74VHC04-3.3V
4
R266
56
CENTER_DAC_MCKI
R265
56
SIDE_DAC_MCKI
R268
56
REAR_DAC_MCKI
U58
74VHC04-3.3V
1
2
U58
74VHC04-3.3V
9
8
[4/C1,17/C8,18/C8]
[4/C1,19/C8,20/C8]
MAIN_DRCVR_FSI
MAIN_DRCVR_SCKI
MAIN_DRCVR_SDO
MAIN_DAC_FSI/
MAIN_DAC_SCKI/
MAIN_DAC_MCKI/
FRONT_DAC_SDI
CENTER_DAC_SDI
SIDE_DAC_SDI
REAR_DAC_SDI
MAIN_DAC_FSI0/
MAIN_DAC_FSI1/
MAIN_DAC_SCKI0/
MAIN_DAC_SCKI1/
MDAC_FSI0
MDAC_FSI1
MDAC_SCKI0
MDAC_SCKI1
[4/C1,17/D8,18/D8]
[4/C1,19/D8,20/D8]
C
ZONE PATH
U58
3
PLL_MCKO
MAIN_MCKO
PLL_OUT
MMCK
[16/A8]
[16/B8]
[16/B8]
[16/C8]
[16/C8]
[16/C8]
U58
[17/D8]
ZMCK
ZDRX_FSI
ZDRX_SCKI
ZDRX_SDO
[18/D8]
ZDAC_FSI
ZDAC_SCKI
ZDAC_MCKI
ZDAC_SDI
ZONE_MCKO
ZONE_DRCVR_FSI
ZONE_DRCVR_SCKI
ZONE_DRCVR_SDO
ZONE_DAC_FSI/
ZONE_DAC_SCKI/
ZONE_DAC_MCKI
ZONE_DAC_SDI
VIDEO CONTROL
[19/D8]
OSD/
VIDEO_REG/
VIDEO_SCLK
VIDEO_DATA
OSD
VREG
VSCLK
VDATA
[20/D8]
B
1MHZ
1MHZ
[5/C7]
SPARES
[4/B7,6/D6]
+3.3VD
74VHC04-3.3V
11
DB0_AUDIO_4MHZ
DB1_AUDIO[10:0]
D
[17/A8]
[18/A8]
[19/A8]
[20/A8]
[17/B8,18/B8,19/B8,20/B8]
[17/A8,18/B8,19/B8,20/A8]
PIC CLOCK
10
NC
U58
[6/C7]
74VHC04-3.3V
13
[4/B7,7/D5]
12
NC
U58
DB1_AUDIO_4MHZ
DB2_AUDIO[10:0]
NOTES
[7/C6]
1 M1,M0 HAVE WEAK PULLUPS
M1,M0 = 1,1 SLAVE SERIAL MODE
[4/A7,8/D6]
M1,M0 = 1,0 MASTER SERIAL MODE
2 JUMPER W3 TO GND TO USE CONFIGURATION ROM.
DB2_AUDIO_4MHZ
ANLG_REG0_CS/
ANLG_REG1_CS/
ANLG_REG3_CS/
ANLG_REG4_CS/
ANLG_REG6_CS/
MEM_AUDIO
IO_AUDIO
[8/C6]
[21/D6]
[21/C6]
[21/B6]
[21/B6]
[21/A6]
APPROVALS
DRAWN
[1/B3]
[2/A3]
4
exicon
CONTRACT
NO.
U87
5
[12/C7]
1
REVISIONS
7
8
NC
NC
NC
NC
*
32
SP0
34
SP1
175
SP2
176
SP3
1
13
25
38
51
66
79
91
103
118
131
143
158
170
182
195
1
2
3
4
122
120
37
48
47
119
123
35
XC17S20
5
R299
R298
R297
R296
R295
R294
MAIN_DRCVR_FSI
MAIN_DRCVR_SCKI
MAIN_DRCVR_NRZI
MAIN_AD_FSI
MAIN_AD_SCKI
MAIN_AD_MCKI
MAIN_DAC_FSI
MAIN_DAC_SCKI
MAIN_DAC_MCKI
MAIN_DAC0_SDI
MAIN_DAC1_SDI
MAIN_DAC2_SDI
MAIN_DAC3_SDI
AUDIO_DONE
E33
ZINT0/
ZINT1/
ZINT2/
2
+3.3VD
4
3
2
87
88
89
90
93
94
112
113
114
115
116
117
AUDIO_CCLK
AUDIO_DIN
4.7K
MAININ_VC_CS/
MAININ_VC_CLK
MAININ_VC_DATA
FRONT_VC_CS
CTR_SUB_VC_CS
SIDE_VC_CS
REAR_VC_CS
MAIN_OUT_VC_CLK
MAIN_OUT_VC_DATA
[2/C3]
[2/C3]
3
R327
100
100
1K
1MHZ
OSD
VIDEO_REG
VIDEO_CCLK
VIDEO_CDATA
ZONE_MCKO
ZONE_DRCVR_SDO
ZONE_C0/
ZONE_CA
ZONE_CB
ZONE_CC
ZONE_CD
ZONE_CE
ZONE_ERF
W3
R307
R306
R305
ZONE_OUT_VC_CS
TCK_ZONE_OUT_VC_CLK
ZONE_OUT_VC_DATA
ZONE_DAC_CCLK
ZONE_DAC_CDATA
ZONE_DAC_CS
MAIN_MCKO
MAIN_ADC_SDO
MAIN_DRCVR_SDO
MAIN_C0/
MAIN_CA
MAIN_CB
MAIN_CC
MAIN_CD
MAIN_CE
MAIN_ERF
NC
*
75
MAIN_IN_VC_CS
76
MAIN_IN_VC_CLK
80
MAIN_IN_VC_DATA
C
[2/B3,4/D1]
[15/B2]
[4/D1,9/D4]
[9/D4]
[9/D4]
[9/D4]
[9/D4]
[9/D4]
[9/C4]
[9/C4]
52
50
104
77
155
153
154
199
ZINT0
198
ZINT1
197
ZINT2
XCS20XL-4PQ208
A0
A1
A2
A3
A4
A5
A6
206
RD
207
WR
205
CS
204
RESET
IO_RD/
IO_WR/
AUDIO_FPGA/
IO_RST/
COAX[4:1]
PROG
SEE NOTES
1&2
12
39
54
65
92
111
FPGA_PROG/
18
26
33
53
71
78
86
105
121
130
140
156
173
183
192
208
NC
NC
NC
NC
NC
NC
+3.3VD
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
AUDIO FPGA
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 4
SHEET
1
4 OF 23
10-19-2004_8:59
8
8
7
6
5
4
3
2
1
REVISIONS
REV
DESCRIPTION
1
CHANGED PER DCR 020430-00
2
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
+3.3VD +5VD
D
J38
[4/B4,4/B7]
[2/B3]
DSP_AUDIO[10:0]
DSP_AUDIO0
DSP_IO
DSP_AUDIO1
DSP_AUDIO2
DSP_AUDIO3
DSP_AUDIO4
DSP_AUDIO5
DSP_AUDIO6
DSP_AUDIO7
DSP_AUDIO8
[4/B4]
[4/B8]
DSP_AUDIO_4MHZ
DSP_AUDIO_SP0
DSP_A13
DSP_A12
C
DSP_A11
[1/D4,2/D8,4/D7,6/C6,7/C6,8/C6,12/A6]
[2/D1,2/D3,4/D8,6/C7,7/C6,8/B6]
[2/D1,2/D3,4/C8,6/B7,7/B6,8/B6]
ZA[15:0]
IO_RD/
IO_WR/
ZA5
ZA3
ZA1
ZA0
ZA2
ZA4
2
4
6
8
1
11
13
15
17
19
ZA6
ZA8
ZA10
ZA12
2
4
6
8
1
ZA13
ZA11
ZA9
ZA7
11
13
15
17
19
B
74VHCT244
A1
A2
A3
A4
G
18
Y1
16
Y2
14
Y3
12
Y4
U81
74VHCT244
9
Y1
7
Y2
5
Y3
3
A1
A2
A3
A4
G
Y4
U81
74VHCT244
18
A1
A2
A3
A4
G
Y1
16
Y2
14
Y3
12
Y4
A1
A2
A3
A4
G
Y1
7
Y2
5
Y3
3
Y4
U82
74VHCT244
9
DSP_A5
DSP_A3
DSP_A1
ZDSP_RD/
DSP_A10
DSP_A9
DSP_A8
DSP_A7
DSP_A6
DSP_A5
DSP_A4
DSP_A3
DSP_A2
DSP_A1
DSP_A0
DSP_A[13:0]
ZDSP_RD/
ZDSP_WR/
DSP_A0
DSP_A2
DSP_A4
ZDSP_WR/
DSP_AUDIO9
DSP_AUDIO10
ZDSP_D[7:0]
ZDSP_D0
ZDSP_D1
ZDSP_D2
ZDSP_D3
ZDSP_D4
ZDSP_D5
ZDSP_D6
ZDSP_D7
DSP_A6
DSP_A8
DSP_A10
DSP_A12
DSP_AUDIO_SP0
DSP_A13
DSP_A11
DSP_A9
DSP_A7
DSP_CS/
DSP_RST/
U82
C32
A32
C31
A31
C30
A30
C29
A29
C28
A28
C27
A27
C26
A26
C25
A25
C24
A24
C23
A23
C22
A22
C21
A21
C20
A20
C19
A19
C18
A18
C17
A17
C16
A16
C15
A15
C14
A14
C13
A13
C12
A12
C11
A11
C10
A10
C9
A9
C8
A8
C7
A7
C6
A6
C5
A5
C4
A4
C3
A3
C2
A2
C1
A1
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
D
C
B
E29
EURO64-F
[2/D1,2/D3,3/D7,3/C7,6/A7,7/A6,8/A6,12/A7]
[2/C3]
A
[3/D3]
ZD[7:0]
RD/WR
2
ZD0
3
ZD1
ZD2
4
ZD3
5
ZD4
6
ZD5
7
ZD6
8
ZD7
9
DSP_CS/ 19
1
74VHCT245
A1
A2
A3
A4
A5
A6
A7
A8
G
DIR
B1
B2
B3
B4
B5
B6
B7
B8
18
17
16
15
14
13
12
11
ZDSP_D0
ZDSP_D1
ZDSP_D2
ZDSP_D3
ZDSP_D4
ZDSP_D5
ZDSP_D6
ZDSP_D7
U80
DSP_CS/
DSP_RST/
exicon
CONTRACT
NO.
APPROVALS
DRAWN
8
7
6
5
4
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
DSP BOARD CONNECTOR
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 5
SHEET
1
5 OF 23
10-19-2004_8:58
[1/D3,2/D6,3/D7,6/B6,7/A6,8/A6]
8
7
6
5
4
3
2
1
REVISIONS
REV
DESCRIPTION
1
CHANGED PER DCR 020430-00
2
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
+3.3VD +5VD
D
J34
[4/B4,4/B7]
[2/B3]
DB0_AUDIO[10:0]
C32
A32
C31
A31
C30
A30
C29
A29
C28
A28
C27
A27
C26
A26
C25
A25
C24
A24
C23
A23
C22
A22
C21
A21
C20
A20
C19
A19
C18
A18
C17
A17
C16
A16
C15
A15
C14
A14
C13
A13
C12
A12
C11
A11
C10
A10
C9
A9
C8
A8
C7
A7
C6
A6
C5
A5
C4
A4
C3
A3
C2
A2
C1
A1
DB0_AUDIO0
DB0_IO
DB0_AUDIO1
DB0_AUDIO2
DB0_AUDIO3
DB0_AUDIO4
DB0_AUDIO5
DB0_AUDIO6
DB0_AUDIO7
DB0_AUDIO8
[4/B4]
[4/B8]
DB0_AUDIO_4MHZ
DB0_A13
DB0_AUDIO_SP0
DB0_A12
C
DB0_A11
[1/D4,2/D8,4/D7,5/C7,7/C6,8/C6,12/A6]
[2/D1,2/D3,4/D8,5/C7,7/C6,8/B6]
[2/D1,2/D3,4/C8,5/B7,7/B6,8/B6]
ZA[15:0]
IO_RD/
IO_WR/
B
11
13
15
17
19
ZA5
ZA3
ZA1
2
4
6
8
1
ZA0
ZA2
ZA4
ZA6
ZA8
ZA10
ZA12
2
4
6
8
1
ZA13
ZA11
ZA9
ZA7
11
13
15
17
19
74VHCT244
A1
A2
A3
A4
G
9
Y1
7
Y2
5
Y3
3
Y4
U68
74VHCT244
18
A1
A2
A3
A4
G
Y1
16
Y2
14
Y3
12
Y4
A1
A2
A3
A4
G
Y1
16
Y2
14
Y3
12
Y4
A1
A2
A3
A4
G
Y1
7
Y2
5
Y3
3
Y4
U68
74VHCT244
18
U67
74VHCT244
9
DB0_A5
DB0_A3
DB0_A1
ZDB0_RD/
DB0_A10
DB0_A9
DB0_A8
DB0_A7
DB0_A6
DB0_A5
DB0_A4
DB0_A3
DB0_A2
DB0_A1
DB0_A0
DB0_A[13:0]
ZDB0_RD/
ZDB0_WR/
DB0_A0
DB0_A2
DB0_A4
ZDB0_WR/
DB0_AUDIO9
ZDB0_D[7:0]
DB0_AUDIO10
DB0_A6
DB0_A8
DB0_A10
DB0_A12
ZDB0_D0
ZDB0_D1
ZDB0_D2
ZDB0_D3
ZDB0_D4
ZDB0_D5
ZDB0_D6
ZDB0_D7
DB0_AUDIO_SP0
DB0_A13
DB0_A11
DB0_A9
DB0_A7
DB0_CS/
DB0_RST/
U67
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
D
C
B
E32
EURO64-F
[2/D1,2/D3,3/D7,3/C7,5/A7,7/A6,8/A6,12/A7]
[2/C3]
[3/D3]
ZD[7:0]
RD/WR
2
ZD0
3
ZD1
4
ZD2
5
ZD3
6
ZD4
7
ZD5
8
ZD6
9
ZD7
DB0_CS/ 19
1
74VHCT245
A1
A2
A3
A4
A5
A6
A7
A8
G
DIR
B1
B2
B3
B4
B5
B6
B7
B8
18
17
16
15
14
13
12
11
ZDB0_D0
ZDB0_D1
ZDB0_D2
ZDB0_D3
ZDB0_D4
ZDB0_D5
ZDB0_D6
ZDB0_D7
U74
DB0_CS/
DB0_RST/
A
exicon
CONTRACT
NO.
APPROVALS
DRAWN
8
7
6
5
4
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
OPTION BD 0 CONNECTOR
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 6
SHEET
1
6 OF 23
10-19-2004_8:58
[1/D3,2/D6,3/D7,5/A7,7/A6,8/A6]
8
7
6
5
4
3
2
1
REVISIONS
REV
+3.3VD +5VD
D
J37 §
[4/B4,4/B7]
[2/B3]
DB1_AUDIO[10:0]
DB1_AUDIO0
DB1_IO
DB1_AUDIO1
DB1_AUDIO2
DB1_AUDIO3
DB1_AUDIO4
DB1_AUDIO5
DB1_AUDIO6
DB1_AUDIO7
DB1_AUDIO8
[4/A4]
[4/A8]
DB1_AUDIO_4MHZ
DB1_A13
DB1_AUDIO_SP0
C
DB1_A12
DB1_A11
[1/D4,2/D8,4/D7,5/C7,6/C6,8/C6,12/A6]
[2/D1,2/D3,4/D8,5/C7,6/C7,8/B6]
[2/D1,2/D3,4/C8,5/B7,6/B7,8/B6]
ZA[15:0]
IO_RD/
IO_WR/
2
4
6
8
1
ZA5
ZA3
ZA1
11
13
15
17
19
ZA0
ZA2
ZA4
ZA6
ZA8
ZA10
ZA12
B
ZA13
ZA11
ZA9
ZA7
2
4
6
8
1
11
13
15
17
19
74VHCT244
A1
A2
A3
A4
G
18
Y1
16
Y2
14
Y3
12
Y4
DB1_A5
DB1_A3
DB1_A1
ZDB1_RD/
DB1_A10
DB1_A9
DB1_A8
DB1_A7
DB1_A6
DB1_A5
DB1_A4
DB1_A3
DB1_A2
DB1_A1
DB1_A0
DB1_A[13:0]
U76 §
74VHCT244
A1
A2
A3
A4
G
9
Y1
7
Y2
5
Y3
3
Y4
U76 §
74VHCT244
A1
A2
A3
A4
G
18
Y1
16
Y2
14
Y3
12
Y4
ZDB1_RD/
ZDB1_WR/
DB1_A0
DB1_A2
DB1_A4
ZDB1_WR/
DB1_AUDIO9
ZDB1_D[7:0]
DB1_A6
DB1_A8
DB1_A10
DB1_A12
U77§
74VHCT244
A1
A2
A3
A4
G
9
Y1
7
Y2
5
Y3
3
Y4
DB1_AUDIO10
ZDB1_D0
ZDB1_D1
ZDB1_D2
ZDB1_D3
ZDB1_D4
ZDB1_D5
ZDB1_D6
ZDB1_D7
DB1_AUDIO_SP0
DB1_A13
DB1_A11
DB1_A9
DB1_A7
DB1_CS/
DB1_RST/
U77 §
C32
A32
C31
A31
C30
A30
C29
A29
C28
A28
C27
A27
C26
A26
C25
A25
C24
A24
C23
A23
C22
A22
C21
A21
C20
A20
C19
A19
C18
A18
C17
A17
C16
A16
C15
A15
C14
A14
C13
A13
C12
A12
C11
A11
C10
A10
C9
A9
C8
A8
C7
A7
C6
A6
C5
A5
C4
A4
C3
A3
C2
A2
C1
A1
DESCRIPTION
1
CHANGED PER DCR 020430-00
2
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
D
C
NOTES
B
E28
EURO64-F
[2/D1,2/D3,3/D7,3/C7,5/A7,6/A7,8/A6,12/A7]
[2/C3]
[3/D3]
A
ZD[7:0]
RD/WR
ZD0
2
ZD1
3
ZD2
4
ZD3
5
ZD4
6
ZD5
7
ZD6
8
ZD7
9
DB1_CS/ 19
1
74VHCT245
A1
A2
A3
A4
A5
A6
A7
A8
G
DIR
B1
B2
B3
B4
B5
B6
B7
B8
18
17
16
15
14
13
12
11
ZDB1_D0
ZDB1_D1
ZDB1_D2
ZDB1_D3
ZDB1_D4
ZDB1_D5
ZDB1_D6
ZDB1_D7
U75 §
DB1_CS/
DB1_RST/
exicon
CONTRACT
NO.
APPROVALS
DRAWN
8
7
6
5
4
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
OPTION BD 1 CONNECTOR
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 7
SHEET
1
7 OF 23
10-21-2004_8:21
[1/D3,2/D6,3/D7,5/A7,6/B6,8/A6]
8
7
6
5
4
3
2
1
REVISIONS
REV
D
DESCRIPTION
1
CHANGED PER DCR 020430-00
2
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
+3.3VD +5VD
J36 §
[4/A4,4/A7]
[2/B3]
DB2_AUDIO[10:0]
DB2_AUDIO0
DB2_IO
DB2_AUDIO1
DB2_AUDIO2
DB2_AUDIO3
DB2_AUDIO4
DB2_AUDIO5
DB2_AUDIO6
DB2_AUDIO7
DB2_AUDIO8
[4/A4]
C
[4/A8]
DB2_AUDIO_4MHZ
DB2_AUDIO_SP0
DB2_A13
DB2_A12
DB2_A11
[1/D4,2/D8,4/D7,5/C7,6/C6,7/C6,12/A6]
[2/D1,2/D3,4/D8,5/C7,6/C7,7/C6]
[2/D1,2/D3,4/C8,5/B7,6/B7,7/B6]
ZA[15:0]
IO_RD/
IO_WR/
2
4
6
8
1
ZA5
ZA3
ZA1
11
13
15
17
19
ZA0
ZA2
ZA4
ZA6
ZA8
ZA10
ZA12
B
2
4
6
8
1
ZA13
ZA11
ZA9
ZA7
11
13
15
17
19
74VHCT244
A1
A2
A3
A4
G
18
Y1
16
Y2
14
Y3
12
Y4
DB2_A5
DB2_A3
DB2_A1
ZDB2_RD/
DB2_A10
DB2_A9
DB2_A8
DB2_A7
DB2_A6
DB2_A5
DB2_A4
DB2_A3
DB2_A2
DB2_A1
DB2_A0
DB2_A[13:0]
U70 §
74VHCT244
A1
A2
A3
A4
G
9
Y1
7
Y2
5
Y3
3
Y4
ZDB2_RD/
ZDB2_WR/
DB2_A0
DB2_A2
DB2_A4
ZDB2_WR/
DB2_AUDIO9
DB2_AUDIO10
U70 §
74VHCT244
18
A1
A2
A3
A4
G
Y1
16
Y2
14
Y3
12
Y4
A1
A2
A3
A4
G
Y1
7
Y2
5
Y3
3
Y4
DB2_A6
DB2_A8
DB2_A10
DB2_A12
ZDB2_D[7:0]
U71 §
74VHCT244
9
ZDB2_D0
ZDB2_D1
ZDB2_D2
ZDB2_D3
ZDB2_D4
ZDB2_D5
ZDB2_D6
ZDB2_D7
DB2_AUDIO_SP0
DB2_A13
DB2_A11
DB2_A9
DB2_A7
DB2_CS/
DB2_RST/
U71 §
C32
A32
C31
A31
C30
A30
C29
A29
C28
A28
C27
A27
C26
A26
C25
A25
C24
A24
C23
A23
C22
A22
C21
A21
C20
A20
C19
A19
C18
A18
C17
A17
C16
A16
C15
A15
C14
A14
C13
A13
C12
A12
C11
A11
C10
A10
C9
A9
C8
A8
C7
A7
C6
A6
C5
A5
C4
A4
C3
A3
C2
A2
C1
A1
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
D
C
NOTES
B
E27
EURO64-F
[2/D1,2/D3,3/D7,3/C7,5/A7,6/A7,7/A6,12/A7]
A
[2/C3]
[3/D3]
ZD[7:0]
RD/WR
2
ZD0
3
ZD1
ZD2
4
ZD3
5
ZD4
6
ZD5
7
ZD6
8
ZD7
9
DB2_CS/ 19
1
74VHCT245
A1
A2
A3
A4
A5
A6
A7
A8
G
DIR
B1
B2
B3
B4
B5
B6
B7
B8
18
17
16
15
14
13
12
11
ZDB2_D0
ZDB2_D1
ZDB2_D2
ZDB2_D3
ZDB2_D4
ZDB2_D5
ZDB2_D6
ZDB2_D7
U69 §
DB2_CS/
DB2_RST/
exicon
CONTRACT
NO.
APPROVALS
DRAWN
8
7
6
5
4
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
OPTION BD 2 CONNECTOR
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 8
SHEET
1
8 OF 23
10-21-2004_8:21
[1/D3,2/D6,3/D7,5/A7,6/B6,7/A6]
8
7
6
5
4
3
2
1
REVISIONS
REV
MAIN DIGITAL AUDIO RECEIVER
[2/B3]
DESCRIPTION
1
CHANGED PER DCR 020430-00
2
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
MAIN_ERR/STATUS
+5VD
C334
D
.1/25
7
[4/C4]
[4/D1,4/C4]
[4/C4,4/D1]
[2/B3]
9
RXP
10
RXN
MAIN_DRCVR_NRZI
MAIN_DRCVR_FSI
11
MAIN_DRCVR_SCKI
12
MAIN_CS12/FCK
13
NC
NC
NC
[2/B3]
8
VD+
FSYNC
SCK
1
C
14
U
15
CBL
MAIN_CA
MAIN_CB
MAIN_CC
MAIN_CD
MAIN_CE
FILT
AGND
D
[4/C8]
[4/C8]
20
R309
470
.1/25
C338
.068/63
C336
C
[2/D1,2/B5]
[4/D1,4/C8]
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
[4/C8]
[4/C8]
[4/C8]
[4/C8]
[4/C8]
MAIN_ERF
NC
U64
21
C337
FB33
.1/25
MAIN_C0/
5
4
3
2
27
25
ERF
28
VERF
22
MAIN_DRCVR_MCKO
MAIN_DRCVR_SDO
56
16
SEL
6
C0/E0
CA/E1
CB/E2
CC/F0
CD/F1
CE/F2
CS12/FCK
VA+
C335
R310
19
MCK
26
SDATA
23
M0
24
M1
18
M2
17
M3
MAIN_DRCVR_RST
CS8414
DGND
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
C
4.7
ZONE DIGITAL AUDIO RECEIVER
ZONE_ERR/STATUS
[2/B3]
+5VD
C339 §
7
[4/B4]
[4/B4,4/C1]
[4/B4,4/C1]
[2/B3]
ZONE_DRCVR_NRZI
9
RXP
10
RXN
ZONE_DRCVR_FSI
11
ZONE_DRCVR_SCKI
12
ZONE_CS12/FCK
13
NC
NC
NC
B
[2/B3]
.1/25
VD+
FSYNC
SCK
ZONE_C0/
ZONE_CA
ZONE_CB
ZONE_CC
ZONE_CD
ZONE_CE
FILT
AGND
VA+
FB34§
ZONE_DRCVR_MCKO
ZONE_DRCVR_SDO
56
5
4
3
2
27
25
ERF
28
VERF
22
§ R312
16
SEL
6
C0/E0
CA/E1
CB/E2
CC/F0
CD/F1
CE/F2
CS12/FCK
23
M0
24
M1
18
M2
17
M3
.1/25
CS8414
19
MCK
26
SDATA
1
C
14
U
15
CBL
ZONE_DRCVR_RST
C340 §
8
DGND
21
C342
§
.1/25
C341§
[4/B8]
[4/B8]
[4/B8]
[4/B8]
[4/B8]
[4/B8]
ZONE_ERF
NC
[2/D1,2/B5]
[4/C1,4/B8]
B
[4/B8]
20
U65 §
R311§
470
C343 §
.068/63
4.7
ZONE DIGITAL OUTPUT
[4/B4]
§ ZONE_S/PDIF_OUT
§
374
1%
R177
90.9
§
.1/25
C228§
33PF
1%
8
7
6
1
RCA
exicon
CONTRACT
NO.
2
APPROVALS
DRAWN
5
4
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
DIGITAL AUDIO RECEIVERS AND
ZONE DIGITAL OUTPUT
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 9
SHEET
1
9 OF 23
10-19-2004_9:02
A
J17 §
C227
R178
ZONE_NRZO
8
7
6
5
4
3
2
1
REVISIONS
REV
D
1
CHANGED PER DCR 020430-00
2
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
CHANGED U56 PER ECO 030213-00
5
UPDATED FOR MC4 PER DCR 040922-00
+5VD
+15V
D26
1N4002
8
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
02/19/03
CBV
02/19/03
RWH
9/24/04
AT
9/27/04
DESCRIPTION
78L05
VIN
VOUT
COMMON
2 3 6 7
1N4002
D27
1
C292
U54
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
02/20/03
KB
02/20/03
CW
10/14/04
AT
9/27/04
D
C293
.1/25
10/10
+5_PLL
SPARES
+5_PLCC
C
13
U55
12
C
NC
74ACT04
FB25
FB26
FB28
11
C294
D33
.1/25
C307
14
PLL_PUMP_UP
7
[2/B3]
74ACT04
1
2
UP/
D30
R255
BAR35
1.2K
74HCU04
9
8
1/50
U57
R261
C303
1.2K
74HCU04
11
10
47/16
[2/B3]
B
[2/B3]
PLL_PUMP_DOWN/ 3
U55
4
P_DOWN
74ACT04
PLL_LOCK_DOWN/ 5
BAR35 R256
D31
-
5
+
4
L_DOWN
6
74ACT04
LK_DN
VCOV
100
U56
C304
.1/25
J31
1
2
3
4
5
VCO
VCO MODULE
2.2M
U57
74HCU04
3
4
C296
R259
R263
U55 D28 R253
8
18.2K
74ACT04 BAR35
1%
4.99K
1%
C301
47/16
8 LF353
2
1
3
+
4
47K
U57
1
14
2
U57 7 74HCU04
R260
56
R258
B
PLL_MCKO
[2/B5,4/D1]
44.1K AND 48K @ 512FS
47K
88.2K AND 96K @ 256 FS
C295
.1/25
2.2M
+15V .1/25
NC
OSC
.1/25
R254
NC
74HCU04
13
12
D29
1N914C299
NC
U57
OSC
49.9K
1%
R252
NC
74HCU04
5
6
BAR35 R257
D32
9
R264
-15V
P_DN
U55
1.2K
VCOV
8 LF353
7
6
NC
U57
+15V
P_UP/
.1/25
C302
1N914
U55
10
74ACT04
C297
.1/25
U55
R262
4.99K
1%
U56
-15V
exicon
CONTRACT
NO.
APPROVALS
DRAWN
8
7
6
5
4
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
PHASE LOCK LOOP
SIZE
B
CODE
NUMBER
060-15259
REV
5
FILE NAME
15259-6 . 10
SHEET
1
10 OF 23
10-19-2004_8:58
A
7
6
5
4
3
2
1
REVISIONS
U44
10
74VHC04-3.3V
REV
+15V
2 CASE=GND
ON-OFF
4
5
VIN
VOUT
LM2941CT
C229
.47UF
D
GND
3
ADJ
1 U36
FB20
R165
C222
8.45K
1%
22/16
R167
1K
1/4W
R166
2
TRIGGER2
C221
1K
1/4W
150PF
5
1
3
DIN5
R168
REMOTE_PWREN1/
NC
1.00K
1%
[3/D3]
7
6
*
SEE NOTE 1
1
CHANGED PER DCR 020430-00
2
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
+15V
2 CASE=GND
ON-OFF
4
5
VIN
VOUT
LM2941CT
C230
.47UF
[3/D3]
GND
3
ADJ
1 U37
R169
R171
C224
8.45K
1%
1K
1/4W
22/16
1
2
3
4
TRIGGER1
R170
C223
1K
1/4W
150PF
SPARES
+3.3VD
1.00K
1%
U44
U44
3
8
74VHC04-3.3V
.47UF
U44
2 CASE=GND
ON-OFF
4
5
VIN
VOUT
LM2941CT
C231
GND
3
ADJ
1 U38
5
FB22
R173
R175
C226
8.45K
1%
1K
1/4W
22/16
TRIGGER0
R174
U44
C225
1K
1/4W
HIGH = OFF, LOW = ON
1
150PF
74VHC04-3.3V
+5VD
2
C217
.1/25
B
RS-232
MAX202E
+5VD
16
C305
.1/25
15
C220
.1/25
6
V+
C1+
VCC C1GND C2+
V-
C2-
R161
1
4.7K
(FEMALE)
R162
4.7K
C218
3
.1/25
NC
NC
4
RXD_A
NC
TXD_A
C219
5
TXDA
NC
FB16
A5
A9
A4
A8
A3
A7
A2
A6
A1
COM1_TX
RX1
12
13
RXDA
10
7
TXDB
9
8
RXDB
FB17
R160
4.7K
1...DCD
2...RXD
C215
150PF
C214
150PF
C213
NC
NC
RXD_B
NC
TXD_B
C212
150PF
NC
150PF
B5
B9
B4
B8
B3
B7
B2
B6
B1
8...CTS
SHD2
SHD1
R164
56
COM1_RX
R163
56
COM0_RX
4
9...RI
J14
exicon
CONTRACT
NO.
5
7...RTS
4...DTR
A
6
6...DSR
DE9F
R159
4.7K
FB19
U29
J14
5...GND
FB18
B
RS-232 PINOUT (MALE)
3...TXD
+5VD
RX0
1. INSTALL FOR JBL PRODUCTS ONLY.
SHD2
14
.1/25
NOTES
DE9F
SHD1
11
COM0_TX
7
C
NC
2
1.00K
1%
RS-232 TRANSCEIVER
8
NC
6
74VHC04-3.3V
R176
REMOTE_PWRENx/ MUST BE HIGH AT POWER UP
[1/C5]
NC
4
74VHC04-3.3V
+15V
C
[1/C5]
D
J15
FB21
R172
9
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
12
74VHC04-3.3V
REMOTE_PWREN0/
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
DESCRIPTION
REMOTE POWER CONTROL DRIVERS
U44
13
J16
4
NC
11
[1/C8]
APPROVALS
DRAWN
[1/C8]
ISSUED
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
REMOTE POWER & RS232 PORTS
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 11
SHEET
1
11 OF 23
10-19-2004_8:58
8
8
7
6
+15V
5
+5VD
75
1/4W
§
SEE NOTE 1
U62
*§
SEE NOTE 1
RED
D47 §
1
2
1N4002
BLACK
[3/D3]
R412 §
FAN_ON
2N4401
Q5 §
470
W1
R317 §
10.0K
1%
1
2
R316 §
*§
C
LM56
VREF
V+
VIDEO_RST/
[1/B3]
J42 §
+3.3VD
8
7
OUT1
6
OUT2
VT2
3
VT1
4
GND
1.2K
47° C
NC
FAN CONNECTOR
TEMPERATURE SENSOR
57° C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
18
Y1
16
Y2
14
Y3
12
Y4
A1
A2
A3
A4
G
R411
R410 §
D
2
4
6
8
1
VTEMP
5
U66
R315 §
TEMP1
TEMP2
3
2
1
REVISIONS
74VHCT244
VIDEO_DATA
VIDEO_SCLK
OSD/
VIDEO_REG/
[4/B1,4/C4]
[4/B1,4/C4]
[4/C1,4/C4]
[4/C1,4/C4]
R277
4
VIDEO BOARD CONNECTOR
REV
VIDEO_0
VIDEO_1
VIDEO_2
SYNC_DETECT
COAX[4:1]
COAX1
[2/A5]
[2/A5]
[2/A5]
[2/A5]
1
CHANGED PER DCR 020430-00
2
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
COAX3
COAX4
OPTO[4:1]
OPTO1
SPARES
[4/C7]
+5VD
OPTO2
OPTO3
74VHCT244
OPTO4
11
13
15
17
19
A1
A2
A3
A4
G
9
Y1
7
Y2
5
Y3
3
Y4
NC
NC
NC
NC
U62
C
§
R414
13.7K
1%
1K
[1/A3]
1
2
3
4
R413
STANDBY_LED
220
D
[4/C7]
+5VD
NC
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
COAX2
J30
[2/A5]
[2/A5]
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
DESCRIPTION
STANDBY_SWITCH/
[1/B8]
NOTES
STANDBY SWITCH
1 INSTALL R410 FOR 12V FAN. INSTALL R411 FOR 5V FAN.
CONNECTOR
J43
74VHCT244
AUDIO_DONE
[4/D2]
11
13
15
17
19
IO_DONE
VFD_EN
[2/D3]
[2/C3]
R407
A1
A2
A3
A4
G
9
Y1
7
Y2
5
Y3
3
Y4
R421
U91
3.3K
R420
R419
YEL
GRN
YEL
D51
D50
D49
220
220
220
R180
REAR PANEL IR INPUT
B
RED
BLACK
1
2
J18
+5VD
+5VD
1K
D19
R179
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2.2K
BAV99
IR0_AUXIN
BAV99
D20
[2/C3]
[1/B3]
[3/B2]
[1/D4,2/D8,4/D7,5/C7,6/C6,7/C6,8/C6]
VFD_EN_BUF
SWRD_LEDWR/
FP_RST
ZA0
ZA1
ZA2
IR_ACK_PIC
74VHCT244
2
4
6
8
1
A1
A2
A3
A4
G
FP_A0
FP_A1
FP_A2
FP_D1
FP_D0
FP_D3
FP_D2
FP_D5
FP_D4
FP_D7
FP_D6
18
Y1
16
Y2
14
Y3
12
Y4
U91
ZA[15:0]
NC
IR_DATA
R415
10K
B
R416
10K
IR_DATA
ENCODER_B
ENCODER_A
R417
[3/C8]
[1/A8,1/C1]
[1/A8,1/C1]
R418
100
100
C411
C412
.01/50
.01/50
J46
[3/D6,4/D7]
[2/C3]
[2/D1,2/D3,3/D7,3/C7,5/A7,6/A7,7/A6,8/A6]
8
7
IODY[7:0]
IODY0
IODY1
IODY2
IODY3
IODY4
IODY5
IODY6
IODY7
FRONT_PANEL/
RD/WR
6
2
3
4
5
6
7
8
9
19
1
74VHCT245
A1
A2
A3
A4
A5
A6
A7
A8
G
DIR
B1
B2
B3
B4
B5
B6
B7
B8
18
17
16
15
14
13
12
11
FP_D[7:0]
FP_D0
FP_D1
FP_D2
FP_D3
FP_D4
FP_D5
FP_D6
FP_D7
FRONT PANEL CONNECTOR
exicon
CONTRACT
NO.
APPROVALS
DRAWN
U97
5
4
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
FRONT PANEL,STANDBY,VIDEO CONN
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 12
SHEET
1
12 OF 23
10-19-2004_9:02
A
8
7
6
5
4
3
2
1
REVISIONS
+15V
+15V
LEFT ANALOG INPUTS
1
1
J13
D
3
RCA
0dBFS=4.0Vrms
C208
R155
D17
100
1/4W
BAV99
6
+
-
8
13
LF353
7
4
R156
C206
150PF
5
10/25
+15V
+15V
4
5
6
7
12
11
10
9
U28
100K
-15V
-15V
+15V
+15V
1
2
J12
3
RCA
C202
R151
D15
100
1/4W
BAV99
10/25
+
6
-
8
LF353
[14/D5,21/C3]
[14/D5,21/C3]
[14/D5,21/C3]
[14/D5,21/C3]
[15/D4]
U27
100K
-15V
3
DG408
V+ GND VS1
S2
S3
S4
8
D
S5
S6
S7
S8
A0 A1 A2 EN
1
7
4
R152
C200
150PF
5
-15V
14
16
2
15
J11
3
RCA
C196
D13
100
1/4W
BAV99
10/25
C
6
+
-
8
13
4
5
6
7
12
11
10
9
LF353
U26
100K
-15V
-15V
+15V
1
4
J10
3
RCA
C190
D11
100
1/4W
BAV99
10/25
+
6
-
[14/C5,21/C3]
[14/C5,21/C3]
[14/C5,21/C3]
LF353
7
4
R144
C188
150PF
5
8
[14/C5,21/C3]
U25
J9
3
RCA
-15V
-15V
R198
1.00K
1%
R200
100K
LEFT_MAIN_IN
[15/B8]
3
CHANGED PER DCR 020827-00
R199
1.00K
1%
4
CHANGED U21-28 PER ECO 030213-00
U42
5
UPDATED FOR MC4 PER DCR 040922-00
ZONE2 SOURCE SELECT LEFT
-15V
14
3
DG408
16
15
2
8
LEFT_DIR_IN
[17/C4]
R197
5
+
MC33078
6
-
U43
D
7
4
UNITY GAIN PASS-THRU
-15V
LEFT_ZONE_IN
[16/D4]
R196 §
R201 §
C
100K
U41§
+15V +5VAD
+15V
C184
R139
D9
BAV99
5
10/25
6
+
-
8
13
VCC
3
S
1
IN
VEE
LF353
7
4
R140
C182
150PF
CHANGED PER DCR 020731-00
100K
-15V
100
1/4W
2
ZONE_ANLG_EN
+15V
1
U43
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
02/20/03
KB
02/20/03
CW
10/14/04
AT
9/27/04
ZONE_ANLG_SEL0
ZONE_ANLG_SEL1
ZONE_ANLG_SEL2
+15V
5
CHANGED PER DCR 020430-00
0dBFS=2.0Vrms
V+ GND VS1
S2
S3
8
S4
D
S5
S6
S7
S8
A0 A1 A2 EN
1
+15V
R143
-
1
1
UNITY GAIN PASS-THRU
+15V
7
4
R148
C194
150PF
5
2
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
02/19/03
CBV
02/19/03
RWH
9/24/04
AT
9/27/04
DESCRIPTION
MC33078
+15V
-15V
R147
+
MAIN_ANLG_SEL0
MAIN_ANLG_SEL1
MAIN_ANLG_SEL2
MAIN_ANLG_EN
LEFT_MAIN_SW
+15V
1
8
3
4
+15V
3
REV
MAIN SOURCE SELECT LEFT
U24
4
100K
-15V
12
ADG451
VDD
D
2
GND
8
+
MC33078
2
-
U39
-15V
-15V
+15V +5VAD
+15V
13
1
4
U40
5
UNITY GAIN PASS-THRU
3
CNTR_DIR_IN
R192
[18/C4]
-15V
+15V
B
1
6
J8
3
RCA
C178
R135
D7
100
1/4W
BAV99
10/25
5
+
6
-
8
14
S
16
IN
VEE
LF353
7
4
R136
C176
150PF
VCC
U23
4
12
ADG451
VDD
D
GND
U40
5
B
15
R193
100K
100K
-15V
-15V
-15V
+15V
+15V
J7
3
RCA
C172
R131
D5
100
1/4W
BAV99
10/25
+
6
-
8
+15V +5VAD
LF353
+15V
7
4
R132
C170
150PF
5
13
U22
100K
-15V
[14/A5,21/D3]
-15V
ANLG_4_5_DIR_IN/
+15V
4
+15V
1
8
A
J6
3
RCA
C166
R127
D3
100
1/4W
BAV99
R128
C164
150PF
10/25
5
+
6
-
8
ADG451
VDD
D
UNITY GAIN PASS-THRU
10
GND
U40
5
LF353
8
5
+
MC33078
6
-
U39
LSUR_DIR_IN
7
4
R194
7
4
13
U21
VCC
-15V
[14/A5,21/C3]
ANLG_7_8_DIR_IN/
6
S
8
IN
VEE
4
12
D
7
GND
5
7
6
5
exicon
CONTRACT
NO.
ADG451
VDD
U40
APPROVALS
DRAWN
R195
100K
-15V
8
[19/C4,20/C4]
-15V
-15V
+15V +5VAD
100K
-15V
VCC
11
S
9
IN
VEE
12
4
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
LEFT ANALOG INPUT MUXES
SIZE
B
CODE
NUMBER
060-15259
REV
5
FILE NAME
15259-6 . 13
SHEET
1
13 OF 23
10-19-2004_8:58
1
7
8
7
6
5
4
3
2
1
REVISIONS
+15V
+15V
RIGHT ANALOG INPUTS
2
1
J13
D
3
RCA
0dBFS=4.0Vrms
C209
R158
D18
100
1/4W
BAV99
2
+
-
8
13
LF353
1
4
R157
C207
150PF
3
10/25
+15V
+15V
4
5
6
7
12
11
10
9
U28
100K
-15V
-15V
+15V
+15V
2
2
J12
3
RCA
C203
R154
D16
100
1/4W
BAV99
10/25
+
2
-
8
LF353
[13/D5,21/C3]
[13/D5,21/C3]
[13/D5,21/C3]
[13/D5,21/C3]
[15/D4]
U27
100K
-15V
3
DG408
V+ GND VS1
S2
S3
8
S4
D
S5
S6
S7
S8
A0 A1 A2 EN
1
1
4
R153
C201
150PF
3
-15V
14
16
2
15
J11
3
RCA
C197
D14
100
1/4W
BAV99
10/25
C
2
+
-
8
13
4
5
6
7
12
11
10
9
LF353
U26
100K
-15V
-15V
+15V
2
4
J10
3
RCA
C191
D12
100
1/4W
BAV99
10/25
+
2
-
[13/C5,21/C3]
[13/C5,21/C3]
[13/C5,21/C3]
LF353
1
4
R145
C189
150PF
3
8
[13/C5,21/C3]
U25
J9
3
RCA
1.00K
1%
R189
100K
2
J8
3
RCA
C185
D10
BAV99
3
10/25
2
+
-
8
-15V
ZONE2 SOURCE SELECT RIGHT
14
3
DG408
16
15
2
8
RIGHT_DIR_IN
R186
5
+
MC33078
6
-
U34
3
CHANGED PER DCR 020827-00
4
CHANGED U21-28 PER ECO 030213-00
5
UPDATED FOR MC4 PER DCR 040922-00
D
[17/B4]
7
4
UNITY GAIN PASS-THRU
-15V
RIGHT_ZONE_IN
R185 §
[16/C4]
R190 §
C
100K
U32
§
VCC
3
S
1
IN
VEE
LF353
U24
4
12
ADG451
VDD
D
2
GND
8
+
MC33078
2
-
U30
-15V
-15V
+15V +5VAD
+15V
13
C179
D8
BAV99
10/25
3
+
2
-
14
S
16
IN
VEE
LF353
1
4
R137
C177
8
VCC
U23
4
100K
-15V
-15V
12
1
4
U31
5
UNITY GAIN PASS-THRU
3
100K
-15V
R138
150PF
R188
1.00K
1%
U33
13
1
4
R141
100
1/4W
[15/B8]
+15V +5VAD
+15V
6
RIGHT_MAIN_IN
+15V
C183
B
R187
ZONE_ANLG_EN
-15V
R142
150PF
CHANGED PER DCR 020731-00
100K
-15V
100
1/4W
2
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
02/20/03
KB
02/20/03
CW
10/14/04
AT
9/27/04
ZONE_ANLG_SEL0
ZONE_ANLG_SEL1
ZONE_ANLG_SEL2
+15V
2
U34
-15V
+15V
5
CHANGED PER DCR 020430-00
0dBFS=2.0Vrms
V+ GND VS1
S2
S3
8
S4
D
S5
S6
S7
S8
A0 A1 A2 EN
1
+15V
R146
-
1
1
UNITY GAIN PASS-THRU
+15V
1
4
R149
C195
150PF
3
2
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
02/19/03
CBV
02/19/03
RWH
9/24/04
AT
9/27/04
DESCRIPTION
MC33078
+15V
-15V
R150
+
MAIN_ANLG_SEL0
MAIN_ANLG_SEL1
MAIN_ANLG_SEL2
MAIN_ANLG_EN
RIGHT_MAIN_SW
+15V
2
8
3
4
+15V
3
REV
MAIN SOURCE SELECT RIGHT
SUB_DIR_IN
R181
[18/B4]
-15V
ADG451
VDD
D
GND
U31
5
B
15
R182
100K
-15V
+15V
+15V
J7
3
RCA
C173
R134
D6
100
1/4W
BAV99
10/25
2
+
-
8
+15V +5VAD
LF353
+15V
1
4
R133
C171
150PF
3
13
U22
VCC
100K
-15V
[13/A5,21/D3]
-15V
ANLG_4_5_DIR_IN/
+15V
11
S
9
IN
VEE
4
12
ADG451
VDD
D
UNITY GAIN PASS-THRU
10
GND
+15V
2
8
A
J6
3
RCA
C167
R130
D4
100
1/4W
BAV99
R129
C165
150PF
10/25
3
+
2
-
8
1
4
13
U21
VCC
100K
-15V
[13/A5,21/C3]
-15V
ANLG_7_8_DIR_IN/
6
S
8
IN
VEE
4
12
MC33078
-
U30
7
RSUR_DIR_IN
R183
ADG451
VDD
D
U31
7
6
5
4
exicon
APPROVALS
DRAWN
R184
100K
-15V
8
[19/B4,20/B4]
CONTRACT
NO.
7
GND
5
+
6
-15V
-15V
+15V +5VAD
LF353
5
4
U31
5
8
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
RIGHT ANALOG INPUT MUXES
SIZE
B
CODE
NUMBER
060-15259
REV
5
FILE NAME
15259-6 . 14
SHEET
1
14 OF 23
10-19-2004_9:04
2
7
8
7
6
5
4
3
2
1
REVISIONS
REV
+3.3VA
D
R43
220
[21/D3]
14
U53
7
74LVC14
MIC_SEL0 1
MIC_SEL1
220
YEL
GRN
D21 §
D22 §
1
2
3
4
5
6
7
8
9
10
2
11
U53
10
74LVC14
-15V
R46 §
MIC_IN_L
2.7K
MIC_IN_R
LEFT_MAIN_SW
-7dB
+5VA
C282
R219
100PF
2.00K
1%
R217
C244
10/10
B
[4/D4]
[4/D4]
[4/D4]
MAININ_VC_CLK
6
MAININ_VC_DATA
3
MAININ_VC_CS/
2
1
[15/A2]
[14/D2]
MAININ_VC_MUTE/
RIGHT_MAIN_IN
8
9
AINL
PGA2311
VD+
47/16
14
DGND
.1/25
5
C250
AINR
AOUTR
AGNDR
10
-
3
+
C246
R215
51
1/4W
4.7
4.7
C268
C269
.1/25
C274
2200PF
MC33078
1
51
U47
R206
C275
C271
1/4W
4.7
C279
10.0K
1%
.1/25
.1/25
2.00K
1%
+5VA
C263
4.7
10/10
C278
U35
R213
2.00K
1%
100PF
E24
R211
8
6
-
5
+
2.49K
1%
+5VA
C248
R210
47/16
5.62K
1%
8
2
-
3
+
U46
R209
VA
C272
.1/25
2
3
C265
26
.1/25
28
C264
.1/25
27
VREFL+
GNDL
VCOML
VCOMR
VREFR+
GNDR
25 AINR+
24
AINR-
51
1/4W
C267
-5VA
2200PF
22
AGND
21
BGND
20
TEST
8
DGND
VD
ZCAL
FSYNC
HPFE
SMODE2
SMODE1
DFS
SDATA
LRCK
SCLK
MCLK
CAL
RST/
7
6
R203
1
2
3
4
*
16
19
11
MAIN_ADC_96K_EN
R204
MAIN_ADC_SDO
47
MAIN_ADC_FSI/
14
MAIN_ADC_SCKI/
17
MAIN_ADC_MCKI/
9
10
13
U53
12
MAININ_VC_MUTE/
74LVC14
MAIN_ADC_RST/
U53
9
47K
18
13
SPARES
+3.3VA
R205
R202
12
15
*
J27
8
B
NC
74LVC14
[21/C3]
[4/C8]
[4/C4]
[4/C4]
[4/C4]
[15/B8]
[21/C3]
U45
MC33078
R208
1
4
MC33078
7
4
1
C273
R212
C276
.1/25
AK5383
4
AINL+
5
AINL-
R214
NC
11
U47
FB23
C270
C266
-5VA
10.0K
1%
7
MC33078
7
4
R207
C247
-5VA
+
0dBFS=0.884Vrms
100PF
.1/25
10/10
-
5
-5VA
+5VA
VA13
6
4.7
ZCEN
SDOUT
5.62K
1%
8
2
4
SDIN
CS
R216
4
C251
MUTE
C249
VA+
SCLK
UPDATED FOR MC4 PER DCR 040922-00
+3.3VD
23
E25
AOUTL
8
2.49K
1%
+5VA
0dBFS=2.0Vrms
C245
[13/D2]
4
D
[14/D5]
+5VA
2.00K
1%
+5VA
MAIN INPUT LEVEL CONTROL
16
CHANGED PER DCR 020827-00
MAIN A/D CONVERTER
R218
10
LEFT_MAIN_IN
3
C
100PF
R191
AGNDL
CHANGED PER DCR 020731-00
C283
+5VA
15
2
§
C
.1/25
12
CHANGED PER DCR 020430-00
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
[13/D5]
R45 §
RIGHT_MAIN_SW
2.7K
J19
0dBFS=2.0Vrms
1
MIC INPUT CONNECTOR
+15V
+3.3VA
[21/D3]
R44 §
§
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
DESCRIPTION
51
U46
E26
1/4W
-5VA
exicon
CONTRACT
NO.
APPROVALS
DRAWN
8
7
6
5
4
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
MIC INPUTS & MAIN A/D CONVERTER
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 15
SHEET
1
15 OF 23
10-19-2004_9:04
A
8
7
6
5
4
3
2
1
REVISIONS
+15V +5VAD
+5VAD
FB11
C121 §
C123§
1
2
3
4
* J20
[21/C3]
[4/C1,4/B4]
[4/C1,4/B4]
[4/C1,4/B4]
[4/C4]
[4/C4]
3
ZONE_DAC_RST/
4
ZONE_DAC_SCKI/
5
ZONE_DAC_SDI
6
ZONE_DAC_FSI/
7
ZONE_DAC_CS/
8
ZONE_DAC_CCLK
10
ZONE_DAC_CDATA
11
12
C
C122 §
C120 §
C118 §
.1/25
.1/25
.1/25
13
14
1
VD+
VA+
MCLK
VREFH
PD
AOUTL+
BICK
AOUTL-
SDATA
DZFR
LRCK
CAD1
CS
DZFL
CAD0
P/S
CCLK
VCOM
CDTI
AOUTR+
DIF0
AOUTR-
DIF1
AGND
DIF2
VREFL
BGND
DGND
U16
4
330/6.3
+7.45dB
R57 §
1.15K
1%
18
§
2.74K
C114 §
1%
2200PF
23
22
28
357
1%
§ C63
680PF
R56
17
NC
R104§
R55 §
1.15K
1%
357
1%
8
OPA2134
C56 §
2
-
U11 §
47/6
4
R54 §
1.15K
1%
15
§
R61§ 357
1%
2.74K
C115 §
C116§
§ C65
680PF
1%
2200PF
4.7
C117 §
.1/25
R106§
R59 §
1.15K
1%
357
1%
R52 §
47K
4
2
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
U6 §
5
12
ADG451
VDD
10
D
GND
LZONE_DACOUT
D
[16/B8]
U6 §
5
ZONE_DACOUT_SEL/
[21/C3]
ZONE_DIRECT_SEL/
[21/C3]
+15V +5VAD
8
E12
13
5
+
OPA2134
C59 §
6
-
U11 §
47/6
7
4
VCC
14
S
16
IN
VEE
R53 §
47K
4
-15V
C62 §
R58 §
CHANGED PER DCR 020430-00
7
D
GND
1
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
-15V
+15V
R60 §
ADG451
VDD
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
DESCRIPTION
680PF
R102§
R105§
VCC
11
S
9
IN
VEE
C61 §
NC
20
16
1
2.74K
1%
21
19
13
+
25
24
E11
3
12
REV
-15V
+15V +5VAD
-15V
27
26
0dBFS=4.0Vrms
+15V
0dBFS=1.7Vrms
R103§
9
[4/C4]
4.7
6
S
8
IN
VEE
ZONE2 D/A CONVERSION
AK4395
2
ZONE_DAC_MCKI
C119 §
VCC
LEFT_ZONE_IN
[13/C2]
4.7
[4/C1,4/B4]
13
§
E21
D
+5VA +5VR
12
ADG451
VDD
15
D
GND
U6
5
RZONE_DACOUT
[16/A8]
C
§
-15V
+15V +5VAD
680PF
13
2.74K
1%
VCC
3
S
1
IN
VEE
RIGHT_ZONE_IN
[14/C2]
4
12
2
D
GND
5
NOTES
ADG451
VDD
U6 §
-15V
E1
ZONE2 OUTPUT
LEVEL CONTROL
R23 §
+15V
C15 §
2.2/35
C16
AGNDL
16
LZONE_DACOUT
[16/D2]
[4/C4]
[4/C4]
[4/C4]
[21/B3]
[21/B3]
ZONE_VC_CLK
6
ZONE_VC_DATA
3
ZONE_VC_CS/
2
ZONE_VC_ZCEN
1
ZONE_VC_MUTE/
8
9
RZONE_DACOUT
[16/C2]
AINL
AOUTL
VD+
DGND
10
C11
§
47/25
4
C41§
CS
.1/25
5
§
R3
6
10K
C42
8
4.7
+5VAD
SDOUT
AINR
AOUTR
7
C14 §
11
47/25
VA13
C13
§
U1 §
§
§
R5
D1
1N4002
10K
+
100
1/4W
RY1
ZONE2 LEFT OUT
3
J1 §
FB2 §
§ C2
2
RCA
ZONE2 RIGHT OUT
3
150PF
§
.1/25
C12
§ C1
1
RCA
13
R4 §
16
J1 §
FB1 §
150PF
11
1
NC
100
1/4W
4
9
MUTE
R2 §
RELAY
§
ZCEN
10
R25 §
§
RZONE+
100
2.2/35
ZONE_RLY_CNTL
E2
-15V
ZONEOUT_MUTE/
[21/D3]
2N4401
Q1 §
8
7
B
0dBFS=2.0Vrms
§
R47
14
SDIN
AGNDR
A
PGA2310
VA+
SCLK
[21/C8]
+5VA
§
.1/25
12
15
LZONE+
100
6
5
4
3
[21/C8]
[21/B8]
exicon
CONTRACT
NO.
APPROVALS
DRAWN
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
ZONE2 DAC
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 16
SHEET
1
16 OF 23
10-21-2004_8:20
B
8
7
6
+5VAD
*
C163
C161
C159
4.7
4.7
330/6.3
C162
C160
C158
+13.5dB
0dBFS=1.7Vrms
.1/25
.1/25
[4/C1,4/C2,18/D8]
[4/C1,4/C4]
[4/C1,4/C2,18/C8]
[4/C4]
3
FRONT_DAC_RST/
4
MAIN_DAC_SCKI0/
5
FRONT_DAC_SDI
6
MAIN_DAC_FSI0/
7
FRONT_DAC_CS/
8
9
[4/C4,18/C8,19/C8,20/C8]
[4/C4,18/C8,19/C8,20/C8]
MAIN_DAC_CCLK
10
MAIN_DAC_CDATA
11
12
13
C
14
1
VD+
VA+
MCLK
VREFH
PD
AOUTL+
BICK
AOUTL-
SDATA
DZFR
LRCK
CAD1
CS
DZFL
CAD0
P/S
CCLK
VCOM
CDTI
AOUTR+
DIF0
AOUTR-
DIF1
AGND
DIF2
VREFL
BGND
DGND
1.21K
1%
18
C110
R97
330/6.3 R96
1%
R124
22
1.21K
1%
NC
28
2
+
C111
330/6.3
25
19
C157
U20
1%
1500PF
4.7
15
R100
330/6.3 R101
5.76K
C155
C156
16
C112
13
.1/25
R126
C113
1.21K
1%
330/6.3
280
1%
8
6
-
OPA2134
[21/A3]
7
[21/A3]
U15
4
C97
[13/D2]
+15V
+
VCC
6
S
8
IN
VEE
LEFT_DIR_IN
4
FRONT_DACOUT_SEL/
C94
49.9K
1%
10
LFRONT_DACOUT
2
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
[17/B8]
D
GND
U10
5
12
ADG451
VDD
D
7
GND
U10
5
-15V
C
+15V +5VAD
-15V
280
1% R98
D
CHANGED PER DCR 020430-00
FRONT_DIRECT_SEL/
220PF
R99
ADG451
VDD
1
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
+15V +5VAD
R92
5
12
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
DESCRIPTION
-15V
220PF
R123
1.21K
1%
4
C93
6.49K
1%
20
U15
4
280
1% R94
1%
R125
11
S
9
IN
VEE
1
-
R95
NC
21
VCC
-15V
49.9K
24
OPA2134
220PF
27
26
+15V +5VAD
E19
13
8
C95
1500PF
23
3
280
1%
5.76K
C154
17
0dBFS=8Vrms
+15V
.1/25
R122
2
1
REV
AK4395
[21/B4]
2
+5VA +5VR
J24
[4/C2]
3
LEFT & RIGHT FRONT D/A CONVERSION
1
2
3
4
FRONT_DAC_MCKI
4
REVISIONS
FB15
D
5
E20
13
220PF
VCC
14
S
16
IN
VEE
R93
6.49K
1%
4
12
ADG451
VDD
D
15
RFRONT_DACOUT
[17/A8]
GND
U10
5
-15V
+15V +5VAD
MAIN_RLY_CNTL
13
[14/D2]
LEFT & RIGHT FRONT
LEVEL CONTROL
VCC
3
S
1
IN
VEE
RIGHT_DIR_IN
E9
4
ADG451
VDD
D
2
GND
5
U10
-15V
+15V
B
12
R39
C39
2.2/35
C40
AGNDL
[17/D3]
[4/D4,18/B8,19/B8,20/B8]
[4/C4,18/B8,19/B8,20/A8]
[4/D4]
[21/B3]
[21/A3]
[17/C3]
LFRONT_DACOUT
16
MAINOUT_VC_CLK
6
MAINOUT_VC_DATA
3
FRONT_VC_CS/
2
FRONT_VC_ZCEN
1
FRONT_VC_MUTE/
8
9
RFRONT_DACOUT
AINL
VA+
SCLK
0dBFS=8.1Vrms
R51
10
C35
14
47/25
4
VD+
C53
SDIN
5
DGND
.1/25
6
R19
10K
C54
4.7
SDOUT
AINR
AOUTR
10
4
8
+5VAD
7
1
NC
11
47/25
13
C37
+
U5
R20
16
R21
10K
C9
1
RCA
LEFT FRONT OUT
3
13
C38
VA-
100
1/4W
J5
FB9
150PF
11
9
MUTE
R18
RELAY
ZCEN
AGNDR
A
PGA2310
AOUTL
CS
100
1/4W
RY5
J5
FB10
C10
2
RCA
RIGHT FRONT OUT
3
150PF
.1/25
2.2/35
R41
-15V
RFRONT+
100
E10
7
exicon
CONTRACT
NO.
C36
8
B
[21/C8]
+5VA
.1/25
12
15
LFRONT+
100
6
5
4
3
[21/C8]
APPROVALS
DRAWN
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
L/R FRONT DACS
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 17
SHEET
1
17 OF 23
10-19-2004_8:58
[18/A3,19/B8,20/B8]
8
7
6
5
4
3
2
1
REVISIONS
+5VAD
+5VA +5VR
REV
CENTER & SUB D/A CONVERSION
FB14
C151
C149
4.7
4.7
330/6.3
C152
C150
C148
C153
D
1
2
3
4
*
+13.5dB
0dBFS=1.7Vrms
.1/25
.1/25
.1/25
J23
AK4395
2
[4/B2]
[19/D8,20/D8,21/B3]
[4/C1,4/C2,17/D8]
[4/C1,4/B4]
[4/C1,4/C2,17/C8]
[4/C4,19/C8,20/C8]
CENTER_DAC_MCKI
3
MAIN_DAC_RST/
4
MAIN_DAC_SCKI0/
5
CENTER_DAC_SDI
6
MAIN_DAC_FSI0/
7
MAIN_DAC_CS/
8
9
[4/C4,17/C8,19/C8,20/C8]
[4/C4,17/C8,19/C8,20/C8]
MAIN_DAC_CCLK
10
MAIN_DAC_CDATA
11
12
13
C
C106
R117
14
1
VD+
MCLK
PD
AOUTL+
BICK
AOUTL-
SDATA
DZFR
LRCK
CAD1
CS
DZFL
CAD0
CCLK
DIF0
AOUTR-
DIF1
AGND
DIF2
VREFL
NC
28
R119
1.21K
1%
330/6.3
2
-
U14
280
1% R84
19
C145
C146
16
1500PF
4.7
15
C147
U19
.1/25
R90
330/6.3 R91
5.76K
1.21K
1%
R121
C109
1.21K
1%
330/6.3
4
280
1%
1%
8
6
4
C89
[13/B2]
OPA2134
7
[19/C4,20/C4,21/B3]
U14
[19/C4,20/C4,21/B3]
C86
49.9K
1%
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
[18/B8]
D
U9
6
S
8
IN
VEE
CNTR_DIR_IN
MAIN_DACOUT_SEL/
4
ADG451
VDD
D
7
GND
U9
5
MAIN_DIRECT_SEL/
-15V
C
+15V +5VAD
-15V
280
1% R88
CNTR_DACOUT
2
GND
12
VCC
220PF
R89
10
CHANGED PER DCR 020430-00
+15V +5VAD
+15V
+
D
5
13
5
ADG451
VDD
1
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
-15V
R82
R118
20
11
S
9
IN
VEE
220PF
6.49K
1%
C108
12
VCC
C85
1%
R120
13
1
4
R85
NC
21
BGND
+
OPA2134
-15V
25
24
E17
3
C87
49.9K
26
8
+15V +5VAD
220PF
27
VCOM
AOUTR+
DGND
22
C107
280
1%
1%
1500PF
23
P/S
CDTI
C144
17
VREFH
R87
330/6.3 R86
5.76K
1.21K
1%
18
VA+
0dBFS=8Vrms
+15V
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
DESCRIPTION
E18
13
220PF
12
VCC
14
S
16
IN
VEE
R83
6.49K
1%
4
ADG451
VDD
D
15
SUB_DACOUT
[18/A8]
GND
U9
5
-15V
+15V +5VAD
13
[14/B2]
E7
CENTER & SUB
LEVEL CONTROL
3
S
1
IN
VEE
SUB_DIR_IN
4
+15V
R35
C33
C34
[4/D4,17/B8,19/B8,20/B8]
[4/C4,17/A8,19/B8,20/A8]
[4/D4]
[21/B3]
[19/A8,20/A8,21/B3]
[18/C3]
16
CNTR_DACOUT
MAINOUT_VC_CLK
6
MAINOUT_VC_DATA
3
CENTER_VC_CS/
2
CENTER_VC_ZCEN
1
MAINOUT_VC_MUTE/
8
SUB_DACOUT
9
AINL
VA+
47/25
5
DGND
.1/25
6
R15
10K
C51
8
4.7
+5VAD
7
D2
47/25
VA13
+
C32
11
AOUTR
C31
U4
R17
1N4002
10K
R16
16
100
1/4W
RY4
C7
1
RCA
CENTER OUT
3
J4
FB8
C8
2
RCA
SUB OUT
3
R37
SUB+
100
2.2/35
8
J4
FB7
150PF
C30
MAIN_RLY_CNTL
E8
-15V
MAINOUTS_MUTE/
[21/D3]
must be low on power-up
2N4401
6
5
[21/C8]
exicon
CONTRACT
NO.
[17/B8,19/B8,20/B8]
APPROVALS
DRAWN
Q2
7
B
[21/C8]
13
.1/25
FROM HOST
CENTER+
150PF
11
1
NC
100
1/4W
4
9
SDOUT
R14
RELAY
ZCEN
10
-15V
0dBFS=8.1Vrms
C29
C50
AINR
U9
10
4
SDIN
MUTE
GND
5
R50
14
VD+
SCLK
AGNDR
A
PGA2310
AOUTL
CS
2
+5VA
.1/25
12
AGNDL
[18/D3]
D
100
2.2/35
15
ADG451
VDD
4
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
CENTER/SUB DACS
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 18
SHEET
1
18 OF 23
10-19-2004_8:58
B
12
VCC
8
7
6
5
4
3
2
1
REVISIONS
+5VAD
+5VA +5VR
REV
LEFT & RIGHT SIDE D/A CONVERSION
FB13
C141
C139
4.7
4.7
330/6.3
C142
C140
C138
C143
D
*
1
2
3
4
.1/25
.1/25
+13.5dB
0dBFS=8Vrms
0dBFS=1.7Vrms
.1/25
J22
R112
AK4395
2
[4/B2]
[18/D8,20/D8,21/B3]
[4/C1,4/C2,20/D8]
[4/C1,4/B4]
[4/C1,4/C2,20/C8]
[4/C4,18/C8,20/C8]
SIDE_DAC_MCKI
3
MAIN_DAC_RST/
4
MAIN_DAC_SCKI1/
5
SIDE_DAC_SDI
6
MAIN_DAC_FSI1/
7
MAIN_DAC_CS/
8
9
[4/C4,17/C8,18/C8,20/C8]
[4/C4,17/C8,18/C8,20/C8]
MAIN_DAC_CCLK
10
MAIN_DAC_CDATA
11
12
13
C
14
1
VD+
MCLK
AOUTL+
BICK
AOUTL-
SDATA
DZFR
LRCK
CAD1
CS
DZFL
CAD0
22
AOUTR+
DIF0
AOUTR-
DIF1
AGND
DIF2
VREFL
DGND
NC
28
330/6.3 R76
5.76K
280
1%
1%
R114
C103
1.21K
1%
330/6.3
2
-
U13
280
1% R74
1.21K
1%
19
16
C137
U18
R80
330/6.3 R81
5.76K
280
1%
1%
.1/25
R116
C105
1.21K
1%
330/6.3
8
6
-
[13/A2,20/C4]
OPA2134
7
4
[18/C4,20/C4,21/B3]
U13
[18/C4,20/C4,21/B3]
VCC
6
S
8
IN
VEE
LSUR_DIR_IN
MAIN_DACOUT_SEL/
MAIN_DIRECT_SEL/
220PF
C78
280
1% R78
49.9K
1%
D
10
LSIDE_DACOUT
2
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
[19/B8]
D
GND
U8
5
4
12
ADG451
VDD
D
7
GND
U8
5
-15V
C
+15V +5VAD
-15V
R79
ADG451
VDD
CHANGED PER DCR 020430-00
+15V +5VAD
+15V
+
12
1
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
-15V
13
5
C81
1500PF
4.7
15
C104
C135
C136
4
R72
R113
20
11
S
9
IN
VEE
220PF
6.49K
1%
R115
VCC
1
4
R75
1%
21
13
C77
25
BGND
+
OPA2134
-15V
NC
24
E15
3
C79
49.9K
26
8
+15V +5VAD
220PF
27
VCOM
CDTI
R77
1500PF
23
P/S
CCLK
C102
C134
17
VREFH
PD
1.21K
1%
18
VA+
+15V
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
DESCRIPTION
E16
13
220PF
VCC
14
S
16
IN
VEE
R73
6.49K
1%
4
12
ADG451
VDD
D
15
RSIDE_DACOUT
[19/A8]
GND
U8
5
-15V
+15V +5VAD
13
[14/A2,20/B4]
E5
LEFT & RIGHT SIDE
LEVEL CONTROL
VCC
3
S
1
IN
VEE
RSUR_DIR_IN
4
+15V
R31
B
C27
C28
[19/D3]
[4/D4,17/B8,18/B8,20/B8]
[4/C4,17/A8,18/B8,20/A8]
[4/D4]
[21/B3]
[18/A8,20/A8,21/B3]
[19/C3]
16
MAINOUT_VC_CLK
6
MAINOUT_VC_DATA
3
SIDE_VC_CS/
2
SIDE_VC_ZCEN
1
MAINOUT_VC_MUTE/
8
RSIDE_DACOUT
9
AINL
5
DGND
47/25
.1/25
6
R11
10K
C48
4.7
4
8
+5VAD
U8
-15V
LSIDE+
7
1
NC
47/25
VA13
U3
100
1/4W
+
R12
16
R13
10K
J3
FB5
C5
1
RCA
LEFT SIDE OUT
3
13
C26
11
AOUTR
C25
B
[21/C8]
150PF
11
9
SDOUT
R10
RELAY
ZCEN
AGNDR
A
C23
C47
SDIN
10
5
10
4
VD+
SCLK
AINR
GND
R49
14
AOUTL
MUTE
2
0dBFS=8.1Vrms
PGA2310
VA+
CS
D
+5VA
.1/25
12
AGNDL
LSIDE_DACOUT
ADG451
VDD
100
2.2/35
15
12
100
1/4W
RY3
J3
FB6
C6
2
RCA
RIGHT SIDE OUT
3
150PF
.1/25
exicon
CONTRACT
NO.
C24
2.2/35
R33
-15V
RSIDE+
100
E6
8
7
6
5
4
3
[21/C8]
APPROVALS
DRAWN
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
L/R SIDE DACS
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 19
SHEET
1
19 OF 23
10-19-2004_8:58
[17/B8,18/A3,20/B8]
MAIN_RLY_CNTL
8
7
6
5
4
3
2
1
REVISIONS
+5VAD
+5VA +5VR
REV
LEFT & RIGHT REAR D/A CONVERSION
FB12
C131
C129
4.7
4.7
330/6.3
C132
C130
C128
C133
D
*
1
2
3
4
.1/25
.1/25
+13.5dB
.1/25
J21
R107
AK4395
2
[4/B2]
[18/D8,19/D8,21/B3]
[4/C1,4/C2,19/D8]
[4/C1,4/B4]
[4/C1,4/C2,19/C8]
[4/C4,18/C8,19/C8]
REAR_DAC_MCKI
3
MAIN_DAC_RST/
4
MAIN_DAC_SCKI1/
5
REAR_DAC_SDI
6
MAIN_DAC_FSI1/
7
MAIN_DAC_CS/
8
9
[4/C4,17/C8,18/C8,19/C8]
[4/C4,17/C8,18/C8,19/C8]
MAIN_DAC_CCLK
10
MAIN_DAC_CDATA
11
12
13
C
14
1
VD+
VA+
MCLK
PD
AOUTL+
BICK
AOUTL-
SDATA
DZFR
LRCK
CAD1
CS
DZFL
CAD0
R67
330/6.3 R66
5.76K
280
1%
1%
NC
R109
C99
1.21K
1%
330/6.3
VCOM
DIF0
AOUTR-
DIF1
AGND
DIF2
VREFL
+
OPA2134
2
-
U12
280
1% R64
1%
1.21K
1%
19
C127
U17
280
1%
1%
.1/25
R111
C101
1.21K
1%
330/6.3
8
6
-
OPA2134
U12
1%
12
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
[20/B8]
D
ADG451
VDD
D
7
GND
4
U7
5
MAIN_DACOUT_SEL/
[18/C4,19/C4,21/B3]
-15V
MAIN_DIRECT_SEL/
[18/C4,19/C4,21/B3]
C
+15V +5VAD
C70
49.9K
CHANGED PER DCR 020731-00
U7
5
6
S
8
IN
VEE
-15V
280
1% R68
2
GND
VCC
LSUR_DIR_IN
[13/A2,19/C4]
220PF
R69
CHANGED PER DCR 020430-00
+15V +5VAD
7
4
LREAR_DACOUT
10
1
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
-15V
+15V
+
D
4
13
5
C73
1500PF
4.7
15
R70
330/6.3 R71
5.76K
C125
C126
16
C100
ADG451
VDD
11
S
9
IN
VEE
R62
R108
R110
12
VCC
220PF
6.49K
1%
21
13
1
4
R65
NC
20
BGND
3
C69
25
AOUTR+
E13
-15V
49.9K
24
+15V +5VAD
220PF
27
26
8
C71
1500PF
28
CDTI
DGND
+15V
C98
C124
23
22
P/S
CCLK
1.21K
1%
18
17
VREFH
0dBFS=8Vrms
0dBFS=1.7Vrms
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
DESCRIPTION
E14
13
220PF
12
VCC
R63
6.49K
1%
ADG451
VDD
14
S
16
IN
VEE
D
RREAR_DACOUT
15
[20/A8]
GND
4
U7
5
-15V
+15V +5VAD
MAIN_RLY_CNTL
13
RSUR_DIR_IN
[14/A2,19/B4]
3
S
1
IN
VEE
E3
LEFT & RIGHT REAR
LEVEL CONTROL
ADG451
VDD
D
2
GND
4
5
U7
-15V
+15V
B
12
VCC
R27
C21
2.2/35
C22
AGNDL
[20/D3]
[4/D4,17/B8,18/B8,19/B8]
[4/C4,17/A8,18/B8,19/B8]
[4/D4]
[21/B3]
[18/A8,19/A8,21/B3]
[20/C3]
16
LREAR_DACOUT
MAINOUT_VC_CLK
6
MAINOUT_VC_DATA
3
REAR_VC_CS/
2
REAR_VC_ZCEN
1
MAINOUT_VC_MUTE/
8
RREAR_DACOUT
9
AINL
10
C17
14
AOUTL
SCLK
47/25
4
VD+
5
DGND
.1/25
6
R7
+5VAD
AINR
AOUTR
10
7
1
NC
11
47/25
13
C19
+
U2
R8
16
R9
10K
C3
1
RCA
LEFT REAR OUT
3
13
C20
VA-
J2
FB3
150PF
11
9
SDOUT
100
1/4W
4
8
4.7
ZCEN
MUTE
R6
RELAY
10K
C45
C44
SDIN
AGNDR
A
0dBFS=8.1Vrms
R48
PGA2310
VA+
CS
B
[21/C8]
+5VA
.1/25
12
15
LREAR+
100
100
1/4W
RY2
J2
FB4
C4
2
RCA
RIGHT REAR OUT
3
150PF
C18
2.2/35
R29
-15V
RREAR+
100
E4
8
7
exicon
CONTRACT
NO.
.1/25
6
5
4
3
[21/C8]
APPROVALS
DRAWN
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
L/R REAR DACS
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 20
SHEET
1
20 OF 23
10-19-2004_8:58
[17/B8,18/A3,19/B8]
8
7
6
5
4
3
2
1
REVISIONS
REV
+3.3VD
FB24
+3.3VA
74VHC273
TO XLR BD (MC-8B)
+5VD +15V
[17/B3]
[18/A3]
[18/B3]
C
[19/A3]
[19/B3]
[20/A3]
[20/B3]
[16/A2]
[16/B2]
[21/D3]
[16/A2]
LFRONT+
SUB+
CENTER+
RSIDE+
LSIDE+
RREAR+
LREAR+
RZONE+
LZONE+
EXPOUTS_MUTE/
ZONE_RLY_CNTL
[4/A4]
RFRONT-
§
R42
LFRONT-
§
R40
100
SUB-
§
R38
100
CENTER-
§
R36
100
RSIDE-
§
R34
100
LSIDE-
§
R32
100
RREAR-
§
R30
100
LREAR-
§
R28
100
ANLG_REG0_CS/
3
4
7
8
13
14
17
18
11
1
10
IODX0
IODX1
IODX2
IODX3
IODX4
IODX5
IODX6
IODX7
§
R26
100
LZONE-
§
R24
100
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
330
RED
20
2
5
6
9
12
15
16
19
D23
NC
R22
R249
390
330
MAINOUTS_MUTE/
EXPOUTS_MUTE/
§ R1
§ R221
§ R220
680
1K
1K
ZONEOUT_MUTE/
MIC_SEL0
MIC_SEL1
[4/A4]
ANLG_REG1_CS/
IODX0
IODX1
IODX2
IODX3
IODX4
IODX5
IODX6
IODX7
3
4
7
8
13
14
17
18
11
1
10
1D
2D
3D
4D
5D
6D
7D
8D
CLK
CLR
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
U53
5
3
74VHC273
6
U53
74LVC14
4
[18/A8]
[21/B8]
20
2
5
6
9
12
15
16
19
1
2
R235
R238
R239
R240
R237
R236
1K
1K
1K
1K
1K
1K
ANLG_4_5_DIR_IN/
[13/A5,14/A5]
ANLG_7_8_DIR_IN/
[13/A5,14/A5]
MAIN_ANLG_SEL0
MAIN_ANLG_SEL1
MAIN_ANLG_SEL2
MAIN_ANLG_EN
MAIN_ADC_RST/
MAIN_ADC_96K_EN
[13/D5,14/D5]
[13/D5,14/D5]
[13/D5,14/D5]
[13/D5,14/D5]
[15/A2]
[15/B2]
*
C
U51
[4/A4]
ANLG_REG3_CS/
3
4
7
8
13
14
17
18
11
1
10
IODX0
IODX1
IODX2
IODX3
IODX4
IODX5
IODX6
IODX7
1D
2D
3D
4D
5D
6D
7D
8D
CLK
CLR
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
[4/A4]
ANLG_REG4_CS/
IODX0
IODX1
IODX2
IODX3
IODX4
IODX5
IODX6
IODX7
3
4
7
8
13
14
17
18
11
1
10
1D
2D
3D
4D
5D
6D
7D
8D
CLK
CLR
GND
20
2
5
6
9
12
15
16
19
§
§
§
§
§
§
§
§
R231
R232
R233
R234
R230
R229
R228
R227
1K
1K
1K
1K
1K
1K
1K
1K
ZONE_ANLG_SEL0
ZONE_ANLG_SEL1
ZONE_ANLG_SEL2
ZONE_ANLG_EN
ZONE_DAC_RST/
ZONE_DACOUT_SEL/
ZONE_DIRECT_SEL/
ZONE_VC_MUTE/
R223
R224
1K
1K
FRONT_VC_ZCEN
CENTER_VC_ZCEN
R226
R225
1K
1K
SIDE_VC_ZCEN
REAR_VC_ZCEN
§ R222
1K
ZONE_VC_ZCEN
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
20
2
5
6
9
12
15
16
19
NC
1
2
J25
*
74VHC273
[4/A4]
DBA_RST/
ANLG_REG6_CS/
3
4
7
8
13
14
17
18
11
1
10
IODX0
IODX1
IODX2
IODX3
IODX4
IODX5
IODX6
IODX7
1D
2D
3D
4D
5D
6D
7D
8D
CLK
CLR
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
[17/A8]
[18/A8]
[19/A8]
[20/A8]
B
U49
IODX[7:0]
[13/C5,14/C5]
[13/C5,14/C5]
[13/C5,14/C5]
[13/C5,14/C5]
[16/D7]
[16/C4]
[16/C4]
[16/A8]
U50 §
74VHC273
B
[16/A8]
E22
20
2
5
6
9
12
15
16
19
R245
R246
R247
R248
R244
R243
R242
R241
1K
1K
1K
1K
1K
1K
1K
1K
MAIN_DAC_RST/
MAIN_DACOUT_SEL/
MAIN_DIRECT_SEL/
MAINOUT_VC_MUTE/
FRONT_DAC_RST/
FRONT_DACOUT_SEL/
FRONT_DIRECT_SEL/
FRONT_VC_MUTE/
[18/D8,19/D8,20/D8]
[18/C4,19/C4,20/C4]
[18/C4,19/C4,20/C4]
[18/A8,19/A8,20/A8]
[17/D8]
[17/C4]
[17/C4]
[17/A8]
E23
U52
A
exicon
CONTRACT
NO.
APPROVALS
DRAWN
8
7
D
[16/A8]
[15/D7]
[15/D7]
74LVC14
J26
74VHC273
-15V
[1/B3]
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
R250
U48
J28 §
[3/D6]
1D
2D
3D
4D
5D
6D
7D
8D
CLK
CLR
GND
100
RZONE-
2
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
6
5
4
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
XLR BD CONN,CONTROL REG
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 21
SHEET
1
21 OF 23
10-19-2004_8:58
[17/A3]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
CHANGED PER DCR 020430-00
+3.3VA
10
RFRONT+
1
+3.3VA
R251
D
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
DESCRIPTION
8
7
6
5
4
3
2
1
REVISIONS
AC
INPUT
REAR PANEL
POWER SWITCH
REV
NEUTRAL
FERRITE
SLEEVE
LINE
D
NC
1
2
3
1
2
3
NEUTRAL
NC
LINE
+5V @ 10A
-5V @ 0.8A
+15V @ 3.0A
-15V @ 0.8A
1.5 TURNS
1
2
3
4
5
6
7
8
9
10
11
12
+5V
+5V
+5V
+5V
GND
GND
GND
GND
+15V
+15V
-5V
-15V
POWER SUPPLY
80W
1
2
3
4
5
6
7
8
9
10
11
12
NC
2
3
NC
FERRITE
5
6
7
SLEEVE
5
6
7
9
9
11
12
NC
2
3
1.5 TURNS 11
12
NC
NC
+5V
GND
GND
1
2
3
4
+5V
-5V
NC
+15V
GND
-15V
1
2
3
4
5
6
TO MAIN BD,
DIGITAL
J31
TO MAIN BD,
ANALOG
J26
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
3/2/04
GAP
5/18/04
RWH
9/24/04
AT
9/27/04
DESCRIPTION
1
CHANGED PER DCR 020430-00
2
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
CHANGED PWR SUPPLY PER ECO 031111-00
5
UPDATED FOR MC4 PER DCR 040922-00
+5VAD
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
5/25/04
KAB
5/26/04
CW
10/14/04
AT
9/27/04
D
+5VAD SOURCE
+5VAD
FB29
+5V
-5VA SOURCE
2.5TURN
C321
C320
.22/50
150PF
C309
100/25
C310
.22/50
D34
C308
C323
1A
150PF
C322
.22/50
1K
R278
S
C313
.22/50
150PF
+15V
2.5TURN
G IRL3803
ANALOG POWER
C312
100/25
FB30 C311
150PF
D36
1
2
3
4
5
6
C
D38
7805
FROM POWER SUPPLY
-15V
+5
-5
NC
+15
GND
-15
C324
.22/50
150PF
2.5TURN
100/25
C316
C330
C314
.22/50
C329
150PF
C328
10/10
-15V2
.1/25
D37
GND
2
.1/25
C315
+15V
CASE=GND
3
VIN
VOUT
1
+15V SOURCE
FB31
C325
TEST POINTS
+5VA
1N4002
+15V
Q3
J32
+5VA
+5VA REGULATOR
-5VA
1N4002
D
+15V
+3.3VD
GNDA
D35
1A
C327
C326
.22/50
150PF
100/25
FB32 C317
C318
C319
.22/50
150PF
1
.1/25
C331
*
2.5TURN
U59
*
1N4002
.1/25
C333
VIN
VOUT
CASE=VIN
7905
D40
-15V
3
*
*
10/10
*
-15V
-15V
*
C332
1N4002
B
GNDA2
GNDA3
GNDA4
GNDA5
GNDA6
GNDA7
GNDA8
GNDA9
GNDA10
GNDA11
D39
GND
2
+5VA3
+3.3VD2
-5VA REGULATOR
-15V SOURCE
C
+5VA
-15V
1N4002
U63
+15V2
+15V3
-5VA
SEE NOTE 1
GNDD2
GNDD3
GNDD4
GNDD5
GNDD6
GNDD7
GNDD8
GNDD9
GNDD10
GNDD11
B
-5VA
NOTES
+15V
DIGITAL POWER
+5VD
D48
+5V POWER CONNECTOR
J45
FROM POWER SUPPLY
1
2
3
4
RED
RED
BLACK
BLACK
+5VD
C409
100/25
C410
.22/50
+5VR REGULATOR
D24
+3.3VD
1N4002
1
LMS1585A
C408
L1
150PF
GNDD
3
24UH
C404
C402
.1/25
560/35
CASE=VOUT
2
VIN
VOUT
TO-220
GND
1
U96
1 INSTALL FOR USE WITH POWER SUPPLIES WITHOUT -5V.
E34
1N4002
+3.3VD
3.3V REGULATOR
+5VD
+5VR
C291
.1/25
CASE=GND
3
VIN
VOUT
MC7805
TERM
4
GND
2
U60
D25
1N4002
C403
10/10
+5VA +5VD
J29
+3.3V CONNECTOR - USED ONLY IF ALTERNATE SUPPLY USED
J44
FROM POWER SUPPLY
8
1
2
*
100/25
RED
BLACK
C405
1
2
3
4
*C406 *C407
.22/50
TO VIDEO BOARD
150PF
*
APPROVALS
DRAWN
-5VA
7
6
5
exicon
CONTRACT
NO.
4
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
POWER SUPPLY
SIZE
B
CODE
NUMBER
060-15259
REV
5
FILE NAME
15259-6 . 22
SHEET
1
22 OF 23
10-19-2004_8:58
A
8
7
6
5
4
3
2
1
REVISIONS
REV
D
+/-15V BYPASS CAPACITORS
DRAFTER
CHECKER
RWH
5/16/02
KB
6/4/02
RWH
8/1/02
CBV
8/5/02
RWH
8/30/02
KB
9/12/02
RWH
9/24/04
AT
9/27/04
DESCRIPTION
1
CHANGED PER DCR 020430-00
2
CHANGED PER DCR 020731-00
3
CHANGED PER DCR 020827-00
4
UPDATED FOR MC4 PER DCR 040922-00
+15V
§
C58
.1/25
§
C43
.1/25
§
C60
C67
C68
C75
C76
C83
C84
C91
C92
C169
C175
C181
C187
C46
C49
C52
C55
C64
C72
C80
C88
C96
C168
C174
C180
C186
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
§
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
C193
.1/25
.1/25
.1/25
C205
C211
C233
C235
C237
C198
C204
C210
C234
C239
C240
.1/25
C192
.1/25
C199
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
§
.1/25
.1/25
.1/25
C238
C242
C252
C254
C256
C241
C243
C253
C258
C259
.1/25
§
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
§
.1/25
.1/25
.1/25
C257
C261
C260
C262
.1/25
§
.1/25
.1/25
.1/25
C298
.1/25
Q.C.
AUTH.
CW
6/24/02
KB
6/26/02
CW
8/5/02
KB
8/14/02
CW
9/12/02
KB
9/12/02
CW
10/14/04
AT
9/27/04
D
C300
.1/25
-15V
+5VD
+5V DIGITAL BYPASS CAPACITORS
+/-5V ANALOG BYPASS CAPACITORS
+5VA
C216
.1/25
C
C362
§
C345
C306
.1/25
§
C346
.1/25
§
C347
.1/25
C358
C348
.1/25
.1/25
§
C359
.1/25
§
C360
.1/25
C361
.1/25
.1/25
C277
C281
C280
C284
.1/25
§
C363
.1/25
C364
.1/25
C365
.1/25
C383
.1/25
C384
.1/25
C386
.1/25
C387
.1/25
C388
.1/25
C
C390
.1/25
.1/25
.1/25
C391
C394
.1/25
C397
.1/25
C398
.1/25
.1/25
.1/25
C401
.1/25
.1/25
-5VA
+5VAD BYPASS CAPACITORS
+5VAD
§
C66
C57
.1/25
C74
.1/25
C82
.1/25
C90
.1/25
C236
.1/25
C255
.1/25
.1/25
+3.3VD
+3.3V DIGITAL BYPASS CAPACITORS
B
C232
C344
C368
C380
.1/25
.1/25
.1/25
§
C349
C350
C351
C352
C353
C354
C355
C356
C366
C367
C369
C370
C371
C372
C373
C374
C375
C376
C377
C378
C379
C381
C382
C389
C395
C399
C400
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
B
.1/25
.1/25
.1/25
+3.3V ANALOG BYPASS CAPACITORS
+3.3VA
C285
.1/25
§
C286
C287
.1/25
.1/25
C288
.1/25
C289
.1/25
exicon
CONTRACT
NO.
C290
.1/25
APPROVALS
DRAWN
8
7
6
5
4
3
DATE
RWH
2/15/02
CHECKED
CV
3/29/02
Q.C.
CW
4/3/02
ISSUED
KAB
4/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MAIN BD,MC4/MC8
BYPASS CAPACITORS
SIZE
B
CODE
NUMBER
060-15259
REV
4
FILE NAME
15259-6 . 23
SHEET
1
23 OF 23
10-19-2004_9:06
A
8
7
6
5
4
3
2
1
REVISIONS
REV
D
+5VV
S-VIDEO INPUTS
J13
2N3904
4
1
C45
SY1
[2/C8,3/C8]
R80
R85
47/6
R81
Q9
22
R78
R82
470K
100K
3
2
1
75.0
1%
C41
SY2
R77
47/6
R73
R72
J12
Q7
22
R70
R74
470K
100K
3
2
1
75.0
1%
C37
R69
47/6
R65
[2/B8]
22
470K
CHANGED SHEET 4 PER EC0 021105-00
4
UPDATED FOR MC4 PER DCR 040922-00
D
R84
SC1
22
[2/B8,3/B8]
Q8
R76
R75
22
R71
SC2
C
[2/B8,3/B8]
1K
R64
R62
R66
3
2N3904
75.0
1%
J11
Q5
CHANGED SHEETS 3,5 PER DCR 020715-00
-5VV
+5VV
1K
4
SY3
R83
C38
5
2N3904
3
SC2B
.1/25
-5VV
+5VV
[2/C8,3/C8]
2
1K
4
2
Q10
R79
1K
2N3904
[2/C8,3/C8]
CHANGED PER DCR 020523-00
2N3904
75.0
1%
5
1
Q.C.
AUTH.
RWH
6/5/02
KAB
6/5/02
RWH
8/14/02
KB
8/14/02
RWH
11/12/02
KAB
11/12/02
CW
10/14/04
AT
9/27/04
+5VV
[2/B8]
C42
.1/25
-5VV
+5VV
C
SC1B
DRAFTER
CHECKER
CW
6/3/02
ECM
6/4/02
CW
8/5/02
ECM
8/13/02
CW
11/11/02
ECM
11/12/02
RWH
9/27/04
AT
9/27/04
DESCRIPTION
100K
3
2
1
75.0
1%
SC3B
-5VV
+5VV
[2/B8]
2N3904
C34
.1/25
75.0
1%
5
Q6
R68
R67
22
R63
1K
SC3
[2/B8,3/B8]
NOTES
1 UNLESS OTHERWISE INDICATED, RESISTORS ARE 1/10W
1K
2 UNLESS OTHERWISE INDICATED, RESISTORS ARE 5%
R56
4
4
B
C33
SY4
[2/C8,3/C8]
R61
47/6
R57
Q3
22
R54
R58
470K
100K
J10
2N3904
1
.1/25
5
C29
R53
470K
47/6
R49
R48
22
R46
R50
75.0
1%
R59
22
[2/B8]
1
.1/25
1K
CHASSIS
GROUND
B
Q15, R172, RY6, U38, Y1.
7 COMPONENTS MARKED WITH
*
ARE NOT INSTALLED.
8 COMPONENTS MARKED WITH §
Q2
R52
R51
22
R47
SC5
ARE NOT INSTALLED ON MC4.
[2/A8,3/B8]
DOCUMENT CONTROL BLOCK: #060-15269
SHEET REVISION TITLE
1 OF 8
4
S-VIDEO INPUTS
MONITOR
2 OF 8
2
ZONE
3 OF 8
3
COMPONENT VIDEO
4 OF 8
3
ON-SCREEN DISPLAY
5 OF 8
3
SYNC STRIPPER
6 OF 8
2
2
CONTROL REGISTERS
7 OF 8
PWR,SPDIF,MAIN&RCA BD CONNS
2
8 OF 8
-5VV
© 2004 Lexicon, Inc.
CONTRACT
NO.
A
exicon
OCT 27 2004
RELEASED COPY
8
7
6
5
POWER
GROUND
6 LAST REFERENCE DESIGNATORS USED ON: C148, CP2, D9, FB4, J19, L1,
[2/B8,3/B8]
1K
-5VV
ANALOG
GROUND
2N3904
75.0
1%
5
DIGITAL
GROUND
5 [XX/XX] DENOTES [SHEET NUMBER/SECTOR]
SC4
-5VV
+5VV
C26
3
2
SC5B
100K
J9
Q1
R60
1K
4
SY5
4
Q4
R55
1K
2N3904
[2/C8,3/C8]
3 UNLESS OTHERWISE INDICATED, CAPACITORS ARE UF/V.
2N3904
75.0
1%
-5VV
+5VV
5
[2/B8]
C30
3
2
75.0
1%
SC4B
-5VV
+5VV
4
3
APPROVALS
DRAWN
RWH
CHECKED
ECM
Q.C.
CW
ISSUED
KB
2
DATE
3/13/02
3/18/02
3/19/02
3/19/02
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,VIDEO BD, MC4/MC8
S-VIDEO INPUTS
SIZE
B
CODE
NUMBER
FILE NAME
15269-4 . 1
SHEET
1
REV
4
060-15269
1
OF
8
10-19-2004_8:43
-5VV
+5VV
8
7
6
5
4
3
2
1
REVISIONS
+5VV
74HC4051
16
[3/D8,8/B6]
[3/D8,8/B6]
[3/D8,8/B6]
D
[8/B6]
[8/B6]
[7/C5]
[7/C5]
[7/C5]
[7/C5]
CVID4
CVID2
NC
CVID1
NC
CVID3
CVID5
13
14
15
12
1
5
2
4
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
VCC
3
6
MCVID_EN/
R121
BPCOR
[6/A5]
475
1%
OUT/IN
11
A
10
B
9
C
MVID_SEL0
MVID_SEL1
MVID_SEL2
100K
MY
U18
10/16
-5VV
3
+
2
-
+5VV
[1/B7,3/C8]
[1/C7,3/C8]
[1/C7,3/C8]
[1/C7]
[1/B7]
SY4
SY2
SY1
SY3
SY5
NC
NC
6
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
R165
VCC
750
4
4
[5/C2]
750
36K
[1/D5]
[1/C5]
[1/B5]
SC1B
SC3B
SC5B
NC
NC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
B
1
U1
X
U17
[7/C5]
[1/C4,3/B8]
[1/C4]
[1/B4]
SC1
SC3
SC5
NC
NC
+5VV
GND V-
7
1
2
3
2
UPDATED FOR MC4 PER DCR 040922-00
SY_MAIN
75.0
1%
D
U26
6
V+
MSTHRU/
IN1
EL4421
Y
15K
Av = 1
VOUT
IN2
R152
-IN
A0
GND V-
7
1
2
3
8
R151
C130
75.0
1%
.1/25
U27
J2
3
SC_MAIN
4
1
2
5
R3
10K
OSD
-5VV
MAIN
S-VIDEO
OUT
10
S
6
INH
VSS VEE
8
7
C
+5VV
R134
10K
Q14
R133
VCC
10K
2N3904
3
OUT/IN
C113
2N3906
.1/25
R131
Q15
R132
1K
33K
CVID_ZON
[3/A3]
C112
.1/25
INH
VSS
[7/B5]
1%
1.15K
MORPHEN/
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
U19
1%
1.15K
[5/C2]
74HC4051
MC
C137
3
OUT/IN
-
R161
100K
R157
750
7
[7/C5]
8 LT1229
5
+
7
6
1000PF
1%
VEE
OSD_Y+C_OUT
+5VV
4
-5VV
8
4
R159
VCC
INH
VSS
+5VV
R162
VEE
11
A
10
B
9
C
6
A0
R148
CHANGED PER DCR 020523-00
-5VV
MORPHEN1/
74HC4051
16
SC4
SC2
-IN
VCC
15
Z
-5VV
+5VV
[1/B4,3/B8]
[1/C4,3/B8]
VOUT
IN2
8
1
VEE
7
8
13
14
15
12
1
5
2
4
15K
Av = 1
74HC4053 16
11
A
10
B
9
C
6
5
+5VV
2
INH
VSS
OSD_C_OUT
1%
OUT/IN
16
SC4B
SC2B
5
U29
[7/D5]
+5VV
[1/B5]
[1/C5]
OSD_SY_OUT
8 LT1229
1
3
-5VV
13
14
15
12
1
5
2
4
[5/C2]
R150
Q.C.
AUTH.
RWH
6/5/02
KAB
6/5/02
CW
10/14/04
AT
9/27/04
-5VV
R164
1%
8
NC
[5/D8]
IN1
EL4421
DRAFTER
CHECKER
CW
6/3/02
ECM
6/4/02
RWH
9/27/04
AT
9/27/04
DESCRIPTION
+5VV
11
A
10
B
9
C
C
OSD_Y_IN
-5VV R163
74HC4051
16
13
14
15
12
1
5
2
4
4
[6/D7]
6
V+
+5VV
C139
VEE
7
8
NC
VIDR
R166
INH
VSS
REV
+5VV
MTHRU/
5
6
V+
IN1
VOUT
IN2
-IN
A0
GND V-
7
1
2
3
R153
15K
Av = 2
R156
8
R155
CVID_MAIN
75.0
1%
OSD
U28
B
1
2
3
4
J16
COMPOSITE VIDEO
OUTPUTS
-5VV
301
R154
U29
C133
301
1%
NU
1%
*
R160
R158
EL4422
750
1%
36K
U16
-5VV
[7/B5]
[7/B5]
[7/A5]
MSVID_SEL0
MSVID_SEL1
MSVID_SEL2
CONTRACT
NO.
OSD_C_IN
[5/C7]
exicon
APPROVALS
DRAWN
RWH
CHECKED
ECM
Q.C.
CW
ISSUED
KB
8
7
6
5
4
3
2
DATE
3/13/02
3/18/02
3/19/02
3/19/02
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,VIDEO BD, MC4/MC8
MONITOR
SIZE
B
CODE
NUMBER
REV
060-15269
2
FILE NAME
15269-4 . 2
SHEET
1
2
OF
8
10-19-2004_8:34
A
8
7
6
5
4
3
2
1
REVISIONS
REV
+5VV
D
74HC4051
16
[2/D8,8/B6]
[2/D8,8/B6]
[2/D8,8/B6]
[8/B6]
[8/B6]
[7/C5]
[7/C5]
[7/C5]
[7/C5]
CVID4
CVID2
NC
CVID1
NC
CVID3
CVID5
13
14
15
12
1
5
2
4
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
VCC
+5VV
C66
OUT/IN
3
47/16
§
6
ZCVID_EN/
2
R116
8 AD8072
+
1
-
100K
§
11
A
10
B
9
C
ZVID_SEL0
ZVID_SEL1
ZVID_SEL2
4
4
SYZON
U15
5
§
6
V+
IN1
8
-5VV
750
R115
VEE
7
CHANGED PER DCR 020523-00
2
CHANGED U14,15 PER DCR 020715-00
3
UPDATED FOR MC4 PER DCR 040922-00
R114
750
U11
§
36K
1%
§
§
[7/C5]
1%
EL4421
Q.C.
AUTH.
RWH
6/5/02
KAB
6/5/02
RWH
8/14/02
KB
8/14/02
CW
10/14/04
AT
9/27/04
D
Av = 1
-IN
A0
GND V-
7
1
2
R99
8
VOUT
IN2
R113
INH
VSS
1
+5VV
ZY
3
DRAFTER
CHECKER
CW
6/3/02
ECM
6/4/02
CW
8/5/02
ECM
8/13/02
RWH
9/27/04
AT
9/27/04
DESCRIPTION
U13
3
§
ZSVID_YOFF
75.0
1%
§
R98
6.8K
§
-5VV
§
-5VV
+5VV
74HC4051
16
C
[1/B7,2/C8]
[1/C7,2/C8]
[1/C7,2/C8]
[1/C7]
[1/B7]
NC
SY4
SY2
NC
SY1
NC
SY3
SY5
13
14
15
12
1
5
2
4
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
VCC
C
3
R102
OUT/IN
+5VV
11
A
10
B
9
C
6
INH
VSS
8
5
+
6
-
VEE
7
6.8K
§
8 AD8072
7
4
U14
C61
R100
.1/25
§
75.0
1%
§
J1
SCZONE
3
SYZONE
4
1
2
5
-5VV
U10
§
R101
§
-5VV
475
1%
§
ZONE
S-VIDEO
OUT
NOTES
1 COMPONENTS ON THIS PAGE ARE NOT INSTALLED ON MC-4
+5VV
74HC4051
16
B
[1/B4,2/B8]
[1/C4,2/B8]
[1/C4,2/B8]
[1/C4]
[1/B4]
SC4
SC2
NC
SC1
NC
SC3
SC5
13
14
15
12
1
5
2
4
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
VCC
3
OUT/IN
6
-
4
R112
SCZON
U15
§
-5VV
R111
INH
VSS
750
VEE
7
-5VV
1%
R110
U9
§
ZSVID_SEL0
ZSVID_SEL1
ZSVID_SEL2
8 AD8072
5
+
7
6
100K
§
8
[7/A5]
[7/A5]
C64
.1/25
§
11
A
10
B
9
C
B
+5VV
ZC
R108
R109 §
750
36K
§
1%
§
R106
1.15K
1%
§
R103
1.15K
1%
§
XREF1=[7/A5]
+5VV
15K
§
8 AD8072
3
+
1
2
-
4
R105
75.0
1%
U14
-5VV
§
CVID_ZON
[2/B3]
ZONE
COMPOSITE VIDEO
OUT
§
R104
750
R107
750
CONTRACT
NO.
1%
§
1%
§
8
7
6
5
exicon
APPROVALS
DRAWN
RWH
CHECKED
ECM
Q.C.
CW
ISSUED
KB
4
3
2
DATE
3/13/02
3/18/02
3/19/02
3/19/02
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,VIDEO BD, MC4/MC8
ZONE
SIZE
B
CODE
NUMBER
FILE NAME
15269-4 . 3
SHEET
1
3
REV
3
060-15269
OF
8
10-21-2004_8:13
A
8
7
6
5
4
3
2
1
REVISIONS
REV
+5VV
OSD_B1
1
7
[5/B6]
14
9
D
OSD_R1
[5/B6]
3
U5
8
OSD_B
OSD_B
74AC04
U5
2
10.0K
1%
OSD_B/
OSD_R/
74AC04
U5
11
U5
10
OSD_G/
[5/B6]
U5
6
R28
R20
1%
976
1%
R26
R25
1.37K
10.0K
1%
OSD_G/
+
2
-
12PF
CHANGED PER DCR 020523-00
2
USE RY5 SPARE PER ECO 021105-00
750
R27
3
UPDATED FOR MC4 PER DCR 040922-00
OSD_PB_OUT
75.0
1%
Q.C.
AUTH.
RWH
6/5/02
KAB
6/5/02
RWH
11/12/02
KAB
11/12/02
CW
10/14/04
AT
9/27/04
D
-5VV
C20
-5VV
OSD_R
8 AD8072
1
U6
R29 4
C19
1%
3
1%
74AC04
OSD_PY_OUT
1
+5VV
15.0K
OSD_R
74AC04
OSD_G1 5
[5/D2]
R21
29.4K
1%
OSD_R/
4
74AC04
R19
DRAFTER
CHECKER
CW
6/3/02
ECM
6/4/02
CW
11/11/02
ECM
11/12/02
RWH
9/27/04
AT
9/27/04
DESCRIPTION
47PF
R24
10.0K
1%
OSD_B/
R22
+5VV
61.9K
1%
OSD_G/
11.8K
1%
COMPONENT VIDEO INPUTS
INPUT 1
C
3
Y_IN1
GRN
1
Y
R41
RED
1
PR
R39
12PF
750
R34
OSD_PR_OUT
75.0
1%
SPARES
-5VV
C25
U5
13
47PF
Y_IN2
NC
12
C
74AC04
R36
PR_IN2
RED
3
15K
R35
PB_IN1
BLU
1
PB
R37
6
NC
8
NC
6
NC
8
4
NC
RY2
4
NC
RY1
PB_IN2
BLU
3
15K
NC
15K
J3
1
3
-
U6
R31 4
C24
1%
6
8 AD8072
7
15K
PR_IN1
J6
PB
10.0K
1%
+
J4
1
3
1.37K
5
1%
GRN
3
15K
J7
PR
R32
-5VV
J5
1
976
1%
R33
INPUT 2
J8
Y
R30
R23
R18
6
15K
NC
4
8
COMPONENT VIDEO OUTPUTS
RY5
J5
INPUT 3
J8
2
Y
3
Y_IN3
GRN
PR_IN3
RED
13 PR_IN13
9
13
9
PR_OUT
15K
B
PR
3
J3
PB_IN3
OSD_PB_OUT
11
11
BLU
Y
3
2
RED
RY3
RY4
RY6
R40
11
PR_IN_SEL
13
9
13 PB_IN13
9
13
9
RY1
RY2
RY5
R38
11
PB_IN_SEL
13
9
PB_OUT
2
BLU
PB
3
15K
+5VR
A
[7/B5]
+5VR
1
1
D5
+
+
1N4002
-
-
16
8
2
GRN
RY3
OSD_PR_OUT
11
11
2
3
PY_OUT
J4
J6
PB
4
8
RY4
RY6
R42
PY_IN_SEL
15K
2
3
4
8
4 PY_IN13
8
J7
PR
6
6
P_SEL0
RY5
R45
16
D4
2N4401
1K
1
1
1
+
+
D3
+
+
-
-
1N4002
-
16
P_SEL2
[7/B5]
R44
1K
Q13
7
1
1N4002
RY6
6
+5VR
RY2
16
16
RY4
2N4401
[7/B5]
Q12
5
4
P_SEL1
R43
1K
RY1
16
RY3
CONTRACT
NO.
exicon
APPROVALS
DRAWN
RWH
CHECKED
ECM
Q.C.
CW
ISSUED
KB
2N4401
Q11
3
2
DATE
3/13/02
3/18/02
3/19/02
3/19/02
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,VIDEO BD, MC4/MC8
COMPONENT VIDEO
SIZE
B
CODE
NUMBER
FILE NAME
15269-4 . 4
REV
3
060-15269
SHEET
1
4
OF
8
10-19-2004_8:34
B
6
8
7
6
5
4
3
2
1
REVISIONS
REV
+5VV
D
[2/D5]
C101
R118
47/16
470K
2
+
-
8
1%
C100
+5VV
3
4.75K
1%
.01/50
R126
5
+
6
-
R124
2.15K
2.15K
1%
1%
8
LF353
7
4
R123
U23
U23
R127
12
R146
475
13
1%
U35
X
Y
+5VV
R135
R136
10/16
681
1%
976
1%
C116
VCC
14
Z
SECAM_EN
R129
2.15K
VCC4
VCC3
VCC2
VCC1
AVCC2
AVCC1
32
35
NC 40
NC 38
SCOSD
GMHSYN/
VSYNC/
12
13
NC 1
NC 21
OSD_TSC/
77
VIDEO_DATA
VIDEO_SCLK
10
9
8
+5VV
NC
NC
NC
NC
NC
R172
10K
19
25
26
27
28
43
78
+5VV
R117
+5VV
10K
OSD_CS/ 1
U35
A
X
Y
YIN
CIN
VIN
VKIN
YOUT
COUT
VOUT
VKOUT
VCC
15
Z
44
45
46
47
48
49
50
51
HSYNC
VSYNC
VBLNK
EXHSYN
EXVSYN
IC
VOC
VOB
B
R
G
MB90092
CBCK
FSCO
POS
TSC
ADR0
ADR1
ADR2
ADR3
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
ADR10
ADR11
ADR12
ADR13
ADR14
ADR15
ADR16
ADR17
ADR18
ADR19
ADR20
SIN
SCLK
CS
NC1
NC2
NC3
NC4
NC5
READ
TEST
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
XS
EXS
XD
EXD
31
34
37
39
C114
3
12PF
-5VV
UPDATED FOR MC4 PER DCR 040922-00
D
VCC
4
Z
X
Y
MSVID_YOFF
14 OSD_CSYNC/
15 OSD_VSYNC/
16 NC
2
3
5
6
7
NC
NC
20
22
NC
NC
53
54
55
56
57
58
59
60
61
63
64
66
67
68
69
70
71
72
73
74
75
18
17
80
79
NC
NC
NC
NC
NC
OSD_B1
OSD_R1
OSD_G1
C125
R141
R142
10/16
681
1%
976
1%
R140
OSD_VSYNC/
5
6
C120
100K
-5VV
OSD_Y+C_OUT
8 LT1229
+
7
R144
-
1.15K
1%
6.8PF
R143
C121
1%
750
SPARES
U24
4
C
+5VV
OSD_C_OUT
[2/C5]
C122
3
+
2
-
8 AD8072
1
4
U25
-5VV
33PF
-5VV
A[15:0]
FILTERS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D[7:0]
[7/C3]
[7/C3]
FONT MEMORY
+5VV
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
+5VV
4
3
4FSC
14.31818MHZ
VDD
OUT
IN
1
NTSC_EN
[7/C5]
GND
U34
2
4
E2
C109
10PF
E1
3
10UH
17.73448MHZ
VDD
OUT
IN
1
PAL_EN
[7/C5]
[7/B5]
GND
U33
2
VROM_WR/
B
+5VV
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
1
31
24
22
16
29F010
A0
VCC
A1
A2
DQ0
A3
DQ1
A4
DQ2
A5
DQ3
A6
DQ4
A7
DQ5
A8
DQ6
A9
DQ7
A10
A11
A12
A13
A14
A15
A16
A17
128KX8
NC1 90NS
WR
OE
CE
GND
32
13
14
15
17
18
19
20
21
D0
D1
D2
D3
D4
D5
D6
D7
U31
C108
15PF
4XFSC OSCILLATORS
CONTRACT
NO.
ON-SCREEN DISPLAY
A[15:0]
5
4
exicon
APPROVALS
DRAWN
RWH
CHECKED
ECM
Q.C.
CW
ISSUED
KB
D[7:0]
6
[2/B5]
C123
+5VV
7
[7/C5]
82PF
[4/D8]
[4/D8]
[4/D8]
NC
U32
[2/D5]
68PF
+5VV
L1
7
OSD_SY_OUT
9
S
6
INH
VSS VEE
8
7
U35
1.15K
1%
-5VV
8
3
[4/D5]
R145
NC
NC
10
S
6
INH
VSS VEE
8
4
5
1%
.1/25
65
52
23
4
36
30
29
24
[7/B4,8/D4]
2
1.15K
1%
U24
14 15
VSS4
VSS3
VSS2
VSS1
AVSS4
AVSS3
AVSS2
AVSS1
D0
D1
D2
D3
D4
D5
D6
D7
74HC4053 16
NC
-
1.15K
1%
-5VV
+5VV
76
62
42
11
33
41
1%
OSD_TEST
75.0
1%
74HC4053 16
R137
C117
4.75K
B
2
8 LT1229
1
R139
1%
[8/D4]
[8/D4]
U25
+5VV
47PF
R130
10/16
+
750
C115
[7/C5]
3
R138
12PF
11
S
6
INH
VSS VEE
8
7
41
+5VV
C106
CHANGED U24 PER DCR 020715-00
475
1%
100K
74HC4053 16
[7/B5]
4
R122
C99
+5VV
1%
.1/25
2
-5VV R149
R119
.1/25
4.75K
[6/C3]
[6/D3]
-
OSD_PY_OUT
C98
2.15K
C105
CHANGED PER DCR 020523-00
Q.C.
AUTH.
RWH
6/5/02
KAB
6/5/02
RWH
8/14/02
KB
8/14/02
CW
10/14/04
AT
9/27/04
1%
R128
[2/A5]
6
8 AD8072
R147
7
4.75K
-5VV
OSD_C_IN
+
1%
-5VV
LF353
1%
C
5
2.15K
1
4
1
+5VV
+5VV
R120
4.75K
.1/25
OSD_Y_IN
+5VV
R125
DRAFTER
CHECKER
CW
6/3/02
ECM
6/4/02
CW
8/5/02
ECM
8/13/02
RWH
9/27/04
AT
9/27/04
3
2
DATE
3/13/02
3/18/02
3/19/02
3/19/02
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,VIDEO BD, MC4/MC8
ON-SCREEN DISPLAY
SIZE
B
CODE
FILE NAME
15269-4. 5
NUMBER
060-15269
SHEET
1
REV
3
5 OF 8
10-19-2004_8:34
C102
DESCRIPTION
8
7
6
5
4
3
2
1
REVISIONS
REV
SYNC STRIPPER
DRAFTER
CHECKER
CW
6/3/02
ECM
6/4/02
RWH
9/27/04
AT
9/27/04
DESCRIPTION
1
CHANGED PER DCR 020523-00
2
UPDATED FOR MC4 PER DCR 040922-00
+5VAS
D
Q.C.
AUTH.
RWH
6/5/02
KAB
6/5/02
CW
10/14/04
AT
9/27/04
+5VV
2
[2/D5]
3
VIDR
8 LF353
1
+
4
-5VV
U2
15
NJM2229
V+
C5
6
.1/25
7
R4
C9
680K
VIDEO-IN
VSYNC-OUT
SYNCDETOUT
LPF
100PF
+5VAS
SYNCDETOUT
CSYNC-OUT
30.1K
10K
AFC-IN
1%
12
11
14
C15
C17
1000PF
AFC-OUT
GND
10/16
SYNC
INTEGR
8
AFC-FILT
VCO-FILT
3
9
1
10K
4
R8
VSYNC/
SYNC_DETECT
5
C10
R7
[5/C8]
[8/D5]
H/
220PF 10K
[7/C5]
16
11
12
HINH
74HC02
13
GMHSYN/
[5/C8]
U4
R6
U3
R13
22K
22K
R15
R14
1K
22K
C18
390
Y1
74HC02
10
U4
VCO-OUT
2
R5
R16
NC
13
MM-INT
MM-TC
8
9
10
R17
R12
-5VV
1.5K
-5VV
330PF
-5VV
503KHZ
C
C
+5VV
C7
C6
1000PF
68NF
1/50
C11
3300PF
2
3
74HC02
1
7
R10
14
R11
100K
C14
D
V/
U4
10K
R9
D2
475 1N914
1%
5
6
74HC02
4
C12
220PF
15KHZ
U4
B
B
DC RESTORER
NC
D1
BAV99
C8
100PF
R2
+5VV
2.2M
+5VV
12
13
A
U1
VCC
14
Z
X
Y
11
S
6
INH
VSS VEE
8
7
R1
1K
8 LF353
7
6
-
5
+
4
BPCOR
[2/D7]
U2
CONTRACT
NO.
-5VV
-5VV
8
7
6
exicon
APPROVALS
DRAWN
RWH
CHECKED
ECM
Q.C.
CW
ISSUED
KB
5
4
3
2
DATE
3/13/02
3/18/02
3/19/02
3/19/02
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,VIDEO BD, MC4/MC8
SYNC STRIPPER
SIZE
B
CODE
NUMBER
FILE NAME
15269-4 . 6
060-15269
SHEET
1
REV
2
6 OF 8
10-19-2004_8:34
74HC4053 16
NC
8
7
6
5
4
3
2
1
REVISIONS
REV
+5VV
+5VV
DRAFTER
CHECKER
CW
6/3/02
ECM
6/4/02
RWH
9/27/04
AT
9/27/04
DESCRIPTION
1
CHANGED PER DCR 020523-00
2
UPDATED FOR MC4 PER DCR 040922-00
74HC4053 16
5
3
D
U1
X
Y
VCC
4
Z
MSTHRU/
[2/C5]
9
S
6
INH
VSS VEE
8
Q.C.
AUTH.
RWH
6/5/02
KAB
6/5/02
CW
10/14/04
AT
9/27/04
D
7
-5VV
VIDEO_DATA
VIDEO_SCLK
VIDEO_SCLK
CONTROL REGISTERS
FLASH INTERFACE
+5VV
SER
11
SRCLK
10
SRCLR
12
RCLK
13 RCLR
GND
8
C
QA
QB
QC
QD
QE
QF
QG
QH
QHH
15
1
2
3
4
5
6
7
9
MVID_SEL0
MVID_SEL1
MVID_SEL2
MCVID_EN/
MSVID_YOFF
MORPHEN1/
MTHRU/
HINH
[2/D8]
[2/D8]
[2/D8]
[2/D8]
[5/C2]
[2/C7]
[2/B5]
[6/C4]
+5VV
14
11
10
12
13
16
VCC
QA
QB
QC
QD
SRCLK
SRCLR
QE
QF
RCLK
QG
QH
G
GND QHH
SER
U38
[5/B3]
SPARES
+5VV
U22
8
12
13
+5VV
RCLK
13 RCLR
GND
8
14
11
10
12
13
16
VCC
QA
QB
QC
QD
SRCLK
SRCLR
QE
QF
RCLK
QG
QH
G
GND QHH
SER
U36
SER
11
SRCLK
10
SRCLR
B
[8/D4]
[8/D4]
VIDEO_REG/
12
VIDEO_RST/
13 RCLR
GND
8
RCLK
QA
QB
QC
QD
QE
QF
QG
QH
QHH
15
1
2
3
4
5
6
7
9
P_SEL0
P_SEL1
P_SEL2
NC
NC
NC
[2/B7]
[5/B8]
[5/A4]
14
11
10
[5/A8,8/D4]
OSD_CS/
12
13
U37
16
VCC
QA
QB
QC
QD
SRCLK
SRCLR
QE
QF
RCLK
QG
QH
G
GND QHH
SER
8
4
5
9
10
1
2
4
5
A
9
10
7
[4/A7]
[4/A4]
[4/A6]
MORPHEN/
OSD_TSC/
VROM_WR/
1
2
8
[5/B3]
+5VV
12
13
74HC08
11
NC
U12
§
+5VV
74HCT594
14
16
VCC
A[15:0]
A0
A1
A2
A3
A4
A5
A6
A7
U21
8
+5VV
15
1
2
3
4
5
6
7
9
14
[3/D8]
[3/D8]
[3/D8]
[3/D8]
[3/C5]
[5/B4]
[5/A4]
[5/C5]
NC
11
U20
7
12
ZVID_SEL0
ZVID_SEL1
ZVID_SEL2
ZCVID_EN/
ZSVID_YOFF
NTSC_EN
PAL_EN
SECAM_EN
74HC595
11
SRCLK
10
SRCLR
15
1
2
3
4
5
6
7
9
74HC595
SER
QA
QB
QC
QD
QE
QF
QG
QH
QHH
74HCT594
14
16
VCC
C
74HC08
7
+5VV
D[7:0]
D0
D1
D2
D3
D4
D5
D6
D7
15
1
2
3
4
5
6
7
9
6
74HC08
3
MSVID_SEL0
U20
74HC08
6
MSVID_SEL1
U20
74HC08
8
MSVID_SEL2
U20
74HC08
3
U12
74HC08
6
U12
74HC08
8
U12
ZSVID_SEL0
15
1
2
3
4
5
6
7
9
A8
A9
A10
A11
A12
A13
A14
A15
NC
B
U30
[2/A8]
[2/A8]
[2/A8]
[3/A8]
§
ZSVID_SEL1
§
ZSVID_SEL2
§
[3/A8]
CONTRACT
NO.
[3/A8]
exicon
APPROVALS
DRAWN
RWH
CHECKED
ECM
Q.C.
CW
ISSUED
KB
5
4
3
2
DATE
3/13/02
3/18/02
3/19/02
3/19/02
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,VIDEO BD, MC4/MC8
CONTROL REGISTERS
SIZE
B
CODE
NUMBER
FILE NAME
15269-4 . 7
060-15269
SHEET
1
REV
2
7 OF 8
10-19-2004_8:34
16
VCC
74HCT594
14
+5VV
14
[8/D4]
VIDEO_DATA
74HC595
[8/D4]
8
7
6
5
4
3
2
1
+5VD
REVISIONS
C55
1
3
RCA
D8
BAV99
.01/50
33PF
C53
R95
R94
47K
2.2K
75
1/4W
74HCU04
1
2
74HCU04
3
4
U8
+5VD
COAX1
U8
NC
NC
NC
J14
C50
1
RCA
D6
BAV99
.01/50
33PF
C48
R89
R88
47K
2.2K
[6/D3]
75
1/4W
74HCU04
1
2
74HCU04
3
4
U7
COAX2
COAX1
U7
COAX2
J15
COAX3
C56
2
RCA
D9
BAV99
.01/50
33PF
C54
R96
R97
47K
2.2K
COAX4
OPTO1
R93
75
1/4W
74HCU04
13
12
74HCU04
11
10
U8
+5VD
C
NC
R86
+5VD
3
SYNC_DETECT
OPTO2
COAX3
OPTO3
U8
OPTO4
VIDEO_SCLK
OSD_CS/
C51
2
RCA
D7
BAV99
.01/50
33PF
C49
R90
R91
47K
2.2K
VIDEO_RST/
74HCU04
13
12
74HCU04
11
10
U7
MH1
[5/B8,7/D8]
MH2
DRAFTER
CHECKER
CW
6/3/02
ECM
6/4/02
RWH
9/27/04
AT
9/27/04
DESCRIPTION
1
CHANGED PER DCR 020523-00
2
UPDATED FOR MC4 PER DCR 040922-00
Q.C.
AUTH.
RWH
6/5/02
KAB
6/5/02
CW
10/14/04
AT
9/27/04
MH3
[7/B8]
D
[7/B8]
+5VR
FB1
+5VR
POWER SUPPLY
CONNECTOR
(FROM MAIN BOARD)
J17
1
2
3
4
FB2
GND3
+5VV
C83
GND2
100/25
C87
FB3
GND4
+5VAS
C84
GND5
100/25
C88
10/16
C
GND1
+5VAS
+5VD
+5VA
-5VA
TEST POINTS
+5VV
10/16
R87
75
1/4W
[5/B8,7/D8]
[5/A8,7/B4]
VIDEO_REG/
J19
J14
3
VIDEO_DATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
R92
D
3
REV
MAIN BOARD CONNECTOR
J15
GND6
COAX4
FB4
U7
-5VV
C89
10/16
C85
100/25
SPARES
-5VV
74HCU04
5
6
RCA BOARD CONNECTOR
NC
U8
+5VD
+5VV
B
-5VV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
74HCU04
9
8
COMPOSITE VIDEO INPUTS
47/6
C140
CVID5
47/6
C141
CVID4
47/6
C142
CVID3
47/6
C143
CVID2
47/6
C144
CVID1
R171
470K
R170
470K
R169
470K
R168
470K
[2/D8,3/D8]
BYPASS CAPACITORS
+5VV
NC
U8
[2/D8,3/D8]
74HCU04
5
6
[2/D8,3/D8]
C2
[2/D8,3/D8]
.1/25
C4
.1/25
C13
.1/25
C21
.1/25
C23
.1/25
C27
.1/25
C31
.1/25
C35
.1/25
C39
.1/25
C43
.1/25
§
U7
C58
.1/25
74HCU04
9
8
+5VD
[2/D8,3/D8]
R167
470K
§
.1/25
C47
C52
.1/25
.1/25
§
§
§
§
C63
C68
C70
C72
C73
C90
C91
C92
C93
C94
C95
.1/25
.1/25
C111
C119
C124
C126
C128
C1
C3
C22
C28
C32
.1/25
C46
§
C60
.1/25
.1/25
.1/25
.1/25
.1/25
C75
C77
.1/25
.1/25
C96
C97
C131
C134
C136
C36
C40
C79
.1/25
C81
.1/25
C107
C110
B
NC
U7
C82
.1/25
NC
C57
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
C103
.1/25
.1/25
.1/25
J18
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
C146
C147
C148
.1/25
.1/25
.1/25
.1/25
C44
C59
§
C62
§
C65
C127
C129
OPTICAL INPUTS
TORX173
+5:3
1
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
§
.1/25
G:2,4
+5VR
+5VAS
A
§
C67
.1/25
+5:3
C86
1
47/16
G:2,4
.1/25
§
C71
.1/25
C74
.1/25
C76
.1/25
C78
.1/25
C80
.1/25
C104
.1/25
C118
.1/25
.1/25
.1/25
CONTRACT
NO.
C16
.1/25
C132
CP1
§
C69
.1/25
C135
.1/25
C138
.1/25
C145
.1/25
-5VV
8
7
6
5
4
3
exicon
APPROVALS
DRAWN
RWH
CHECKED
ECM
Q.C.
CW
ISSUED
KB
2
DATE
3/13/02
3/18/02
3/19/02
3/19/02
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,VIDEO BD, MC4/MC8
PWR,SPDIF,MAIN&RCA BD CONNS
SIZE
B
CODE
NUMBER
FILE NAME
15269-4 . 8
060-15269
SHEET
1
REV
2
8 OF 8
10-21-2004_8:13
CP2
TORX173
8
7
6
5
4
2
3
1
REVISIONS
REV
COMPOSITE VIDEO INPUTS
DRAFTER
CHECKER
DESCRIPTION
Q.C.
AUTH.
+5VV
C10
CVID
D
J5
.1/25
2N3904
D
1
1
R15
2 YEL RCA
75.0
1%
C9
Q5
R14
R13
22
CVID[5:1]
CVID1
CVID5
CVID4
1K
OPTICAL INPUTS
.1/25
-5VV
+5:3
J4
.1/25
G:2,4
CP1
2N3904
TORX173
1
2
+5:3
R12
2 YEL RCA
1
2
+5VV
Q4
75.0
1%
R10
C7
R11
1
1
CVID2
G:2,4
22
CVID2
CVID1
TORX173
C8
CVID3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
+5VD
+5VV
C13
10/16
10/16
-5VV
J6
+5VD
C11
.1/25
C
C14
-5VV
CP2
1K
+5VV
.1/25
+5VD
C12
.1/25
C
-5VV
+5VV
C6
J3
.1/25
NOTES
1 UNLESS OTHERWISE INDICATED, RESISTORS ARE 1/10W
2N3904
2 UNLESS OTHERWISE INDICATED, RESISTORS ARE 5%
1
3
R9
2 YEL RCA
Q3
75.0
1%
R7
C5
R8
3 UNLESS OTHERWISE INDICATED, CAPACITORS ARE UF/V
CVID3
4
22
1K
DIGITAL
GROUND
ANALOG
GROUND
CHASSIS
GROUND
POWER
GROUND
5 LAST REFERENCE DESIGNATORS USED: C14, CP2, J6, Q5, R15
.1/25
-5VV
+5VV
C4
J2
B
.1/25
2N3904
B
1
4
R6
2 YEL RCA
Q2
75.0
1%
R4
C3
R5
CVID4
22
1K
.1/25
-5VV
+5VV
C2
J1
2N3904
R3
2 YEL RCA
Q1
75.0
1%
R1
C1
R2
CVID5
22
1K
.1/25
A
© 2002 Lexicon, Inc.
CONTRACT
NO.
exicon
-5VV
APPROVALS
DRAWN
8
7
6
5
4
3
DATE
RWH
1/9/02
CHECKED
ECM
1/10/02
Q.C.
CW
1/10/02
ISSUED
KAB
1/11/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,VIDEO RCA BD,MC8
RCA , OPTICAL DIGITAL INPUTS
SIZE
B
CODE
NUMBER
060-15279
REV
0
FILE NAME
15279-0 . 1
SHEET
1
1 OF 1
1-16-2002_12:16
5
.1/25
1
8
7
6
5
4
2
3
1
REVISIONS
REV
D
DRAFTER
CHECKER
DESCRIPTION
Q.C.
AUTH.
D
IR/ENCODER BOARD CONNNECTOR
+5VD
J2
IR_AUXIN
IR_AUXRET
[2/C3]
[2/C3]
[2/C3]
SYSTEM_ON_LED
OVLD_LED
IR_ACK_LED
2N3904
R27
HOST_ACK_LED
3K
1
2
3
4
5
6
7
8
9
10
11
12
13
14
IR_DATA
ENCODER_B
ENCODER_A
Q1
R26
3K
C
C
VFD CONNECTOR
FP_D6
FP_D7
FP_D4
FP_D5
FP_D2
FP_D3
FP_D0
FP_D1
FP_A1
VFD_EN
FRONT PANEL CONNECTOR
+5VD
J3
B
SRD_LWR/
IR_AUXIN
IR_AUXRET
IR_DATA
ENCODER_B
ENCODER_A
VFD_EN
IR_DATA
FP_A0
IR_ACK_PIC
VFD_EN
NOTES
1 UNLESS OTHERWISE INDICATED, RESISTORS ARE 1/10W
2 UNLESS OTHERWISE INDICATED, RESISTORS ARE 5%
3 UNLESS OTHERWISE INDICATED, CAPACITORS ARE UF/V
NC
+5VD
4
DIGITAL
GROUND
ANALOG
GROUND
CHASSIS
GROUND
POWER
GROUND
5 [XX/XX] DENOTES [SHEET NUMBER/SECTOR]
6 LAST REFERENCE DESIGNATORS USED: C7, D22, J3, Q1, R29, SW21, U6.
B
100UF
[2/C8]
[2/B8]
FP_A[2:0]
FP_A0
FP_A1
FP_A2
FP_D1
FP_D0
FP_D3
FP_D2
FP_D5
FP_D4
FP_D7
FP_D6
FP_D[7:0]
[2/D8]
[2/D6]
DOCUMENT CONTROL BLOCK: #060-15289
SHEET
1 OF 3
2 OF 3
3 OF 3
REVISION
0
0
0
TITLE
CONNECTORS
CONTROL & STATUS REG
SWITCHES & LEDS
© 2002 Lexicon, Inc.
CONTRACT
NO.
A
exicon
APPROVALS
DRAWN
8
CHASSIS
SCREW
C1
SWRD_LEDWR/
FP_RST
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
7
6
5
4
3
DATE
RWH
12/21/01
CHECKED
KAB
1/4/02
Q.C.
CW
1/8/02
ISSUED
KAB
1/8/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,SW/LED BD,MC8
CONNECTORS
SIZE
B
CODE
NUMBER
060-15289
REV
0
FILE NAME
15289-0. 1
SHEET
1
1 OF 3
1-16-2002_12:35
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
J1
8
7
6
5
4
2
3
1
REVISIONS
REV
D
FP_D[7:0]
[1/A3]
L_CTRL2
L_CTRL1
L_CTRL0
+5VD
74VHCT138
FP_A[2:0]
[1/B3]
SWRD_LEDWR/
[1/B6]
FP_A0
FP_A1
FP_A2
1
A
2
B
3
C
6
G1
4
G2A
5
G2B
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
FP_D0
FP_D1
FP_D2
FP_D3
FP_D4
FP_D5
FP_D6
FP_D7
15
14
13
12
11
10
9
7
LED_CTRL0
LED_CTRL1
LED_CTRL2
NC
NC
NC
FP_D0
FP_D1
FP_D2
FP_D3
FP_D4
FP_D5
FP_D6
FP_D7
SWITCH_COLUMN
SWITCH_ROW
U6
SW_COL
SW_ROW
FP_D0
FP_D1
FP_D2
FP_D3
FP_D4
FP_D5
FP_D6
FP_D7
C
FP_RST
[1/B6]
B
FP_D0
FP_D1
FP_D2
FP_D3
FP_D4
FP_D5
FP_D6
FP_D7
2
3
4
5
6
7
8
9
1
11
2
3
4
5
6
7
8
9
1
11
2
3
4
5
6
7
8
9
1
11
2
3
4
5
6
7
8
9
1
11
74HC574
1D
2D
3D
4D
5D
6D
7D
8D
OC
CLK
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
19
18
17
16
15
14
13
12
LED8
LED9
LED10
LED11
LED12
LED13
LED14
LED15
19
18
17
16
15
14
13
12
LED16
LED17
LED18
OVLD_LED
HOST_ACK_LED
SYSTEM_ON_LED
NC
NC
[1/D8]
[1/C8]
[1/D8]
C
U5
74HC574
1D
2D
3D
4D
5D
6D
7D
8D
OC
CLK
D
[3/C8]
U2
74HC574
1D
2D
3D
4D
5D
6D
7D
8D
OC
CLK
LED[18:0]
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
Q.C.
AUTH.
U4
74HC574
1D
2D
3D
4D
5D
6D
7D
8D
OC
CLK
19
18
17
16
15
14
13
12
DRAFTER
CHECKER
DESCRIPTION
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
SWITCHCOL_[2:0]
19 SWITCHCOL_0
18 SWITCHCOL_1
17 SWITCHCOL_2
NC
16
NC
15
NC
14
NC
13
NC
12
[3/C8]
U3
SROW_[7:0]
[3/A2]
SROW_0
SROW_1
SROW_2
SROW_3
SROW_4
SROW_5
SROW_6
SROW_7
B
R22
2.2K
R23
R29
2.2K
2.2K
R19
R17
2.2K
2.2K
R20
R18
2.2K
2.2K
R21
SROW_0
SROW_1
SROW_2
SROW_3
SROW_4
SROW_5
SROW_6
SROW_7
9
8
7
6
5
4
3
2
1
19
74HC541
A8
A7
A6
A5
A4
A3
A2
A1
1G
2G
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
11
12
13
14
15
16
17
18
FP_D0
FP_D1
FP_D2
FP_D3
FP_D4
FP_D5
FP_D6
FP_D7
U1
2.2K
A
C3
.1/25
BYPASS CAPACITORS
C4
C5
.1/25
.1/25
C6
.1/25
C7
.1/25
C2
exicon
CONTRACT
NO.
.1/25
APPROVALS
DRAWN
8
7
6
5
4
3
DATE
RWH
12/21/01
CHECKED
KAB
1/4/02
Q.C.
CW
1/8/02
ISSUED
KAB
1/8/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,SW/LED BD,MC8
CONTROL & STATUS REG
SIZE
B
CODE
NUMBER
060-15289
REV
0
FILE NAME
15289-0. 2
SHEET
1
2 OF 3
1-16-2002_12:36
+5VD
8
7
6
5
4
2
3
1
REVISIONS
REV
D
MAIN
+5VD
LED0
D8
BLU
LED4
D16
YEL
LED16
D22
C
[2/D3]
[2/C3]
R8
+5VD
BLU
LED1
D7
390
R16
Q.C.
AUTH.
D
ZONE 2
+5VD
BLU
DRAFTER
CHECKER
DESCRIPTION
BLU
LED5
D15
390
+5VD
BLU
R7
LED2
D6
390
BLU
R15
LED6
D14
390
R6
+5VD
BLU
LED3
D5
390
R14
BLU
LED7
D13
390
RED
R28
LED17
D21
1.5K
R5
390
R13
390
+5VD
YEL
LED8
D4
YEL
LED12
D12
+5VD
YEL
R4
LED9
D3
1.5K
YEL
R12
LED13
D11
1.5K
+5VD
YEL
R3
LED10
D2
1.5K
YEL
R11
LED14
D10
1.5K
R2
+5VD
YEL
LED11
D1
1.5K
R10
YEL
LED15
D9
1.5K
RED
R25
LED18
D20
180
R1
1.5K
R9
1.5K
R24
180
LED[18:0]
C
SWITCHCOL_[2:0]
SWITCHCOL_2
D17
1N914
SWITCHCOL_1
D19
1N914
SWITCHCOL_0
D18
1N914
1
4
2 SROW_0
3 SROW_0
SW9
B
B
4
2 SROW_1
1
3 SROW_1
4
SW18
2 SROW_0
1
3 SROW_0
4
SW8
1
4
1
3 SROW_1
4
SW7
2 SROW_4
1
3 SROW_4
4
SW17
2 SROW_1
2 SROW_2
1
3 SROW_2
4
SW6
2 SROW_5
1
3 SROW_5
4
SW16
2 SROW_3
1
3 SROW_3
4
SW5
2 SROW_6
1
3 SROW_6
4
SW15
2 SROW_0
1
3 SROW_0
4
SW4
2 SROW_7
1
3 SROW_7
4
SW14
1
3 SROW_1
4
SW3
2 SROW_4
1
3 SROW_4
4
SW13
2 SROW_1
2 SROW_2
1
3 SROW_2
4
SW2
2 SROW_5
1
3 SROW_5
4
SW12
2 SROW_3
3 SROW_3
SW1
2 SROW_6
1
3 SROW_6
4
SW11
2 SROW_7
3 SROW_7
SW10
SROW_[7:0]
1
2 SROW_2
4
3 SROW_2
1
2 SROW_3
1
4
3 SROW_3
4
SW20
SW21
2 SROW_4
3 SROW_4
SW19
A
exicon
CONTRACT
NO.
APPROVALS
DRAWN
8
7
6
5
[2/B7]
4
3
DATE
RWH
12/21/01
CHECKED
KAB
1/4/02
Q.C.
CW
1/8/02
ISSUED
KAB
1/8/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,SW/LED BD,MC8
SWITCHES & LEDS
SIZE
B
CODE
NUMBER
060-15289
REV
0
FILE NAME
15289-0. 3
SHEET
1
3 OF 3
1-16-2002_12:36
1
8
7
6
5
4
2
3
1
REVISIONS
RA[22:15]
REV
DRAFTER
CHECKER
DESCRIPTION
ZD[7:0]
ZA[14:0]
Q.C.
AUTH.
+5VD
+5VD
27C020
ZA0
ZA1
ZA2
ZA3
ZA4
ZA5
ZA6
ZA7
ZA8
ZA9
ZA10
ZA11
ZA12
ZA13
ZA14
RA15
RA16
RA17
D
+5VD
EURO48-M-RA
C
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
RA20
RA21
RA22
+3.3VD
ZA12
ZA13
ZA14
EURO48-M-RA
BSY/RDY
ZD4
ZD5
ZD6
ZD7
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
J1
RA15
RA16
RA17
RA18
RA19
ZA6
ZA7
ZA8
ZA9
ZA10
ZA11
EURO48-M-RA
ZD0
ZD1
ZD2
ZD3
J1
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
EPROM/
FLASH_RST/
FLASH_WR/
FLASH0/
MEM_SPARE
MEM_RD/
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
1
31
24
22
16
MEM_RD/
EPROM/
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
VPP
PGM
OE
CE
GND
32
VCC
13
14
15
17
18
19
20
21
D0
D1
D2
D3
D4
D5
D6
D7
C5
ZD0
ZD1
ZD2
ZD3
ZD4
ZD5
ZD6
ZD7
.1/25
RA[22:15]
ZA[15:0]
256KX8
70NS
U3
(N/C)
+5VD
+5VD
FLASH
ZA0
ZA1
ZA2
ZA3
ZA4
ZA5
ZA6
ZA7
ZA8
ZA9
ZA10
ZA11
ZA12
ZA13
ZA14
RA15
RA16
RA17
RA18
RA19
RA20
ZA0
ZA1
ZA2
ZA3
ZA4
ZA5
J1
FLASH0/
MEM_RD/
FLASH_WR/
16
15
14
13
10
9
8
7
6
5
4
3
42
41
40
39
38
37
36
35
32
43
29
30
FLASH_RST/
2
22
21
B
ZD[7:0]
44
23
A0
VCC0
A1
VCC1
A2
A3
A4
PSOP
A5
A6
A7
A8
2MX8
A9
70NS
A10
A11
A12
D0
A13
D1
A14
D2
A15
D3
A16
D4
A17
D5
A18
D6
D7
A19
A20
BSY/RDY
CE
OE
NC1
WE
NC2
RESET NC3
NC4
GND0 NC5
GND1 NC6
C3
.1/25
17
18
19
20
24
25
26
27
ZD0
ZD1
ZD2
ZD3
ZD4
ZD5
ZD6
ZD7
28
1
11
12
31
33
34
D
TEST POINTS
C4
.1/25
EPROM/
MEM_RD/
BSY/RDY
FLASH_RST/
FLASH_WR/
FLASH0/
MEM_SPARE
+5VD
RA15
RA16
RA17
RA18
RA19
RA20
RA21
RA22
ZA0
ZA1
ZA2
ZA3
ZA4
ZA5
ZA6
ZA7
ZA8
ZA9
ZA10
ZA11
ZA12
ZA13
ZA14
ZD0
ZD1
ZD2
ZD3
ZD4
ZD5
ZD6
ZD7
R1
RA15
RA16
RA17
RA18
RA19
RA20
RA21
RA22
ZA0
ZA1
ZA2
ZA3
ZA4
ZA5
ZA6
ZA7
ZA8
ZA9
ZA10
ZA11
ZA12
ZA13
ZA14
ZD0
ZD1
ZD2
ZD3
ZD4
ZD5
ZD6
ZD7
EPROM/
RD/
BSY/RDY
RST
WR/
F0/
SP
C
NOTES
10K
1 UNLESS OTHERWISE INDICATED, CAPACITORS ARE UF/V
BSY/RDY
2
NC
NC
NC
NC
NC
NC
DIGITAL
GROUND
ANALOG
GROUND
CHASSIS
GROUND
POWER
GROUND
3 LAST REFERENCE DESIGNATORS USED: C5, J1, R1, U3
4 DUAL LAYOUT: INSTALL EITHER
OR
U1, C1, C2
U2, C3, C4
B
U2
+5VD
SEE NOTE 4
+5VD
FLASH
A
30
29
28
27
22
21
20
19
18
17
16
15
10
9
8
7
6
5
4
3
46
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
FLASH0/
MEM_RD/
FLASH_WR/
11
CE
43
OE
44
WE
FLASH_RST/
14
12
VCC0
37
VCC1
D0
D1
D2
D3
D4
D5
D6
D7
31
32
33
34
38
39
40
41
C1
ZD0
ZD1
ZD2
ZD3
ZD4
ZD5
ZD6
ZD7
.1/25
8
7
6
5
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
1
2
13
23
24
25
26
45
47
48
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
© 2002 Lexicon, Inc.
exicon
CONTRACT
NO.
RESET
42
BSY/RDY
35
GND0
36
GND1 TSOP
4
.1/25
2MX8
70NS
BSY/RDY
APPROVALS
DRAWN
U1
FLASH0/ ($1N1391)
C2
3
DATE
RWH
12/6/01
CHECKED
KAB
1/4/02
Q.C.
CW
1/8/02
ISSUED
KAB
1/8/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MEMORY BD,MC8
SIZE
B
CODE
NUMBER
060-15299
REV
0
FILE NAME
15299-0 . 1
SHEET
1
1 OF 1
1-16-2002_12:45
ZA0
ZA1
ZA2
ZA3
ZA4
ZA5
ZA6
ZA7
ZA8
ZA9
ZA10
ZA11
ZA12
ZA13
ZA14
RA15
RA16
RA17
RA18
RA19
RA20
8
7
6
5
4
3
2
1
REVISIONS
REV
DRAFTER
CHECKER
RWH
5/3/02
KAB
5/6/02
CW
9/30/02
KAB
10/15/02
DESCRIPTION
1
CHANGED PER DCR 020429-00
2
UPDATE SIGNAL NAMES ON SHEETS 1,8
PER DCR 020927-00
D
+5VD +3.3VD
B
C1
A1
C2
A2
C3
A3
C4
A4
C5
A5
C6
A6
C7
A7
C8
A8
C9
A9
C10
A10
C11
A11
C12
A12
C13
A13
C14
A14
C15
A15
C16
A16
C17
A17
C18
A18
C19
A19
C20
A20
C21
A21
C22
A22
C23
A23
C24
A24
C25
A25
C26
A26
C27
A27
C28
A28
C29
A29
C30
A30
C31
A31
C32
A32
EURO64-F
EURO64-M
[8/A4]
[6/C8]
[6/C8]
[8/A4]
A12
IO
(IO)
DSPD_1A_SDO
(AUDIO6)
DSPD_1B_SDO
(AUDIO7)
AUDIO8
(AUDIO8)
AUDIO_SP0
(AUDIO_SP0)
TEST POINTS
DSPA_0A_SDI
DSPA_0B_SDI
A0A_SDI
A0B_SDI
C1
A1
C2
A2
C3
A3
C4
A4
C5
A5
C6
A6
C7
A7
C8
A8
C9
A9
C10
A10
C11
A11
C12
A12
C13
A13
C14
A14
C15
A15
C16
A16
C17
A17
C18
A18
C19
A19
C20
A20
C21
A21
C22
A22
C23
A23
C24
A24
C25
A25
C26
A26
C27
A27
C28
A28
C29
A29
C30
A30
C31
A31
C32
A32
(AUDIO0)
DSP_MCKI
(AUDIO1)
DSP_FSI
(AUDIO2)
DSP_PROG/
(AUDIO3)
DSPA_0A_SDI
(AUDIO4)
DSPA_0B_SDI
(AUDIO5)
AUDIO5
[8/B7,8/C1]
[8/B7,8/C1]
[8/D7]
[1/D1,2/C8]
[1/D1,2/C8]
[8/A4]
C
(AUDIO)
AUDIO_4MHZ
[8/A4]
NC
NC
NC
NC
NC
NC
NC
NC
NC
NOTES
DSP_A4
DSP_A3
DSP_A2
DSP_A1
DSP_A0
1 UNLESS OTHERWISE INDICATED, RESISTORS ARE 1/10W
DSP_A[4:0]
ZDSP_RD/
ZDSP_WR/
ZDSP_D0
ZDSP_D1
ZDSP_D2
ZDSP_D3
ZDSP_D4
ZDSP_D5
ZDSP_D6
ZDSP_D7
(AUDIO9)
DSP_CCLK
(AUDIO10)
DSP_DIN
2 UNLESS OTHERWISE INDICATED, RESISTORS ARE 5%
[8/D7]
[8/C7,8/D1]
[8/C7,8/D1]
[8/D5]
[8/D5]
3 UNLESS OTHERWISE INDICATED, CAPACITORS ARE UF/V
4
DIGITAL
GROUND
ANALOG
GROUND
CHASSIS
GROUND
ZDSP_D[7:0]
5 [XX/XX] DENOTES [SHEET NUMBER/SECTOR]
6 LAST REFERENCE DESIGNATORS USED: C98, D9, FB5, J3, Q1, R48, U20, W1
7 COMPONENTS MARKED WITH
[8/C7]
NC
ZDSP_CS/
ZDSP_RST/
[8/C7,8/D1]
[8/C7,8/C1]
J1
*
ARE NOT INSTALLED.
REV
2
1
1
1
1
1
1
2
1
DESCRIPTION
MAIN BD CONNECTOR
DSP A
DSP B
DSPAB EXT MEM
DSP C
DSP D
DSPCD EXT MEM
FPGA
BYPASS CAPACITORS & DSP CLOCKS
exicon
APPROVALS
DRAWN
RWH
6
5
4
3
B
DOCUMENT CONTROL BLOCK: #060-15309
SHEET
1 OF 9
2 OF 9
3 OF 9
4 OF 9
5 OF 9
6 OF 9
7 OF 9
8 OF 9
9 OF 9
© 2002 Lexicon, Inc.
CONTRACT
NO.
7
POWER
GROUND
8 NAMES IN PARENTHESES DESIGNATE GENERIC NOMENCLATURE USED
ON THE MATING CONNECTOR OF THE MAIN BOARD SCHEMATIC.
A
8
D
DATE
2/28/02
CHECKED
KB
3/5/02
Q.C.
CW
3/5/02
ISSUED
KB
3/5/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,DSP BD,MC8
MAIN BD CONNECTOR
SIZE
B
CODE
NUMBER
060-15309
REV
2
FILE NAME
15309-2. 1
SHEET
1
1 OF 9
11-18-2002_15:51
C
C32
A32
C31
A31
C30
A30
C29
A29
C28
A28
C27
A27
C26
A26
C25
A25
C24
A24
C23
A23
C22
A22
C21
A21
C20
A20
C19
A19
C18
A18
C17
A17
C16
A16
C15
A15
C14
A14
C13
A13
C12
A12
C11
A11
C10
A10
C9
A9
C8
A8
C7
A7
C6
A6
C5
A5
C4
A4
C3
A3
C2
A2
C1
A1
Q.C.
AUTH.
CW
5/7/02
KAB
5/13/02
RWH
10/15/02
KAB
10/15/02
8
7
6
5
4
2
3
1
REVISIONS
REV
1
DRAFTER
CHECKER
RWH
5/3/02
KAB
5/6/02
DESCRIPTION
CHANGED PER DCR 020429-00
Q.C.
AUTH.
CW
5/7/02
KAB
5/13/02
TEST POINTS
D
MASTER - ID0 HIGH, ID1 LOW
+3.3VD
ABCLK
ABWR/
ABRD/
ABBMS/
ABHOST_CS/
ABSRAM_CS/
R45
[3/C8,8/C4,8/C1]
[3/C8,8/C4,8/C1]
[3/C8,5/C8,6/C8,8/B4,8/C1]
[3/C8,8/C4]
[8/C4,8/C1]
[3/C6,5/C8,8/B4,8/C1]
[8/B4,8/C1]
[1/D1,1/C3]
[1/D1,1/C3]
DSPA_CLK
R46
VCC
DSPA_CLK
NC
30
31
152
157
144
143
69
AB_RST/
DSPAB_ACK
DSPAB_ACK
DSP_FSI_IRQ
SP_IRQAB
DSPAB_CMD_RDY/
CLKIN
XTAL2
BSEL
RESET
ID0
ID1
ACK
205
IRQ0
206
IRQ1
207
IRQ2
2
4
5
6
7
8
11
12
DSPABC_FSI
DSPA_SCKI
DSPA_0A_SDI
DSPA_0B_SDI
NC
NC
NC
C
13
15
16
17
18
19
22
23
NC
NC
NC
NC
RAS
CAS
SDWE
DQM
SDCKE
SDA10
SDCLK0
SDCLK1
BMS
MS0
MS1
MS2
MS3
SW
WR
RD
ADSP21065
RFS0
RCLK0
DR0A
DR0B
TFS0
TCLK0
DT0A
DT0B
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
RFS1
RCLK1
DR1A
DR1B
TFS1
TCLK1
DT1A
DT1B
26
PWMEVENT0
24
PWMEVENT1
NC
NC
38
DMAR1
39
DMAR2
50
DMAG1
51
DMAG2
40
52
55
63
56
NC
NC
[2/C1,3/B8]
[2/C1,3/B8]
[2/C1,3/B8]
B
R42
DSPAB_CPA/
DSPAB_BR1/
DSPAB_BR2/
DSPAB_STATUS_FULL
DSP_FLAG1
145
146
148
151
149
147
NC
197
198
199
201
138
137
136
134
80
79
78
76
NC
NC
NC
NC
NC
NC
102
103
115
142
202
203
NC
AF3
AF4
AF5
AF6
AF7
AF8
DEVELOPMENT ONLY:
PIN 7, BTCK, JUMP TO PIN 8
PIN 9, BTRST/, JUMP TO PIN 10
NC
NC
A
NC
+3.3VD
1
3
5
7
9
11
13
* J3
[3/B8]
[2/D1,9/C4]
8
2
4
6
8
10
12
14
R48
DSPAB_EMU/
DSPAB_ICE_CLK
DSPAB_TMS
DSPAB_TCK
DSPAB_TRST
DSPAB_TDI
DSPA_TDO
DSPAB_EMU/
DSPAB_TMS
DSPAB_TCK
DSPAB_TRST
[3/B8]
[3/B8]
EMU
TDO
TDI
TCK
TMS
TRST
FLAG0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
FLAG6
FLAG7
FLAG8
FLAG9
FLAG10
FLAG11
NC1
NC2
NC3
NC4
NC5
NC6
BMSTR
NC7
153
70
71
74
75
64
58
59
DSPAB_RAS/
DSPAB_CAS/
DSPAB_SDWE/
DSPAB_DQM
DSPAB_SDCKE
DSPAB_SDA10
DSPAB_SDCLK
NC
DSPAB_BMS/
DSPAB_SDRAM_CS/
DSPAB_HOST_CS/
DSPAB_SRAM_CS/
NC
NC
195
194
193
190
189
188
185
184
183
180
179
178
175
174
173
171
170
169
166
165
164
162
161
160
DSPAB_A0
DSPAB_A1
DSPAB_A2
DSPAB_A3
DSPAB_A4
DSPAB_A5
DSPAB_A6
DSPAB_A7
DSPAB_A8
DSPAB_A9
DSPAB_A10
DSPAB_A11
DSPAB_A12
DSPAB_A13
DSPAB_A14
DSPAB_A15
DSPAB_A16
DSPAB_A17
DSPAB_A18
DSPAB_A19
DSPAB_A20
DSPAB_A21
DSPAB_A22
DSPAB_A23
82
83
84
86
87
88
90
91
92
96
97
98
100
101
104
107
108
109
111
112
113
116
117
118
121
122
123
126
127
128
132
133
DSPAB_D0
DSPAB_D1
DSPAB_D2
DSPAB_D3
DSPAB_D4
DSPAB_D5
DSPAB_D6
DSPAB_D7
DSPAB_D8
DSPAB_D9
DSPAB_D10
DSPAB_D11
DSPAB_D12
DSPAB_D13
DSPAB_D14
DSPAB_D15
DSPAB_D16
DSPAB_D17
DSPAB_D18
DSPAB_D19
DSPAB_D20
DSPAB_D21
DSPAB_D22
DSPAB_D23
DSPAB_D24
DSPAB_D25
DSPAB_D26
DSPAB_D27
DSPAB_D28
DSPAB_D29
DSPAB_D30
DSPAB_D31
53
DSPA_BMSTR
208
NC
DSPAB_WR/
DSPAB_RD/
[2/D1,3/D3,4/C8]
[2/D1,3/D3,4/C8]
[2/D1,3/D3,4/C8]
[2/D1,3/D3,4/C8]
[2/D1,3/D3,4/C8]
[2/D1,3/D3,4/D8]
[2/D1,3/D3,4/C8]
[2/D1,3/C3,8/C7]
[2/D1,3/C3,4/C8]
[2/D1,3/C3,8/C7]
[2/D1,3/C3,4/D4]
ABCPA/
ABBR1/
ABBR2/
DSPAB_SDRAM_CS/
DSPAB_RAS/
DSPAB_CAS/
DSPAB_SDWE/
DSPAB_DQM
DSPAB_SDCKE
DSPAB_SDA10
DSPAB_SDCLK
DSPAB_CPA/
DSPAB_BR1/
DSPAB_BR2/
[2/D1,3/C3,4/B4]
[2/D1,3/C3,4/B4]
C
DSPAB_A[23:0]
[3/B3,4/D6]
B
DSPAB_D[31:0]
[3/A3,4/D7,8/C4]
DSPA_BMSTR
[3/B8]
[3/B8]
[3/B8]
U16
DSPA_OUT1
DSPA_OUT0
DSPB_TDO
DSPAB_ICE_CLK
6
5
4
exicon
CONTRACT
NO.
R47
7
ABSDRAM_CS/
ABRAS/
ABCAS/
ABSDWE/
ABDQM
ABSDCKE
ABSDA10
ABSDCLK
GND
3
10
14
25
33
35
41
49
57
60
62
68
72
73
81
89
94
99
106
114
119
125
129
135
139
150
154
155
159
167
168
177
181
186
187
196
204
+3.3VD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
65
CPA
27
BR1
28
BR2
DSPAB_EMU/
DSPA_TDO
DSPAB_TDI
DSPAB_TCK
DSPAB_TMS
DSPAB_TRST
[3/B8,8/C4]
[3/B8,5/B8,6/B8,8/B4]
HBR
HBG
CS
REDY
SBTS
42
43
44
46
47
48
37
34
D
DSPAB_ICE_CLK
DSPAB_WR/
DSPAB_RD/
DSPAB_BMS/
DSPAB_HOST_CS/
DSPAB_SRAM_CS/
3
[4/B8,8/C7]
[4/B8,8/C7]
APPROVALS
DRAWN
DATE
RWH
2/28/02
CHECKED
KB
3/5/02
Q.C.
CW
3/5/02
ISSUED
KB
3/5/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,DSP BD,MC8
DSP A
SIZE
B
CODE
NUMBER
060-15309
REV
1
FILE NAME
15309-2. 2
SHEET
1
2 OF 9
11-18-2002_15:51
[9/D4]
1
9
20
21
29
32
36
45
54
61
66
67
77
85
93
95
105
110
120
124
130
131
140
141
156
158
163
172
176
182
191
192
200
SLAVE - ID0 LOW, ID1 HIGH
8
7
6
5
4
2
3
1
REVISIONS
REV
1
D
MASTER - ID0 HIGH, ID1 LOW
DRAFTER
CHECKER
RWH
5/3/02
KAB
5/6/02
DESCRIPTION
CHANGED PER DCR 020429-00
Q.C.
AUTH.
CW
5/7/02
KAB
5/13/02
D
+3.3VD
1
9
20
21
29
32
36
45
54
61
66
67
77
85
93
95
105
110
120
124
130
131
140
141
156
158
163
172
176
182
191
192
200
SLAVE - ID0 LOW, ID1 HIGH
R44
[9/D4]
[2/C8,8/C4,8/C1]
[2/C8,8/C4,8/C1]
[2/C8,5/C8,6/C8,8/B4,8/C1]
[2/C8,8/C4]
VCC
R43
DSPB_CLK
NC
AB_RST/
DSPAB_ACK
C
DSPABC_FSI
DSPB_SCKI
NC
NC
NC
[3/D1,5/C8]
[3/D1,5/C8]
CLKIN
XTAL2
BSEL
RESET
ID0
ID1
ACK
205
IRQ0
206
IRQ1
207
IRQ2
DSP_FSI_IRQ
SP_IRQAB
NC
[2/C8,5/C8,8/B4,8/C1]
[8/A4]
30
31
152
157
144
143
69
DSPB_1A_SDO
DSPB_1B_SDO
NC
NC
2
4
5
6
7
8
11
12
13
15
16
17
18
19
22
23
ADSP21065
RFS0
RCLK0
DR0A
DR0B
TFS0
TCLK0
DT0A
DT0B
RFS1
RCLK1
DR1A
DR1B
TFS1
TCLK1
DT1A
DT1B
38
DMAR1
39
DMAR2
50
DMAG1
51
DMAG2
NC
NC
[2/C1,2/B8]
[2/C1,2/B8]
[2/C1,2/B8]
B
[2/A6]
[2/A8]
[2/A6]
[2/A6]
[2/A6]
[2/A6]
[2/B8,8/C4]
[2/B8,5/B8,6/B8,8/B4]
DSPAB_CPA/
DSPAB_BR1/
DSPAB_BR2/
HBR
HBG
CS
REDY
SBTS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
65
CPA
27
BR1
28
BR2
145
146
148
151
149
147
DSPAB_EMU/
DSPB_TDO
DSPA_TDO
DSPAB_TCK
DSPAB_TMS
DSPAB_TRST
DSPAB_STATUS_FULL
DSP_FLAG1
197
198
199
201
138
137
136
134
80
79
78
NC 76
NC
BF3
BF4
BF5
BF6
BF7
BF8
NC
NC
NC
NC
NC
NC
102
103
115
142
202
203
EMU
TDO
TDI
TCK
TMS
TRST
FLAG0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
FLAG6
FLAG7
FLAG8
FLAG9
FLAG10
FLAG11
NC1
NC2
NC3
NC4
NC5
NC6
DSPAB_RAS/
DSPAB_CAS/
DSPAB_SDWE/
DSPAB_DQM
DSPAB_SDCKE
DSPAB_SDA10
DSPAB_SDCLK
NC
153
70
71
74
75 NC
64 NC
58
59
BMS
MS0
MS1
MS2
MS3
SW
WR
RD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
26
PWMEVENT0
24
PWMEVENT1
40
52
55
63
56
42
43
44
46
47
48
37
34
RAS
CAS
SDWE
DQM
SDCKE
SDA10
SDCLK0
SDCLK1
DSPAB_WR/
DSPAB_RD/
195
194
193
190
189
188
185
184
183
180
179
178
175
174
173
171
170
169
166
165
164
162
161
160
DSPAB_A0
DSPAB_A1
DSPAB_A2
DSPAB_A3
DSPAB_A4
DSPAB_A5
DSPAB_A6
DSPAB_A7
DSPAB_A8
DSPAB_A9
DSPAB_A10
DSPAB_A11
DSPAB_A12
DSPAB_A13
DSPAB_A14
DSPAB_A15
DSPAB_A16
DSPAB_A17
DSPAB_A18
DSPAB_A19
DSPAB_A20
DSPAB_A21
DSPAB_A22
DSPAB_A23
82
83
84
86
87
88
90
91
92
96
97
98
100
101
104
107
108
109
111
112
113
116
117
118
121
122
123
126
127
128
132
133
DSPAB_D0
DSPAB_D1
DSPAB_D2
DSPAB_D3
DSPAB_D4
DSPAB_D5
DSPAB_D6
DSPAB_D7
DSPAB_D8
DSPAB_D9
DSPAB_D10
DSPAB_D11
DSPAB_D12
DSPAB_D13
DSPAB_D14
DSPAB_D15
DSPAB_D16
DSPAB_D17
DSPAB_D18
DSPAB_D19
DSPAB_D20
DSPAB_D21
DSPAB_D22
DSPAB_D23
DSPAB_D24
DSPAB_D25
DSPAB_D26
DSPAB_D27
DSPAB_D28
DSPAB_D29
DSPAB_D30
DSPAB_D31
53
BMSTR
DSPAB_BMS/
DSPAB_SDRAM_CS/
DSPAB_HOST_CS/
DSPAB_SRAM_CS/
FB5
FB4
DSPAB_WR_X/
DSPAB_RD_X/
DSPAB_A[23:0]
TEST POINTS
[2/D1,2/D3,4/C8]
[2/D1,2/D3,4/C8]
[2/D1,2/D3,4/C8]
[2/D1,2/D3,4/C8]
[2/D1,2/D3,4/C8]
[2/D1,2/D3,4/D8]
[2/D1,2/D3,4/C8]
B1A_SDO
B1B_SDO
DSPB_1A_SDO
DSPB_1B_SDO
[2/D1,2/C3,8/C7]
[2/D1,2/C3,4/C8]
[2/D1,2/C3,8/C7]
[2/D1,2/C3,4/D4]
[2/D1,2/C3,4/B4]
[2/D1,2/C3,4/B4]
[8/C7]
C
[8/C7]
[2/B3,4/D6]
B
DSPAB_D[31:0]
DSPB_BMSTR
[2/A3,4/D7,8/C4]
DSPB_BMSTR
208 NC
NC7
A
U15
exicon
CONTRACT
NO.
DSPB_OUT1
DSPB_OUT0
8
7
6
5
4
3
[4/B8,8/C7]
[4/B8,8/C7]
APPROVALS
DRAWN
DATE
RWH
2/28/02
CHECKED
KB
3/5/02
Q.C.
CW
3/5/02
ISSUED
KB
3/5/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,DSP BD,MC8
DSP B
SIZE
B
CODE
NUMBER
060-15309
REV
1
FILE NAME
15309-2 . 3
SHEET
1
3 OF 9
11-18-2002_15:51
3
10
14
25
33
35
41
49
57
60
62
68
72
73
81
89
94
99
106
114
119
125
129
135
139
150
154
155
159
167
168
177
181
186
187
196
204
GND
8
6
5
4
3
REV
DSPAB_A[23:0]
[2/D1,2/D3,3/D3]
[2/D1,2/D3,3/D3]
[2/D1,2/D3,3/D3]
[2/D1,2/C3,3/C3]
[2/D1,2/D3,3/D3]
[2/D1,2/D3,3/D3]
DSPAB_A9
DSPAB_A8
DSPAB_A7
DSPAB_A6
DSPAB_A5
DSPAB_A4
DSPAB_A3
DSPAB_A2
DSPAB_A1
DSPAB_A0
24
66
65
64
63
62
61
60
27
26
25
VDD
VDDQ
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
2MX32
100MHZ
59
DQM3
28
DQM2
71
DQM1
16
DQM0
DSPAB_DQM
DSPAB_RAS/
DSPAB_CAS/
DSPAB_SDWE/
DSPAB_SDRAM_CS/
19
RAS
18
CAS
17
WE
20
CS
DSPAB_SDCKE
DSPAB_SDCLK
67
CKE
68
CLK
73
70
69
57
30
21
14
NC6
NC5
NC4
NC3
NC2
NC1
NC0
VSS
56
54
53
51
50
48
47
45
42
40
39
37
36
34
33
31
85
83
82
80
79
77
76
74
13
11
10
8
7
5
4
2
DSPAB_D31
DSPAB_D30
DSPAB_D29
DSPAB_D28
DSPAB_D27
DSPAB_D26
DSPAB_D25
DSPAB_D24
DSPAB_D23
DSPAB_D22
DSPAB_D21
DSPAB_D20
DSPAB_D19
DSPAB_D18
DSPAB_D17
DSPAB_D16
DSPAB_D15
DSPAB_D14
DSPAB_D13
DSPAB_D12
DSPAB_D11
DSPAB_D10
DSPAB_D9
DSPAB_D8
DSPAB_D7
DSPAB_D6
DSPAB_D5
DSPAB_D4
DSPAB_D3
DSPAB_D2
DSPAB_D1
DSPAB_D0
1
2
3
4
13
14
15
16
17
18
19
20
21
29
30
31
32
DSPAB_SRAM_CS/ 5
12
DSPAB_WR/
28
DSPAB_RD/
9
25
DSPAB_A0
DSPAB_A1
DSPAB_A2
DSPAB_A3
DSPAB_A4
DSPAB_A5
DSPAB_A6
DSPAB_A7
DSPAB_A8
DSPAB_A9
DSPAB_A10
DSPAB_A11
DSPAB_A12
DSPAB_A13
DSPAB_A14
DSPAB_A15
DSPAB_A16
VSSQ
44
58
72
86
NC
NC
NC
NC
NC
NC
NC
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
6
12
32
38
46
52
78
84
[2/D1,2/D3,3/D3]
DSPAB_SDA10
23
BA1
22
BA0
3
9
35
41
49
55
75
81
1
15
29
43
DSPAB_A13
DSPAB_A12
C
DSPAB_A0
DSPAB_A1
DSPAB_A2
DSPAB_A3
DSPAB_A4
DSPAB_A5
DSPAB_A6
DSPAB_A7
DSPAB_A8
DSPAB_A9
DSPAB_A10
DSPAB_A11
DSPAB_A12
DSPAB_A13
DSPAB_A14
DSPAB_A15
DSPAB_A16
+3.3VD
D
[2/D1,2/D3,3/D3]
1
2
3
4
13
14
15
16
17
18
19
20
21
29
30
31
32
DSPAB_SRAM_CS/ 5
12
DSPAB_WR/
28
DSPAB_RD/
U14
9
25
R32
270
1/4W
R31
270
1/4W
B
[2/A3,8/C7]
[2/A3,8/C7]
[3/A3,8/C7]
[3/A3,8/C7]
DSPA_OUT0
DSPA_OUT1
DSPB_OUT0
DSPB_OUT1
R28
74VHC244-3.3V
11
13
15
17
19
A1
A2
A3
A4
G
270
1/4W
9
Y1
7
Y2
5
Y3
3
Y4
R27
270
1/4W
U8
R25
270
1/4W
R26
270
1/4W
[6/A3,8/B7]
[6/A3,8/B7]
[5/A3,8/B7]
[5/A3,8/B7]
DSPD_OUT0
DSPD_OUT1
DSPC_OUT0
DSPC_OUT1
R29
74VHC244-3.3V
2
4
6
8
1
A1
A2
A3
A4
G
270
1/4W
18
Y1
16
Y2
14
Y3
12
Y4
R30
270
1/4W
U8
D9
RED
D8
GRN
D5
RED
D4
DSPAB_A0
DSPAB_A1
DSPAB_A2
DSPAB_A3
DSPAB_A4
DSPAB_A5
DSPAB_A6
DSPAB_A7
DSPAB_A8
DSPAB_A9
DSPAB_A10
DSPAB_A11
DSPAB_A12
DSPAB_A13
DSPAB_A14
DSPAB_A15
DSPAB_A16
DSP A LED #1
A
DSP A LED #2
B
DSP B LED #1
C
DSP B LED #2
D
DSPAB_SRAM_CS/ 5
12
DSPAB_WR/
28
DSPAB_RD/
GRN
D2
RED
D3
GRN
D6
RED
D7
1
2
3
4
13
14
15
16
17
18
19
20
21
29
30
31
32
DSP D LED #2
H
9
25
DSP D LED #1
G
DSPAB_A0
DSPAB_A1
DSPAB_A2
DSPAB_A3
DSPAB_A4
DSPAB_A5
DSPAB_A6
DSPAB_A7
DSPAB_A8
DSPAB_A9
DSPAB_A10
DSPAB_A11
DSPAB_A12
DSPAB_A13
DSPAB_A14
DSPAB_A15
DSPAB_A16
DSP C LED #2
F
DSP C LED #1
E
DSPAB_SRAM_CS/
DSPAB_WR/
DSPAB_RD/
1
2
3
4
13
14
15
16
17
18
19
20
21
29
30
31
32
DSPAB_SRAM_CS/ 5
DSPAB_WR/
12
DSPAB_RD/
28
9
25
8
7
6
A0 VDD1
A1 VDD2
A2
A3
A4 128KX8
A5 12NS
A6 SRAM
A7
A8
A9
D0
D1
A10
A11
D2
A12
D3
D4
A13
D5
A14
D6
A15
D7
A16
1
5
4
DRAFTER
CHECKER
RWH
5/3/02
KAB
5/6/02
DESCRIPTION
CHANGED PER DCR 020429-00
8
24
Q.C.
AUTH.
CW
5/7/02
KAB
5/13/02
D
6
7
10
11
22
23
26
27
DSPAB_D0
DSPAB_D1
DSPAB_D2
DSPAB_D3
DSPAB_D4
DSPAB_D5
DSPAB_D6
DSPAB_D7
E
W
G
VSS1
VSS2
A0 VDD1
A1 VDD2
A2
A3
A4 128KX8
A5 12NS
A6 SRAM
A7
A8
D0
A9
D1
A10
A11
D2
A12
D3
A13
D4
D5
A14
D6
A15
D7
A16
+3.3VD
U20
8
24
C
DSPAB_D8
DSPAB_D9
DSPAB_D10
DSPAB_D11
DSPAB_D12
DSPAB_D13
DSPAB_D14
DSPAB_D15
6
7
10
11
22
23
26
27
E
W
G
VSS1
VSS2
GRN
A
[2/D1,2/C3,3/C3]
[2/D1,2/C3,3/C3]
[2/D1,2/C3,3/C3]
1
REVISIONS
+3.3VD
[2/B3,3/B3]
2
A0 VDD1
A1 VDD2
A2
A3
A4 128KX8
A5 12NS
A6 SRAM
A7
A8
D0
A9
D1
A10
A11
D2
A12
D3
D4
A13
D5
A14
D6
A15
D7
A16
+3.3VD
U19
8
24
DSPAB_D16
DSPAB_D17
DSPAB_D18
DSPAB_D19
DSPAB_D20
DSPAB_D21
DSPAB_D22
DSPAB_D23
6
7
10
11
22
23
26
27
B
E
W
G
VSS1
VSS2
A0 VDD1
A1 VDD2
A2
A3
A4 128KX8
A5 12NS
A6 SRAM
A7
A8
D0
A9
D1
A10
D2
A11
D3
A12
A13
D4
D5
A14
D6
A15
D7
A16
+3.3VD
U18
8
24
6
7
10
11
22
23
26
27
DSPAB_D24
DSPAB_D25
DSPAB_D26
DSPAB_D27
DSPAB_D28
DSPAB_D29
DSPAB_D30
DSPAB_D31
E
W
G
VSS1
VSS2
exicon
CONTRACT
NO.
APPROVALS
DRAWN
U17
3
DATE
RWH
2/28/02
CHECKED
KB
3/5/02
Q.C.
CW
3/5/02
ISSUED
KB
3/5/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,DSP BD,MC8
DSPAB EXT MEM
SIZE
B
CODE
NUMBER
060-15309
REV
1
FILE NAME
15309-2 . 4
SHEET
1
4 OF 9
11-18-2002_15:51
[2/A3,3/A3,8/C4]
7
DSPAB_D[31:0]
8
7
6
5
4
2
3
1
REVISIONS
REV
1
DRAFTER
CHECKER
RWH
5/3/02
KAB
5/6/02
DESCRIPTION
CHANGED PER DCR 020429-00
Q.C.
AUTH.
CW
5/7/02
KAB
5/13/02
+3.3VD
MASTER - ID0 HIGH, ID1 LOW
SLAVE - ID0 LOW, ID1 HIGH
R21
DSPC_CLK
R22
VCC
DSPC_CLK
NC
30
31
152
157
144
143
69
CD_RST/
[6/D8,8/B4,8/C1]
DSPCD_ACK
[6/D8,8/B4,8/C1]
DSPCD_ACK
2
4
5
6
7
8
11
12
DSPABC_FSI
DSPC_SCKI
DSPB_1A_SDO
DSPB_1B_SDO
[2/C8,3/C6,8/B4,8/C1]
[8/A4,8/C1]
[3/D1,3/C8]
[3/D1,3/C8]
CLKIN
XTAL2
BSEL
RESET
ID0
ID1
ACK
205
IRQ0
206
IRQ1
207
IRQ2
DSP_FSI_IRQ
SP_IRQCD
DSPCD_CMD_RDY/
[2/C8,3/C8,6/C8,8/B4,8/C1]
[6/C8,8/B4]
[8/B4,8/C1]
NC
NC
NC
C
13
15
16
17
18
19
22
23
NC
NC
NC
NC
RAS
CAS
SDWE
DQM
SDCKE
SDA10
SDCLK0
SDCLK1
BMS
MS0
MS1
MS2
MS3
SW
WR
RD
ADSP21065
RFS0
RCLK0
DR0A
DR0B
TFS0
TCLK0
DT0A
DT0B
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
RFS1
RCLK1
DR1A
DR1B
TFS1
TCLK1
DT1A
DT1B
26
PWMEVENT0
24
PWMEVENT1
NC
NC
38
DMAR1
39
DMAR2
50
DMAG1
51
DMAG2
40
52
55
63
56
NC
NC
R20
DSPCD_CPA/
DSPCD_BR1/
DSPCD_BR2/
[5/C1,6/B8]
[5/C1,6/B8]
[5/C1,6/B8]
145
146
148
151
149
147
DSPCD_EMU/
DSPC_TDO
DSPCD_TDI
DSPCD_TCK
DSPCD_TMS
DSPCD_TRST
DSPCD_STATUS_FULL
DSP_FLAG1
A
NC
+3.3VD
* J2
[6/B8]
[5/D1,9/C4]
2
4
6
8
10
12
14
102
103
115
142
202
203
R24
DSPCD_EMU/
DSPCD_ICE_CLK
DSPCD_TMS
DSPCD_TCK
DSPCD_TRST
DSPCD_TDI
DSPC_TDO
DSPCD_EMU/
DSPCD_TMS
DSPCD_TCK
DSPCD_TRST
[6/B8]
[6/B8]
EMU
TDO
TDI
TCK
TMS
TRST
FLAG0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
FLAG6
FLAG7
FLAG8
FLAG9
FLAG10
FLAG11
NC1
NC2
NC3
NC4
NC5
NC6
BMSTR
NC7
153
70
71
74
75
64
58
59
DSPCD_RAS/
DSPCD_CAS/
DSPCD_SDWE/
DSPCD_DQM
DSPCD_SDCKE
DSPCD_SDA10
DSPCD_SDCLK
NC
DSPCD_BMS/
DSPCD_SDRAM_CS/
DSPCD_HOST_CS/
DSPCD_SRAM_CS/
NC
NC
195
194
193
190
189
188
185
184
183
180
179
178
175
174
173
171
170
169
166
165
164
162
161
160
DSPCD_A0
DSPCD_A1
DSPCD_A2
DSPCD_A3
DSPCD_A4
DSPCD_A5
DSPCD_A6
DSPCD_A7
DSPCD_A8
DSPCD_A9
DSPCD_A10
DSPCD_A11
DSPCD_A12
DSPCD_A13
DSPCD_A14
DSPCD_A15
DSPCD_A16
DSPCD_A17
DSPCD_A18
DSPCD_A19
DSPCD_A20
DSPCD_A21
DSPCD_A22
DSPCD_A23
82
83
84
86
87
88
90
91
92
96
97
98
100
101
104
107
108
109
111
112
113
116
117
118
121
122
123
126
127
128
132
133
DSPCD_D0
DSPCD_D1
DSPCD_D2
DSPCD_D3
DSPCD_D4
DSPCD_D5
DSPCD_D6
DSPCD_D7
DSPCD_D8
DSPCD_D9
DSPCD_D10
DSPCD_D11
DSPCD_D12
DSPCD_D13
DSPCD_D14
DSPCD_D15
DSPCD_D16
DSPCD_D17
DSPCD_D18
DSPCD_D19
DSPCD_D20
DSPCD_D21
DSPCD_D22
DSPCD_D23
DSPCD_D24
DSPCD_D25
DSPCD_D26
DSPCD_D27
DSPCD_D28
DSPCD_D29
DSPCD_D30
DSPCD_D31
53
DSPC_BMSTR
208
NC
DSPCD_WR/
DSPCD_RD/
FB2
FB3
DSPCD_RD_X/
DSPCD_A[23:0]
DSPCD_D[31:0]
CDCLK
CDWR/
CDRD/
CDBMS/
CDHOST_CS/
CDSRAM_CS/
[5/D1,6/D3,8/B7]
[5/C1,6/D3,7/C8]
[5/C1,6/D3,8/B7]
[5/C1,6/C3,7/D4]
CDSDRAM_CS/
CDRAS/
CDCAS/
CDSDWE/
CDDQM
CDDCKE
CDSDA10
CDSDCLK
[5/D1,6/C3,7/B4]
[5/D1,6/C3,7/B4]
[8/B7]
CDCPA/
CDBR1/
CDBR2/
[8/B7]
DSPCD_ICE_CLK
DSPCD_WR/
DSPCD_RD/
DSPCD_BMS/
DSPCD_HOST_CS/
DSPCD_SRAM_CS/
DSPCD_SDRAM_CS/
DSPCD_RAS/
DSPCD_CAS/
DSPCD_SDWE/
DSPCD_DQM
DSPCD_SDCKE
DSPCD_SDA10
DSPCD_SDCLK
DSPCD_CPA/
DSPCD_BR1/
DSPCD_BR2/
C
[6/C3,7/D5]
[6/A3,7/D7,8/B4]
DSPC_BMSTR
[6/B8]
[6/B8]
[6/B8]
U6
exicon
CONTRACT
NO.
R23
DSPC_OUT1
DSPC_OUT0
DSPCD_ICE_CLK
7
TEST POINTS
B
DSPD_TDO
8
DSPCD_WR_X/
[5/C1,6/D3,7/C8]
[5/C1,6/D3,7/C8]
[5/C1,6/D3,7/C8]
[5/C1,6/D3,7/C8]
[5/C1,6/D3,7/C8]
[5/C1,6/D3,7/D8]
[5/C1,6/D3,7/C8]
GND
3
10
14
25
33
35
41
49
57
60
62
68
72
73
81
89
94
99
106
114
119
125
129
135
139
150
154
155
159
167
168
177
181
186
187
196
204
1
3
5
7
9
11
13
NC
NC
NC
NC
NC
NC
CF3
CF4
CF5
CF6
CF7
CF8
PIN 7, BTCK, JUMP TO PIN 8
PIN 9, BTRST/, JUMP TO PIN 10
NC
NC
NC
197
198
199
201
138
137
136
134
80
79
78
76
NC
DEVELOPMENT ONLY:
+3.3VD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
65
CPA
27
BR1
28
BR2
B
[6/B8,8/B4]
[2/B8,3/B8,6/B8,8/B4]
HBR
HBG
CS
REDY
SBTS
42
43
44
46
47
48
37
34
6
5
4
3
[4/A8,8/B7]
[4/A8,8/B7]
APPROVALS
DRAWN
DATE
RWH
2/28/02
CHECKED
KB
3/5/02
Q.C.
CW
3/5/02
ISSUED
KB
3/5/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,DSP BD,MC8
DSP C
SIZE
B
CODE
FILE NAME
15309-2. 5
NUMBER
060-15309
SHEET
1
REV
1
5 OF 9
11-18-2002_15:51
[9/C4]
D
1
9
20
21
29
32
36
45
54
61
66
67
77
85
93
95
105
110
120
124
130
131
140
141
156
158
163
172
176
182
191
192
200
D
8
7
6
5
4
2
3
1
REVISIONS
REV
1
DRAFTER
CHECKER
RWH
5/3/02
KAB
5/6/02
DESCRIPTION
CHANGED PER DCR 020429-00
+3.3VD
Q.C.
AUTH.
CW
5/7/02
KAB
5/13/02
MASTER - ID0 HIGH, ID1 LOW
SLAVE - ID0 LOW, ID1 HIGH
D
1
9
20
21
29
32
36
45
54
61
66
67
77
85
93
95
105
110
120
124
130
131
140
141
156
158
163
172
176
182
191
192
200
D
R19
[9/C4]
[5/C8,8/B4,8/C1]
[5/C8,8/B4,8/C1]
[2/C8,3/C8,5/C8,8/B4,8/C1]
[5/C8,8/B4]
VCC
R18
DSPD_CLK
NC
CD_RST/
DSPCD_ACK
DSP_FSI_IRQ
SP_IRQCD
DSPD_FSI
DSPD_SCKI
NC
NC
C
NC
[1/C7]
[1/C7]
CLKIN
XTAL2
BSEL
RESET
ID0
ID1
ACK
205
IRQ0
206
IRQ1
207
IRQ2
NC
[8/B4,8/C1]
[8/A4]
30
31
152
157
144
143
69
DSPD_1A_SDO
DSPD_1B_SDO
NC
NC
2
4
5
6
7
8
11
12
13
15
16
17
18
19
22
23
ADSP21065
RFS0
RCLK0
DR0A
DR0B
TFS0
TCLK0
DT0A
DT0B
RFS1
RCLK1
DR1A
DR1B
TFS1
TCLK1
DT1A
DT1B
38
DMAR1
39
DMAR2
50
DMAG1
51
DMAG2
NC
NC
[5/C1,5/B8]
[5/C1,5/B8]
[5/C1,5/B8]
[5/A6]
[5/A8]
[5/A6]
[5/A6]
[5/A6]
[5/A6]
B
[5/B8,8/B4]
[2/B8,3/B8,5/B8,8/B4]
HBR
HBG
CS
REDY
SBTS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
65
CPA
27
BR1
28
BR2
DSPCD_CPA/
DSPCD_BR1/
DSPCD_BR2/
DSPCD_EMU/
DSPD_TDO
DSPC_TDO
DSPCD_TCK
DSPCD_TMS
DSPCD_TRST
145
146
148
151
149
147
DSPCD_STATUS_FULL
DSP_FLAG1
197
198
199
201
138
137
136
134
80
79
78
NC 76
NC
DF3
DF4
DF5
DF6
DF7
DF8
NC
NC
NC
NC
NC
NC
102
103
115
142
202
203
BMS
MS0
MS1
MS2
MS3
SW
WR
RD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
26
PWMEVENT0
24
PWMEVENT1
40
52
55
63
56
RAS
CAS
SDWE
DQM
SDCKE
SDA10
SDCLK0
SDCLK1
EMU
TDO
TDI
TCK
TMS
TRST
FLAG0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
FLAG6
FLAG7
FLAG8
FLAG9
FLAG10
FLAG11
NC1
NC2
NC3
NC4
NC5
NC6
BMSTR
NC7
42
43
44
46
47
48
37
34
DSPCD_RAS/
DSPCD_CAS/
DSPCD_SDWE/
DSPCD_DQM
DSPCD_SDCKE
DSPCD_SDA10
DSPCD_SDCLK
NC
153
70
71
74
75 NC
64 NC
58
59
DSPCD_BMS/
DSPCD_SDRAM_CS/
DSPCD_HOST_CS/
DSPCD_SRAM_CS/
DSPCD_WR/
DSPCD_RD/
195
194
193
190
189
188
185
184
183
180
179
178
175
174
173
171
170
169
166
165
164
162
161
160
DSPCD_A0
DSPCD_A1
DSPCD_A2
DSPCD_A3
DSPCD_A4
DSPCD_A5
DSPCD_A6
DSPCD_A7
DSPCD_A8
DSPCD_A9
DSPCD_A10
DSPCD_A11
DSPCD_A12
DSPCD_A13
DSPCD_A14
DSPCD_A15
DSPCD_A16
DSPCD_A17
DSPCD_A18
DSPCD_A19
DSPCD_A20
DSPCD_A21
DSPCD_A22
DSPCD_A23
82
83
84
86
87
88
90
91
92
96
97
98
100
101
104
107
108
109
111
112
113
116
117
118
121
122
123
126
127
128
132
133
DSPCD_D0
DSPCD_D1
DSPCD_D2
DSPCD_D3
DSPCD_D4
DSPCD_D5
DSPCD_D6
DSPCD_D7
DSPCD_D8
DSPCD_D9
DSPCD_D10
DSPCD_D11
DSPCD_D12
DSPCD_D13
DSPCD_D14
DSPCD_D15
DSPCD_D16
DSPCD_D17
DSPCD_D18
DSPCD_D19
DSPCD_D20
DSPCD_D21
DSPCD_D22
DSPCD_D23
DSPCD_D24
DSPCD_D25
DSPCD_D26
DSPCD_D27
DSPCD_D28
DSPCD_D29
DSPCD_D30
DSPCD_D31
53
DSPD_BMSTR
[5/C1,5/D2,7/C8]
[5/C1,5/D2,7/C8]
[5/C1,5/D2,7/C8]
[5/C1,5/D2,7/C8]
[5/C1,5/D2,7/C8]
[5/C1,5/D2,7/D8]
[5/C1,5/D2,7/C8]
[5/D1,5/C2,8/B7]
[5/C1,5/C2,7/C8]
[5/C1,5/C2,8/B7]
[5/C1,5/C2,7/D4]
[5/C2,5/D1,7/B4]
[5/C2,5/D1,7/B4]
C
DSPCD_A[23:0]
[5/B3,7/D5]
B
DSPCD_D[31:0]
[5/A3,7/D7,8/B4]
DSPD_BMSTR
208 NC
U5
A
exicon
CONTRACT
NO.
DSPD_OUT1
DSPD_OUT0
8
7
6
5
4
3
[4/A8,8/B7]
[4/A8,8/B7]
APPROVALS
DRAWN
DATE
RWH
2/28/02
CHECKED
KB
3/5/02
Q.C.
CW
3/5/02
ISSUED
KB
3/5/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,DSP BD,MC8
DSP D
SIZE
B
CODE
NUMBER
060-15309
REV
1
FILE NAME
15309-2 . 6
SHEET
1
6 OF 9
11-18-2002_15:51
3
10
14
25
33
35
41
49
57
60
62
68
72
73
81
89
94
99
106
114
119
125
129
135
139
150
154
155
159
167
168
177
181
186
187
196
204
GND
[5/A3,6/A3,8/B4]
7
6
5
4
2
3
1
REVISIONS
DSPCD_D[31:0]
REV
1
DRAFTER
CHECKER
RWH
5/3/02
KAB
5/6/02
DESCRIPTION
CHANGED PER DCR 020429-00
+3.3VD
[5/B3,6/C3]
DSPCD_A[23:0]
+3.3VD
[5/C1,5/D2,6/D3]
[5/C1,5/D2,6/D3]
[5/C1,5/D2,6/D3]
[5/C1,5/D2,6/D3]
[5/C1,5/D2,6/D3]
[5/C1,5/C2,6/D3]
C
[5/C1,5/D2,6/D3]
[5/C1,5/D2,6/D3]
DSPCD_SDA10
DSPCD_A9
DSPCD_A8
DSPCD_A7
DSPCD_A6
DSPCD_A5
DSPCD_A4
DSPCD_A3
DSPCD_A2
DSPCD_A1
DSPCD_A0
24
66
65
64
63
62
61
60
27
26
25
VDD
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DSPCD_DQM
59
DQM3
28
DQM2
71
DQM1
16
DQM0
DSPCD_RAS/
DSPCD_CAS/
DSPCD_SDWE/
DSPCD_SDRAM_CS/
19
RAS
18
CAS
17
WE
20
CS
DSPCD_SDCKE
DSPCD_SDCLK
67
CKE
68
CLK
73
70
69
57
30
21
14
NC6
NC5
NC4
NC3
NC2
NC1
NC0
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
2MX32
100MHZ
VSS
44
58
72
86
NC
NC
NC
NC
NC
NC
NC
VDDQ
56
54
53
51
50
48
47
45
42
40
39
37
36
34
33
31
85
83
82
80
79
77
76
74
13
11
10
8
7
5
4
2
DSPCD_D31
DSPCD_D30
DSPCD_D29
DSPCD_D28
DSPCD_D27
DSPCD_D26
DSPCD_D25
DSPCD_D24
DSPCD_D23
DSPCD_D22
DSPCD_D21
DSPCD_D20
DSPCD_D19
DSPCD_D18
DSPCD_D17
DSPCD_D16
DSPCD_D15
DSPCD_D14
DSPCD_D13
DSPCD_D12
DSPCD_D11
DSPCD_D10
DSPCD_D9
DSPCD_D8
DSPCD_D7
DSPCD_D6
DSPCD_D5
DSPCD_D4
DSPCD_D3
DSPCD_D2
DSPCD_D1
DSPCD_D0
1
2
3
4
13
14
15
16
17
18
19
20
21
29
30
31
32
DSPCD_SRAM_CS/
DSPCD_WR/
DSPCD_RD/
5
12
28
9
25
VSSQ
6
12
32
38
46
52
78
84
DSPCD_A13 23
BA1
DSPCD_A12 22
BA0
3
9
35
41
49
55
75
81
1
15
29
43
D
DSPCD_A0
DSPCD_A1
DSPCD_A2
DSPCD_A3
DSPCD_A4
DSPCD_A5
DSPCD_A6
DSPCD_A7
DSPCD_A8
DSPCD_A9
DSPCD_A10
DSPCD_A11
DSPCD_A12
DSPCD_A13
DSPCD_A14
DSPCD_A15
DSPCD_A16
U4
DSPCD_A0
DSPCD_A1
DSPCD_A2
DSPCD_A3
DSPCD_A4
DSPCD_A5
DSPCD_A6
DSPCD_A7
DSPCD_A8
DSPCD_A9
DSPCD_A10
DSPCD_A11
DSPCD_A12
DSPCD_A13
DSPCD_A14
DSPCD_A15
DSPCD_A16
1
2
3
4
13
14
15
16
17
18
19
20
21
29
30
31
32
DSPCD_SRAM_CS/
DSPCD_WR/
DSPCD_RD/
5
12
28
9
25
B
DSPCD_A0
DSPCD_A1
DSPCD_A2
DSPCD_A3
DSPCD_A4
DSPCD_A5
DSPCD_A6
DSPCD_A7
DSPCD_A8
DSPCD_A9
DSPCD_A10
DSPCD_A11
DSPCD_A12
DSPCD_A13
DSPCD_A14
DSPCD_A15
DSPCD_A16
1
2
3
4
13
14
15
16
17
18
19
20
21
29
30
31
32
DSPCD_SRAM_CS/
DSPCD_WR/
DSPCD_RD/
5
12
28
9
25
A
[5/C1,5/C2,6/C3]
[5/C2,5/D1,6/C3]
[5/C2,5/D1,6/C3]
DSPCD_SRAM_CS/
DSPCD_WR/
DSPCD_RD/
DSPCD_A0
DSPCD_A1
DSPCD_A2
DSPCD_A3
DSPCD_A4
DSPCD_A5
DSPCD_A6
DSPCD_A7
DSPCD_A8
DSPCD_A9
DSPCD_A10
DSPCD_A11
DSPCD_A12
DSPCD_A13
DSPCD_A14
DSPCD_A15
DSPCD_A16
1
2
3
4
13
14
15
16
17
18
19
20
21
29
30
31
32
DSPCD_SRAM_CS/
DSPCD_WR/
DSPCD_RD/
5
12
28
9
25
8
7
6
5
4
A0 VDD1
A1 VDD2
A2
A3
A4 128KX8
A5 12NS
A6 SRAM
A7
A8
A9
D0
D1
A10
A11
D2
A12
D3
A13
D4
D5
A14
D6
A15
D7
A16
Q.C.
AUTH.
CW
5/7/02
KAB
5/13/02
8
24
D
DSPCD_D0
DSPCD_D1
DSPCD_D2
DSPCD_D3
DSPCD_D4
DSPCD_D5
DSPCD_D6
DSPCD_D7
6
7
10
11
22
23
26
27
E
W
G
VSS1
VSS2
A0 VDD1
A1 VDD2
A2
A3
A4 128KX8
A5 12NS
A6 SRAM
A7
A8
D0
A9
D1
A10
A11
D2
A12
D3
A13
D4
D5
A14
D6
A15
D7
A16
+3.3VD
U12
8
24
C
DSPCD_D8
DSPCD_D9
DSPCD_D10
DSPCD_D11
DSPCD_D12
DSPCD_D13
DSPCD_D14
DSPCD_D15
6
7
10
11
22
23
26
27
E
W
G
VSS1
VSS2
A0 VDD1
A1 VDD2
A2
A3
A4 128KX8
A5 12NS
A6 SRAM
A7
A8
A9
D0
D1
A10
A11
D2
A12
D3
A13
D4
D5
A14
D6
A15
D7
A16
+3.3VD
U11
8
24
DSPCD_D16
DSPCD_D17
DSPCD_D18
DSPCD_D19
DSPCD_D20
DSPCD_D21
DSPCD_D22
DSPCD_D23
6
7
10
11
22
23
26
27
B
E
W
G
VSS1
VSS2
A0 VDD1
A1 VDD2
A2
A3
A4 128KX8
A5 12NS
A6 SRAM
A7
A8
D0
A9
D1
A10
A11
D2
A12
D3
A13
D4
D5
A14
D6
A15
D7
A16
+3.3VD
U10
8
24
6
7
10
11
22
23
26
27
E
W
G
VSS1
VSS2
DSPCD_D24
DSPCD_D25
DSPCD_D26
DSPCD_D27
DSPCD_D28
DSPCD_D29
DSPCD_D30
DSPCD_D31
exicon
CONTRACT
NO.
APPROVALS
DRAWN
U9
3
DATE
RWH
2/28/02
CHECKED
KB
3/5/02
Q.C.
CW
3/5/02
ISSUED
KB
3/5/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,DSP BD,MC8
DSPCD EXT MEM
SIZE
B
CODE
NUMBER
060-15309
REV
1
FILE NAME
15309-2 . 7
SHEET
1
7 OF 9
11-18-2002_15:51
8
7
6
5
4
2
3
+3.3VD
[1/B3]
[1/B3]
REV
R40
DSP_DIN
270
1/4W
GRN
DSP_CCLK
+3.3VD
+3.3VD
+3.3VD
R36
SEE NOTES
[1/C3]
[1/B4]
[1/B4]
[1/B3,8/D1]
[1/B3,8/D1]
[1/B3,8/D1]
[1/B3,8/C1]
C
[2/D1,2/C3,3/C3]
[2/D1,2/C3,3/C3]
[3/C3]
[3/C3]
[2/A3,4/B8]
[3/A3,4/B8]
[2/A3,4/B8]
[3/A3,4/B8]
DSP_PROG/
E17
R37
DSP_A[4:0]
ZDSP_D[7:0]
NC
NC
22
M1
26
NC2
52
PROGRAM
DSP_A0
DSP_A1
DSP_A2
DSP_A3
DSP_A4
7
8
9
10
13
ZDSP_D0
ZDSP_D1
ZDSP_D2
ZDSP_D3
ZDSP_D4
ZDSP_D5
ZDSP_D6
ZDSP_D7
14
15
16
17
18
19
20
31
VCC
M0
XCS05XL-VQ100
DONE
INIT
CCLK
IO_DIN
IO_DOUT
A0
A1
A2
A3
A4
B
[4/A8,5/A3]
[4/A8,6/A3]
[4/A8,5/A3]
[4/A8,6/A3]
[1/D3,8/C1]
[1/C3,8/C1]
[9/D4]
D0
D1
D2
D3
D4
D5
D6
D7
DSPAB_D0
DSPAB_D1
DSPAB_D2
DSPAB_D3
DSPAB_D4
DSPAB_D5
DSPAB_D6
DSPAB_D7
29
ZDB_RD
21
ZDB_WR
32
DB_CS
3
DB_RST
DSPAB_HOST_CS/
DSPAB_BMS/
DSPAB_WR_X/
DSPAB_RD_X/
34
DSPAB_HOST_CS
35
DSPAB_BMS
48
DSPAB_WR
40
DSPAB_RD
DSPA_OUT0
DSPB_OUT0
DSPA_OUT1
DSPB_OUT1
4
DSPA_OUT0
5
DSPB_OUT0
27
DSPA_OUT1
85
DSPB_OUT1
W1
4
3
2
5
IO_DOUT
60
61
62
65
66
67
68
69
DSPAB_D0
DSPAB_D1
DSPAB_D2
DSPAB_D3
DSPAB_D4
DSPAB_D5
DSPAB_D6
DSPAB_D7
*
VPP
VCC
CE
OE DATA
CLK CEO
GND
41
DSPCD_HOST_CS
42
DSPCD_BMS
54
DSCD_WR
44
DSPCD_RD
DSPC_OUT0
DSPD_OUT0
DSPC_OUT1
DSPD_OUT1
6
DSPC_OUT0
56
DSPD_OUT0
86
DSPC_OUT1
87
DSPD_OUT1
DSP_MCKI
DSP_FSI
99
DB_MCKI
93
DB_FSI
70
71
78
80
81
82
83
84
DSPCD_D0
DSPCD_D1
DSPCD_D2
DSPCD_D3
DSPCD_D4
DSPCD_D5
DSPCD_D6
DSPCD_D7
Q1
TEST POINTS
U13
ZRD/
ZWR/
ZCS/
ZRST/
DSP_FLAG1
DSP_FSI_IRQ
DSPABC_FSI
DSPD_FSI
DSPA_SCKI
DSPB_SCKI
DSPC_SCKI
DSPD_SCKI
DSP_CLK
SP0
SP1
SP2
SP3
SP4
DSPCD_D[31:0]
DSP_FLAG1
94
91
59
95
96
97
98
DSP_FSI_IRQ
DSPABC_FSI
DSPD_FSI
DSPA_SCKI
DSPB_SCKI
DSPC_SCKI
DSPD_SCKI
33
33
33
33
R38
92
90
79
55
58
R35
R34
88
77
64
49
38
23
11
1
U7
SP4
5
[2/A3,3/A3,4/D7]
[2/C8,3/C8,8/C1]
[2/C8,3/C8,8/C1]
[2/C8,8/C1]
[2/B8,3/B8]
[2/C8,3/C8]
MCKI
DSP_FSI
DSPAB_ACK
DSPAB_CMD_RDY/
AB_RST/
DSPCD_ACK
DSPCD_CMD_RDY/
CD_RST/
DSPABC_FSI
DSPD_FSI
DSP_FSI_IRQ
DSPA_SCKI
DSPC_SCKI
C
DSP_MCKI
DSP_FSI
M1,M0 = 1,1 SLAVE SERIAL MODE
76
R17
R16
R15
R14
ABC_FSI
D_FSI
FSI_IRQ
A_SCKI
C_SCKI
ZDSP_RD/
ZDSP_WR/
ZDSP_CS/
ZDSP_RST/
1 M1,M0 HAVE WEAK PULLUPS
CD_RST/
DSPCD_ACK
DSPCD_CMD_RDY/
DSPCD_STATUS_FULL
SP_IRQCD
30
CD_RST
39
DSPCD_ACK
46
DSPCD_CMD_RDY
33
DSP_CD_STAT_FULL
53
SP_IRQCD
D
NOTES
GND
6
CHANGE SIGNAL AUDIO9 TO AUDIO_4MHZ
PER DCR 020927-00
Q.C.
AUTH.
CW
5/7/02
KAB
5/13/02
RWH
10/15/02
KAB
10/15/02
1
6 NC
DSPAB_D[31:0]
R33
7
2
2N3904
CDACK
CDRDY/
CDRST/
A
8
CHANGED PER DCR 020429-00
DRAFTER
CHECKER
RWH
5/3/02
KAB
5/6/02
CW
9/30/02
KAB
10/15/02
7
8
AB_RST/
DSPAB_ACK
DSPAB_CMD_RDY/
DSPAB_STATUS_FULL
SP_IRQAB
43
AB_RST
47
DSPAB_ACK
45
DSPAB_CMD_RDY
28
DSPAB_STAT_FULL
57
SP_IRQAB
DSPCD_HOST_CS/
DSPCD_BMS/
DSPCD_WR_X/
DSPCD_RD_X/
2
*
24
50
36
74
72
73
1
ABACK
ABRDY/
ABRST/
ZDSP_RD/
ZDSP_WR/
ZDSP_CS/
ZDSP_RST/
DSP_30MHZ
XC17S05XL
DSP FPGA
DSPCD_D0
DSPCD_D1
DSPCD_D2
DSPCD_D3
DSPCD_D4
DSPCD_D5
DSPCD_D6
DSPCD_D7
[5/C1,5/C2,6/D3]
[5/D1,5/C2,6/D3]
[5/C2]
[5/C2]
R41
R39
4.7K
+3.3VD
4.7K
89
100
12
25
37
51
63
75
10K
FPGA_DONE
DESCRIPTION
FPGA DONE LED
D1
D
1
REVISIONS
M1,M0 = 1,0 MASTER SERIAL MODE
[5/A3,6/A3,7/D7]
2 JUMPER W1 TO GND TO USE CONFIGURATION ROM.
[5/C8,6/D8,8/C1]
[5/C8,6/D8,8/C1]
[5/C8,8/C1]
[5/B8,6/B8]
[5/C8,6/C8]
B
[2/B8,3/B8,5/B8,6/B8]
[2/C8,3/C8,5/C8,6/C8,8/C1]
[2/C8,3/C6,5/C8,8/C1]
[6/C6,8/C1]
[2/C8,8/C1]
[3/C8]
[5/C8,8/C1]
[6/C8]
IO
AUDIO5
AUDIO8
AUDIO_4MHZ
[1/D7]
[1/C3]
[1/C7]
exicon
CONTRACT
NO.
[1/C3]
IO
A5
A8
A9
SP4
APPROVALS
DRAWN
4
3
DATE
RWH
2/28/02
CHECKED
KB
3/5/02
Q.C.
CW
3/5/02
ISSUED
KB
3/5/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,DSP BD,MC8
FPGA
SIZE
B
CODE
NUMBER
060-15309
REV
2
FILE NAME
15309-2. 8
SHEET
1
8 OF 9
11-18-2002_15:51
8
8
7
6
5
4
3
2
1
REVISIONS
REV
1
DRAFTER
CHECKER
RWH
5/3/02
KAB
5/6/02
DESCRIPTION
CHANGED PER DCR 020429-00
Q.C.
AUTH.
CW
5/7/02
KAB
5/13/02
+3.3VD
D
R3
10K
1
4
30.000MHZ
VDD
3.3V
IN
OUT
GND
2
D
R6
33
DSP_30MHZ
R11
33
DSPA_CLK
33
DSPB_CLK
33
DSPAB_ICE_CLK
R8
33
DSPC_CLK
R10
33 DSPD_CLK
3
R4
[8/A7]
R7
U2
33
1
U3
2
[2/D8]
74LCX14-3.3V
+3.3VD
3
U3
4
R12
[3/D8]
74LCX14-3.3V
FB1
*
R2
1
CLK_IN
NC 2
NC
*
R1
4 SS%
7 FS1
8 FS2
C
6
W181-01
GND
5
*
U1
U3
6
R13
[2/D1,2/A8]
74LCX14-3.3V
C1
VDD
CLK_OUT
3
*
5
.1/25
R5
*
C2
*
13
*
U3
12
[5/D8]
74LCX14-3.3V
10/10
9
U3
8
[6/D8]
74LCX14-3.3V
11
U3
10
C
R9
33 DSPCD_ICE_CLK
[5/D1,5/A8]
74LCX14-3.3V
+3.3VD
C3
.1/25
B
C15
C5
.1/25
C10
C11
C12
C13
C14
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C44
C45
C46
C47
C49
C50
C56
C57
C58
C59
C61
C62
C68
C69
C51
.1/25
C63
.1/25
C75
.1/25
C87
.1/25
.1/25
C40
C41
.1/25
.1/25
C52
C53
.1/25
.1/25
C64
C65
.1/25
.1/25
C76
C77
.1/25
.1/25
C88
C89
.1/25
.1/25
.1/25
C42
.1/25
C54
.1/25
C66
.1/25
C78
.1/25
C90
.1/25
C19
C9
.1/25
.1/25
C18
C8
.1/25
.1/25
C39
C17
C7
.1/25
.1/25
.1/25
C16
C6
.1/25
.1/25
.1/25
A
C4
.1/25
.1/25
C43
.1/25
C55
.1/25
C67
.1/25
C79
.1/25
C91
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
C80
.1/25
C92
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
C48
.1/25
.1/25
C60
.1/25
.1/25
.1/25
.1/25
C70
C71
.1/25
.1/25
.1/25
.1/25
C81
C82
C83
C84
C85
C86
C97
C98
C93
.1/25
C94
.1/25
.1/25
C95
.1/25
C73
.1/25
.1/25
.1/25
C72
.1/25
.1/25
C96
.1/25
.1/25
B
.1/25
.1/25
.1/25
.1/25
.1/25
C74
.1/25
exicon
CONTRACT
NO.
.1/25
APPROVALS
DRAWN
8
7
6
5
4
3
DATE
RWH
2/28/02
CHECKED
KB
3/5/02
Q.C.
CW
3/5/02
ISSUED
KB
3/5/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,DSP BD,MC8
BYPASS CAPACITORS & DSP CLOCKS
SIZE
B
CODE
NUMBER
060-15309
REV
1
FILE NAME
15309-2 . 9
SHEET
1
9 OF 9
11-18-2002_15:51
+3.3V DIGITAL BYPASS CAPACITORS
8
7
6
5
4
2
3
1
REVISIONS
REV
DRAFTER
CHECKER
RWH
6/10/02
KB
6/12/02
RWH
8/29/02
KB
9/5/02
DESCRIPTION
1
CHANGED PER DCR 020604-00
2
CHANGED PER DCR 020814-00
D
Q.C.
AUTH.
CW
6/24/02
KB
6/24/02
CW
9/5/02
KB
9/9/02
D
+5VD +3.3VD
EURO64-RA-M
[2/B4,2/C1]
[2/B4,2/C1]
[2/B4,2/C1]
[2/B4]
C
[2/C4]
DB_SDO0
(AUDIO4)
DB_SDO1
(AUDIO5)
DB_SDO2
(AUDIO6)
DB_SDO3
(AUDIO7)
DB_AB_C_INT/
(AUDIO8)
C32
A32
C31
A31
C30
A30
C29
A29
C28
A28
C27
A27
C26
A26
C25
A25
C24
A24
C23
A23
C22
A22
C21
A21
C20
A20
C19
A19
C18
A18
C17
A17
C16
A16
C15
A15
C14
A14
C13
A13
C12
A12
C11
A11
C10
A10
C9
A9
C8
A8
C7
A7
C6
A6
C5
A5
C4
A4
C3
A3
C2
A2
C1
A1
B
(AUDIO0)
DB_MCKI
(IO)
IO
(MC12 - DAR)
(AUDIO1)
DB_FSI
(AUDIO2)
DB_PROG/
(AUDIO3)
DB_SDI
[2/B7,2/C1]
[2/A7,2/C1]
[2/B7,2/C1]
[2/D7]
[2/B7]
C
(AUDIO)
DB_4MHZ
[2/C7]
NC
NC
NC
NC
NC
NC
NC
NC
NC
DB_A[4:0]
DB_A4
DB_A3
DB_A2
DB_A1
DB_A0
NOTES
[2/D6]
1 UNLESS OTHERWISE INDICATED, RESISTORS ARE 1/10W
2 UNLESS OTHERWISE INDICATED, RESISTORS ARE 5%
3 UNLESS OTHERWISE INDICATED, CAPACITORS ARE UF/V
DB_RD/
[2/C7,2/D1]
DB_WR/
DB_D0
DB_D1
DB_D2
DB_D3
DB_D4
DB_D5
DB_D6
DB_D7
(AUDIO9)
DB_CCLK
(AUDIO10)
DB_DIN
[2/C7,2/D1]
[2/D5]
[2/D5]
4
DIGITAL
GROUND
ANALOG
GROUND
CHASSIS
GROUND
POWER
GROUND
5 [XX/XX] DENOTES [SHEET NUMBER/SECTOR]
6 LAST REFERENCE DESIGNATORS USED: C28, D3, FB1, J1, Q1, R8, RP6,
U6, W1.
7 COMPONENTS MARKED WITH
*
B
ARE NOT ON BOM.
8. NAMES IN PARENTHESES DESIGNATE GENERIC NOMENCLATURE USED
ON THE MATING CONNECTOR OF THE MAIN BOARD SCHEMATIC.
DB_D[7:0]
[2/C6]
DOCUMENT CONTROL BLOCK: #060-15319
AUDIO12
(AUDIO12) (MC12- IO)
[2/A7,2/C1]
NC
DB_CS/
[2/C7,2/D1]
DB_RST/
SHEET
1 OF 4
2 OF 4
3 OF 4
3 OF 4
REV
2
2
2
2
DESCRIPTION
MAIN BD CONNECTOR
FPGA
DOLBY DIGITAL/DTS DECODER
REGULATOR & BYPASS CAPS
[2/C7,2/C1]
J1
© 2002 Lexicon, Inc.
CONTRACT
NO.
exicon
APPROVALS
DRAWN
RWH
8
7
6
5
4
3
DATE
3/21/02
CHECKED
KB
3/26/02
Q.C.
CW
3/26/02
ISSUED
KB
3/26/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,DECODER BD,MC8/MC12
MAIN BD CONNECTOR
SIZE
B
CODE
NUMBER
060-15319
REV
2
FILE NAME
15319-2. 1
SHEET
1
1 OF 4
10-23-2002_14:31
A
7
6
5
4
2
3
1
REVISIONS
+3.3VD
REV
[1/B3]
[1/B3]
R6
DB_DIN
270
1/4W
GRN
DB_CCLK
FPGA DONE LED
D2
+3.3VD
+3.3VD
D
+3.3VD
SEE NOTES
R3
E1
DB_PROG/
[1/C3]
[3/C1,3/C7]
[3/C1,3/C8]
[3/C1,3/C8]
[3/C1,3/C8]
[3/C1,3/C8]
[3/C1,3/A3]
[3/C1,3/A3]
[3/C1,3/C3]
[3/C1,3/A3]
[1/D3,2/C1]
[1/C3,2/C1]
[1/C3]
[3/B1,3/B3]
[3/B1,3/B3]
[3/B1,3/B3]
[3/B1,3/B3]
[1/D3,2/C1]
14
15
16
17
18
19
20
21
VCC
M0
XCS05XL-VQ100
DONE
INIT
CCLK
IO_DIN
IO_DOUT
PROGRAM
A0
A1
A2
A3
A4
2
DB_4MHZ
DEC_AB_ABOOT/IRQ
DEC_C_ABOOT/IRQ
DEC_HINBSY/
31
DEC_AB_ABOOT/IRQ
29
DEC_C_ABOOT/IRQ
57
DEC_HINBSY
DEC_AB_SCDOUT
DEC_C_SCDOUT
39
DEC_GPIO20
40
DEC_GPIO21
DEC_NVWE/
41
DEC_CLK
48
DB_MCKI
DB_FSI
79
DB_MCKI
80
DB_FSI
DB_SDI
81
DEC_SDO0
DEC_SDO1
DEC_SDO2
DEC_SDO3
68
DEC_SDO0
69
DEC_SDO1
70
DEC_SDO2
71
DEC_SDO3
DEC_NVWE
DB_AB_C_INT/
43
DEC_FLASH_CS
47
DEC_SRAM_CS
DEC_FLASH_CS/
DEC_SRAM_CS/
44
DEC_FLASH_A1
45
DEC_FLASH_A0
DEC_FLASH_A0
DEC_FLASH_A1
6
RD
WR
CS
RST
46
AU12
IO
CLKSEL
DEC_NVWE_DLY/
DB_RD/
DB_WR/
DB_CS/
DB_RST/
DB_MCKI
DB_FSI
DB_SDO0
DB_SDO1
DB_SDO2
AUDIO12
IO
DEC_CLK_SEL
C
[3/C1,3/C8]
[3/C1,3/C8]
[3/C1,3/C8]
[3/C1,3/D8]
[3/C1,3/C8]
[3/C1,3/C8]
NOTES
[1/C7]
1 M1,M0 HAVE WEAK PULLUPS
[3/C1,3/C3]
SRAM/
M1,M0 = 1,1 SLAVE SERIAL MODE
M1,M0 = 1,0 MASTER SERIAL MODE
[3/C1,3/D3]
[3/C1,3/D3]
2 JUMPER W1 TO GND TO USE CONFIGURATION ROM.
[3/C3]
DEC_CLK
B
DEC_MCKI
DEC_IN_FSI
DEC_OUT_FSI
DEC_IN_SCKI
DEC_OUT_SCKI
DB_SDI
DEC_SDI
78
59
66
61
67
R5
33
62
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
AUDIO12
IO_SPARE
5
92
93
94
95
96
86
87
65
4
5
6
60
DEC_MCKI
DEC_IN_FSI
DEC_OUT_FSI
DEC_IN_SCKI
DEC_OUT_SCKI
DEC_SDI
83
DB_SDO0
84
DB_SDO1
82
DB_SDO2
90
DB_SDO3
88
77
64
49
38
23
11
1
7
U5
DEC_AB_CS/
DEC_AB_SCCLK
DEC_AB_SCDIN
91
GND
8
1
6 NC
[3/D1,3/D8]
DEC_C_CS/
DEC_C_SCCLK
DEC_C_SCDIN
DEC_NVWE_DLY
D
Q1
TEST POINTS
GND
53
DEC_C_CS
54
DEC_C_SCCLK
55
DEC_C_SCDIN
DB_AB_C_INT
DEC_NV_CS
DEC_GPIO20
DEC_GPIO21
85
CHANGED PER DCR 020814-00
Q.C.
AUTH.
CW
6/24/02
KB
6/24/02
CW
9/5/02
KB
9/9/02
7
8
DEC_RST/
58
32
DEC_AB_CS
33
DEC_AB_SCLK
34
DEC_AB_SCDIN
27
DEC_A0
28
DEC_A1
30
DEC_A19
IO
CE
OE DATA
CLK CEO
*
DEC_RST
56
76
5
IO_DOUT
VPP
VCC
2
2N3904
AU4
AU5
DBSD0
DEC_C_SCDOUT
AUDIO12
4
3
2
CHANGED PER DCR 020604-00
DBMCKI
DBFSI
35
42
*
24
50
36
74
72
73
1
D0
D1
D2
D3
D4
D5
D6
D7
DEC_AB_SCDOUT
DEC_A0
DEC_A1
DEC_A19
XC17S05XL
W1
DECODER FPGA
98
RD
99
WR
97
CS
3
RST
DEC_A[19:0]
[3/D3]
A
DB_D0
DB_D1
DB_D2
DB_D3
DB_D4
DB_D5
DB_D6
DB_D7
DEC_NVCS/
[3/C3]
[1/B3,2/C1]
7
8
9
10
13
DB_4MHZ
[1/C3]
B
DB_A0
DB_A1
DB_A2
DB_A3
DB_A4
DB_RD/
DB_WR/
DB_CS/
DB_RST/
[1/B3,2/D1]
[1/B3,2/D1]
[1/B3,2/D1]
[1/B3,2/C1]
22
M1
26
NC2
52
DB_D[7:0]
[1/B5]
C
R4
DB_A[4:0]
[1/B5]
NC
NC
R7
R8
4.7K
+3.3VD
4.7K
89
100
12
25
37
51
63
75
10K
FPGA_DONE
DRAFTER
CHECKER
RWH
6/10/02
KB
6/12/02
RWH
8/29/02
KB
9/5/02
DESCRIPTION
[3/C1,3/B8]
DB_SDO0
DB_SDO1
DB_SDO2
DB_SDO3
WE_DLY1
WE_DLY2
WE_DLY3
SP6
WE_DLY4
SP10
SP11
[3/B1,3/B3]
[3/C1,3/B8]
[3/B1,3/B3]
[3/C1,3/B8]
[3/B1,3/B3]
[1/C7,2/C1]
[1/C7,2/C1]
[1/C7,2/C1]
[1/C7]
WRITE ENABLE DELAYS
SP0
SP1
SP2
SP3
SP4
SP5
USE THE THROUGH-PART DELAY
TO MEET THE FLASH WRITE ADDRESS SETUP TIME
FOR THE REV A2 CS49400
DEC_CLK_SEL
SP8
SP9
[2/C1,3/B8]
exicon
CONTRACT
NO.
U4
APPROVALS
DRAWN
4
3
DATE
RWH
2/28/02
CHECKED
KB
3/5/02
Q.C.
CW
3/5/02
ISSUED
KB
3/5/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,DECODER BD,MC8/MC12
FPGA
SIZE
B
CODE
NUMBER
060-15319
REV
2
FILE NAME
15319-2. 2
SHEET
1
2 OF 4
10-23-2002_14:48
8
8
7
6
5
4
2
3
1
REVISIONS
REV
CS49400 ABOOT/IRQ PINS ARE DUAL PURPOSE OPEN DRAIN I/O
WHEN RESET RISES WITH ABOOT LOW - > AUTOBOOT MODE
AT RUN TIME, PIN IS THE IRQ OUTPUT
CS49400 REQUIRES 2.5 VOLT SUPPLY
PIN SHOULD NOT BE DRIVEN EXTERNALLY WHEN CHIP IS IN RUN MODE
PINS ARE 3.3 VOLT TOLERANT
D
5
3.3K
RP3
4
DEC_C_ABOOT/IRQ
RP6 4
DEC_HINBSY/
5 10K
C
DEC_AB_ABOOT/IRQ
DEC_AB_CS/
DEC_AB_SCCLK
DEC_AB_SCDIN
DEC_AB_SCDOUT
[2/C7,3/C1]
[2/C4,3/C1]
[2/C4,3/C1]
[2/C4,3/C1]
[2/C7,3/C1]
[2/B4,3/C1]
[2/B4,3/C1]
[2/B4,3/C1]
[2/A4,2/C1]
RP3 6
RP3 7
3 3.3K
2 3.3K
DEC_IN_FSI
DEC_IN_SCKI
DEC_SDI
85
86
82
81
80
79
+2.5VD
FB1
DEC_CLK
PLL_2.5VD
C12
DEC_CLK_SEL
4.7
3.3K
3.3K
3.3K
C15
.1/25
R1
68PF
SDADDR0,EXTA0
SDADDR1,EXTA1
SDADDR2,EXTA2
SDADDR3,EXTA3
SDADDR4,EXTA4
SDADDR5,EXTA5
SDADDR6,EXTA6
SDADDR7,EXTA7
SDADDR8,EXTA8
SDADDR9,EXTA9
SDADR10,EXTA10
SDDAT8,EXTA11
SDDAT9,EXTA12
SDDAT10,EXTA13
SDDAT11,EXTA14
SDDAT12,EXTA15
SDDAT13,EXTA16
SDDAT14,EXTA17
SDDAT15,EXTA18
SD_BA ,EXTA19
FINTREQ
FCS
FA0 ,FSCCLK
FA1 ,FSCDIN
FHS2 ,FSCDIO,FSCDOUT
FHS0 ,FWR/,FDS/
FHS1 ,FRD/,FR_W/
FDAT0
FDAT1
FDAT2
FDAT3
FDAT4
FDAT5
FDAT6
FDAT7
SDDAT0 ,EXTD0
SDDAT1 ,EXTD1
SDDAT2 ,EXTD2
SDDAT3 ,EXTD3
SDDAT4 ,EXTD4
SDDAT5 ,EXTD5
SDDAT6 ,EXTD6
SDDAT7 ,EXTD7
117
CMPREQ ,FLRCLKN2
111
CMPCLK ,FSCLKN2
118
CMPDAT ,FSDATAN2
CLKSEL LOW = FAST CLOCK FOR NORMAL MODE
CLKSEL HIGH = SLOW CLOCK FOR FLASH LOAD
4 RP4
2 RP4
3 RP4
143
2
1
5
8
LRCLKN ,GPIO23
SCLKN,GPIO22
SDATAN0 ,GPIO24
SDATAN1 ,GPIO25
SDATAN2 ,GPIO26
SDATAN3 ,GPIO27
1/10W
C16
SCLK0
LRCLK0
AUDATA0
AUDATA1
AUDATA2
AUDATA3 ,XMT958A
UHS2 ,CS_OUT/,GPIO17
UHS1 ,GPIO19
UHS0 ,GPIO18
GPIO20
GPIO21
89
88
84
83
48
1200PF
MCLK
CLKIN ,XTALI
XTALO
PLLVDD
FILT2
FILT1
CLKSEL
PLLVSS
NC1
NC2
NC3
NC4
NC5
3K
5
7
6
127
NC 126
125
123
124
128
122
68
64
61
59
39
45
78
77
33
SD_CS
SDCKE
SDCLKI
SDCLKO
DQM0
DQM1
SD_CAS
SD_RAS
SDWE
RP6
RP5
RP5
RP5
RP1
RP1
RP6
RP6
RP1
[2/B4,3/C1]
[2/B4,3/C1]
8
6
7
8
2
1
6
7
3
1
3
2
1
7
8
3
2
6
10K
10K
10K
10K
10K
10K
10K
10K
10K
[2/B4]
[2/B4,3/C1]
32
NVCSN ,GPIO14
31
NV0EN ,GPIO15
30
NVWEN ,GPIO16
119
FLRCLKN1
134
FSCLKN1,STCCLK2
131
FSDATAN1
DEC_CLK_SEL
C13
16
15
6
4
7
12
13
29
27
24
22
19
18
14
9
CS494001-CL
INTREQ ,ABOOT/
CS,GPIO9
HINBSY,GPIO8
WR,DS/,GPIO10
RD,R_W/,GPIO11
A0 ,GPIO13
A1 ,GPIO12
HDATA0 ,GPIO0
HDATA1 ,GPIO1
HDATA2 ,GPIO2
HDATA3 ,GPIO3
HDATA4 ,GPIO4
HDATA5 ,GPIO5
HDATA6 ,GPIO6
HDATA7 ,GPIO7
SCLK1
LRCLK1
AUDATA4,GPIO28
AUDATA5,GPIO29
AUDATA6,GPIO30
AUDATA7 ,XMT958B,GPIO31
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
[2/C7,3/C1]
3
129
141
120
121
130
139
116
115
112
105
103
97
96
95
RESET
SCS
SCCLK
SCDIN
SCDOUT,SCDIO
91
101
113
133
137
11
21
[2/C7,3/C1]
144
135
142
136
140
70
VDDSD1
58
VDDSD2
51
VDDSD3
42
VDDSD4
3.3K
RP3
1
+3.3VD
69
VSSSD1
57
VSSSD2
50
VSSSD3
41
VSSSD4
DEC_RST/
DEC_C_CS/
DEC_C_SCCLK
DEC_C_SCDIN
DEC_C_SCDOUT
[2/C4,3/D1]
[2/C4,3/C1]
[2/C4,3/C1]
[2/C4,3/C1]
[2/C7,3/C1]
8
90
100
114
132
138
10
20
3.3K
RP4
1
CHANGED PER DCR 020604-00
2
CHANGED PER DCR 020814-00
Q.C.
AUTH.
CW
6/24/02
KB
6/24/02
CW
9/5/02
KB
9/9/02
+3.3VD
1A
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
8
1
[2/B7]
D1
+2.5VD
B
DEC_A[19:0]
DRAFTER
CHECKER
RWH
6/10/02
KB
6/12/02
RWH
8/29/02
KB
9/5/02
DESCRIPTION
73
74
75
76
67
66
65
63
62
60
72
56
55
54
53
52
49
47
46
71
DEC_A0
DEC_A1
DEC_A2
DEC_A3
DEC_A4
DEC_A5
DEC_A6
DEC_A7
DEC_A8
DEC_A9
DEC_A10
DEC_A11
DEC_A12
DEC_A13
DEC_A14
DEC_A15
DEC_A16
DEC_A17
DEC_A18
DEC_A19
34
35
36
37
38
40
43
44
DEC_D0
DEC_D1
DEC_D2
DEC_D3
DEC_D4
DEC_D5
DEC_D6
DEC_D7
DEC_A2
DEC_A3
DEC_A4
DEC_A5
DEC_A6
DEC_A7
DEC_A8
DEC_A9
DEC_A10
DEC_A11
DEC_A12
DEC_A13
DEC_A14
DEC_A15
DEC_A16
DEC_A17
DEC_A18
DEC_NVWE_DLY/
DEC_FLASH_CS/
DEC_NVOE/
20
19
18
17
16
15
14
13
3
2
31
1
12
4
5
11
10
6
9
AT29LV040A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
VCC
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
8
21
22
23
25
26
27
28
29
SPARES
NC
NC
DEC_D0
DEC_D1
DEC_D2
DEC_D3
DEC_D4
DEC_D5
DEC_D6
DEC_D7
DEC_NVCS/
DEC_NVWE/
RP1 5
RP5 4
4 10K
5 10K
NC
NC
TEST POINTS
DRST
DCLK
ABIRQ
CIRQ
HINBSY
ABCS/
ABCK
ABIN
ABOUT
7
WE
30
CE
32
OE 512KX8
24
GND 200NS
CCS/
CCK
CIN
COUT
U1
A1
A0
G21
G20
FA0
FA1
[2/B7]
[2/B7,3/C1]
NVOE/
NVWE/
FLASHCS/
INFSI
INSCKI
SDI
MCKI
OUTFSI
OUTSCKI
SDO0
SDO1
SDO2
SDO3
DEC_D[7:0]
DEC_RST/
DEC_CLK
DEC_AB_ABOOT/IRQ
DEC_C_ABOOT/IRQ
DEC_HINBSY/
DEC_AB_CS/
DEC_AB_SCCLK
DEC_AB_SCDIN
DEC_AB_SCDOUT
DEC_C_CS/
DEC_C_SCCLK
DEC_C_SCDIN
DEC_C_SCDOUT
C
DEC_A1
DEC_A0
DEC_GPIO21
DEC_GPIO20
DEC_FLASH_A0
DEC_FLASH_A1
DEC_NVOE/
DEC_NVWE/
DEC_FLASH_CS/
DEC_IN_FSI
DEC_IN_SCKI
DEC_SDI
DEC_MCKI
DEC_OUT_FSI
DEC_OUT_SCKI
DEC_SDO0
DEC_SDO1
DEC_SDO2
DEC_SDO3
NOTES
99
DEC_MCKI
104
108
110
109
107
106
DEC_OUT_SCKI
DEC_OUT_FSI
DEC_SDO0
DEC_SDO1
DEC_SDO2
DEC_SDO3
98
87
102
94
93
92
DEC_FLASH_A0
DEC_FLASH_A1
D
1. TO SELECT SERIAL INTERFACE
AT RISING EDGE OF RESET
[2/B4,3/B1]
B
DSP AB
FSH2 (PIN7), IS PULLED HIGH
FHS1 (PIN13), IS PULLED LOW
FSH0 (PIN12), IS PULLED HIGH
[2/B4,3/B1]
[2/B4,3/B1]
[2/B7,3/B1]
[2/B7,3/B1]
[2/B7,3/B1]
[2/B7,3/B1]
DSP C
USH2 (PIN143), IS PULLED HIGH
USH1 (PIN2), IS PULLED LOW
UHS0 (PIN1), IS PULLED HIGH
NC
NC
NC
NC
+2.5VD
28
TEST
26
DBCK
25
DBDA
RP2 1
RP2 2
8 10K
7 10K
23
FDBDA
17
FDBCK
RP2 3
RP2 4
6 10K
5 10K
U2
+3.3VD
DEC_GPIO21
C17
.1/25
R2
10K
12.288MHZ
1
VDD
IN
DEC_GPIO20
4
OUT
DEC_CLK
3
[2/B7,3/C1]
[2/B7,3/C1]
APPROVALS
DRAWN
GND
2
8
exicon
CONTRACT
NO.
[2/B7,3/C1]
RWH
U3
7
6
5
4
3
DATE
3/21/02
CHECKED
KB
3/26/02
Q.C.
CW
3/26/02
ISSUED
KB
3/26/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,DECODER BD,MC8/MC12
DOLBY DIGITAL/DTS DECODER
SIZE
B
CODE
NUMBER
060-15319
REV
2
FILE NAME
15319-2. 3
SHEET
1
3 OF 4
10-23-2002_14:48
A
8
7
6
5
4
3
2
1
REVISIONS
REV
D
+5VD
2.5V REGULATOR
DRAFTER
CHECKER
RWH
6/10/02
KB
6/12/02
RWH
8/29/02
KB
9/5/02
DESCRIPTION
1
CHANGED PER DCR 020604-00
2
CHANGED PER DCR 020814-00
Q.C.
AUTH.
CW
6/24/02
KB
6/24/02
CW
9/5/02
KB
9/9/02
+2.5VD
D
D3
+2.5VD
1N4002
1
C28
VIN
LM2937
VOUT
TERM
.1/25
4
GND
2
3
C27
10/10
U6
C
C
BYPASS CAPACITORS
+3.3VD
C1
.1/25
B
C2
C3
.1/25
.1/25
C4
.1/25
C5
.1/25
C18
.1/25
C19
.1/25
C20
C21
.1/25
.1/25
C22
.1/25
C23
.1/25
C24
.1/25
C25
.1/25
C26
.1/25
B
+2.5VD
C7
.1/25
.1/25
C8
.1/25
C9
.1/25
C10
.1/25
C11
.1/25
C14
.1/25
A
exicon
CONTRACT
NO.
APPROVALS
DRAWN
RWH
8
7
6
5
4
3
DATE
3/21/02
CHECKED
KB
3/26/02
Q.C.
CW
3/26/02
ISSUED
KB
3/26/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,DECODER BD,MC8/MC12
REGULATOR & BYPASS CAPS
SIZE
B
CODE
NUMBER
060-15319
REV
2
FILE NAME
15319-2. 4
SHEET
1
4 OF 4
10-23-2002_14:48
C6
8
7
6
5
4
3
2
1
REVISIONS
REV
DRAFTER
CHECKER
DESCRIPTION
Q.C.
AUTH.
D
D
C
C
J1
1
2
3
4
RED
D1
STANDBY LED
1
2
4
3
SW1
NOTES
1
DIGITAL
GROUND
ANALOG
GROUND
CHASSIS
GROUND
2 LAST REFERENCE DESIGNATORS USED:
POWER
GROUND
D1, J1, SW1
B
B
© 2002 Lexicon, Inc.
CONTRACT
NO.
exicon
APPROVALS
DRAWN
8
7
6
5
4
3
DATE
RWH
12/7/01
CHECKED
KAB
1/4/02
Q.C.
CW
1/8/02
ISSUED
KAB
1/8/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,STANDBY BD, MC8
SIZE
B
CODE
NUMBER
060-15329
REV
0
FILE NAME
15329-0. 1
SHEET
1
1 OF 1
1-16-2002_12:48
A
8
7
6
5
4
3
2
1
REVISIONS
REV
1
DRAFTER
CHECKER
RWH
9/24/04
AT
9/27/04
DESCRIPTION
UPDATED FOR MC4 PER DCR 040922-00
Q.C.
AUTH.
CW
10/14/04
AT
9/27/04
D
D
VIDEO BOARD CONNECTOR
J1
1
ZONE
C
§
C
2 YEL RCA
1
2
3
4
J2
MONITOR
J3
1
2 YEL RCA
NOTES
1 LAST REFERENCE DESIGNATORS USED: J3
2 COMPONENTS MARKED WITH § ARE NOT ON INSTALLED ON MC4.
B
B
OCT 27 2004
RELEASED COPY
© 2004 Lexicon, Inc.
CONTRACT
NO.
exicon
8
7
6
5
4
3
APPROVALS
DRAWN
DATE
RWH
1/9/02
CHECKED
ECM
1/10/02
Q.C.
CW
1/10/02
ISSUED
KAB
1/11/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,VIDEO OUT BD,MC4/MC8
RCA OUTPUTS
SIZE
B
CODE
NUMBER
060-15339
REV
1
FILE NAME
15339-1 . 1
SHEET
1
1
OF 1
10-19-2004_8:24
A
8
7
6
5
4
2
3
1
REVISIONS
REV
LFR2
D
2.94K
1%
3.01K C88
1%
+15V
3
2
8
+
OPA2134
-
U10
-15V
R95
R102
18PF
C87
+
6
-
OPA2134 R100
7
4
U10
51
1/4W
2.94K
1%
3
2
8
+
OPA2134
R97
C84
51
47/25
-
U9
-15V
R85
R92
18PF
6
3.01K
1%
C80
8
+
OPA2134 R90
7
4
U9
51
1/4W
2.94K
1%
3
8
+
13
9
1
22K
R87
C77
51
47/25
16
RFR+
C18
150PF
6
R83
FB18
4
FB17
C17
3 1
2
150PF
J9
+
RIGHT FRONT OUT
C
4
7
RY9
+15V
OPA2134
-
U8
-15V
R75
5
R82
18PF
6
3.01K
1%
1
4
C73
NOTES
8
+
OPA2134 R80
-
U8
7
4
51
1/4W
22K
R77
1/4W
2.94K
1%
3.01K C67
1%
+15V
SUB1
3
2
8
+
OPA2134
-
U7
4
-15V
R65
2.94K
1%
18PF
C66
R68 18PF
C70
16
CTR+
47/25
2 UNLESS OTHERWISE INDICATED, RESISTORS ARE 5%
C16
4
FB15
C15
3 1
2
150PF
J8
+
CENTER OUT
4
7
3 UNLESS OTHERWISE INDICATED, CAPACITORS ARE UF/V
4
DIGITAL
GROUND
5
R72
6
8
+
4
5 [XX/XX] DENOTES [SHEET NUMBER/SECTOR]
RY10, U10.
7 COMPONENTS MARKED WITH
-
OPA2134 R70
U7
51
1/4W
C64
11
47/25
6
R63
1
22K
R67
C63
51
47/25
1/4W
A
[2/A5,3/C3]
16
SUB+
FB14
4
+
FB13
C13
3 1
2
150PF
J7
EXPOUTS_MUTE/
390
SUB OUT
7
RY7
R2
0dBFS=16Vrms
© 2002 Lexicon, Inc.
CONTRACT
NO.
exicon
2N4401
Q2
CHECKED
Q.C.
ISSUED
7
6
5
TITLE
FRONT,CENTER,SUB OUTPUTS
SIDE,REAR OUTPUTS
ZONE2 OUTPUTS
4
APPROVALS
DRAWN
8
B
ARE NOT ON BOM.
C14
150PF
8
18PF
0dBFS=8Vrms
13
9
R64
C68
SHEET NUMBER REVISION
1 OF 3
0
2 OF 3
0
3 OF 3
0
RELAY
SUB-
R71 -15V
3.01K
1%
*
RY8
22K
3.01K
1%
POWER
GROUND
CHASSIS
GROUND
DOCUMENT CONTROL BLOCK: #060-15349
7
-
ANALOG
GROUND
6 LAST REFERENCE DESIGNATORS USED: C92, D2, FB22, J11, Q2, R102
+15V
3.01K
1%
1
6
1
FB16
150PF
8
51
SUB2
13
9
R73
C75
18PF
R69
11
47/25
22K
3.01K
1%
1 UNLESS OTHERWISE INDICATED, RESISTORS ARE 1/10W
RELAY
CTRR74
3.01K
1%
R66
C71
R81 -15V
R78 18PF
2.94K
1%
SUB-
7
J10
-
11
47/25
C82
18PF
3.01K C74
1%
+15V
2
[3/D3]
LEFT FRONT OUT
4
R79
R76
SUB+
+
8
3.01K
1%
3.01K
1%
CTR1
[3/D3]
C19
150PF
3 1
2
RELAY
RFR22K
CTR2
[3/D3]
C78
R84
1/4W
B
4
FB19
RY10
R91 -15V
R88 18PF
2.94K
1%
CENTER-
16
LFR+
C20
+15V
5
1
4
CENTER+
1
22K
FB20
150PF
6
R93
C89
18PF
3.01K C81
1%
+15V
C
[3/D3]
13
9
R89
RFR1
[3/D3]
11
8
3.01K
1%
3.01K
1%
R86
RFRONT-
1N4002
22K
RFR2
[3/D3]
LFR-
47/25
D
MAIN OUTPUTS
RELAY
D2
R94
1/4W
RFRONT+
C85
R101-15V
R98 18PF
2.94K
1%
8
5
3.01K
1%
1
4
LFRONT-
+5VD +5VD
R99
LFR1
[3/D3]
+15V
Q.C.
AUTH.
4
3
2
DATE
CW
4/8/02
CV
4/9/02
RWH
4/9/02
KAB
4/10/02
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,XLR BD,MC-8B
FRONT,CENTER,SUB OUTPUTS
SIZE
B
CODE
NUMBER
060-15349
REV
0
FILE NAME
15349-0. 1
SHEET
1
1 OF 3
4-12-2002_11:43
[3/D3]
R96
LFRONT+
DRAFTER
CHECKER
DESCRIPTION
8
7
6
5
4
2
3
1
REVISIONS
REV
LSD2
[3/D3]
2.94K
1%
LSD1
8
3
+
2
-
U6
-15V
R55
LSIDE-
OPA2134
R62
18PF
+5VD +5VD
+
OPA2134 R60
6
-
U6
7
4
51
1/4W
2.94K
1%
18PF
3.01K C53
1%
+15V
C
8
3
+
2
-
OPA2134
U5
-15V
R45
+
6
-
3.01K
1%
R57
C56
51
47/25
OPA2134 R50
U5
2.94K
1%
3
8
+
OPA2134
51
1/4W
-
U4
-15V
R35
J6
-
11
13
9
6
R43
1
22K
R47
C49
51
47/25
4
16
RSD+
FB10
C10
150PF
FB9
3 1
2
C9
RIGHT SIDE OUT
C
4
7
150PF
J5
+
RY5
+15V
5
R42
18PF
6
3.01K
1%
8
+
OPA2134 R40
7
4
U4
51
1/4W
RELAY
LRR-
11
47/25
6
R41 -15V
3.01K
1%
4
8
R33
C47
18PF
RRR2
13
9
22K
C45
3.01K
1%
R26
C43
R34
1
22K
R37
51
FB8
C8
150PF
FB7
3 1
2
C7
LEFT REAR OUT
4
7
150PF
J4
+
B
C42
16
LRR+
47/25
RY4
+15V
R29
2.94K
1%
3.01K C39
1%
+15V
RRR1
3
2
8
+
OPA2134
-
U3
-15V
R25
2.94K
1%
18PF
5
R32
6
3.01K
1%
1
4
8
+
OPA2134 R30
7
4
U3
51
1/4W
C36
RELAY
RRR-
11
47/25
22K
C38
6
R31 -15V
3.01K
1%
R28 18PF
3.01K
1%
13
9
R24
4
8
R23
C40
18PF
1
22K
R27
C35
51
47/25
1/4W
A
LEFT SIDE OUT
4
7
150PF
+
8
18PF
R38 18PF
2.94K
1%
RREAR-
3 1
2
C11
RELAY
RSD-
47/25
C54
1/4W
[3/C3]
C50
R44
3.01K
1%
1
4
RREAR+
FB11
RY6
R51 -15V
3.01K C46
1%
+15V
2
[3/C3]
4
C12
150PF
R39
LRR1
B
16
LSD+
22K
C52
3.01K
1%
R36
LREAR-
1
22K
7
4
R48 18PF
2.94K
1%
8
5
LRR2
[3/C3]
6
R53
1/4W
[3/C3]
9
FB12
+15V
R52
18PF
1
4
LREAR+
13
R49
R46
RSIDE-
11
8
C61
3.01K
1%
RSD1
[3/D3]
1N4002
R54
3.01K
1%
RSD2
[3/D3]
LSD-
47/25
D
MAIN OUTPUTS
RELAY
D1
R61 -15V
1/4W
RSIDE+
C57
22K
C59
R58 18PF
2.94K
1%
8
5
3.01K
1%
1
4
[3/D3]
3.01K C60
1%
+15V
16
RRR+
FB6
C6
150PF
FB5
3 1
2
C5
RIGHT REAR OUT
4
7
150PF
J3
+
RY3
0dBFS=16Vrms
0dBFS=8Vrms
exicon
CONTRACT
NO.
[1/A5,3/C3]
EXPOUTS_MUTE/
R1
390
2N4401
APPROVALS
DRAWN
Q1
CHECKED
Q.C.
ISSUED
8
Q.C.
AUTH.
7
6
5
4
3
2
DATE
CW
4/8/02
CV
4/9/02
RWH
4/9/02
KAB
4/10/02
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,XLR BD,MC-8B
SIDE,REAR OUTPUTS
SIZE
B
CODE
NUMBER
060-15349
REV
0
FILE NAME
15349-0. 2
SHEET
1
2 OF 3
4-12-2002_11:43
D
+15V
R59
R56
LSIDE+
DRAFTER
CHECKER
DESCRIPTION
8
7
6
5
4
2
3
1
REVISIONS
REV
DRAFTER
CHECKER
DESCRIPTION
Q.C.
AUTH.
FROM ANALOG I/O BOARD
GND-1
D
BYPASS CAPACITORS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GND-2
GND-3
+15V
GND-4
C44
C58
C51
.1/25
.1/25
C48
C55
.1/25
.1/25
C65
.1/25
.1/25
C62
C69
.1/25
.1/25
C72
.1/25
C76
.1/25
C79
C86
.1/25
.1/25
C83
C90
.1/25
C23
.1/25
C27
.1/25
.1/25
C30
C37
.1/25
.1/25
C34
C41
.1/25
GND-5
GND-6
.1/25
GND-7
-15V
+5VD
+5V
C
ZONE_RLY_CNTL
RFRONTRFRONT+
LFRONTLFRONT+
SUBSUB+
CENTERCENTER+
[1/C8]
[1/C8]
[1/D8]
[1/D8]
[1/A8]
[1/B8]
[1/B8]
[1/B8]
RSIDERSIDE+
LSIDELSIDE+
RREARRREAR+
LREARLREAR+
D
[2/C8]
[2/C8]
[2/D8]
[2/D8]
[2/A8]
[2/B8]
[2/B8]
[2/B8]
RZONERZONE+
LZONELZONE+
[3/A8]
[3/A8]
[3/B8]
[3/B8]
EXPOUTS_MUTE/
[1/A5,2/A5]
C
MUTE/
J11
+15V
FB22
2.5TURN
+15V
C92
560/35
FB21
C91
560/35
NOTES
-15V
2.5TURN
ZN_RLY/
-15V
LZN2
2.94K
1%
B
8
3
+
OPA2134
2
-
U2
-15V
R15
5
R22
18PF
C31
8
+
+5VD
OPA2134 R20
7
4
U2
51
1/4W
RELAY
11
13
9
6
4
R13
C33
1
22K
R17
C28
51
47/25
LZN+
16
FB4
B
C4
150PF
FB3
C3
150PF
+
3 1
2
LEFT ZONE OUT
4
7
J2
RY2
+15V
R9
2.94K
1%
3.01K C25
1%
+15V
RZN1
3
2
8
+
OPA2134
-
U1
-15V
R5
2.94K
1%
18PF
5
R12
6
3.01K
1%
1
4
A
RZONE-
ZONE2 OUTPUTS
8
18PF
RZN2
[3/C3]
47/25
R21 -15V
3.01K
1%
R6
RZONE+
LZN22K
1/4W
[3/C3]
C29
R14
3.01K
1%
R18 18PF
2.94K
1%
6
3.01K
1%
1
4
LZONE-
3.01K C32
1%
+15V
LZN1
[3/C3]
+15V
C24
R8 18PF
8
+
OPA2134 R10
7
4
U1
51
1/4W
C22
RZN-
47/25
R4
6
R11 -15V
3.01K
1%
4
8
R3
C26
18PF
0dBFS=2.0Vrms
13
9
22K
3.01K
1%
RELAY
11
1
22K
R7
C21
51
47/25
1/4W
RZN+
16
+
FB2
C2
150PF
FB1
C1
3 1
2
RIGHT ZONE OUT
4
J1
APPROVALS
DRAWN
-
0dBFS=4.0Vrms
RY1
CHECKED
Q.C.
ISSUED
8
7
6
5
exicon
CONTRACT
NO.
7
150PF
4
3
2
DATE
CW
4/8/02
CV
4/9/02
RWH
4/9/02
KAB
4/10/02
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SIZE
B
SCHEM,XLR BD,MC-8B
ZONE2 OUTPUTS
CODE
NUMBER
060-15349
REV
0
FILE NAME
15349-0. 3
SHEET
1
3 OF 3
4-12-2002_11:43
[3/C3]
R19
R16
LZONE+
8
7
6
5
4
3
2
1
REVISIONS
REV
DESCRIPTION
1
REVISED SIGNAL NAMES ON SHEETS 1,8;
ADD NOTE 8 PER DCR 020926-00
2
SHOW DEPOPULATION FOR MIC BD. ON
SHTS. 2-8 & 10 PER ECO 041201-00.
D
+5VD+3.3VD
[8/A4]
[6/C8]
[6/C8]
C
[8/A4]
IO
DSPD_1A_SDO
(IO)
(AUDIO6)
DSPD_1B_SDO
(AUDIO7)
AUDIO8
(AUDIO8)
B
ASP0
AUDIO_SP0
(AUDIO_SP0)
Q.C.
AUTH.
RWH
10/15/02
KAB
10/15/02
CW
12/14/04
MSJ
12/9/04
D
TEST POINTS
EURO64-RA-M
C32
A32
C31
A31
C30
A30
C29
A29
C28
A28
C27
A27
C26
A26
C25
A25
C24
A24
C23
A23
C22
A22
C21
A21
C20
A20
C19
A19
C18
A18
C17
A17
C16
A16
C15
A15
C14
A14
C13
A13
C12
A12
C11
A11
C10
A10
C9
A9
C8
A8
C7
A7
C6
A6
C5
A5
C4
A4
C3
A3
C2
A2
C1
A1
DRAFTER
CHECKER
CW
9/27/02
KAB
10/11/02
RWH
12/7/04
AF
12/9/04
DSPA_0A_SDI
DSPA_0B_SDI
A0A_SDI
A0B_SDI
(AUDIO0)
DSP_MCKI
(AUDIO1)
DSP_FSI
(AUDIO2)
DSP_PROG/
(AUDIO3)
DSPA_0A_SDI
(AUDIO4)
DSPA_0B_SDI
(AUDIO5)
AUDIO5
[8/B7,8/C1]
[8/B7,8/C1]
[8/D7]
[1/D1,2/C8]
[1/D1,2/C8]
[8/A4]
C
(AUDIO)
AUDIO_4MHZ
[8/A4]
NC
NC
NC
NC
NC
NC
NC
NC
NC
NOTES
DSP_A4
DSP_A3
DSP_A2
DSP_A1
DSP_A0
1 UNLESS OTHERWISE INDICATED, RESISTORS ARE 1/10W
DSP_A[4:0]
ZDSP_RD/
ZDSP_WR/
ZDSP_D0
ZDSP_D1
ZDSP_D2
ZDSP_D3
ZDSP_D4
ZDSP_D5
ZDSP_D6
ZDSP_D7
(AUDIO9)
DSP_CCLK
(AUDIO10)
DSP_DIN
2 UNLESS OTHERWISE INDICATED, RESISTORS ARE 5%
[8/D7]
[8/C7,8/D1]
[8/C7,8/D1]
[8/D5]
[8/D5]
3 UNLESS OTHERWISE INDICATED, CAPACITORS ARE UF/V
4
DIGITAL
GROUND
ANALOG
GROUND
CHASSIS
GROUND
POWER
GROUND
5 [XX/XX] DENOTES [SHEET NUMBER/SECTOR]
6 LAST REFERENCE DESIGNATORS USED: C150, D11, FB14, J8, Q1, R95,
U26, W1.
7 COMPONENTS MARKED WITH
*§
B
ARE NOT INSTALLED.
8 COMPONENTS MARKED WITH
ARE NOT INSTALLED ON MIC BD.
9 NAMES IN PARENTHESES DESIGNATE GENERIC NOMENCLATURE USED
ON THE MATING CONNECTOR OF THE MAIN BOARD SCHEMATIC.
ZDSP_D[7:0]
[8/C7]
NC
ZDSP_CS/
ZDSP_RST/
[8/C7,8/D1]
[8/C7,8/C1]
J3
DOCUMENT CONTROL BLOCK: #060-15389
SHEET
1 OF 10
2 OF 10
3 OF 10
4 OF 10
5 OF 10
6 OF 10
7 OF 10
8 OF 10
9 OF 10
10 OF 10
REV
2
1
1
1
1
1
1
2
0
1
DESCRIPTION
MAIN BD CONNECTOR
DSP A
DSP B
DSPAB EXT MEM
DSP C
DSP D
DSPCD EXT MEM
FPGA
MICROPHONE INPUTS
BYPASS CAPACITORS & DSP CLOCKS
RELEASED COPY
© 2004 Lexicon, Inc.
CONTRACT
NO.
exicon
APPROVALS
DRAWN
8
7
6
5
4
3
DATE
RWH
5/20/02
CHECKED
KB
5/29/02
Q.C.
CW
6/3/02
ISSUED
KB
6/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MIC/DSP BD,MC8
MAIN BD CONNECTOR
SIZE
B
CODE
NUMBER
060-15389
REV
2
FILE NAME
15389-2 . 1
SHEET
1
1 OF 10
12-28-2004_16:35
A
8
7
6
5
4
3
2
1
REVISIONS
REV
1
DRAFTER
CHECKER
RWH
12/7/04
AF
12/9/04
DESCRIPTION
SHOW DEPOPULATION FOR MIC BD.
PER ECO 041201-00.
Q.C.
AUTH.
CW
12/14/04
MSJ
12/9/04
TEST POINTS
D
MASTER - ID0 HIGH, ID1 LOW
+3.3VD
ABCLK
ABWR/
ABRD/
ABBMS/
ABHOST_CS/
ABSRAM_CS/
§
R66
DSPA_CLK
§
R67
VCC
DSPA_CLK
NC
30
31
152
157
144
143
69
AB_RST/
[3/C8,8/C4,8/C1]
DSPAB_ACK
[3/C8,8/C4,8/C1]
DSPAB_ACK
DSPABC_FSI
DSPA_SCKI
DSPA_0A_SDI
DSPA_0B_SDI
[3/C6,5/C8,8/B4,8/C1]
[8/B4,8/C1]
[1/D1,1/C3]
[1/D1,1/C3]
CLKIN
XTAL2
BSEL
RESET
ID0
ID1
ACK
205
IRQ0
206
IRQ1
207
IRQ2
DSP_FSI_IRQ
SP_IRQAB
DSPAB_CMD_RDY/
[3/C8,5/C8,6/C8,8/B4,8/C1]
[3/C8,8/C4]
[8/C4,8/C1]
2
4
5
6
7
8
11
12
NC
NC
NC
C
13
15
16
17
18
19
22
23
NC
NC
NC
NC
NC
NC
RAS
CAS
SDWE
DQM
SDCKE
SDA10
SDCLK0
SDCLK1
BMS
MS0
MS1
MS2
MS3
SW
WR
RD
ADSP21065
RFS0
RCLK0
DR0A
DR0B
TFS0
TCLK0
DT0A
DT0B
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
RFS1
RCLK1
DR1A
DR1B
TFS1
TCLK1
DT1A
DT1B
26
PWMEVENT0
24
PWMEVENT1
38
DMAR1
39
DMAR2
50
DMAG1
51
DMAG2
40
52
55
63
56
NC
NC
DSPAB_CPA/
DSPAB_BR1/
DSPAB_BR2/
[2/C1,3/B8]
[2/C1,3/B8]
[2/C1,3/B8]
B
R65 §
DSPAB_STATUS_FULL
DSP_FLAG1
145
146
148
151
149
147
NC
197
198
199
201
138
137
136
134
80
79
78
76
NC
NC
NC
NC
NC
NC
102
103
115
142
202
203
NC
AF3
AF4
AF5
AF6
AF7
AF8
DEVELOPMENT ONLY:
PIN 7, BTCK, JUMP TO PIN 8
PIN 9, BTRST/, JUMP TO PIN 10
NC
NC
A
NC
+3.3VD
1
3
5
7
9
11
13
* J2
[3/B8]
[2/D1,10/C6]
8
2
4
6
8
10
12
14
R61 §
DSPAB_EMU/
DSPAB_ICE_CLK
DSPAB_TMS
DSPAB_TCK
DSPAB_TRST
DSPAB_TDI
DSPA_TDO
DSPAB_EMU/
DSPAB_TMS
DSPAB_TCK
DSPAB_TRST
[3/B8]
[3/B8]
EMU
TDO
TDI
TCK
TMS
TRST
FLAG0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
FLAG6
FLAG7
FLAG8
FLAG9
FLAG10
FLAG11
NC1
NC2
NC3
NC4
NC5
NC6
BMSTR
NC7
153
70
71
74
75
64
58
59
NC
NC
NC
195
194
193
190
189
188
185
184
183
180
179
178
175
174
173
171
170
169
166
165
164
162
161
160
DSPAB_A0
DSPAB_A1
DSPAB_A2
DSPAB_A3
DSPAB_A4
DSPAB_A5
DSPAB_A6
DSPAB_A7
DSPAB_A8
DSPAB_A9
DSPAB_A10
DSPAB_A11
DSPAB_A12
DSPAB_A13
DSPAB_A14
DSPAB_A15
DSPAB_A16
DSPAB_A17
DSPAB_A18
DSPAB_A19
DSPAB_A20
DSPAB_A21
DSPAB_A22
DSPAB_A23
82
83
84
86
87
88
90
91
92
96
97
98
100
101
104
107
108
109
111
112
113
116
117
118
121
122
123
126
127
128
132
133
DSPAB_D0
DSPAB_D1
DSPAB_D2
DSPAB_D3
DSPAB_D4
DSPAB_D5
DSPAB_D6
DSPAB_D7
DSPAB_D8
DSPAB_D9
DSPAB_D10
DSPAB_D11
DSPAB_D12
DSPAB_D13
DSPAB_D14
DSPAB_D15
DSPAB_D16
DSPAB_D17
DSPAB_D18
DSPAB_D19
DSPAB_D20
DSPAB_D21
DSPAB_D22
DSPAB_D23
DSPAB_D24
DSPAB_D25
DSPAB_D26
DSPAB_D27
DSPAB_D28
DSPAB_D29
DSPAB_D30
DSPAB_D31
53
DSPA_BMSTR
208
NC
DSPAB_RAS/
DSPAB_CAS/
DSPAB_SDWE/
DSPAB_DQM
DSPAB_SDCKE
DSPAB_SDA10
DSPAB_SDCLK
DSPAB_BMS/
DSPAB_SDRAM_CS/
DSPAB_HOST_CS/
DSPAB_SRAM_CS/
DSPAB_WR/
DSPAB_RD/
[2/D1,3/D3,4/C8]
[2/D1,3/D3,4/C8]
[2/D1,3/D3,4/C8]
[2/D1,3/D3,4/C8]
[2/D1,3/D3,4/C8]
[2/D1,3/D3,4/D8]
[2/D1,3/D3,4/C8]
[2/D1,3/C3,8/C7]
[2/D1,3/C3,4/C8]
[2/D1,3/C3,8/C7]
[2/D1,3/C3,4/D4]
ABCPA/
ABBR1/
ABBR2/
DSPAB_SDRAM_CS/
DSPAB_RAS/
DSPAB_CAS/
DSPAB_SDWE/
DSPAB_DQM
DSPAB_SDCKE
DSPAB_SDA10
DSPAB_SDCLK
DSPAB_CPA/
DSPAB_BR1/
DSPAB_BR2/
[2/D1,3/C3,4/B4]
[2/D1,3/C3,4/B4]
C
DSPAB_A[23:0]
[3/B3,4/D6]
B
DSPAB_D[31:0]
[3/A3,4/D7,8/C4]
DSPA_BMSTR
[3/B8]
[3/B8]
[3/B8]
U16
DSPA_OUT1
DSPA_OUT0
DSPB_TDO
DSPAB_ICE_CLK
6
5
4
exicon
CONTRACT
NO.
§
R62 §
7
ABSDRAM_CS/
ABRAS/
ABCAS/
ABSDWE/
ABDQM
ABSDCKE
ABSDA10
ABSDCLK
GND
3
10
14
25
33
35
41
49
57
60
62
68
72
73
81
89
94
99
106
114
119
125
129
135
139
150
154
155
159
167
168
177
181
186
187
196
204
+3.3VD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
65
CPA
27
BR1
28
BR2
DSPAB_EMU/
DSPA_TDO
DSPAB_TDI
DSPAB_TCK
DSPAB_TMS
DSPAB_TRST
[3/B8,8/C4]
[3/B8,5/B8,6/B8,8/B4]
HBR
HBG
CS
REDY
SBTS
42
43
44
46
47
48
37
34
D
DSPAB_ICE_CLK
DSPAB_WR/
DSPAB_RD/
DSPAB_BMS/
DSPAB_HOST_CS/
DSPAB_SRAM_CS/
3
[4/B8,8/C7]
[4/B8,8/C7]
APPROVALS
DRAWN
DATE
RWH
5/20/02
CHECKED
KB
5/29/02
Q.C.
CW
6/3/02
ISSUED
KB
6/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MIC/DSP BD,MC8
DSP A
SIZE
B
CODE
NUMBER
060-15389
REV
1
FILE NAME
15389-2 . 2
SHEET
1
2 OF 10
12-15-2004_8:52
[10/D6]
1
9
20
21
29
32
36
45
54
61
66
67
77
85
93
95
105
110
120
124
130
131
140
141
156
158
163
172
176
182
191
192
200
SLAVE - ID0 LOW, ID1 HIGH
8
7
6
5
4
3
2
1
REVISIONS
REV
1
D
MASTER - ID0 HIGH, ID1 LOW
DRAFTER
CHECKER
RWH
12/7/04
AF
12/9/04
DESCRIPTION
SHOW DEPOPULATION FOR MIC BD.
PER ECO 041201-00.
Q.C.
AUTH.
CW
12/14/04
MSJ
12/9/04
D
+3.3VD
§
R64
[10/D6]
[2/C8,8/C4,8/C1]
[2/C8,8/C4,8/C1]
[2/C8,5/C8,6/C8,8/B4,8/C1]
[2/C8,8/C4]
1
9
20
21
29
32
36
45
54
61
66
67
77
85
93
95
105
110
120
124
130
131
140
141
156
158
163
172
176
182
191
192
200
SLAVE - ID0 LOW, ID1 HIGH
§
VCC
R63
DSPB_CLK
NC
AB_RST/
DSPAB_ACK
C
DSPABC_FSI
DSPB_SCKI
NC
NC
NC
[3/D1,5/C8]
[3/D1,5/C8]
CLKIN
XTAL2
BSEL
RESET
ID0
ID1
ACK
205
IRQ0
206
IRQ1
207
IRQ2
DSP_FSI_IRQ
SP_IRQAB
NC
[2/C8,5/C8,8/B4,8/C1]
[8/A4]
30
31
152
157
144
143
69
DSPB_1A_SDO
DSPB_1B_SDO
NC
NC
2
4
5
6
7
8
11
12
13
15
16
17
18
19
22
23
ADSP21065
RFS0
RCLK0
DR0A
DR0B
TFS0
TCLK0
DT0A
DT0B
RFS1
RCLK1
DR1A
DR1B
TFS1
TCLK1
DT1A
DT1B
38
DMAR1
39
DMAR2
50
DMAG1
51
DMAG2
NC
NC
[2/B8,2/C1]
[2/C1,2/B8]
[2/C1,2/B8]
B
[2/A6]
[2/A8]
[2/A6]
[2/A6]
[2/A6]
[2/A6]
[2/B8,8/C4]
[2/B8,5/B8,6/B8,8/B4]
HBR
HBG
CS
REDY
SBTS
DSPAB_EMU/
DSPB_TDO
DSPA_TDO
DSPAB_TCK
DSPAB_TMS
DSPAB_TRST
145
146
148
151
149
147
DSPAB_STATUS_FULL
DSP_FLAG1
197
198
199
201
138
137
136
134
80
79
78
NC 76
NC
BF3
BF4
BF5
BF6
BF7
BF8
NC
NC
NC
NC
NC
NC
102
103
115
142
202
203
BMS
MS0
MS1
MS2
MS3
SW
WR
RD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
65
CPA
27
BR1
28
BR2
DSPAB_CPA/
DSPAB_BR1/
DSPAB_BR2/
EMU
TDO
TDI
TCK
TMS
TRST
FLAG0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
FLAG6
FLAG7
FLAG8
FLAG9
FLAG10
FLAG11
NC1
NC2
NC3
NC4
NC5
NC6
DSPAB_RAS/
DSPAB_CAS/
DSPAB_SDWE/
DSPAB_DQM
DSPAB_SDCKE
DSPAB_SDA10
DSPAB_SDCLK
NC
DSPAB_BMS/
DSPAB_SDRAM_CS/
DSPAB_HOST_CS/
DSPAB_SRAM_CS/
153
70
71
74
75 NC
64 NC
58
59
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
26
PWMEVENT0
24
PWMEVENT1
40
52
55
63
56
42
43
44
46
47
48
37
34
RAS
CAS
SDWE
DQM
SDCKE
SDA10
SDCLK0
SDCLK1
195
194
193
190
189
188
185
184
183
180
179
178
175
174
173
171
170
169
166
165
164
162
161
160
DSPAB_A0
DSPAB_A1
DSPAB_A2
DSPAB_A3
DSPAB_A4
DSPAB_A5
DSPAB_A6
DSPAB_A7
DSPAB_A8
DSPAB_A9
DSPAB_A10
DSPAB_A11
DSPAB_A12
DSPAB_A13
DSPAB_A14
DSPAB_A15
DSPAB_A16
DSPAB_A17
DSPAB_A18
DSPAB_A19
DSPAB_A20
DSPAB_A21
DSPAB_A22
DSPAB_A23
82
83
84
86
87
88
90
91
92
96
97
98
100
101
104
107
108
109
111
112
113
116
117
118
121
122
123
126
127
128
132
133
DSPAB_D0
DSPAB_D1
DSPAB_D2
DSPAB_D3
DSPAB_D4
DSPAB_D5
DSPAB_D6
DSPAB_D7
DSPAB_D8
DSPAB_D9
DSPAB_D10
DSPAB_D11
DSPAB_D12
DSPAB_D13
DSPAB_D14
DSPAB_D15
DSPAB_D16
DSPAB_D17
DSPAB_D18
DSPAB_D19
DSPAB_D20
DSPAB_D21
DSPAB_D22
DSPAB_D23
DSPAB_D24
DSPAB_D25
DSPAB_D26
DSPAB_D27
DSPAB_D28
DSPAB_D29
DSPAB_D30
DSPAB_D31
53
BMSTR
DSPAB_WR/
DSPAB_RD/
TEST POINTS
[2/D1,2/D3,4/C8]
[2/D1,2/D3,4/C8]
[2/D1,2/D3,4/C8]
[2/D1,2/D3,4/C8]
[2/D1,2/D3,4/C8]
[2/D1,2/D3,4/D8]
[2/D1,2/D3,4/C8]
B1A_SDO
B1B_SDO
DSPB_1A_SDO
DSPB_1B_SDO
[2/D1,2/C3,8/C7]
[2/D1,2/C3,4/C8]
[2/D1,2/C3,8/C7]
[2/D1,2/C3,4/D4]
[2/D1,2/C3,4/B4]
[2/D1,2/C3,4/B4]
FB12 §
DSPAB_WR_X/
FB11 §
DSPAB_RD_X/
DSPAB_A[23:0]
[8/C7]
C
[8/C7]
[2/B3,4/D6]
B
DSPAB_D[31:0]
DSPB_BMSTR
[2/A3,4/D7,8/C4]
DSPB_BMSTR
208 NC
NC7
A
U17
§
DSPB_OUT1
DSPB_OUT0
8
7
6
5
4
exicon
CONTRACT
NO.
3
[4/B8,8/C7]
[4/B8,8/C7]
APPROVALS
DRAWN
DATE
RWH
5/20/02
CHECKED
KB
5/29/02
Q.C.
CW
6/3/02
ISSUED
KB
6/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MIC/DSP BD,MC8
DSP B
SIZE
B
CODE
NUMBER
060-15389
REV
1
FILE NAME
15389-2 . 3
SHEET
1
3 OF 10
12-15-2004_8:57
3
10
14
25
33
35
41
49
57
60
62
68
72
73
81
89
94
99
106
114
119
125
129
135
139
150
154
155
159
167
168
177
181
186
187
196
204
GND
8
6
5
4
3
REV
DSPAB_A[23:0]
[2/D1,2/D3,3/D3]
[2/D1,2/D3,3/D3]
[2/D1,2/D3,3/D3]
[2/D1,2/C3,3/C3]
[2/D1,2/D3,3/D3]
[2/D1,2/D3,3/D3]
DSPAB_A9
DSPAB_A8
DSPAB_A7
DSPAB_A6
DSPAB_A5
DSPAB_A4
DSPAB_A3
DSPAB_A2
DSPAB_A1
DSPAB_A0
24
66
65
64
63
62
61
60
27
26
25
VDD
VDDQ
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
2MX32
100MHZ
59
DQM3
28
DQM2
71
DQM1
16
DQM0
DSPAB_DQM
DSPAB_RAS/
DSPAB_CAS/
DSPAB_SDWE/
DSPAB_SDRAM_CS/
19
RAS
18
CAS
17
WE
20
CS
DSPAB_SDCKE
DSPAB_SDCLK
67
CKE
68
CLK
73
70
69
57
30
21
14
NC6
NC5
NC4
NC3
NC2
NC1
NC0
VSS
VSSQ
44
58
72
86
NC
NC
NC
NC
NC
NC
NC
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
6
12
32
38
46
52
78
84
[2/D1,2/D3,3/D3]
DSPAB_SDA10
23
BA1
22
BA0
3
9
35
41
49
55
75
81
1
15
29
43
DSPAB_A13
DSPAB_A12
C
DSPAB_A0
DSPAB_A1
DSPAB_A2
DSPAB_A3
DSPAB_A4
DSPAB_A5
DSPAB_A6
DSPAB_A7
DSPAB_A8
DSPAB_A9
DSPAB_A10
DSPAB_A11
DSPAB_A12
DSPAB_A13
DSPAB_A14
DSPAB_A15
DSPAB_A16
+3.3VD
D
[2/D1,2/D3,3/D3]
56
54
53
51
50
48
47
45
42
40
39
37
36
34
33
31
85
83
82
80
79
77
76
74
13
11
10
8
7
5
4
2
U7
DSPAB_D31
DSPAB_D30
DSPAB_D29
DSPAB_D28
DSPAB_D27
DSPAB_D26
DSPAB_D25
DSPAB_D24
DSPAB_D23
DSPAB_D22
DSPAB_D21
DSPAB_D20
DSPAB_D19
DSPAB_D18
DSPAB_D17
DSPAB_D16
DSPAB_D15
DSPAB_D14
DSPAB_D13
DSPAB_D12
DSPAB_D11
DSPAB_D10
DSPAB_D9
DSPAB_D8
DSPAB_D7
DSPAB_D6
DSPAB_D5
DSPAB_D4
DSPAB_D3
DSPAB_D2
DSPAB_D1
DSPAB_D0
1
2
3
4
13
14
15
16
17
18
19
20
21
29
30
31
32
DSPAB_SRAM_CS/ 5
DSPAB_WR/
12
DSPAB_RD/
28
9
25
DSPAB_A0
DSPAB_A1
DSPAB_A2
DSPAB_A3
DSPAB_A4
DSPAB_A5
DSPAB_A6
DSPAB_A7
DSPAB_A8
DSPAB_A9
DSPAB_A10
DSPAB_A11
DSPAB_A12
DSPAB_A13
DSPAB_A14
DSPAB_A15
DSPAB_A16
§
1
2
3
4
13
14
15
16
17
18
19
20
21
29
30
31
32
DSPAB_SRAM_CS/ 5
DSPAB_WR/
12
DSPAB_RD/
28
9
25
R4
§
270
1/4W
R3
§
270
1/4W
B
[2/A3,8/C7]
[2/A3,8/C7]
[3/A3,8/C7]
[3/A3,8/C7]
DSPA_OUT0
DSPA_OUT1
DSPB_OUT0
DSPB_OUT1
R2
74VHC244-3.3V
11
13
15
17
19
A1
A2
A3
A4
G
§
270
1/4W
9
Y1
7
Y2
5
Y3
3
Y4
R1
§
270
1/4W
U6 §
R5 §
270
1/4W
R6 §
270
1/4W
[6/A3,8/B7]
[6/A3,8/B7]
[5/A3,8/B7]
[5/A3,8/B7]
DSPD_OUT0
DSPD_OUT1
DSPC_OUT0
DSPC_OUT1
R7 §
74VHC244-3.3V
2
4
6
8
1
A1
A2
A3
A4
G
270
1/4W
18
Y1
16
Y2
14
Y3
12
Y4
R8 §
270
1/4W
U6 §
D4 §
RED
D3 §
GRN
D2 §
RED
D1 §
DSPAB_A0
DSPAB_A1
DSPAB_A2
DSPAB_A3
DSPAB_A4
DSPAB_A5
DSPAB_A6
DSPAB_A7
DSPAB_A8
DSPAB_A9
DSPAB_A10
DSPAB_A11
DSPAB_A12
DSPAB_A13
DSPAB_A14
DSPAB_A15
DSPAB_A16
DSP A LED #1
A
DSP A LED #2
B
DSP B LED #1
C
DSP B LED #2
D
DSPAB_SRAM_CS/ 5
DSPAB_WR/
12
DSPAB_RD/
28
GRN
D5
§
DSP D LED #2
H
§
DSP D LED #1
G
§
DSP C LED #2
F
§
DSP C LED #1
E
RED
D6
GRN
D7
RED
D8
1
2
3
4
13
14
15
16
17
18
19
20
21
29
30
31
32
9
25
DSPAB_A0
DSPAB_A1
DSPAB_A2
DSPAB_A3
DSPAB_A4
DSPAB_A5
DSPAB_A6
DSPAB_A7
DSPAB_A8
DSPAB_A9
DSPAB_A10
DSPAB_A11
DSPAB_A12
DSPAB_A13
DSPAB_A14
DSPAB_A15
DSPAB_A16
DSPAB_SRAM_CS/
DSPAB_WR/
DSPAB_RD/
1
2
3
4
13
14
15
16
17
18
19
20
21
29
30
31
32
DSPAB_SRAM_CS/ 5
DSPAB_WR/
12
DSPAB_RD/
28
9
25
8
7
6
A0 VDD1
A1 VDD2
A2
A3
A4 128KX8
A5 12NS
A6 SRAM
A7
A8
A9
D0
D1
A10
A11
D2
A12
D3
D4
A13
D5
A14
D6
A15
D7
A16
1
VSS1
VSS2
A0 VDD1
A1 VDD2
A2
A3
A4 128KX8
A5 12NS
A6 SRAM
A7
A8
A9
D0
D1
A10
A11
D2
A12
D3
D4
A13
D5
A14
D6
A15
D7
A16
5
4
DRAFTER
CHECKER
RWH
12/7/04
AF
12/9/04
DESCRIPTION
SHOW DEPOPULATION FOR MIC BD.
PER ECO 041201-00.
8
24
Q.C.
AUTH.
CW
12/14/04
MSJ
12/9/04
D
DSPAB_D0
DSPAB_D1
DSPAB_D2
DSPAB_D3
DSPAB_D4
DSPAB_D5
DSPAB_D6
DSPAB_D7
6
7
10
11
22
23
26
27
E
W
G
+3.3VD
U8
§
8
24
C
DSPAB_D8
DSPAB_D9
DSPAB_D10
DSPAB_D11
DSPAB_D12
DSPAB_D13
DSPAB_D14
DSPAB_D15
6
7
10
11
22
23
26
27
E
W
G
VSS1
VSS2
GRN
A
[2/D1,2/C3,3/C3]
[2/D1,2/C3,3/C3]
[2/D1,2/C3,3/C3]
1
REVISIONS
+3.3VD
[2/B3,3/B3]
2
A0 VDD1
A1 VDD2
A2
A3
A4 128KX8
A5 12NS
A6 SRAM
A7
A8
A9
D0
D1
A10
A11
D2
A12
D3
D4
A13
D5
A14
D6
A15
D7
A16
+3.3VD
U9
§
8
24
E
W
G
VSS1
VSS2
A0 VDD1
A1 VDD2
A2
A3
A4 128KX8
A5 12NS
A6 SRAM
A7
A8
A9
D0
D1
A10
A11
D2
A12
D3
A13
D4
D5
A14
D6
A15
D7
A16
DSPAB_D16
DSPAB_D17
DSPAB_D18
DSPAB_D19
DSPAB_D20
DSPAB_D21
DSPAB_D22
DSPAB_D23
6
7
10
11
22
23
26
27
B
+3.3VD
§
U11
8
24
6
7
10
11
22
23
26
27
DSPAB_D24
DSPAB_D25
DSPAB_D26
DSPAB_D27
DSPAB_D28
DSPAB_D29
DSPAB_D30
DSPAB_D31
E
W
G
VSS1
VSS2
exicon
CONTRACT
NO.
APPROVALS
DRAWN
§
U10
3
DATE
RWH
5/20/02
CHECKED
KB
5/29/02
Q.C.
CW
6/3/02
ISSUED
KB
6/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MIC/DSP BD,MC8
DSPAB EXT MEM
SIZE
B
CODE
NUMBER
060-15389
REV
1
FILE NAME
15389-2 . 4
SHEET
1
4 OF 10
12-15-2004_8:52
[2/A3,3/A3,8/C4]
7
DSPAB_D[31:0]
8
7
6
5
4
3
2
1
REVISIONS
REV
1
DRAFTER
CHECKER
RWH
12/7/04
AF
12/9/04
DESCRIPTION
SHOW DEPOPULATION FOR MIC BD.
PER ECO 041201-00.
Q.C.
AUTH.
CW
12/14/04
MSJ
12/9/04
+3.3VD
D
§
R78
DSPC_CLK
[10/C6]
1
9
20
21
29
32
36
45
54
61
66
67
77
85
93
95
105
110
120
124
130
131
140
141
156
158
163
172
176
182
191
192
200
MASTER - ID0 HIGH, ID1 LOW
SLAVE - ID0 LOW, ID1 HIGH
§
R79
VCC
DSPC_CLK
NC
30
31
152
157
144
143
69
CD_RST/
[6/D8,8/B4,8/C1]
DSPCD_ACK
[6/D8,8/B4,8/C1]
DSPCD_ACK
[2/C8,3/C8,6/C8,8/B4,8/C1]
[6/C8,8/B4]
[8/B4,8/C1]
DSPABC_FSI
DSPC_SCKI
DSPB_1A_SDO
DSPB_1B_SDO
[2/C8,3/C6,8/B4,8/C1]
[8/A4,8/C1]
[3/D1,3/C8]
[3/D1,3/C8]
CLKIN
XTAL2
BSEL
RESET
ID0
ID1
ACK
205
IRQ0
206
IRQ1
207
IRQ2
DSP_FSI_IRQ
SP_IRQCD
DSPCD_CMD_RDY/
2
4
5
6
7
8
11
12
NC
NC
NC
C
13
15
16
17
18
19
22
23
NC
NC
NC
NC
NC
NC
RAS
CAS
SDWE
DQM
SDCKE
SDA10
SDCLK0
SDCLK1
BMS
MS0
MS1
MS2
MS3
SW
WR
RD
ADSP21065
RFS0
RCLK0
DR0A
DR0B
TFS0
TCLK0
DT0A
DT0B
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
RFS1
RCLK1
DR1A
DR1B
TFS1
TCLK1
DT1A
DT1B
26
PWMEVENT0
24
PWMEVENT1
38
DMAR1
39
DMAR2
50
DMAG1
51
DMAG2
40
52
55
63
56
NC
NC
R9 §
DSPCD_CPA/
DSPCD_BR1/
DSPCD_BR2/
[5/C1,6/B8]
[5/C1,6/B8]
[5/C1,6/B8]
DSPCD_EMU/
DSPC_TDO
DSPCD_TDI
DSPCD_TCK
DSPCD_TMS
DSPCD_TRST
DSPCD_STATUS_FULL
DSP_FLAG1
A
NC
1
3
5
7
9
11
13
2
4
6
8
10
12
14
J1
[6/B8]
[5/D1,10/C6]
*
NC
NC
NC
NC
NC
NC
102
103
115
142
202
203
§
DSPCD_EMU/
DSPCD_ICE_CLK
DSPCD_TMS
DSPCD_TCK
DSPCD_TRST
DSPCD_TDI
DSPC_TDO
DSPCD_EMU/
DSPCD_TMS
DSPCD_TCK
DSPCD_TRST
[6/B8]
[6/B8]
EMU
TDO
TDI
TCK
TMS
TRST
FLAG0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
FLAG6
FLAG7
FLAG8
FLAG9
FLAG10
FLAG11
NC1
NC2
NC3
NC4
NC5
NC6
BMSTR
NC7
DSPCD_A0
DSPCD_A1
DSPCD_A2
DSPCD_A3
DSPCD_A4
DSPCD_A5
DSPCD_A6
DSPCD_A7
DSPCD_A8
DSPCD_A9
DSPCD_A10
DSPCD_A11
DSPCD_A12
DSPCD_A13
DSPCD_A14
DSPCD_A15
DSPCD_A16
DSPCD_A17
DSPCD_A18
DSPCD_A19
DSPCD_A20
DSPCD_A21
DSPCD_A22
DSPCD_A23
82
83
84
86
87
88
90
91
92
96
97
98
100
101
104
107
108
109
111
112
113
116
117
118
121
122
123
126
127
128
132
133
DSPCD_D0
DSPCD_D1
DSPCD_D2
DSPCD_D3
DSPCD_D4
DSPCD_D5
DSPCD_D6
DSPCD_D7
DSPCD_D8
DSPCD_D9
DSPCD_D10
DSPCD_D11
DSPCD_D12
DSPCD_D13
DSPCD_D14
DSPCD_D15
DSPCD_D16
DSPCD_D17
DSPCD_D18
DSPCD_D19
DSPCD_D20
DSPCD_D21
DSPCD_D22
DSPCD_D23
DSPCD_D24
DSPCD_D25
DSPCD_D26
DSPCD_D27
DSPCD_D28
DSPCD_D29
DSPCD_D30
DSPCD_D31
53
DSPC_BMSTR
208
NC
DSPCD_WR/
DSPCD_RD/
CDCLK
CDWR/
CDRD/
CDBMS/
CDHOST_CS/
CDSRAM_CS/
[5/D1,6/D3,8/B7]
[5/C1,6/D3,7/C8]
[5/C1,6/D3,8/B7]
[5/C1,6/C3,7/D4]
CDSDRAM_CS/
CDRAS/
CDCAS/
CDSDWE/
CDDQM
CDDCKE
CDSDA10
CDSDCLK
[5/D1,6/C3,7/B4]
[5/D1,6/C3,7/B4]
DSPCD_WR_X/
FB1 §
DSPCD_RD_X/
DSPCD_A[23:0]
[8/B7]
CDCPA/
CDBR1/
CDBR2/
[8/B7]
DSPCD_D[31:0]
C
[6/A3,7/D7,8/B4]
§
DSPCD_ICE_CLK
4
DSPCD_CPA/
DSPCD_BR1/
DSPCD_BR2/
DSPC_BMSTR
DSPC_OUT1
DSPC_OUT0
5
DSPCD_SDRAM_CS/
DSPCD_RAS/
DSPCD_CAS/
DSPCD_SDWE/
DSPCD_DQM
DSPCD_SDCKE
DSPCD_SDA10
DSPCD_SDCLK
B
exicon
CONTRACT
NO.
6
DSPCD_ICE_CLK
DSPCD_WR/
DSPCD_RD/
DSPCD_BMS/
DSPCD_HOST_CS/
DSPCD_SRAM_CS/
[6/C3,7/D5]
§
R83
7
TEST POINTS
FB2 §
DSPD_TDO
8
[5/C1,6/D3,7/C8]
[5/C1,6/D3,7/C8]
[5/C1,6/D3,7/C8]
[5/C1,6/D3,7/C8]
[5/C1,6/D3,7/C8]
[5/C1,6/D3,7/D8]
[5/C1,6/D3,7/C8]
DSPCD_BMS/
DSPCD_SDRAM_CS/
DSPCD_HOST_CS/
DSPCD_SRAM_CS/
NC
NC
195
194
193
190
189
188
185
184
183
180
179
178
175
174
173
171
170
169
166
165
164
162
161
160
U14
DSPCD_RAS/
DSPCD_CAS/
DSPCD_SDWE/
DSPCD_DQM
DSPCD_SDCKE
DSPCD_SDA10
DSPCD_SDCLK
NC
153
70
71
74
75
64
58
59
GND
[6/B8]
[6/B8]
[6/B8]
3
10
14
25
33
35
41
49
57
60
62
68
72
73
81
89
94
99
106
114
119
125
129
135
139
150
154
155
159
167
168
177
181
186
187
196
204
NC
NC
NC
197
198
199
201
138
137
136
134
80
79
78
76
CF3
CF4
CF5
CF6
CF7
CF8
+3.3VD
R82
145
146
148
151
149
147
NC
DEVELOPMENT ONLY:
PIN 7, BTCK, JUMP TO PIN 8
PIN 9, BTRST/, JUMP TO PIN 10
+3.3VD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
65
CPA
27
BR1
28
BR2
B
[6/B8,8/B4]
[2/B8,3/B8,6/B8,8/B4]
HBR
HBG
CS
REDY
SBTS
42
43
44
46
47
48
37
34
3
[4/A8,8/B7]
[4/A8,8/B7]
APPROVALS
DRAWN
DATE
RWH
5/20/02
CHECKED
KB
5/29/02
Q.C.
CW
6/3/02
ISSUED
KB
6/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MIC/DSP BD,MC8
DSP C
SIZE
B
CODE
FILE NAME
15389-2 . 5
NUMBER
060-15389
SHEET
1
REV
1
5 OF 10
12-15-2004_8:52
D
8
7
6
5
4
3
2
1
REVISIONS
REV
1
DRAFTER
CHECKER
RWH
12/7/04
AF
12/9/04
DESCRIPTION
SHOW DEPOPULATION FOR MIC BD.
PER ECO 041201-00.
+3.3VD
Q.C.
AUTH.
CW
12/14/04
MSJ
12/9/04
MASTER - ID0 HIGH, ID1 LOW
SLAVE - ID0 LOW, ID1 HIGH
D
1
9
20
21
29
32
36
45
54
61
66
67
77
85
93
95
105
110
120
124
130
131
140
141
156
158
163
172
176
182
191
192
200
§
R81
[10/C6]
[5/C8,8/B4,8/C1]
[5/C8,8/B4,8/C1]
[2/C8,3/C8,5/C8,8/B4,8/C1]
[5/C8,8/B4]
§
VCC
R80
DSPD_CLK
NC
CD_RST/
DSPCD_ACK
DSPD_FSI
DSPD_SCKI
NC
NC
C
NC
[1/C7]
[1/C7]
CLKIN
XTAL2
BSEL
RESET
ID0
ID1
ACK
205
IRQ0
206
IRQ1
207
IRQ2
DSP_FSI_IRQ
SP_IRQCD
NC
[8/B4,8/C1]
[8/A4]
30
31
152
157
144
143
69
DSPD_1A_SDO
DSPD_1B_SDO
NC
NC
2
4
5
6
7
8
11
12
13
15
16
17
18
19
22
23
ADSP21065
RFS0
RCLK0
DR0A
DR0B
TFS0
TCLK0
DT0A
DT0B
RFS1
RCLK1
DR1A
DR1B
TFS1
TCLK1
DT1A
DT1B
38
DMAR1
39
DMAR2
50
DMAG1
51
DMAG2
NC
NC
[5/B8,5/C1]
[5/C1,5/B8]
[5/C1,5/B8]
[5/A6]
[5/A8]
[5/A6]
[5/A6]
[5/A6]
[5/A6]
B
[5/B8,8/B4]
[2/B8,3/B8,5/B8,8/B4]
DSPCD_CPA/
DSPCD_BR1/
DSPCD_BR2/
HBR
HBG
CS
REDY
SBTS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
65
CPA
27
BR1
28
BR2
DSPCD_EMU/
DSPD_TDO
DSPC_TDO
DSPCD_TCK
DSPCD_TMS
DSPCD_TRST
145
146
148
151
149
147
DSPCD_STATUS_FULL
DSP_FLAG1
197
198
199
201
138
137
136
134
80
79
78
NC 76
NC
DF3
DF4
DF5
DF6
DF7
DF8
NC
NC
NC
NC
NC
NC
102
103
115
142
202
203
BMS
MS0
MS1
MS2
MS3
SW
WR
RD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
26
PWMEVENT0
24
PWMEVENT1
40
52
55
63
56
RAS
CAS
SDWE
DQM
SDCKE
SDA10
SDCLK0
SDCLK1
EMU
TDO
TDI
TCK
TMS
TRST
FLAG0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
FLAG6
FLAG7
FLAG8
FLAG9
FLAG10
FLAG11
NC1
NC2
NC3
NC4
NC5
NC6
BMSTR
NC7
42
43
44
46
47
48
37
34
NC
DSPCD_BMS/
DSPCD_SDRAM_CS/
DSPCD_HOST_CS/
DSPCD_SRAM_CS/
153
70
71
74
75 NC
64 NC
58
59
DSPCD_WR/
DSPCD_RD/
195
194
193
190
189
188
185
184
183
180
179
178
175
174
173
171
170
169
166
165
164
162
161
160
DSPCD_A0
DSPCD_A1
DSPCD_A2
DSPCD_A3
DSPCD_A4
DSPCD_A5
DSPCD_A6
DSPCD_A7
DSPCD_A8
DSPCD_A9
DSPCD_A10
DSPCD_A11
DSPCD_A12
DSPCD_A13
DSPCD_A14
DSPCD_A15
DSPCD_A16
DSPCD_A17
DSPCD_A18
DSPCD_A19
DSPCD_A20
DSPCD_A21
DSPCD_A22
DSPCD_A23
82
83
84
86
87
88
90
91
92
96
97
98
100
101
104
107
108
109
111
112
113
116
117
118
121
122
123
126
127
128
132
133
DSPCD_D0
DSPCD_D1
DSPCD_D2
DSPCD_D3
DSPCD_D4
DSPCD_D5
DSPCD_D6
DSPCD_D7
DSPCD_D8
DSPCD_D9
DSPCD_D10
DSPCD_D11
DSPCD_D12
DSPCD_D13
DSPCD_D14
DSPCD_D15
DSPCD_D16
DSPCD_D17
DSPCD_D18
DSPCD_D19
DSPCD_D20
DSPCD_D21
DSPCD_D22
DSPCD_D23
DSPCD_D24
DSPCD_D25
DSPCD_D26
DSPCD_D27
DSPCD_D28
DSPCD_D29
DSPCD_D30
DSPCD_D31
53
DSPD_BMSTR
[5/C1,5/D3,7/C8]
[5/C1,5/D3,7/C8]
[5/C1,5/D3,7/C8]
[5/C1,5/D3,7/C8]
[5/C1,5/D3,7/C8]
[5/C1,5/D3,7/D8]
[5/C1,5/D3,7/C8]
[5/D1,5/C3,8/B7]
[5/C1,5/C3,7/C8]
[5/C1,5/C3,8/B7]
[5/C1,5/C3,7/D4]
[5/C3,5/D1,7/B4]
[5/C3,5/D1,7/B4]
C
DSPCD_A[23:0]
[5/B3,7/D5]
B
DSPCD_D[31:0]
[5/A3,7/D7,8/B4]
DSPD_BMSTR
208 NC
GND
3
10
14
25
33
35
41
49
57
60
62
68
72
73
81
89
94
99
106
114
119
125
129
135
139
150
154
155
159
167
168
177
181
186
187
196
204
DSPCD_RAS/
DSPCD_CAS/
DSPCD_SDWE/
DSPCD_DQM
DSPCD_SDCKE
DSPCD_SDA10
DSPCD_SDCLK
U13
§
A
exicon
CONTRACT
NO.
DSPD_OUT1
DSPD_OUT0
8
7
6
5
4
3
[4/A8,8/B7]
[4/A8,8/B7]
APPROVALS
DRAWN
DATE
RWH
5/20/02
CHECKED
KB
5/29/02
Q.C.
CW
6/3/02
ISSUED
KB
6/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MIC/DSP BD,MC8
DSP D
SIZE
B
CODE
NUMBER
060-15389
REV
1
FILE NAME
15389-2 . 6
SHEET
1
6 OF 10
12-15-2004_8:52
D
[5/A3,6/A3,8/B4]
7
6
5
4
3
2
DSPCD_D[31:0]
REV
1
+3.3VD
[5/B3,6/C3]
DSPCD_A[23:0]
+3.3VD
[5/C1,5/D3,6/D3]
[5/C1,5/D3,6/D3]
[5/C1,5/D3,6/D3]
[5/C1,5/D3,6/D3]
[5/C1,5/C3,6/D3]
C
[5/C1,5/D3,6/D3]
[5/C1,5/D3,6/D3]
DSPCD_SDA10
DSPCD_A9
DSPCD_A8
DSPCD_A7
DSPCD_A6
DSPCD_A5
DSPCD_A4
DSPCD_A3
DSPCD_A2
DSPCD_A1
DSPCD_A0
24
66
65
64
63
62
61
60
27
26
25
VDD
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DSPCD_DQM
59
DQM3
28
DQM2
71
DQM1
16
DQM0
DSPCD_RAS/
DSPCD_CAS/
DSPCD_SDWE/
DSPCD_SDRAM_CS/
19
RAS
18
CAS
17
WE
20
CS
DSPCD_SDCKE
DSPCD_SDCLK
67
CKE
68
CLK
73
70
69
57
30
21
14
NC6
NC5
NC4
NC3
NC2
NC1
NC0
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
2MX32
100MHZ
VSS
44
58
72
86
NC
NC
NC
NC
NC
NC
NC
VDDQ
DSPCD_D31
DSPCD_D30
DSPCD_D29
DSPCD_D28
DSPCD_D27
DSPCD_D26
DSPCD_D25
DSPCD_D24
DSPCD_D23
DSPCD_D22
DSPCD_D21
DSPCD_D20
DSPCD_D19
DSPCD_D18
DSPCD_D17
DSPCD_D16
DSPCD_D15
DSPCD_D14
DSPCD_D13
DSPCD_D12
DSPCD_D11
DSPCD_D10
DSPCD_D9
DSPCD_D8
DSPCD_D7
DSPCD_D6
DSPCD_D5
DSPCD_D4
DSPCD_D3
DSPCD_D2
DSPCD_D1
DSPCD_D0
56
54
53
51
50
48
47
45
42
40
39
37
36
34
33
31
85
83
82
80
79
77
76
74
13
11
10
8
7
5
4
2
VSSQ
6
12
32
38
46
52
78
84
DSPCD_A13 23
BA1
DSPCD_A12 22
BA0
3
9
35
41
49
55
75
81
1
15
29
43
D
[5/C1,5/D3,6/D3]
U5
DSPCD_A0
DSPCD_A1
DSPCD_A2
DSPCD_A3
DSPCD_A4
DSPCD_A5
DSPCD_A6
DSPCD_A7
DSPCD_A8
DSPCD_A9
DSPCD_A10
DSPCD_A11
DSPCD_A12
DSPCD_A13
DSPCD_A14
DSPCD_A15
DSPCD_A16
1
2
3
4
13
14
15
16
17
18
19
20
21
29
30
31
32
DSPCD_SRAM_CS/
DSPCD_WR/
DSPCD_RD/
5
12
28
9
25
§
DSPCD_A0
DSPCD_A1
DSPCD_A2
DSPCD_A3
DSPCD_A4
DSPCD_A5
DSPCD_A6
DSPCD_A7
DSPCD_A8
DSPCD_A9
DSPCD_A10
DSPCD_A11
DSPCD_A12
DSPCD_A13
DSPCD_A14
DSPCD_A15
DSPCD_A16
1
2
3
4
13
14
15
16
17
18
19
20
21
29
30
31
32
DSPCD_SRAM_CS/
DSPCD_WR/
DSPCD_RD/
5
12
28
9
25
B
DSPCD_A0
DSPCD_A1
DSPCD_A2
DSPCD_A3
DSPCD_A4
DSPCD_A5
DSPCD_A6
DSPCD_A7
DSPCD_A8
DSPCD_A9
DSPCD_A10
DSPCD_A11
DSPCD_A12
DSPCD_A13
DSPCD_A14
DSPCD_A15
DSPCD_A16
1
2
3
4
13
14
15
16
17
18
19
20
21
29
30
31
32
DSPCD_SRAM_CS/
DSPCD_WR/
DSPCD_RD/
5
12
28
9
25
A
[5/C1,5/C3,6/C3]
[5/C3,5/D1,6/C3]
[5/C3,5/D1,6/C3]
DSPCD_SRAM_CS/
DSPCD_WR/
DSPCD_RD/
DSPCD_A0
DSPCD_A1
DSPCD_A2
DSPCD_A3
DSPCD_A4
DSPCD_A5
DSPCD_A6
DSPCD_A7
DSPCD_A8
DSPCD_A9
DSPCD_A10
DSPCD_A11
DSPCD_A12
DSPCD_A13
DSPCD_A14
DSPCD_A15
DSPCD_A16
1
2
3
4
13
14
15
16
17
18
19
20
21
29
30
31
32
DSPCD_SRAM_CS/
DSPCD_WR/
DSPCD_RD/
5
12
28
9
25
8
1
REVISIONS
7
6
5
4
A0 VDD1
A1 VDD2
A2
A3
A4 128KX8
A5 12NS
A6 SRAM
A7
A8
D0
A9
D1
A10
D2
A11
D3
A12
D4
A13
D5
A14
D6
A15
D7
A16
A0 VDD1
A1 VDD2
A2
A3
A4 128KX8
A5 12NS
A6 SRAM
A7
A8
A9
D0
D1
A10
A11
D2
A12
D3
D4
A13
D5
A14
D6
A15
D7
A16
D
A0 VDD1
A1 VDD2
A2
A3
A4 128KX8
A5 12NS
A6 SRAM
A7
A8
A9
D0
D1
A10
A11
D2
A12
D3
D4
A13
D5
A14
D6
A15
D7
A16
+3.3VD
§
U3
8
24
C
A0 VDD1
A1 VDD2
A2
A3
A4 128KX8
A5 12NS
A6 SRAM
A7
A8
A9
D0
D1
A10
A11
D2
A12
D3
D4
A13
D5
A14
D6
A15
D7
A16
DSPCD_D8
DSPCD_D9
DSPCD_D10
DSPCD_D11
DSPCD_D12
DSPCD_D13
DSPCD_D14
DSPCD_D15
6
7
10
11
22
23
26
27
+3.3VD
§
U4
8
24
DSPCD_D16
DSPCD_D17
DSPCD_D18
DSPCD_D19
DSPCD_D20
DSPCD_D21
DSPCD_D22
DSPCD_D23
6
7
10
11
22
23
26
27
E
W
G
VSS1
VSS2
DSPCD_D0
DSPCD_D1
DSPCD_D2
DSPCD_D3
DSPCD_D4
DSPCD_D5
DSPCD_D6
DSPCD_D7
6
7
10
11
22
23
26
27
E
W
G
VSS1
VSS2
B
+3.3VD
§
U2
8
24
6
7
10
11
22
23
26
27
E
W
G
VSS1
VSS2
SHOW DEPOPULATION FOR MIC BD.
PER ECO 041201-00.
Q.C.
AUTH.
CW
12/14/04
MSJ
12/9/04
8
24
E
W
G
VSS1
VSS2
DRAFTER
CHECKER
RWH
12/7/04
AF
12/9/04
DESCRIPTION
DSPCD_D24
DSPCD_D25
DSPCD_D26
DSPCD_D27
DSPCD_D28
DSPCD_D29
DSPCD_D30
DSPCD_D31
exicon
CONTRACT
NO.
APPROVALS
DRAWN
DATE
TITLE
RWH
5/20/02
SCHEM,MIC/DSP BD,MC8
DSPCD EXT MEM
SIZE
CHECKED
KB
5/29/02
§
U1
Q.C.
CW
6/3/02
ISSUED
KB
6/3/02
3
2
A
3 OAK PARK
BEDFORD, MA 01730
B
CODE
NUMBER
060-15389
REV
1
FILE NAME
15389-2 . 7
SHEET
1
7 OF 10
12-15-2004_8:52
8
7
6
5
4
3
2
+3.3VD
[1/B3]
[1/B3]
+3.3VD
D
SEE NOTES
[1/B4]
[1/B4]
[1/B3,8/D1]
[1/B3,8/D1]
[1/B3,8/D1]
[1/B3,8/C1]
C
[2/D1,2/C3,3/C3]
[2/D1,2/C3,3/C3]
[3/C3]
[3/C3]
[2/A3,4/B8]
[3/A3,4/B8]
[2/A3,4/B8]
[3/A3,4/B8]
DSP_PROG/
E17
R69 §
DSP_A[4:0]
ZDSP_D[7:0]
NC
NC
22
M1
26
NC2
52
PROGRAM
DSP_A0
DSP_A1
DSP_A2
DSP_A3
DSP_A4
7
8
9
10
13
ZDSP_D0
ZDSP_D1
ZDSP_D2
ZDSP_D3
ZDSP_D4
ZDSP_D5
ZDSP_D6
ZDSP_D7
14
15
16
17
18
19
20
31
VCC
M0
XCS05XL-VQ100
DONE
INIT
CCLK
IO_DIN
IO_DOUT
A0
A1
A2
A3
A4
B
[4/A8,5/A3]
[4/A8,6/A3]
[4/A8,5/A3]
[4/A8,6/A3]
[1/D3,8/C1]
[1/C3,8/C1]
[10/D6]
D0
D1
D2
D3
D4
D5
D6
D7
DSPAB_D0
DSPAB_D1
DSPAB_D2
DSPAB_D3
DSPAB_D4
DSPAB_D5
DSPAB_D6
DSPAB_D7
29
ZDB_RD
21
ZDB_WR
32
DB_CS
3
DB_RST
DSPAB_HOST_CS/
DSPAB_BMS/
DSPAB_WR_X/
DSPAB_RD_X/
34
DSPAB_HOST_CS
35
DSPAB_BMS
48
DSPAB_WR
40
DSPAB_RD
DSPA_OUT0
DSPB_OUT0
DSPA_OUT1
DSPB_OUT1
4
DSPA_OUT0
5
DSPB_OUT0
27
DSPA_OUT1
85
DSPB_OUT1
DSPCD_HOST_CS/
DSPCD_BMS/
DSPCD_WR_X/
DSPCD_RD_X/
41
DSPCD_HOST_CS
42
DSPCD_BMS
54
DSCD_WR
44
DSPCD_RD
DSPC_OUT0
DSPD_OUT0
DSPC_OUT1
DSPD_OUT1
6
DSPC_OUT0
56
DSPD_OUT0
86
DSPC_OUT1
87
DSPD_OUT1
DSP_MCKI
DSP_FSI
99
DB_MCKI
93
DB_FSI
2
XC17S05XL
*
W1
24
50
36
74
72
73
4
3
2
5
IO_DOUT
VPP
VCC
CE
OE DATA
CLK CEO
GND
AB_RST
DSPAB_ACK
DSPAB_CMD_RDY
DSPAB_STAT_FULL
SP_IRQAB
CD_RST
DSPCD_ACK
DSPCD_CMD_RDY
DSP_CD_STAT_FULL
SP_IRQCD
DSP_FLAG1
DSP_FSI_IRQ
DSPABC_FSI
DSPD_FSI
DSPA_SCKI
DSPB_SCKI
DSPC_SCKI
DSPD_SCKI
DSP_CLK
SP0
SP1
SP2
SP3
SP4
60
61
62
65
66
67
68
69
DSPAB_D0
DSPAB_D1
DSPAB_D2
DSPAB_D3
DSPAB_D4
DSPAB_D5
DSPAB_D6
DSPAB_D7
43
47
45
28
57
70
71
78
80
81
82
83
84
88
77
64
49
38
23
11
1
GND
*
U21
ZRD/
ZWR/
ZCS/
ZRST/
5
ABC_FSI
D_FSI
FSI_IRQ
A_SCKI
C_SCKI
[2/A3,3/A3,4/D7]
[2/C8,3/C8,8/C1]
[2/C8,3/C8,8/C1]
[2/C8,8/C1]
[2/B8,3/B8]
[2/C8,3/C8]
MCKI
DSP_FSI
ZDSP_RD/
ZDSP_WR/
ZDSP_CS/
ZDSP_RST/
DSPAB_ACK
DSPAB_CMD_RDY/
AB_RST/
DSPCD_ACK
DSPCD_CMD_RDY/
CD_RST/
DSPABC_FSI
DSPD_FSI
DSP_FSI_IRQ
DSPA_SCKI
DSPC_SCKI
C
DSP_MCKI
DSP_FSI
NOTES
1 M1,M0 HAVE WEAK PULLUPS
M1,M0 = 1,1 SLAVE SERIAL MODE
DSPCD_D[31:0]
CD_RST/
DSPCD_ACK
DSPCD_CMD_RDY/
DSPCD_STATUS_FULL
SP_IRQCD
76
DSP_FLAG1
94
91
59
95 § R74
96 § R75
97 § R76
98 § R77
DSP_FSI_IRQ
DSPABC_FSI
DSPD_FSI
DSPA_SCKI
DSPB_SCKI
DSPC_SCKI
DSPD_SCKI
R73 §
92
90
79
55
58
R72 §
R71 §
U15§
SP4
6
TEST POINTS
DSPAB_D[31:0]
R68 §
7
1
6 NC
30
39
46
33
53
33
33
33
33
D
7
8
AB_RST/
DSPAB_ACK
DSPAB_CMD_RDY/
DSPAB_STATUS_FULL
SP_IRQAB
DSPCD_D0
DSPCD_D1
DSPCD_D2
DSPCD_D3
DSPCD_D4
DSPCD_D5
DSPCD_D6
DSPCD_D7
Q.C.
AUTH.
RWH
10/15/02
KAB
10/15/02
CW
12/14/04
MSJ
12/9/04
Q1§
CDACK
CDRDY/
CDRST/
A
8
2
2N3904
ABACK
ABRDY/
ABRST/
ZDSP_RD/
ZDSP_WR/
ZDSP_CS/
ZDSP_RST/
DSP_30MHZ
§
§
4.7K
+3.3VD
R93
R94
1
DONE LED
DRAFTER
CHECKER
CW
REVISED SIGNAL NAMES PER DCR 020926-00
9/27/02
KAB
10/11/02
RWH
SHOW DEPOPULATION FOR MIC BD.
12/7/04
PER ECO 041201-00.
AF
12/9/04
DESCRIPTION
DSP FPGA
DSPCD_D0
DSPCD_D1
DSPCD_D2
DSPCD_D3
DSPCD_D4
DSPCD_D5
DSPCD_D6
DSPCD_D7
[5/C1,5/C3,6/D3]
[5/D1,5/C3,6/D3]
[5/C2]
[5/C2]
FPGA_DONE
4.7K
89
100
12
25
37
51
63
75
[1/C3]
D11 §
+3.3VD
R70
10K
270 FPGA
GRN
DSP_CCLK
+3.3VD
§
REV
R95 §
DSP_DIN
1
REVISIONS
M1,M0 = 1,0 MASTER SERIAL MODE
2 JUMPER W1 TO GND TO USE CONFIGURATION ROM.
[5/A3,6/A3,7/D7]
[5/C8,6/D8,8/C1]
[5/C8,6/D8,8/C1]
[5/C8,8/C1]
[5/B8,6/B8]
[5/C8,6/C8]
B
[2/B8,3/B8,5/B8,6/B8]
[2/C8,3/C8,5/C8,6/C8,8/C1]
[2/C8,3/C6,5/C8,8/C1]
[6/C6,8/C1]
[2/C8,8/C1]
[3/C8]
[5/C8,8/C1]
[6/C8]
IO
AUDIO5
AUDIO8
AUDIO_4MHZ
[1/D7]
[1/C3]
[1/C7]
exicon
CONTRACT
NO.
[1/C3]
IO
A5
A8
A9
SP4
APPROVALS
DRAWN
4
3
DATE
RWH
5/20/02
CHECKED
KB
5/29/02
Q.C.
CW
6/3/02
ISSUED
KB
6/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MIC/DSP BD,MC8
FPGA
SIZE
B
CODE
NUMBER
060-15389
REV
2
FILE NAME
15389-2 . 8
SHEET
1
8 OF 10
12-15-2004_8:52
8
7
6
5
4
3
2
MIC_SEL0/
MIC_IN_1+
MIC IN 1
[10/B5]
+15VA
10.0K
1%
J5
2
D
3
FB3
C34
C12
R18
10/16
10.0K
1%
150PF
1
+15VA
8
+
MC33078
2
-
U18
FB4
MIC_IN_1-
MIC_IN_2+
MIC IN 2
MC33078
R26
C8
6
-
U18
270
1/4W
10/25
R19
10/16
10.0K
1%
-15VA
2
3
FB5
C41
C18
R31
MIC_IN_3+
2
3
FB7
C46
10/16
10.0K
1%
C19
R32
10/16
10.0K
1%
8
+15VA
1%
+15VA
8
+
MC33078
2
-
U19
+
MC33078
R37
C14
6
-
U19
270
1/4W
10/25
3
FB9
C51
R42
10/16
10.0K
1%
C25
R43
10/16
10.0K
1%
8
+
C45
102
1%
8
8
13
5
+
MC33078
R48
C20
6
-
U20
270
1/4W
10/25
7
4
-
R49
15K
-15VA
U20
-15VA
12
VCC
MC33078
3
S
1
IN
VEE
4
ADG451
VDD
2
D
GND
U25
5
B
-15VA
R47
2.00K
1%
C50
C49
47PF
R46
R45 47PF
102
1%
R55
+15VA
10.0K
1%
8
3
+
2
-
C33
R54
10/16
10.0K
1%
[10/A5]
+15VA +5VAD
+15VA
47PF
R53
8
13
5
+
MC33078
R59
C28
6
-
U26
270
1/4W
10/25
7
4
VCC
R60
15K
MC33078
1
-15VA
U26
-15VA
R56
MIC_IN_4-
+15VA +5VAD
+15VA
14
S
16
IN
VEE
4
12
ADG451
VDD
D
15
GND
5
U25
-15VA
R58
C52
FB10
47PF
R35
1
4
150PF
C
10.0K
1%
1
A
J4
U25
5
-15VA
R36
+15VA
[10/A5]
150PF
GND
4
-15VA
2.00K
1%
47PF
[10/A5]
10/16
RIGHT_MAIN_IN
10
D
-15VA
GNDA
R44
C24
C32
LEFT_MAIN_IN
-15VA
10.0K
C53
1%
2
R38
ADG451
VDD
11
S
9
IN
VEE
15K
C47
J8
12
VCC
1
4
MIC_IN_4+
7
C44
[10/A5]
B
MIC IN 4
13
5
-15VA
2
MIC_IN_3-
+15VA +5VAD
1
2
3
4
5
6
7
8
9
10
10.0K
1%
1
FB8
+15VA
102
4
3
3
150PF
47PF
R24
+15VA
[10/B5]
150PF
D
C57
.1/25
C40
10.0K
C48
1%
J7
U25
5
C39
R34 47PF
MIC IN 3
GND
4
2.00K
1%
47PF
4
MIC_IN_2-
7
D
-15VA
R25
C42
FB6
6
S
8
IN
VEE
R33
1
150PF
ADG451
VDD
10.0K
1%
[10/B5]
150PF
R27
15K
-15VA
R22 47PF
[10/B5]
7
12
VCC
1
10.0K
1% C43
J6
C
C13
13
+
C35
150PF
Q.C.
AUTH.
FB13
+15VA
5
4
3
4
DRAFTER
CHECKER
DESCRIPTION
C38
47PF
8
REV
+5VD
+5VAD
R21
1
REVISIONS
2.00K
1%
C54
R57
47PF
MIC_SEL1/
47PF
APPROVALS
DRAWN
102
1%
10.0K
1%
7
6
exicon
CONTRACT
NO.
C55
5
4
3
DATE
RWH
5/20/02
CHECKED
KB
5/29/02
Q.C.
CW
6/3/02
ISSUED
KB
6/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MIC/DSP BD,MC8
MICROPHONE INPUTS
SIZE
B
CODE
NUMBER
060-15389
REV
0
FILE NAME
15389-2 . 9
SHEET
1
9 OF 10
12-7-2004_10:16
8
8
7
6
5
4
3
2
1
REVISIONS
REV
+3.3VD
+3.3V DIGITAL BYPASS CAPACITORS
1
DRAFTER
CHECKER
RWH
12/7/04
AF
12/9/04
DESCRIPTION
SHOW DEPOPULATION FOR MIC BD.
PER ECO 041201-00.
+3.3VD
10K
VDD
3.3V
IN
1
GND
2
R12
3
OUT
R11 §
§
U22
33
§ DSP_30MHZ
C4 §
C5 §
C59 §
C60 §
C61 §
C62 §
C63 §
C64 §
C65
C66 §
C67 §
C68 §
C69 §
C70 §
C71 §
C72 §
C73 §
C74 §
C75 §
C76 §
C77 §
C78 §
C79 §
C80 §
C81 §
C82 §
C83 §
C84 §
C85 §
C86 §
C87 §
C88 §
C89 §
[3/D8]
C90 §
C91 §
C92 §
C93 §
C94 §
C95 §
C96 §
C97
§
C98 §
C99 §
C100§
C101§
[2/D1,2/A8]
C102 §
C103 §
C104 §
C105§
C106§
C107§
C108§
C109§
C110§
C111§
C112§
C113§
C114 §
C115 §
C116 §
C117§
C118§
C119§
C120§
C121§
C122§
C123§
C124§
C125§
C126 §
C127 §
C128 §
C129§
C130§
C131§
C132§
C133§
C134§
C135§
C136§
C137§
C138 §
C139 §
C140 §
C141§
C142§
C143§
C144§
C145§
C146§
C147§
C149§
C150§
[8/A7]
1
U24
§
2
§ DSPA_CLK
R84
33
R85
33 DSPB_CLK
R86
33 DSPAB_ICE_CLK
.1/25
.1/25
R13§
33
§
C3 §
.1/25
R10§ 30.000MHZ 4
D
§
C2 §
C1
.1/25
.1/25
[2/D8]
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
Q.C.
AUTH.
CW
12/14/04
MSJ
12/9/04
.1/25
D
.1/25
.1/25
74LCX14-3.3V
+3.3VD
3
U24
§
4
§
.1/25
74LCX14-3.3V
FB14
R91
*
*
1
CLK_IN
NC 2
NC
6
5
W181-01
3
*
.1/25
R90
*
C6
*
GND
U23
*
U24
§
6
§
.1/25
74LCX14-3.3V
C148
VDD
CLK_OUT
4 SS%
7 FS1
8 FS2
R92
5
13
*
§
U24
12 R88
33
§ DSPC_CLK
[5/D8]
10/10
9
§
8
R89
§
33 DSPD_CLK
[6/D8]
74LCX14-3.3V
C
11
.1/25
.1/25
74LCX14-3.3V
U24
.1/25
.1/25
.1/25
§
U24
10 R87
§
33 DSPCD_ICE_CLK
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
C
[5/D1,5/A8]
74LCX14-3.3V
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
.1/25
MICROPHONE BIAS VOLTAGE SUPPLY
+15VA
D9
1N4002
3
B
C37
.1/25
CASE=VOUT
VIN
VOUT
2
LM317M
ADJ
1
9V
R20
U12
D10
237
1%
1N4002
R17
1K
C7
22/16
C36
R15
R14
330
2.2K
.1/25
C11
10/16
R16
MIC_IN_1+
MIC_IN_1-
2.2K
[9/D7]
B
[9/C7]
R23
1%
R29
R28
330
2.2K
C17
10/16
R30
MIC_IN_2+
BYPASS CAPACITORS
[9/C7]
+15VA
MIC_IN_2-
2.2K
[9/C7]
C10
R40
R39
330
2.2K
C23
10/16
A
R41
R50
330
2.2K
C31
R52
2.2K
.1/25
MIC_IN_4+
MIC_IN_4-
C16
.1/25
C22
.1/25
C30
.1/25
C58
.1/25
[9/B7]
C9
MIC_IN_3-
2.2K
R51
10/16
MIC_IN_3+
.1/25
[9/B7]
C15
.1/25
C21
.1/25
C29
C56
.1/25
.1/25
*C26
22/16
*C27
22/16
-15VA
[9/B7]
exicon
CONTRACT
NO.
[9/A7]
APPROVALS
DRAWN
8
7
6
5
4
3
DATE
RWH
5/20/02
CHECKED
KB
5/29/02
Q.C.
CW
6/3/02
ISSUED
KB
6/3/02
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM,MIC/DSP BD,MC8
BYPASS CAPACITORS & DSP CLOCKS
SIZE
B
CODE
NUMBER
060-15389
REV
1
FILE NAME
15389-2 . 10
SHEET
1
10 OF 10
12-15-2004_8:52
1.50K
8
7
6
5
4
3
2
1
REVISIONS
REV
DRAFTER
CHECKER
DESCRIPTION
Q.C.
AUTH.
D
D
FB1
C5
C
+5VD
.1/25
C
C4
.1/25
D1
BB132
2
3
MC1648
VCC VCCO
1
TANK
L1
1UH
C3
OUT
10PF
8
C2
.1/25
VREF
AGC
GND1 GND2
6
7
4
5
R1
OSC
47
VCO_V
5
4
3
2
1
NOTES
1 UNLESS OTHERWISE INDICATED, RESISTORS ARE 1/10W
C1
U1
.1/25
J1
2 UNLESS OTHERWISE INDICATED, RESISTORS ARE 5%
3 UNLESS OTHERWISE INDICATED, CAPACITORS ARE UF/V
4
DIGITAL
GROUND
ANALOG
GROUND
CHASSIS
GROUND
POWER
GROUND
5 LAST REFERENCE DESIGNATORS USED: C5, D1, FB1, J1, L1, R1, U1.
B
B
© 2003 Lexicon, Inc.
CONTRACT
NO.
exicon
APPROVALS
DRAWN
RWH
3/3/03
CHECKED
ECM
3/5/03
Q.C.
CW
3/7/03
KAB
3/11/03
ISSUED
8
7
6
5
4
3
DATE
2
A
3 OAK PARK
BEDFORD, MA 01730
TITLE
SCHEM, VCO BD, MCLK
SIZE
B
CODE
NUMBER
060-16139
REV
0
FILE NAME
16139-0. 1
SHEET
1
1 OF 1
3-18-2003_9:15
A
Harman Specialty Group 3 Oak Park, Bedford, MA, 01730-1413 USA
Customer Service: Telephone: 781-280-0300 | Service Fax: 781-280-0499 | www.lexicon.com
Part No. 070-17536 | Rev 0

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