Download MiTAC MITAC 8050D User's Manual
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SERVICE MANUAL FOR 8050D BY: Grass.Ren Repair Technology Research Department /EDVD Mar.2004 8050D N/B Maintenance Contents 1. Hardware Engineering Specification ………………………………………………………………….. 1.1 Introduce ……………………………………………………………………………………………… 1.2 System Overview ………………………………………………………………………………………. 1.3 System Hardware Parts ………………………………………………………………………………… 1.4 Other Functions …………………………………………………………………………………….…. 1.5 Power Management ……………………………………………………………………………………. t t n e e 2. System View & Disassembly ………………………………………………………………………….. r c m ………………………………………………………………………………………….. e ……………………………………………………………………………………. u S c c Setting o……………………………………………… 3. Definition & Location of Connectors / Switches a D l iT i………………………………………………………….. 4. Definition & Location of Major Component a M t 5. Pin Description of Major Component………………………………………………………………….. n …………………………………………………………………….. e d i………………………………………………………………….……. f ………………………………….. n o 6. System Block DiagramC ……………………………………………………….………………………..... 2.1 System View 2.2 System Disassembly 5.1 Intel Pentium M (Banias) Processor 5.2 Intel 855GM/GME North Bridge 5.3 Intel 82801 IDBM I/O Controller Hub 4 Mobile(ICH4-M) South Bridge 7. Maintenance Diagnostics ……………………………………………………………………………….. 7.1 Introduction …………………………………………………………………………………………… 7.2 Debug Card …………………………………… ……………………………………………………… 7.3 Error code……………………………… …………………………………………………………….. 3 3 6 7 34 40 43 43 46 66 69 71 71 75 84 92 93 93 94 95 1 8050D N/B Maintenance Contents 8. Trouble Shooting ……………………………………………………………………………………..…. 8.1 No Power ………………………………………………………………………………………………. 8.2 Battery Can not Be Charged …………………………………………………………………………….. 8.3 No Display ………………………………… …………………………………………………………... 8.4 External Monitor No Display ……………………………………………………………………………. 8.5 Memory Test Error …………………………………………………………………………………….. 8.6 Keyboard/Touch-pad Test Error ………………………………………………………………………... 8.7 USB Port Test error……………………………………………………………………………………... 8.8 Hard Disk Drive Test Error……………………………………………………………………………… 8.9 CD-ROM Test Error ……………………………………………………………………………………. 8.10 Audio Test Failure………………………………………………………………………………..….… 8.11 LAN Test Error ……………………………………………………………………………………….. 8.12 Modem Test Error…………… …………………………………………………………………..…… 8.13 Mini-PCI Test Error……….. ……… ……………………………………………………………….... 8.14 Card Bus&Reader Test Error…………………………………………………………………………... 8.15 IEEE1394 Test Failure ………………………………………………………………………………… t t n e e r c m e u S c c Do a iT ial M t n e id f n 9. Spare Parts List ………………………………………………………………………………….…..…... o C 98 99 104 106 112 114 116 118 120 122 124 127 129 131 133 135 137 10. System Exploded View ……………………………………………………………………………...….. 148 11. Circuit Diagram ……………………………………………………………………………………….... 149 12. Reference Material …………………………………………………………………………………..…. 183 2 8050D N/B Maintenance 1. Engineer Hardware Specification 1.1 Introduce The MiTAC 8050D model is designed for Intel Banias processor with 400MHz FSB with Micro-FCPGA package. It can support Banias 1.5G ~ 1.9GHz/Dothan 2.0GHz and above. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has standard hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface (ACPI) 2.0. It also provides easy configuration through CMOS setup, which is built in system BIOS software and can be pop-up by pressing F2 key at system start up or warm reset. System also provides icon LEDs to display system status, such as AC Power indicator, Battery Power indicator, Battery status indicator, HDD,CD-ROM, NUM LOCK, CAP LOCK, SCROLL LOCK, RF on/off Card Reader indicator. It also equipped with LAN, 56K Fax MODEM, 3 USB port, S-Video and audio line in/out , external microphone function. The memory subsystem supports two expansion DDR SDRAM slot with unbuffered PC1600/PC2100 DDRSDRAM. The Montara-GME GMCH Host Memory Controller integrates a high performance host interface for Intel Banias processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, Digital Video port (DVOB & DVOC) interface, and Intel Hub interface Technology connecting with Intel 82801DBM ICH4-M. The Intel ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio Controller with AC97 interface, the Ethernet includes a 32-bit PCI controller, the IDE Master/Slave controllers, and Intel Hub interface technology. 3 8050D N/B Maintenance The MOBILITY M10 provides one of the fastest and most advanced 2D, 3D, and multimedia graphics performance for notebooks. It’s architecture introduces the latest achievements in the graphics industry, which enable the use of the progressive new features in upcoming applications, but without compromising performance. ATIs support of support of DirectX® 9 features, highly optimized Open GL® support, and flexible memory configurations allow implementations targeted at the gaming enthusiast, consumer, business and workstation platforms. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C The Realtek RTL8100C(L) is a highly integrated, cost-effective single-chip Fast Ethernet controller that provides 32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications and IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power management Interface (ACPI). The VT6307L is a single chip PCI Host Controller for IEEE 1394-1995 Release 1.0 and IEEE 1394a P2000. It implements the Link and PHY layers for IEEE 1394-1995 High Performance Serial Bus specification release 1.0 and 1394a P2000. It is compliant with 1394 Open HCI 1.0 and 1.1 with DMA engine support for high performance data transfer via a 32-bit bus master PCEI host bus interface. The VT6307L supports 100, 200 and 400 Mbit/sec transmission via an integrated 2-port PHY. The VT6307L services two types of data packets: asynchronous and isochronous(real time). The 1394 link core performs arbitration requesting, packet generation and checking, and bus cycle master operations. It also has root node capability and performs retry operations. The RICOH R5C592 CardBus/Media Reader controller functions as a single slot PCI to Cardbus bridge and also PCI interface smart card and MS/SD/MMC flash card reader. The R5C592 provide one Cardbus slot and all reader interface may operate simultaneously. The CH7011A is a display controller device which accepts a digital graphics input signal, and encodes and 4 8050D N/B Maintenance transmits data to a TV output (analog composite, s-video or RGB). The device accepts data over one 12-bit wide variable voltage data port which supports five different data format including RGB and YcrCb. The TV-Out processor will perform non-interlace to interlace conversion with scaling and flicker filters, and encode the data into any of the NTSC or PAL video standards. The scaling and flicker filter is adaptive and programmable to enable superior text display. Eight graphics resolutions are supported up to 1024 X 768 with full vertical and horizontal underscan capability in all modes. A high accuracy low jitter phase locked loop is integrated to create outstanding video quality. Support is provided for Macrovision and RGB bypass mode which enable driving a VGA CRT with the input data. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C The W83L950D is a high performance micro-controller on-chip supporting functions optimized for embedded control. These include ROM, RAM, four types of timers, a serial communication interface, optional I²C bus interface, host interface, A/D converter, D/A converter, I/O ports, and other functions needed in control system configurations, so that compact, high performance systems can be implemented easily. A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME, Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus mastering IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled power shutdown. Following chapters will have more detail description for each individual sub-systems and functions. 5 8050D N/B Maintenance 1.2 System Overview CPU Mobile Pentium-M Processor 1.5G ~ 1.9GHz/Dothan 2.0GHz and above Thermal spec 35W TDP Core logic VGA Control System BIOS Memory Intel 855GME + ICH4-M chipset t t n e e r c m e u S c c Do a iT ial M t n e id f n o C ATi M10 ST39SF040 DDR RAM : Apacer : 77.11021.460 Samsung 16*16 256MB 1st Apacer : 77.11021.580 Winbond 16*16 256MB 2nd A-DATA : 256MB Video Memory Clock Generator TV IEEE1394 LAN Share memory 32Mb ICS 950812 ATi M10 VT6307L RTL8100C PCMCIA + 4 IN 1 CARD ENE CB710 Audio System AC97 CODEC: Advance Logic, Inc, ALC655 Power Amplifier: TI TPA0212 Modem AC97 Link: MDC (Mobile Daughter Card) Askey: V1456VQL-P1(INT) 6 8050D N/B Maintenance 1.3 System Hardware Parts 1.3.1 Intel Banias Processors in Micro-FCPGA Package Intel Banias Processors with 478 pins Micro-FCPGA package. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C The first Intel mobile processor with the Intel Net Burst micro-architecture which features include hyper-pipelined technology, a rapid execution engine, a 400MHz system, an execution trace cache, advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2). The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition. Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock. Support Enhanced Intel Speed Step technology, which enables real-time dynamic switching of the voltage and frequency between two performance modes. 1.3.2 Clock Generator System frequency synthesizer: ICS950812 Programmable output frequency, divider ratios, output rise/fall time, output skew. Programmable spread percentage for EMI control. Watchdog timer technology to reset system if 7 8050D N/B Maintenance system malfunctions. Programmable watchdog safe frequency. Support I2C Index read/write and block read/write operations. Use external 14.318MHz crystal. Provides standard frequencies and additional 5% and 10% over-clocked frequencies Supports spread spectrum modulation: No spread, Center Spread (±0.35%, ±0.5%,or ±0.75%), or Down Spread (- 0.5%, -1.0%, or -1.5%) t t n e e r c m e u S c c Do a iT ial M t n e 1.3.3 Montara-GME GMCH idIGUI 3D Graphic DDR/SDR Chipset f n o C Offers adjustable PCI early clock via latch inputs Selectable 1X or 2X strength for REF via I2C interface Efficient power management scheme through PD#,CPU_STOP# and PCI_STOP#. Uses external 14.318MHz crystal Stop clocks and functional control available through Montara-GME GMCH IGUI Host Memory Controller integrates a high performance host interface for Intel Banias processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4Xinterface, and Intel®’ I/O Hub architecture INTEL 82801DBM ICH4-M Montara-GME GMCH Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated on-die termination to support Intel Banias processors. Montara-GME GMCH provides a 12-deep In 8 8050D N/B Maintenance -Order-Queue to support maximum outstanding transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the Intel Banias series based PC systems. It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain the bandwidth demand from the integrated GUI or external AGP master, host processor, as well as the multi I/O masters. In addition to integrated GUI, Montara-GME GMCH also can support external AGP slot with AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and mature Intel®’ I/O Hub architecture is incorporated to connect Montara-GME GMCH and INTEL 82801DBM ICH4-M together. Intel®’ I/O Hub architecture is developed into three layers, the Multi-threaded I/O Link Layer delivering 1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O Link layer, the Multi-threaded I/O Link Encoder/Decoder in INTEL 82801DBM ICH4-M to transfer data w/ 533 MB/s bandwidth from/to Multi-threaded I/O Link layer to/from Montara-GME GMCH, and the Multi-threaded I/O Link Encoder/Decoder in Montara-GME GMCH to transfer data w/ 533 MB/s from/to Multi-threaded I/O Link layer to/from INTEL 82801DBM ICH4-M. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C An Unified Memory Controller supporting DDR266 DRAM is incorporated, delivering a high performance data transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The Montara-GME GMCH adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by organizing the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB. 9 8050D N/B Maintenance Features Processor/Host Bus Support Intel® Banias processor 2X Address, 4X data t t n e e r c m e u S c c Do a iT ial M t n e id f n Memory System o C Support host bus Dynamic Bus Inversion (DBI) Supports system bus at 400MT/s (100 MHz) Supports 64-bit host bus addressing 8-deep In-Order-Queue AGTL+ bus driver technology with integrated GTL termination resistors and low voltage operation (1.05V) Supports Enhanced Intel® Speed Step TM Technology (EIST) and Geyserville III Support for DPWR# signal to Banias processor for PSB power management Directly supports one DDR channel, 64-bits wide (72-b with ECC). Supports 200-MHz and 266-MHz DDR devices with max of 2 Double-Sided SO-DIMMs(4 rows populated) with unbuffered PC1600/PC2100 DDR(with ECC). Supports 128-Mb, 256-Mb and 512-Mbit technologies providing maximum capacity of 1-GB with only x 10 8050D N/B Maintenance 16 devices. All supported devices have 4 banks. Supports up to 16 simultaneous open pages. Supports page sizes of 2KB, 4KB, 8KB, and 16KB. Page size is individually selected for every row. UMA support only. t t n System Interrupt e e r c m e u S c c Do a iT ial M t n e id f n o C Supports 8259 and Processor System Bus interrupt delivery mechanism Supports interrupts signaled as upstream Memory Writes from PCI and Hub interface MSI sent to the CPU through the system Bus From IOxAPIC in ICH4-M Provides redirection for upstream interrupts to the System Bus Video Stream Decoder Improved HW Motion Compensation for MPEG2All format decoder (18 ATSC formats) supported Dynamic Bob and Weave support for Video Streams Software DVD at 60 fields/second and 30 frames/second full screen Support for 720x480 pixel resolution DVD quality encoding at low CPU utilization 11 8050D N/B Maintenance Video Overlay Single high quality scalable overlay and second Sprite to support second overlay Multiple overay functionality provided via Arithmetic Stretch Blt Direct YUV from Overlay to TV-out Independent Gamma Correction t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Independent Brightness / Contrast / Saturation Independent Tint / Hue support Destination Color keying Source Chromakeying Maximum source resolution of 1920x1080 pixels Maximum overlay clock of 133 MHz/200 MHz provides a pixel resolution up to 1600x1200@ 60Hz or 1280x1024@ 85 Hz Display Analog Display Support 350 MHz integrated 24-bit RAMDAC that can drive a standard progressive scan analog monitor up to 1800x1350 @ 85 Hz accompanying I2C and DDC channels provided through multiplexed interface hot plug and display support Dual independent pipe with single display support Simultaneous: Same images and native display timings on 12 8050D N/B Maintenance each display device DVO (DVOB) support Digital video out port DVOB with 165-MHz dot clock on 12-bit interface Variety of DVO devices channel t t n e e r c m e u 1.3.4 I/O Controller Hub : INTEL 82801DBM S c c Do a iT ial M t n e id f n o C Compliant with DVI Specification 1.0, thereby providing support for a flat panel up to 2048x1536 pixel resolution, or digital CRT up to 1920x1080 pixel resolution The INTEL 82801DBM ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers, the Audio Controller with AC 97 Interface, the IDE Master/Slave controllers, and Intel®’ I/O Hub architecture. The PCI to LPC Bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O and legacy power management functionalities are integrated as well. The integrated Universal Serial Bus Host Controllers features Dual Independent UHCI Compliant Host controllers with six USB ports delivering 480 Mb/s bandwidth and rich connectivity. Besides, Legacy USB devices as well as over current detection are also implemented. The Integrated AC97 v2.3 compliance Audio Controller that features a 7-channels of audio speaker out and HSP v.90 modem support. Additionally, the AC97 interface supports 4 separate SDATAIN pins that is capable of supporting multiple audio codecs with one separate modem codec. 13 8050D N/B Maintenance The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting PIO mode transfers up to 16 Mbytes/sec and Ultra DMA 33/66/100. It provides two separate data paths for the dual IDE channels that sustain the high data transfer rate in the multitasking environment. INTEL 82801DBM ICH4-M supports 6 PCI masters and complies with PCI 2.2 specification. It also incorporates the legacy system I/O like: two 82C37 compatible DMA controllers, Channels 0-3 are hardwired to 8 bit, three 8254 compatible programmable 16-bit counters channels 5-7, hardwired keyboard controller and PS2 mouse interface(not use in MiTAC 8050 model), Real Time clock with 512Bytes CMOS SRAM and two 82C59 compatible Interrupt controllers. Besides, the I/O APIC managing up to 14 interrupts with both Serial and FSB interrupt delivery modes is supported. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2 compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use logic for specific application. In addition, the INTEL 82801DBM ICH4-M supports Deeper Sleep power state for Intel Mobile processor. A high bandwidth and mature Intel®’ I/O Hub architecture is incorporated to connect Montara and Intel 82801DBM ICH4-M Hub interface together. Intel®’ I/O Hub architecture is developed 1.3.5 VGA Control Introducing MOBILITY M10 14 8050D N/B Maintenance The MOBILITY M10 provides one of the fastest and most advanced 2D, 3D, and multimedia graphics performance for notebooks. Its architecture introduces the latest achievements in the graphics industry, which enable the use of the progressive new features in upcoming applications, but without compromising performance. ATI’s support of DirectX® 9 features, highly optimized OpenGL® support, and flexible memory configurations allow implementations targeted at the gaming enthusiast, consumer, business and workstation platforms. t t n e e r c m e u S c c Do a iT ial M t n e MOOTHVISION™ 2.0 — Flexible Anti-Aliasing and Anisotropic Filtering d i f n o C SMARTSHADER™ 2.0 — Advanced Shader Technology Provides complete hardware-accelerated support for the new DirectX® 9 programmable shader model, enabling more complex and realistic texture and lighting effects than ever before. Significant improvement over first-generation shaders introduced in DirectX® 8, with a much more powerful and intuitive instruction set. Offers full support for this feature in OpenGL® applications. 2x/4x/6x full-scene anti-aliasing modes Adaptive algorithm with programmable sample patterns 2x/4x/8x/16x anisotropic filtering modes Adaptive algorithm with bi-linear (performance) and tri-linear (quality) options 15 8050D N/B Maintenance High Performance Memory Support Incorporates support for DDR SDRAM/SGRAM. Features key items from ATI’s third generation HYPER Z™ III technology that conserves memory bandwidth for improved performance in demanding applications. t t n e e r c m e u S c c Do a iT ial M t n e id f n o VIDEO Acceleration C Dual Display Support Leading-edge technology, fully optimized with HYDRA VISION™, flexibly supports multiple combinations of notebook LCD, traditional CRT monitors, flat panel displays and TV. Features Dual Channel DVI support. 230MHz LVDS transmitter supports LCD panels up to QXGA (2048x1536) resolution. Integrated 165MHz TMDS transmitter supports external flat panels up to UXGA (1600x1200) resolution. High performance DAC speeds of 400MHz. Features in Detail M10 allows the integration of industry leading digital video features, including advanced de-interlacing algorithms for unprecedented video quality and integrated digital TV decode capability. Includes programmable,independent gamma control for the video overlay. New FULLSTREAM™ technology removes blocky artifacts from streaming and Internet video and 16 8050D N/B Maintenance provides sharper image quality. Integrated general purpose xDCT engine (capable of performing both forward and inverse discrete cosine transform) and motion compensation (MC) support for the acceleration of MPEG encoding and decoding as well as DV (digital video) encoding and decoding. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 1.3.6 CardBus: CB710 Features 3.3V operation with 5V tolerant 208-pin LQFP / 209-ball LFBGA package for CB710 328-ball LFBGA package for CB720 PCI Interface compliant with PCI Local Bus Specification, Revision 2.2 PCI Bus Power Management Interface Specification, Revision 1.1 PCI Mobile Design Guide, Version 1.1 Advanced Configuration and Power Interface Specification, Revision 1.0 CardBus Interface Compliant with PC Card Standard 8.0Support Standardized Zoomed Video Register Model 17 8050D N/B Maintenance Support CardBay PC card interface Smart Card Interface Compliant with PC/SC Specification 1.0 Support ISO7816 T=0 and T=1 asynchronous communication protocols Two power enable pins to support 5V and 3V smart cards t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Support programmable card clock frequencies Programmable F and D parameters to support different data rates One traffic LED pin. Secure Digital Interface Compliant with SD Memory Card Specification Version 1.0 Support 4 parallel data lines Has an optional reference clock source to control the operating clock frequency of SD card Up to 10MByte/sec Read/Write rate when the optional reference clock source is used Contains 16 Bytes of data buffer to regulate the data flow between PCI interface and the SD card interface Support Write Protect Switch Support Card Detect either by DAT3 or by dedicated Card Detect Switch One Traffic LED pin 18 8050D N/B Maintenance One power enable pin. Memory Stick Interface Compliant with Memory Stick Standard Format Specification Version 1.3 Has an optional reference clock source to control the operating clock frequency of Memory Stick Up to 2.5MByte/sec Read/Write rate when the optional reference clock source is used Stick interface t t n e e r c m e u S c c Do a iT ial M t n e id f n o C One Traffic LED pin One power enable pin Smart Media Interface One traffic LED pin Interrupt configuration Supports CLKRUN# protocol Supports SUSPEND# Supports D3STATE# Supports Zoomed Video port. Power Switch Interface Misc Control Logic 19 8050D N/B Maintenance Supports socket activity LED Supports 12 GPIOs and GPE# Supports PCI LOCK t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 1.3.7 AC’97 AUDIO SYSTEM: Advance Logic, Inc, ALC655 The ALC655 is a 16-bit, full duplex AC'97 2.3 compatible six channels audio CODEC designed for PC multimedia systems,including host/soft audio and AMR/CNR based designs. The ALC655 incorporates proprietary converter technology to meet performance requirements on PC99/2001 systems. The ALC655 CODEC provides three pairs of stereo outputs with 5-Bitvolume controls, a mono output, and multiple stereo and mono inputs, along with flexible mixing, gain and mute functions to provide a complete integrated audio solution for PCs. The digital interface circuitry of the ALC655 CODEC operates from a 3.3V power supply for use in notebook and PC applications. The ALC655 integrates 50mW/20ohm headset audio amplifiers at Front-Out and Surr-Out, built-in 14.318M 24.576MHz PLL and PCBEEP generator, those can save BOM costs. The ALC655also supports the S/PDIF input and output function, which can offer easy connection of PCs to consumer electronic products, such as AC3 decoder/speaker and mini disk devices. ALC655 supports host/soft audio from Intel ICHx chipsets as well as audio controller based VIA/SIS/ALI/AMD/nVIDIA/ATI chipset. Bundled Windows series drivers (Win XP/ME/2000/98/NT), EAX/Direct Sound 3D/ I3DL2/ A3D compatible sound effect utilities (supporting Karaoke, 26-kind of environment sound emulation,10-band equalizer), HRTF 3D positional audio and Sensaura™ 3D (optional) provide an excellent entertainment package and game experience for PC users. Besides, ALC655 includes Realtek’s impedance sensing techniques that makes device load on outputs and inputs can be detected. 20 8050D N/B Maintenance Meets performance requirements for audio on PC99/2001 systems Meets Microsoft WHQL/WLP 2.0 audio requirements 16-bit Stereo full-duplex CODEC with 48KHz sampling rate Compliant with AC’97 2.3 specifications 14.318MHz- 24.576MHz PLL to save crystal t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 12.288MHz BITCLK input can be consumed Integrated PCBEEP generator to save buzzer Interrupt capability Three analog line-level stereo inputs with 5-bit volume control: LINE_IN, CD, AUX High quality differential CD input Two analog line-level mono input: PCBEEP,PHONE-IN Two software selectable MIC inputs applications (software selectable) Boost preamplifier for MIC input 50mW/20 amplifier External Amplifier Power Down (EAPD) capability Power management and enhanced power saving features. Stereo MIC record for AEC/BF application 21 8050D N/B Maintenance Supports Power Off CD function Adjustable VREFOUT control Supports double sampling rate (96KHz) of DVD audio playback Support 48KHz of S/PDIF output is compliant with AC’97 rev2.3 specification Power support: Digital: 3.3V; Analog: 3.3V/5V t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 1.3.8 MDC:PCTEL MODEM DAUGHTER CARD PCT2303W (ASKEY V1456VQL-P1) The PCT2303W chipset is designed to meet the demand of this emerging worldwide AMR/MDC market. The combination of PC-TEL’s well proven PCT2303W chipset and the HSP56TM MR software modem driver allows systems manufactures to implement modem functions in PCs at a lower bill of materials (BOM) while maintaining higher system performance. PC-TEL has streamlined the traditional modem into the Host Signal Processing (HSP) solution. Operating with the Pentium class processors, HSP becomes part of the host computer’s system software. It requires less power to operate and less physical space than standard modem solutions. PC-TEL’s HSP modem is an easily integrated, cost-effective communications solution that is flexible enough to carry you into the future. The PCT2303W chip set is an integrated direct access arrangement (DAA) and Codec that provides a programmable line interface to meet international telephone line requirements. The PCT2303W chip set is available in two 16-pin small outline packages (AC’97 interface on PCT303A and phone-line interface on PCT303W). The chip set eliminates the need for an AFE, an isolation transformer, relays, opto-isolators, and 2-to 22 8050D N/B Maintenance 4-wire hybrid. The PCT2303W chip set dramatically reduces the number of discrete components and cost required to achieve compliance with international regulatory requirements. The PCT2303W complies with AC’97 Interface specification Rev. 2.1. The chip set is fully programmable to meet world-wide telephone line interface requirements including those described by CTR21, NET4, JATE, FCC, and various country-specific PTT specifications. The programmable parameters of the PCT2303W chip set include AC termination, DC termination, ringer impedance, and ringer threshold. The PCT2303W chip set has been designed to meet stringent world-wide requirements for out-of-band energy, billing-tone immunity, lightning surges, and safety requirements. Features t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Virtual com port with a DTE throughout up to 460.8Kbps. G3 Fax compatible Auto dial and auto answer Ring detection Codec/DAA Features AC97 2.1 compliant 86dB dynamic range TX/RX paths 2-4-wire hybrid Integrated ring detector 23 8050D N/B Maintenance High voltage isolation of 4000V Support for “Caller ID” Compliant with FCC Part68, CTR21, Net4 and JATE Low power standby Low profile SOIC package 16 pins 10x3x1.55mm t t n e e r c m e u S c c Do a iT ial M t Standard Features n e id f n o C Low power consumption 10mA @ 3.3V operation 1mA @ 3.3V power down Integrated modem codec Data ITU-T V.90 (56Kbps), V.34 (4.8Kbps TO 33.6 Kbps), V.32 bits (4.8Kbps to 14.4Kbps), V.22 bits (1.2 bps to 2.4 Kbps), V.21 and Bell 103 and 212A(300 to 1200 bps) modulation protocol. Data Compression ITU-T V.42bis MNP Class 5 Error Correction ITU-T V.42 LAPM MNP 2-4 24 8050D N/B Maintenance Fax ITU-T V. 17, V.29, V.27ter, V.21, Channel 2, Group 3, EIA Class I t t n e e r c m e u S c c Do a iT ial M t n e 1.3.9 IEEE1394 VT6307L f(Option) id n o 1.3.9.1 Overview C The VT6307 IEEE 1394 OHCI Host Controller provides high performance serial connectivity. It implements the Link and Phy layers for IEEE 1394-1995 High Performance Serial Bus specification release 1.0 and 1394a-2000. It is compliant with 1394 Open HCI 1.0 and 1.1 with DMA engine support for high performance data transfer via a 32-bit bus master PCI host bus interface. The VT6307 supports 100, 200 and 400 M bit/sec transmission via an 25 8050D N/B Maintenance integrated 2-port PHY. The VT6307 services two types of data packets: asynchronous and isochronous (real time). The 1394 link core performs arbitration requesting, packet generation and checking, and bus cycle master operations. It also has root node capability and performs retry operations. The VT6307 is ready to provide industry-standard IEEE 1394 peripheral connections for desktop and mobile PC platforms. Support for the VT6307 is built into Microsoft Windows 98, Windows ME, Windows 2000, and Windows XP. 1.3.9.2 Features t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 32 bit CRC generator and checker for receive and transmit data On-chip isochronous and asynchronous receive and transmit FIFOs for packets (2K for general receive plus 2K for isochronous transmit plus 2K for asynchronous transmit) 8 isochronous transmit contexts 4 isochronous receive context 3-deep physical post-write queue 2-deep physical response queue Dual buffer mode enhancements Skip Processing enhancements Block Read Request handling Ack_tardy processing 26 8050D N/B Maintenance 1.3.10 System Flash Memory (BIOS) Firmware Hub for Intel® 810, 810E, 815, 815E,815EP, 820, 840, 850 Chipsets Flexible Erase Capability Uniform 4 K Byte Sectors t t n e e r c m e u S c c Do a iT ial M t n Single 3.0-3.6V Read and Writee Operations d i f Superior Reliability n o C Uniform 16 K Byte overlay blocks for SST49LF002A Uniform 64 K Byte overlay blocks for SST49LF004ATop boot block protection 16 K Byte for SST49LF002A 64 K Byte for SST49LF004A Chip-Erase for PP Mode Firmware Hub Hardware Interface Mode 5-signal communication interface supporting byte Read and Write 33 MHz clock frequency operation WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot Block 27 8050D N/B Maintenance Block Locking Register for all blocks Standard SDP Command Set Data# Polling and Toggle Bit for End-of-Write detection 5 GPI pins for system design flexibility 4 ID pins for multi-chip selection t t n e e r c m 1.3.11 Memory System e u S c c (x64)D200-Pin o DDR SDRAM SODIMM a 1.3.11.1 64MB, 128MB, 256MB, 512MB iT ial M t n e id f n o C JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM) Utilizes 200 Mb/s and 266 Mb/s DDR SDRAM components 64MB (8 Meg x 64 [H]); 128MB (16 Meg x 64, [H] and [HD]); 256MB (32 Meg x 64 [HD]); Meg x 64 [HD]) 512MB (64 VDD= VDDQ= +2.5V ±0.2V VDDSPD = +2.2V to +5.5V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge 28 8050D N/B Maintenance DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bidirectional data strobe (DQS) transmitted/received with data—i.e.,source-synchronous data capture Differential clock inputs (CK and CK# - can be multiple clocks, CK0/CK0#, CK1/CK1#, etc.) Four internal device banks for concurrent operation t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Selectable burst lengths: 2, 4, or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15.6µs (MT4VDDT864H, MT8VDDT1664HD), 7.8125µs (MT4VDDT1664H, MT8VDDT3264HD, MT8VDDT6464HD) maximum average periodic refresh interval Serial Presence Detect (SPD) with EEPROM Fast data transfer rates PC2100 or PC1600 Selectable READ CAS latency for maximum compatibility Gold-plated edge contacts 29 8050D N/B Maintenance 1.3.12 PHY: 3.3-V 10Base-T/100Base-TX Integrated PHY Ceiver ,The ICS1893 is a low-power, physical-layer device (PHY) General The Realtek RTL8100C(L) is a highly integrated, cost-effective single-chip Fast Ethernet controller that provides 32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications and IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power management Interface (ACPI), PCI power management for modern operating systems that are capable of Operating System Directed Power Management (OSPM) to achieve the most efficient power management possible. The RTL8100C(L) does not support CardBus mode as the RTL8139C does. In addition to the ACPI feature, the RTL8100C(L) also supports remote wake-up(including AMD Magic Packet, LinkChg, and Microsoft® wake-up frame) in both ACPI and APM environments. The RTL8100C(L) is capable of performing an internal reset through the application of auxiliary power. When auxiliary power is applied and the main power remains off, the RTL8100C(L) is ready and waiting for the Magic Packet or Link Change to wake the system up. Also, the LWAKE pin provides 4 different output signals including active high, active low, positive pulse, and negative pulse. The versatility of the RTL8100C(L) LWAKE pin provides motherboards with Wake-On-LAN (WOL) functionality. The RTL8100C(L) also supports Analog Auto-Power-down, that is, the analog part of the RTL8100C(L) can be shut down temporarily according to user requirements or when the RTL8100C(L) is in a power down state with the wakeup function disabled. In addition, when the analog part is shut down and the Isolate B pin is low (i.e. the main power is off), then both the analog and digital parts stop functioning and the power consumption of the RTL8100C(L) will be negligible. The RTL8100C(L) also supports an auxiliary power auto-detect function, and will auto-configure related bits of their own PCI power management registers in PCI configuration space. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 30 8050D N/B Maintenance 128 pin QFP/LQFP Integrated Fast Ethernet MAC, Physical chip and transceiver in one chip 10 Mb/s and 100 Mb/s operation Supports 10 Mb/s and 100 Mb/s N-way Auto-negotiation operation PCI local bus single-chip Fast Ethernet controller t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Compliant to PCI Revision 2.2 Supports PCI clock 16.75MHz-40MHz Supports PCI target fast back-to-back transaction Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of RTL8100C(L)'s operational registers Supports PCI VPD (Vital Product Data) Supports ACPI, PCI power management Supports 25MHz crystal or 25MHz OSC as the internal clock source. The frequency deviation of either crystal or OSC must be within 50 PPM. Compliant to PC99/PC2001 standard Supports Wake-On-LAN function and remote wake-up (Magic Packet*, LinkChg and Microsoft® wake-up frame) 31 8050D N/B Maintenance Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, and negative pulse) Supports auxiliary power-on internal reset, to be ready for remote wake-up when main power still remains off Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI configuration space. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Includes a programmable, PCI burst size and early Tx/Rx threshold. Supports a 32-bit general-purpose timer with the external PCI clock as clock source, to generate timerinterrupt Contains two large (2Kbyte) independent receive and transmit FIFOs Advanced power saving mode when LAN function or wakeup function is not used Uses 93C46 (64*16-bit EEPROM) to store resource configuration, ID parameter, and VPD data. Supports LED pins for various network activity indications Supports loop back capability Half/Full duplex capability Supports Full Duplex Flow Control (IEEE 802.3x) 32 8050D N/B Maintenance 1.3.13 Keyboard System: Winbond W83L950D The Winbond Keyboard controller architecture consists of a Turbo 51 core controller surrounded by various registers, nine general purpose I/O port, 2k+256 bytes of RAM, four timer/counters, dual serial ports, 40K MTPROM that is divided into four banks, two SMBus interface for master and slave, Support 4 PWM channels, 2 D-A and 8 A-D converters. 2 8051 uC based t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Keyboard Controller Embedded Controller Supply embedded programmable flash memory (internal ROM size: 40KB) and RAM size is 2 KB. Support 4 Timer (8 bit) signal with 3 prescalers. Support 2 PWM channels, 2 D-A and 8 A-D converters. Reduce Firmware burden by Hardware PS/2 decoding Support 72 useful GPIOs totally Support Flash utility for on board re-flash Support ACPI Hardware fast Gate A20 with software programmable 33 8050D N/B Maintenance 1.4 Other Functions 1.4.1 Hot Key Function Keys Combination Feature Fn + F1 Power down Meaning t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Mini PCI power down Fn + F2 Reserve Fn + F3 Volume Down Fn + F4 Volume Up Fn + F5 LCD/external CRT switching Rotate display mode in LCD only, CRT only, and simultaneously display. Fn + F6 Brightness down Decreases the LCD brightness Fn + F7 Brightness up Increases the LCD brightness Fn + F10 Battery Low Beep On/Off Battery Low Beep Fn + F11 Panel Off/On Toggle Panel on/off Fn + F12 Suspend to DRAM / HDD Force the computer into either Suspend to HDD or Suspend to DRAM mode depending on BIOS Setup. 34 8050D N/B Maintenance 1.4.2 Power on/off/suspend/resume button APM mode At APM mode, Power button is on/off system power. t t n e e r c m e u S c c Do a iT ial M t n 1.4.3 Cover Switch e id f n o C ACPI mode At ACPI mode. Windows power management control panel set power button behavior.You could set “standby”, “power off” or “hibernate”(must enable hibernate function in power Management) to power button function. Continue pushing power button over 4 seconds will force system off at ACPI mode. System automatically provides power saving by monitoring Cover Switch. It will save battery power and prolong the usage time when user closes the notebook cover. At ACPI mode there are four functions to be chosen at windows power management control panel. None Standby 35 8050D N/B Maintenance Off Hibernate (must enable hibernate function in power management) 1.4.4 LED Indicators t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Three LED indicators at front side: From left to right that indicate BATTERY POWER, BATTERY STATUS and AC POWER AC POWER: This LED lights green when the notebook was powered by AC power line, Flashes (on 1 second, off 1 second) when entered suspend to RAM state with AC powered. The LED is off when the notebook is in power off state or powered by battery. BATTERY POWER: This LED lights green when the notebook is being powered by Battery, and flashes (on 1 second, off 1 second) when entered suspend to RAM state with AC powered. The LED is off when the notebook is in power off state or powered by AC adapter. 36 8050D N/B Maintenance BATTERY STATUS: During normal operation, this LED stays off as long as the battery is charged. When the battery charge drops to 10% of capacity, the LED lights red, flashes per 1 second and beeps per 2 second. When AC is connected, this indicator glows green if the battery pack is fully charged or orange (amber) if the battery is being charged. AC POWER: t t n e e r c m e u S c c Do a iT ial M t n e Seven LED indicators: id f n o C This LED lights green when AC is powering the notebook, and flash (on 1 second, off 1 second) when Suspend to RAM no matter using AC power or Battery power. The LED is off when the notebook is off or powered by battery. BATTERY POWER: This LED lights green when the notebook is being powered by Battery, and flash (on 1 second, off 1 second) when Battery is low. The LED is off when the notebook is off or powered by AC adaptor. System has seven status LED indicators at front side which to display system activity. From left to right that indicate HARD DISK, CD-ROM, NUM LOCK, CAPS LOCK, SCROLL LOCK, Mini PCI and Card Reader. 37 8050D N/B Maintenance 1.4.5 Battery status Battery Warning System also provides Battery capacity monitoring and gives users a warning signal to alarm they to store data before battery dead. This function also protects system from mal-function while battery capacity is low. t t n e e r c m e u S c c Do Battery Low State a iT ial M t n e Battery Dead State id f n o C Battery Warning: Capacity below 10%, Battery Capacity LED flashes per second, system beeps per 2 seconds. System will Suspend to HDD after 2 Minutes to protect users data. After Battery Warning State, and battery capacity is below 5%, system will generate beep sound for twice per second. When the battery voltage level reaches 11.5 volts, system will shut down automatically in order to extend the battery packs' life. 38 8050D N/B Maintenance 1.4.6 Fan power on/off management FAN is controlled by W83L950D embedded controller-using ADT7460 to sense CPU temperature and PWM control fan speed. Fan speed is depended on CPU temperature. Higher CPU temperature faster Fan Speed. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 1.4.7 CMOS Battery CR2032 3V 220mAh lithium battery When AC in or system main battery inside, CMOS battery will consume no power AC or main battery not exists, CMOS battery life at less (220mAh/5.8uA) 4 years. 1.4.8 I/O Port One Power Supply Jack. One External CRT Connector For CRT Display Supports three USB port for all USB devices. One MODEM RJ-11 phone jack for PSTN line One RJ-45 for LAN. One IEEE1394 port 39 8050D N/B Maintenance Headphone Out Jack. Microphone Input Jack. Line in Jack t t n e e r c m e u S c c o a 1.5 Power management D iT ial M t n e id f n o C 1.4.9 Battery current limit and learning. Implanted H/W current limit and battery learning circuit to enhance protection of battery. The 8050D system has built in several power saving modes to prolong the battery usage for mobile purpose. User can enable and configure different degrees of power management modes via ROM CMOS setup (booting by pressing F2 key). Following are the descriptions of the power management modes supported. 1.5.1 System Management Mode Full on mode In this mode, each device is running with the maximal speed. CPU clock is up to its maximum. 40 8050D N/B Maintenance Doze Mode In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling. This can save battery power without loosing much computing capability. The CPU power consumption and temperature is lower in this mode. t t n e e r c m e u S c c Do a iT ial M t n e id Suspend to DRAM f n o C Standby mode For more power saving, it turns of the peripheral components. In this mode, the following is the status of each device: -- CPU: Stop grant -- LCD: backlight off -- HDD: spin down The most chipset of the system is entering power down mode for more power saving. In this mode, the following is the status of each device: Suspend to DRAM CPU: off Intel 855GME: Partial off 41 8050D N/B Maintenance VGA: Suspend PCMCIA: Suspend Audio: off SDRAM: self refresh t t n e e r c m e u S c c Do a iT ial M functions t 1.5.2 Other power management n e id HDD & Video access f n o C Suspend to HDD All devices are stopped clock and power-down System status is saved in HDD All system status will be restored when powered on again System has the ability to monitor video and hard disk activity. User can enable monitoring function for video and/or hard disk individually. When there is no video and/or hard disk activity, system will enter next PMU state depending on the application. When the VGA activity monitoring is enabled, the performance of the system will have some impact. 42 8050D N/B Maintenance 2. System View and Disassembly 2.1 System View 2.1.1 Front View t t n e e r c m e u S c c Do a iT ial M t n e 2.1.2 Left-side View id f n o C 1394 Jack Line Out Connector Line In Connector MIC In Connector SD Card Slot Top Cover Latch VGA Port S-Video Port USB Ports *1 Ventilation Openings RJ-11 Connector RJ-45 Connector PCMCIA Card Socket 43 8050D N/B Maintenance 2.1.3 Right-side View CD-ROM/DVD-ROM Drive Kensington Lock 2.1.4 Rear View Kensington Lock Power Connector USB Port*2 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 44 8050D N/B Maintenance 2.1.5 Bottom View Hard Disk Drive DDR SDRAM Card Wireless Card CPU t t n e e r c m e u S c c Do a 2.1.6 Top-open View iT ial M t n e d i f n o C Battery Park Stereo Speaker Set LCD Screen Power Button Stereo Speaker Set Keyboard Device LED Indicators Touch Pad Hard Disk Drive Indicator Battery Power Charging Indicator Power Indicator 45 8050D N/B Maintenance 2.2 System Disassembly The section discusses at length each major component for disassembly/reassembly and show corresponding illustrations.Use the chart below to determine the disassembly sequence for removing components from the notebook. NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the notebook is not turned on or connected to AC power. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 2.2.1 Battery Pack 2.2.2 Keyboard Modular Components 2.2.3 CPU 2.2.4 HDD Module 2.2.5 DVD-ROM Drive 2.2.6 Wireless Card NOTEBOOK 2.2.7 Modem Card 2.2.8 DDR-SDRAM 2.2.9 LCD Assembly LCD Assembly Components 2.2.10 LCD Panel 2.2.11 Inverter Board 2.2.12 System Board Base Unit Components 2.2.13 Touch Pad 46 8050D N/B Maintenance 2.2.1 Battery Pack Disassembly 1. Carefully put the notebook upside down. 2. Slide the two release lever outwards to the “unlock” ( the compartment (). (Figure 2-1) ) position (), while take the battery pack out of t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-1 Remove the battery pack Reassembly 1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you hear a clicking sound. 2. Slide the release lever to the “lock” ( ) position. 47 8050D N/B Maintenance 2.2.2 Keyboard Disassembly 1. Remove the battery pack. (Refer to section 2.2.1 Disassembly) 2. Open the top cover. 3. Loosen the four latches locking the keyboard. (Figure 2-2) 4. Slightly lift up the keyboard and disconnect the cable from the mother board, then separate the keyboard. (Figure 2-3) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-2 Loosen the four latches Figure 2-3 Disconnect the cable Reassembly 1. Reconnect the keyboard cable and fit the keyboard back into place with four latches. 2. Replace the battery pack. (Refer to section 2.2.1 reassembly) 48 8050D N/B Maintenance 2.2.3 CPU Disassembly 1. Remove the battery pack. (Refer to section 2.2.1 Disassembly) 2. Remove three screws fastening the heatsink cover. (Figure 2-4) 3. Remove three spring screws that secure the heatsink upon the CPU and disconnect the fan’s power cord from system board. (Figure 2-5) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-4 Remove three screws Figure 2-5 Free the heatsink 49 8050D N/B Maintenance 4. To remove the existing CPU, Loosen the screw by a flat screwdriver,upraise the CPU socket to unlock the CPU. (Figure 2-6) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-6 Remove the CPU Reassembly 1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pins into the holes. Tighten the screw by a flat screwdriver to locking the CPU. 2. Connect the fan’s power cord to the system board, fit the heatsink upon the CPU and secure with three spring screws. 3. Replace the CPU cover and secure with three screws. 4. Replace the battery pack. (Refer to section 2.2.1 reassembly) 50 8050D N/B Maintenance 2.2.4 HDD Module Disassembly 1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly) 2. Remove two screws fastening the HDD compartment cover. (Figure 2-7) 3. Remove the one screw and slide the HDD module out of the compartment. (Figure 2-8) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-7 Remove the HDD compartment cover Figure 2-8 Remove HDD module 51 8050D N/B Maintenance 4. Remove four screws to separate the hard disk drive from the bracket, remove four screws. (Figure 2-9) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-9 Remove hard disk drive Reassembly 1. Attach the bracket to hard disk drive and secure with four screws. 2. Slide the HDD module into the compartment and secure with one screw. 3. Place the HDD compartment cover and secure with two screws. 4. Replace the battery pack. (Refer to section 2.2.1 reassembly) 52 8050D N/B Maintenance 2.2.5 CD/DVD-ROM Drive Disassembly 1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly) 2. Remove one screw fastening the CD/DVD-ROM drive. (Figure 2-10) 3. Push firmly to release the tray. Then gently pull out the CD/DVD-ROM drive by holding the tray that pops out. (Figure 2-11) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-10 Remove one screw Figure 2-11 Remove the CD/DVDROM drive Reassembly 1. Push the CD/DVD-ROM drive into the compartment and secure with one screw. 2. Replace the battery pack. (Refer to section 2.2.1 reassembly) 53 8050D N/B Maintenance 2.2.6 Wireless Card Disassembly 1. Carefully put the notebook upside down. Remove the battery pack. (Refer to sections 2.2.1 Disassembly) 2. Remove the two screws fastening the Mini PCI compartment cover. (Figure 2-12) 3. Disconnect the wireless card’s antennae first (). Then pull the retaining clips outwards () and remove the wireless card (). (Figure 2-13) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-12 Remove two screws Reassembly Figure 2-13 Remove the Wireless card 1. To install the wireless card, match the wireless card 's notched part with the socket's projected part and firmly insert it into the socket. Then push down until the retaining clips lock the wireless card into position. Then sure that the antennae fully populated. 2. Tighten the screws to secure the wireless card compartment cover to the housing. 3. Replace the battery pack. (Refer to section 2.2.1 reassembly) 54 8050D N/B Maintenance 2.2.7 Modem Card Disassembly 1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.2.1 Disassembly) 2. Remove two screws fastening modem card’s compartment cover. (Refer to steps 1-2 of section 2.2.6 Disassembly) 3. Remove two screws fastening the modem card. (Figure 2-14) 4. Lift up the modem card and disconnect the cord. (Figure 2-15) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-14 Remove two screws Reassembly Figure 2-15 Disconnect the cord 1. Reconnect the cord and fit the modem card. 2. Fasten the modem card by two screws. 3. Replace the modem card’s compartment cover by two screws. (Refer to step 2 of section 2.2.6 reassembly). 4. Replace the battery pack. (Refer to section 2.2.1 reassembly) 55 8050D N/B Maintenance 2.2.8 DDR-SDRAM Disassembly 1. Carefully put the notebook upside down. And remove the battery pack. (See section 2.2.1 disassembly) 2. Remove two screws fastening the DDR compartment cover to access the SO-DIMM socket. (Figure 2-16) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-16 Remove the cover Figure 2-17 Remove the SO-DIMM 3. Pull the retaining clips outwards () and remove the SO-DIMM (). (Figure 2-17) Reassembly 1. To install the DDR, match the DDR's notched part with the socket's projected part and firmly insert the SO-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the DDR into position. 2. Replace two screws to fasten the DDR compartment cover. 3. Replace the battery pack. (See section 2.2.1 reassembly) 56 8050D N/B Maintenance 2.2.9 LCD ASSY Disassembly 1. Remove the battery pack, keyboard,CPU, hard disk drive, CD/DVD-drive and wireless card. (See sections 2.2.1,2.2.2, 2.2.3, 2.2.4, 2.2.5 and 2.2.6 Disassembly) 2. Remove the nineteen screws on the bottom of notebook. (Figure 2-18) 3. Remove the four screws that secure the hinge cover. (Figure 2-19) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-18 Remove nineteen screws Figure 2-19 Remove four screws 57 8050D N/B Maintenance 4. Remove the two screws and disconnect the touch pad’s cable, then free the top cover.(Figure 2-20) 5. Remove the two hinge covers. (Figure 2-21) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-20 Free the Top cover Figure 2-21 Remove the hinge covers 58 8050D N/B Maintenance 6. Disconnect the two cables and remove the four screws. (Figure 2-22) 7. Remove the eight screws. (Figure 2-23) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-22 Remove the four screws and Disconnect the two cables Figure 2-23 Remove the eight screws 59 8050D N/B Maintenance 8. Carefully pull the antenna wires out. Now you can lift up the LCD ASSY from base unit. (Figure 2-24) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-24 Free the LCD ASSY Reassembly 1. Attach the LCD assembly to the base unit and secure with four screws. 2. Rip the antenna wires back into Min-PCI compartment. 3. Reconnect the two cables to the system board. Screw the hinge covers by two screws. 4. Replace the shield and secure with eight screws. 5. Replace the top cover and secure with two screws. And reconnect the touch pad’s cable. 6. Upside down the notebook. secure the housing by nineteen screws and secure two screws in the rear. 7. Replace the Wireless card, CD/DVD-ROM, hard disk drive, CPU, keyboard and battery pack. (Refer to sections 2.2.6, 2.2.5, 2.2.4, 2.2.3, 2.2.2 and 2.2.1 reassembly) 60 8050D N/B Maintenance 2.2.10 LCD Panel Disassembly 1. Remove the battery, keyboard, hard disk drive, CD/DVD-ROM drive and LCD assembly. (Refer to section 2.2.1, 2.2.2, 2.2.4, 2.2.5 and 2.2.9 Disassembly) 2. Remove the two rubber pads and two screws on the corners of the panel. (Figure 2-25) 3. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out. Repeat the process until the cover is completely separated from the housing. 4. Remove the twelve screws and disconnect the cable. (Figure 2-26) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-25 Remove LCD cover Figure 2-26 Remove twelve screws and disconnect the cable 61 8050D N/B Maintenance 5. Remove the six screws that secure the LCD bracket. (Figure 2-27) 6. Disconnect the cable to free the LCD panel. (Figure 2-28) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-27 Remove the six screws Reassembly Figure 2-28 Free the LCD panel 1. Replace the cable to the LCD. 2. Attach the LCD panel’s bracket back to LCD panel and secure with six screws. 3. Replace the LCD panel into LCD housing.and reconnect two cables to inverter board and secure with two screws. 4. Fasten the LCD panel by ten screws. 5. Fit the LCD cover and secure with two screws and rubber pads. 6. Replace the LCD assembly, CD/DVD-ROM drive, hard disk drive, keyboard, battery pack. (See sections 2.2.9, 2.2.5, 2.2.4, 2.2.2, and 2.2.1 reassembly) 62 8050D N/B Maintenance 2.2.11 Inverter Board Disassembly 1. Remove the battery, keyboard, hard disk drive, CD/DVD-ROM drive and LCD assembly. (Refer to section 2.2.1, 2.2.2, 2.2.4, 2.2.5 and 2.2.9 Disassembly) 2. Remove the LCD cover and LCD panel. (Refer to the steps 1-4 of section 2.2.10 Disassembly ) 3. Remove the one screw fastening the inverter board and disconnect the cable, Then free the inverter board. (Figure 2-29) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-29 Free the inverter board Reassembly 1. Reconnect the cable. Fit the inverter board back into place and secure with one screw. 2. Replace the LCD Panel and LCD cover. (Refer to section 2.2.10 reassembly) 3. Replace the LCD assembly. (Refer to section 2.2.9 reassembly) 4. Replace the CD/DVD-ROM drive, hard disk drive, keyboard and battery pack. (Refer to sections 2.2.5, 2.2.4, 2.2.2 and 2.2.1 reassembly) 63 8050D N/B Maintenance 2.2.12 System Board Disassembly 1. Remove the battery, keyboard, hard disk drive, CD/DVD-ROM drive, Wireless card and LCD assembly. (Refer to sections 2.2.1, 2.2.2, 2.2.4, 2.2.5, 2.2.6 and 2.2.9 Disassembly) 2. Remove the four screws that secure the system board and disconnect the two speaker’s cables. Then lift it up from the housing. (Figure 2-30) 3. Disconnect the one speaker’s cables from the system board and remove the two screws, Then separate the bracket and free the system board. (Figure 2-31) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-30 Remove four screws and disconnect the two cables Reassembly Figure 2-31 Free the system board 1. Fit the bracket and secure with two screws . 2. Turn over the system board. Reconnect the speaker’s cords. 3. Replace the system board back into the housing and secure with four screws, then reconnect the cable. 4. Replace the LCD assembly, CD/DVD-ROM, HDD, keyboard and battery pack. (Refer to previous section reassembly) 64 8050D N/B Maintenance 2.2.13 Touch Pad Disassembly 1. Remove the battery pack, keyboard, hard disk drive and CD/DVD-drive. (See sections 2.2.1,2.2.2 , 2.2.4 and 2.2.5 Disassembly) 2. Remove the top cover. (See steps 1-5 in section 2.2.9 Disassembly) 3. Remove the two screws and free the touch pad. (Figure 2-32). t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Figure 2-32 Remove the two screws Reassembly 1. Replace the touch pad and secure the two screws. 2. Replace the top cover. (Refer to the section in 2.2.9 reassembly) 3. Replace the battery pack, keyboard, hard disk drive and CD/DVD-drive. (See sections 2.2.1,2.2.2 , 2.2.4 and 2.2.5 Disassembly). 65 8050D N/B Maintenance 3. Definition & Location of Connectors / Switches 3.1 Mother Board - A t t n e e r c m e u S c c Do a iT ial M t n e id f n o C J1 : Inverter Board Connector J3 J2 J6 J1 SW2 J2 : LCD panel connector J3 : Internal Left Speaker Connector J4 : Touch-pad Module Connector J5 : Internal Key-board Connector J6 : PCMCIA Card Connector J7 : Internal Right Speaker Connector SW4 J5 J7 SW5 J4 SW2 : Power Button SW4 : Left Button Switch of Touch-pad SW5 : Right Button Switch of Touch-pad 66 8050D N/B Maintenance 3. Definition & Location of Connectors / Switches 3.2 Mother Board - B PJ701 : AC Adaptor Connector J706 J709 J704 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C J701&J706 : USB Port Connector J702 : CRT Connector J701 J713 J703 : Battery Connector J704 : External VGA Connector PJ701 J705 : Internal Subwoofer Speaker J707 J707: FAN Connector J708 : CD-ROM IDE Connector J711 J709: RJ45 & RJ11 Connector J712 J702 J710 : RTC Battery Connector J711&J712 : DDR SO-DIMM Module Socket J713 : Mini-PCI Connector J703 J714 : Hard Disk Driver Connector J710 J705 J708 J714 -----To next page----- 67 8050D N/B Maintenance 3. Definition & Location of Connectors / Switches 3.2 Mother Board - B -----Continue From Previous Page----- t t n e e r c m e u S c c Do a iT ial M t n e id f n o C J715 J717 J715&J717: Modem Daughter Board Connector J716 : SD&MS Card Socket J718 : IEEE 1394 Connector J719 : External Micro Phone Jack J720 : Line Out HP/OPT Jack J718 J721 : External Line-in Jack J720 J721 J719 J716 68 8050D N/B Maintenance 4. Definition & Location of Major Components 4.1 Mother Board - A PU2 : +3VS/+5VS Voltage Generator t t n e e r c m e u S c c Do a iT ial M t n e id f n o C PU3 : CPU Core Voltage Generator PU14: +1.8V/+1.35V Voltage Generator PU2 PU3 PU15 : +2.5VS/+1.25V Voltage Generator U2 : TV Encoder Controller U15: SYS BIOS Controller U16: WINBOND KBC Controller U15 U524: TPA02012 Audio Amplifier U524 PU15 U16 U2 PU14 69 8050D N/B Maintenance 4. Definition & Location of Major Components 4.2 Mother Board - B U706 : Thermal Sensor/Fan Controller t t n e e r c m e u S c c Do a iT ial M t n e id f n o C U710 : ATI-M10-P U719 U713 : Intel BANIAS CPU U714 : Intel 855GM/GME North Bridge U713 U706 U727 U715 : Intel ICH4-M South Bridge U724 U719 : LAN-RTL8100CL Controller U724 : IEEE1394 Controller U725 : SUBWOOFER AMP Controller U726 : Audio CODEC(ALC655) U714 U727 : CB710 Card Bus Reader Controller U710 U725 U715 U726 70 8050D N/B Maintenance 5. Pin Descriptions of Major Components 5.1 Intel Pentium M(Banias) Processor(1) Signal Name A[31:3]# A20M# Type Description I/O A[31:3]# (Address) define a 2 32 -byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the Intel Pentium M processor system bus. A[31:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. Signals Associated Strobe REQ[4:0]#, A[16:3]# ADSTB[0]# A[31:17]# ADSTB[1]# The differential pair BCLK (Bus Clock) determines the system bus frequency. All processor system bus agents must receive these signals to drive their outputs and latch their inputs. BNR# (Block Next Request) is used to assert a bus stall by any bus agent that is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all Intel Pentium M processor system bus agents. This includes debug or performance monitoring tools. I ADS# I/O ADSTB[1:0]# I/O BCLK[1:0] I BNR# I/O BPM[2:0]# BPM[3] O I/O Signal Name BPRI# Type Description I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor system bus. It must connect the appropriate pins of both processor system bus agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. I/O BR0# is used by the processor to request the bus. The arbitration is done between the Intel Pentium M processor (Symmetric Agent) and the MCH-M (High Priority Agent) of the Intel 855PM or Intel 855GM chipset. Analog COMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. Refer to the platform design guides for more implementation details. I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#. Quad-Pumped Signal Groups Data Group DSTBN#/DSTBP# DINV# D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]# 3 3 Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high. O DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect. DBR# is not a processor signal. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C BR0# COMPP3:0] D[63:0]# DBR# 71 8050D N/B Maintenance 5.1 Intel Pentium M(Banias) Processor(2) Signal Name DBSY# DEFER# DINV[3:0]# DPSLP# DRDY# Type Description I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both processor system bus agents. DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of both processor system bus agents. DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. DINV[3:0]# Assignment To Data Bus Bus Signal Data Bus Signals DINV[3]# D[63:48]# DINV[2]# D[47:32]# DINV[1]# D[31:16]# DINV[0]# D[15:0]# DPSLP# when asserted on the platform causes the processor to transition from the Sleep state to the Deep Sleep state. In order to return to the Sleep state, DPSLP# must be deasserted. DPSLP# is driven by the ICH4-M component and also connects to the MCH-M component of the Intel 855PM or Intel 855GM chipset. DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both processor system bus agents. Data strobe used to latch in D[63:0]#. Signals Associated Strobe D[15:0]#, DINV[0]# DSTBN[0]# D[31:16]#, DINV[1]# DSTBN[1]# D[47:32]#, DINV[2]# DSTBN[2]# D[63:48]#, DINV[3]# DSTBN[3]# Data strobe used to latch in D[63:0]#. Signals Associated Strobe D[15:0]#, DINV[0]# DSTBP[0]# D[31:16]#, DINV[1]# DSTBP[1]# D[47:32]#, DINV[2]# DSTBP[2]# D[63:48]#, DINV[3]# DSTBP[3]# I I/O I I/O DSTBN[3:0]# I/O DSTBP[3:0]# I/O Signal Name Type Description DPWR# I FERR#/PBE# O DPWR# is a control signal from the Intel 855PM and Intel 855GM chipsets used to reduce power on the Intel Pentium M data bus input buffers. FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 80387 coprocessor, and is included for compatibility with systems using MS-DOS* type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event. GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 VCCP . GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either system bus agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor system bus. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#. IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. REQ[4:0]# (Request Command) must connect the appropriate pins of both processor system bus agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[0]#. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C GTLREF I HIT# HITM# I/O I/O IERR# O IGNNE# I REQ[4:0]# I/O 72 8050D N/B Maintenance 5.1 Intel Pentium M(Banias) Processor(3) Signal Name INIT# LINT[1:0] LOCK# Type Description I INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power on Reset vector configured during power on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output Write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# must connect the appropriate pins of both processor system bus agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST) LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured using BIOS programming of the APIC register space and used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of both processor system bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the processor system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock. Probe Ready signal used by debug tools to determine processor debug readiness. Probe Request signal used by debug tools to request debug operation of the processor. PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. This signal may require voltage translation on the motherboard. Processor Power Status Indicator signal. This signal is asserted when the processor is in a lower state (Deep Sleep and Deeper Sleep). I I/O PRDY# O PREQ# I PROCHOT# O PSI# O Signal Name PWRGOOD Type Description I PWRGOOD (Power Good) is a processor input. The processor requires this signal as a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout the boundary scan operation. ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects. These are not processor signals. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both system bus agents will deassert their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted. RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of both processor system bus agents. These pins are RESERVED and must be left unconnected on the board. However, it is recommended that routing channels to these pins on the board be kept open for possible future use. Please refer to the platform design guides for more details. SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C ITP_CLK[1:0] I RESET# I RS[2:0]# I RSVD - SLP# I 73 8050D N/B Maintenance 5.1 Intel Pentium M(Banias) Processor(4) Signal Name SMI# STPCLK# TCK TDI TDO TEST1, TEST2, TEST3 THERMDA THERMDC THERMTRIP# TMS TRDY# TRST# Type I Description SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs. I STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. I TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). I TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. O TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. I TEST1, TEST2, and TEST3 must be left unconnected but should have a stuffing option connection to V SS separately using 1-k, pull-down resisitors. Other Thermal Diode Anode. Other Thermal Diode Cathode. O The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125°C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin. I TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. I TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both system bus agents. I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. Type Description VCC VCCA[3:0] VCCP VCCQ[1:0] Signal Name I I I I VCCSENSE O VID[5:0] O VSSSENSE O Processor core power supply. VCCA provides isolated power for the internal processor core PLL’s. Processor I/O Power Supply. Quiet power supply for on die COMP circuitry. These pins should be connected to VCCP on the motherboard. However, these connections should enable addition of decoupling on the VCCQ lines if necessary. VCCSENSE is an isolated low impedance connection to processor core power (VCC ). It can be used to sense or measure power near the silicon with little noise. VID[5:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (Vcc). Unlike some previous generations of processors, these are CMOS signals that are driven by the Intel Pentium M processor. The voltage supply for these pins must be valid before the VR can supply Vcc to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. VSSSENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 74 8050D N/B Maintenance 5.2 Intel 855GM/GME North Bridge(1) Host Interface Signal Descriptions(Continued) Host Interface Signal Descriptions Signal Name Type Description ADS# I/O AGTL+ BNR# I/O AGTL+ BPRI# O AGTL+ Address Strobe: The system bus owner asserts ADS# to indicate the first of two cycles of a request phase. The GMCH can assert this signal for snoop cycles and interrupt messages. Block Next Request: Used to block the current request bus owner from issuing a new request. This signal is used to dynamically control the CPU bus pipeline depth. Bus Priority Request: The GMCH is the only Priority Agent on the system bus. It asserts this signal to obtain the ownership of the address bus. This signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the HLOCK# signal was asserted. Bus Request 0#: The GMCH pulls the processor bus BREQ0# signal low during CPURST#. The signal is sampled by the processor on the active-to-inactive transition of CPURST#. The minimum setup time for this signal is 4 BCLKs. The minimum hold time is 2 clocks and the maximum hold time is 20 BCLKs. BREQ0# should be tristated after the hold time requirement has been satisfied. During regular operation, the GMCH will use BREQ0# as an early indication for FSB Address and Ctl input buffer and sense amp activation. CPU Reset: The CPURST# pin is an output from the GMCH. The GMCH asserts CPURST# while RESET# (PCIRST# from ICH4-M) is asserted and for approximately 1 ms after RESET# is deasserted. The CPURST# allows the processor to begin execution in a known state. Note that the ICH4-M must provide CPU strap set-up and hold-times around CPURST#. This requires strict synchronization between GMCH, CPURST# deassertion and ICH4-M driving the straps. Data Bus Busy: Used by the data bus owner to hold the data bus for transfers requiring more than one cycle. Defer: GMCH will generate a deferred response as defined by the rules of the GMCH’s Dynamic Defer policy. The GMCH will also use the DEFER# signal to indicate a CPU retry response. BREQ0# CPURST# DBSY# DEFER# I/O AGTL+ O AGTL+ I/O AGTL+ O AGTL+ Signal Name DINV[3:0]# Type Description I/O AGTL+ Dynamic Bus Inversion: Driven along with the HD[63:0]# signals. Indicates if the associated signals are inverted or not. DINV[3:0]# are asserted such that the number of data bits driven electrically low (low voltage) within the corresponding 16-bit group never exceeds 8. DINV# Data Bits DINV[3]# HD[63:48]# DINV[2]# HD[47:32]# DINV[1]# HD[31:16]# DINV[0]# HD[16:0]# Deep Sleep #: This signal comes from the ICH4-M device, providing an indication of C3 and C4 state control to the CPU. Deassertion of this signal is used as an early indication for C3 and C4 wake up (to active HPLL). Note that this is a low-voltage CMOS buffer operating on the FSB VTT power plane. Data Ready: Asserted for each cycle that data is transferred. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C DPSLP# I CMOS DRDY# I/O AGTL+ I/O AGTL+ HA[31:3]# HADSTB[1:0]# I/O AGTL+ HD[63:0]# I/O AGTL+ Host Address Bus: HA[31:3]# connects to the CPU address bus. During processor cycles the HA[31:3]# are inputs. The GMCH drives HA[31:3]# during snoop cycles on behalf of Hub interface. HA[31:3]# are transferred at 2x rate. Note that the address is inverted on the CPU bus. Host Address Strobe: HA[31:3]# connects to the CPU address bus. During CPU cycles, the source synchronous strobes are used to transfer HA[31:3]# and HREQ[4:0]# at the 2x transfer rate. Strobe Address Bits HADSTB[0]# HA[16:3]#, HREQ[4:0]# HADSTB[1]# HA[31:17]# Host Data: These signals are connected to the CPU data bus. HD[63:0]# are transferred at 4x rate. Note that the data signals are inverted on the CPU bus. 75 8050D N/B Maintenance 5.2 Intel 855GM/GME North Bridge(2) Host Interface Signal Descriptions (Continued) Signal Name HDSTBP[3:0]# HDSTBN[3:0]# Type Description I/O AGTL+ Differential Host Data Strobes: The differential source synchronous strobes are used to transfer HD[63:0]# and DINV[3:0]# at the 4x transfer rate. Strobe Data Bits HDSTBP[3]#, HDSTBN[3]# HD[63:48]#, DINV[3]# HDSTBP[2]#, HDSTBN[2]# HD[47:32]#, DINV[2]# HDSTBP[1]#, HDSTBN[1]# HD[31:16]#, DINV[1]# HDSTBP[0]#, HDSTBN[0]# HD[15:0]#, DINV[0]# Hit: Indicates that a caching agent holds an unmodified version of the requested line. Also, driven in conjunction with HITM# by the target to extend the snoop window. Hit Modified: Indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. Also, driven in conjunction with HIT# to extend the snoop window. Host Lock: All CPU bus cycles sampled with the assertion of HLOCK# and ADS#, until the negation of HLOCK# must be atomic, i.e. no Hub interface snoopable access to system memory is allowed when HLOCK# is asserted by the CPU. Host Request Command: Defines the attributes of the request. HREQ[4:0]# are transferred at 2x rate. Asserted by the requesting agent during both halves of the Request Phase. In the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second half the signals carry additional information to define the complete transaction type. The transactions supported by the GMCH Host Bridge are defined in the Host Interface section of this document. Host Target Ready: Indicates that the target of the processor transaction is able to enter the data transfer phase. Response Status: Indicates the type of response according to the following the table: RS[2:0]# Response type 000 Idle state 001 Retry response 010 Deferred response 011 Reserved (not driven by GMCH) 100 Hard Failure (not driven by GMCH) 101 No data response 110 Implicit Write back 111 Normal data response HIT# I/O AGTL+ HITM# I/O AGTL+ HLOCK# HREQ[4:0]# HTRDY# RS[2:0]# I/O AGTL+ I/O AGTL+ O AGTL+ O AGTL+ DDR SDRAM Interface Descriptions Signal Name SCS[3:0]# Type Description O SSTL_2 Chip Select: These pins select the particular DDR SDRAM components during the active state. NOTE: There is one SCS# per DDR-SDRAM Physical SO-DIMM device row. These signals can be toggled on every rising System Memory Clock edge (SCMDCLK). Multiplexed Memory Address: These signals are used to provide the multiplexed row and column address to the DDR SDRAM. Bank Select (Memory Bank Address): These signals define which banks are selected within each DDR SDRAM row. The SMA and SBA signals combine to address every possible location within a DDR SDRAM device. DDR Row Address Strobe: SRAS# may be heavily loaded and requires tw0 DDR SDRAM clock cycles for setup time to the DDR SDRAMs. Used with SCAS# and SWE# (along with SCS#) to define the system memory commands. DDR Column Address Strobe: SCAS# may be heavily loaded and requires two clock cycles for setup time to the DDR SDRAMs. Used with SRAS# and SWE# (along with SCS#) to define the system memory commands. Write Enable: Used with SCAS# and SRAS# (along with SCS#) to define the DDR SDRAM commands. SWE# is asserted during writes to DDR SDRAM. SWE# may be heavily loaded and requires two clock cycles for setup time to the DDR SDRAMs. Data Lines: These signals are used to interface to the DDR SDRAM data bus. NOTE: ECC error detection is supported: by the SDQ[71:64] signals. O SSTL_2 O SSTL_2 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C SMA[12:0] SBA[1:0] SRAS# O SSTL_2 SCAS# O SSTL_2 SWE# O SSTL_2 SDQ[71:0] I/O SSTL_2 76 8050D N/B Maintenance 5.2 Intel 855GM/GME North Bridge(3) DDR SDRAM Interface Descriptions (Continued) Signal Name SDQS[8:0] Type Description I/O SSTL_2 Data Strobes: Data strobes are used for capturing data. During writes, SDQS is centered on data. During reads, SDQS is edge aligned with data. The following list matches the data strobe with the data bytes. There is an associated data strobe (DQS) for each data signal (DQ) and check bit (CB) group. SDQS[7] -> SDQ[63:56] SDQS[6] -> SDQ[55:48] SDQS[5] -> SDQ[47:40] SDQS[4] -> SDQ[39:32] SDQS[3] -> SDQ[31:24] SDQS[2] -> SDQ[23:16] SDQS[1] -> SDQ[15:8] SDQS[0] -> SDQ[7:0] NOTE: ECC error detection is supported by the SDQS[8] signal. Clock Enable: These pins are used to signal a self-refresh or power down command to the DDR SDRAM array when entering system suspend. SCKE is also used to dynamically power down inactive DDR SDRAM rows. There is one SCKE per DDR SDRAM row. These signals can be toggled on every rising SCK edge. Memory Address Copies: These signals are identical to SMA[5,4,2,1] and are used to reduce loading for selective CPC(clock-per-command). These copies are not inverted. Data Mask: When activated during writes, the corresponding data groups in the DDR SDRAM are masked. There is one SDM for every eight data lines. SDM can be sampled on both edges of the data strobes. NOTE: ECC error detection is supported by the SDM[8] signal. Clock Output: Reserved, NC. SCKE[3:0] O SSTL_2 SMAB[5,4,2,1] O SSTL_2 SDM[8:0] O SSTL_2 RCVENOUT# O SSTL_2 O SSTL_2 RCVENIN# AGP Addressing Signal Descriptions Signal Name Type Description Pipelined Read: This signal is asserted by the AGP master to indicate a full width address is to be enqueued on by the target using the AD bus. One address is placed in the AGP request queue on each rising clock edge while PIPE# is asserted. When PIPE# is deasserted no new requests are queued across the AD bus. During SBA Operation: This signal is not used if SBA (Side Band Addressing) is selected. During FRAME# Operation: This signal is not used during AGP FRAME# operation. PIPE# is a sustained tri-state signal from masters (graphics controller), and is an input to the GMCH. I Side-band Address: These signals are used by the AGP master GSBA[7:0] AGP (graphics controller) to pass address and command to the GMCH. The SBA bus and AD bus operate independently. That is, transactions can proceed on the SBA bus and the AD bus simultaneously. During PIPE# Operation: These signals are not used during PIPE# operation. During FRAME# Operation: These signals are not used during AGP FRAME# operation. NOTE: When sideband addressing is disabled, these signals are isolated (no external/internal pull-ups are required). 5 contains two mechanisms to queue requests by the AGP master. Note that the master can only use one mechanism. The master may not switch methods without a full reset of the system. When PIPE# is used to queue addresses the master isnot allowed to queue addresses using the SBA bus. For example, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use. Once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism, but rather a static decision when the device is first being configured after reset GPIPE# I AGP t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Clock Input: Reserved, NC. 77 8050D N/B Maintenance 5.2 Intel 855GM/GME North Bridge(4) AGP Flow Control Signals AGP Status Signal Descriptions Signal Name GST[2:0] Type O AGP Description Status: Provides information from the arbiter to an AGP Master on what it may do. ST[2:0] only have meaning to the master when its GNT# is asserted. When GNT# is deasserted these signals have no meaning and must be gnored. ST[2:0 Meaning 000 Previously requested low priority read data is being returned to the master arbiter to an AGP 001 010 011 100 101 110 111 Signal Name GRBF# Type Description I AGP Read Buffer Full: Read buffer full indicates if the master is ready to accept previously requested low priority read data. When RBF# is asserted the GMCH is not allowed to initiate the return low priority read data. That is, the GMCH can finish returning the data for the request currently being serviced. RBF# is only sampled at the beginning of a cycle. If the AGP master is always ready to accept return read data then it is not required to implement this signal. During FRAME# Operation: This signal is not used during AGP FRAME# operation. Write-Buffer Full: indicates if the master is ready to accept Fast Write data from the GMCH. When WBF# is asserted the GMCH is not allowed to drive Fast Write data to the AGP master. WBF# is only sampled at the beginning of a cycle. If the AGP master is always ready to accept fast write data then it is not required to implement this signal. During FRAME# Operation: This signal is not used during AGP FRAME# operation. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Previously requested high priority read data is being returned to the master The master is to provide low priority write data for a previously queued write command The master is to provide high priority write data for a previously queued write command. Reserved GWBF# I AGP Reserved Reserved The master has been given permission to start a bus transaction. The master may queue AGP requests by asserting PIPE# or start a PCI transaction by asserting FRAME# 78 8050D N/B Maintenance 5.2 Intel 855GM/GME North Bridge(5) AGP Strobe Descriptions AGP/PCI Signals-Semantics Descriptions Signal Name GFRAME# GIRDY# Type Description I/O AGP G_FRAME: Frame. During PIPE# and SBA Operation: Not used by AGP SBA and PIPE# operations. During Fast Write Operation: Used to frame transactions as an output during Fast Writes. During FRAME# Operation: G_FRAME# is an output when the GMCH acts as an initiator on the AGP Interface. G_FRAME# is asserted by the GMCH to indicate the beginning and duration of an access. G_FRAME# is an input when the GMCH acts as a FRAME#-based AGP target. As a FRAME#-based AGP target, the GMCH latches the C/BE[3:0]# and the AD[31:0] signals on the first clock edge on which GMCH samples FRAME# active. G_IRDY#: Initiator Ready. During PIPE# and SBA Operation: Not used while enqueueing requests via AGP SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions. During FRAME# Operation: G_IRDY# is an output when GMCH acts as a FRAME#-based AGP initiator and an input when the GMCH acts as a FRAME#-based AGP target. The assertion of G_IRDY# indicates the current FRAME#-based AGP bus initiator's ability to complete the current data phase of the transaction. During Fast Write Operation: In Fast Write mode, G_IRDY# indicates that the AGP-compliant master is ready to provide all write data for the current transaction. Once G_IRDY# is asserted for a write operation, the master is not allowed to insert wait states. The master is never allowed to insert a wait state during the initial data transfer (32 bytes) of a write transaction. However, it may insert wait states after each 32-byte block is transferred. I/O AGP Signal Name Type Description GADSTB[0] I/O AGP GADSTB#[0] I/O AGP Address/Data Bus Strobe-0: provides timing for 2x and 4x data on AD[15:0] and C/BE[1:0]# signals. The agent that is providing the data will drive this signal. Address/Data Bus Strobe-0 Complement: With AD STB0, forms a differential strobe pair that provides timing information for the AD[15:0] and C/BE[1:0]# signals. The agent that is providing the data will drive this signal. Address/Data Bus Strobe-1: Provides timing for 2x and 4x data on AD[31:16] and C/BE[3:2]# signals. The agent that is providing the data will drive this signal. Address/Data Bus Strobe-1 Complement: With AD STB1, forms a differential strobe pair that provides timing information for the AD[15:0] and C/BE[1:0]# signals in 4X mode. The agent that is providing the data will drive this signal. Sideband Strobe: Provides timing for 2x and 4x data on the SBA[7:0] bus. It is driven by the AGP master after the system has been configured for 2x or 4x sideband address mode. Sideband Strobe Complement: The differential complement to the SB_STB signal. It is used to provide timing 4x mode. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C GADSTB[1] I/O AGP GADSTB#[1] I/O AGP GSBSTB I AGP GSBSTB# I AGP 79 8050D N/B Maintenance 5.2 Intel 855GM/GME North Bridge(6) AGP/PCI Signals-Semantics Descriptions (Continued) Signal Name GTRDY# Type Description I/O AGP G_TRDY#: Target Ready. During PIPE# and SBA Operation: Not used while enqueueing requests via AGP SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions. During FRAME# Operation: G_TRDY# is an input when the GMCH acts as an AGP initiator and is an output when the GMCH acts as a FRAME#-based AGP target. The assertion of G_TRDY# indicates the target’s ability to complete the current data phase of the transaction. During Fast Write Operation: In Fast Write mode, G_TRDY# indicates the AGP-compliant target is ready to receive write data for the entire transaction (when the transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes. The target is allowed to insert wait states after each block (32 bytes) is transferred on write transactions. G_STOP#: Stop. During PIPE# and SBA Operation: This signal is not used during PIPE# or SBA operation. During FRAME# Operation: G_STOP# is an input when the GMCH acts as a FRAME#-based AGP initiator and is an output when the GMCH acts as a FRAME#-based AGP target. G_STOP# is used for disconnect, retry, and abort sequences on the AGP interface. G_ DEVSEL#: Device Select. During PIPE# and SBA Operation: This signal is not used during PIPE# or SBA operation. During FRAME# Operation: G_DEVSEL#, when asserted, indicates that a FRAME#-based AGP target device has decoded its address as the target of the current access. The GMCH asserts G_DEVSEL# based on the DDR SDRAM address range being accessed by a PCI initiator. As an input, G_DEVSEL# indicates whether the AGP master has recognized a PCI cycle to it. G_REQ#: Request. During SBA Operation: This signal is not used during SBA operation. During PIPE# and FRAME# Operation: G_REQ#, when asserted, indicates that the AGP master is requesting use of the AGP interface to run a FRAME#- or PIPE#-based operation. GSTOP# I/O AGP GDEVSEL# I/O AGP GREQ# I AGP ATP/PCI Signals-Semantics Descriptions(Continued) Signal Name GGNT# Type Description O AGP G_GNT#: Grant. During SBA, PIPE# and FRAME# Operation: G_GNT#, along with the information on the ST[2:0] signals (status bus), indicates how the AGP interface will be used next. Refer to the AGP Interface Specification, Revision 2.0 for further explanation of the ST[2:0] values and their meanings. I/O GAD[31:0] G_AD[31:0]: Address/Data Bus. AGP During PIPE# and FRAME# Operation: The G_AD[31:0] signals are used to transfer both address and data information on the AGP interface. During SBA Operation: The G_AD[31:0] signals are used to transfer data on the AGP interface. I/O GCBE#[3:0] Command/Byte Enable. AGP During FRAME# Operation: During the address phase of a transaction, the G_CBE[3:0]# signals define the bus command. During the data phase, the G_CBE[3:0]# signals are used as byte enables. The byte enables determine which byte lanes carry meaningful data. The commands issued on the G_CBE# signals during FRAME#-based AGP transactions are the same G_CBE# command described in the PCI 2.2 specification. During PIPE# Operation: When an address is enqueued using PIPE#, the C/BE# signals carry command information. The command encoding used during PIPE#-based AGP is different than the command encoding used during FRAME#-based AGP cycles (or standard PCI cycles on a PCI bus). During SBA Operation: These signals are not used during SBA operation. I/O GPAR Parity. AGP During FRAME# Operation: G_PAR is driven by the GMCH when it acts as a FRAME#-based AGP initiator during address and data phases for a write cycle, and during the address phase for a read cycle. G_PAR is driven by the GMCH when it acts as a FRAME#-based AGP target during each data phase of a FRAME#-based AGP memory read cycle. Even parity is generated across G_AD[31:0] and G_CBE[3:0]#. During SBA and PIPE# Operation: This signal is not used during SBA and PIPE# operation. PCIRST# from the ICH4-M is assumed to be connected to RSTIN# and is used to reset AGP interface logic within the GMCH. The AGP agent will also typically use PCIRST# provided by the ICH4-M as an input to reset its internal logic. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 80 8050D N/B Maintenance 5.2 Intel 855GM/GME North Bridge(7) Digital Video Output B (DVOB) Port Signal Descriptions Hub Interface Signals Signal Name Type I/O Hub I/O Hub I/O Hub HL[10:0] HLSTB HLSTB# Description Packet Data: Data signals used for HI read and write operations. Type ICLKAP O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS O LVDS ICLKAM IYAP[3:0] IYAM[3:0] ICLKBP ICLKBM IYBP[3:0] IYBM[3:0] DVOBD[11:0] Type O DVO Packet Strobe: One of two differential strobe signals used to transmit or receive packet data over HI. Packet Strobe Complement: One of two differential strobe signals used to transmit or receive packet data over HI. Voltage DVOBHSYNC O DVO DVOBVSYNC O DVO Description DVOB Data: This data bus is used to drive 12-bit RGB data on each edge of the differential clock signals, DVOBCLK and DVOBCLK#. This provides 24-bits of data per clock period. In dual channel mode, this provides the lower 12-bits of pixel data. DVOBD[11:0] should be left as left as NC (“Not Connected”) if not used. Horizontal Sync: HSYNC signal for the DVOB interface. DVOBHSYNC should be left as left as NC (“Not Connected”) if not used. Vertical Sync: VSYNC signal for the DVOB interface. DVOBVSYNC should be left as left as NC (“Not Connected”) if the signal is NOT used when using internal graphics device. Flicker Blank or Border Period Indication: DVOBBLANK# is a programmable output pin driven by the GMCH. When programmed as a blank period indication, this pin indicates active pixels excluding the border. When programmed as a border period indication, this pin indicates active pixel including the border pixels. DVOBBLANK# should be left as left as NC (“Not Connected”) if not used. TV Field and Flat Panel Stall Signal. This input can be programmed to be either a TV Field input from the TV encoder or Stall input from the flat panel. DVOB TV Field Signal: When used as a Field input, it synchronizes the overlay field with the TV encoder field when the overlay is displaying an interleaved source. DVOB Flat Panel Stall Signal: When used as the Stall input, it indicates that the pixel pipeline should stall one horizontal line. The signal changes during horizontal blanking. The panel fitting logic, when expanding the image vertically, uses this. DVOBFLDSTL needs to be pulled down if not used. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Dedicated LVDS LCD Flat Panel Interface Signal Descriptions Name Name Description 1.25 V± 225 mV Channel A differential clock pair output (true): 245-800 MHz 1.25 V±225 mV Channel A differential clock pair output (compliment): 245-800 MHz. 1.25 V±225 mV Channel A differential data pair 3:0 output (true): 245-800MHz. 1.25 V±225 mV Channel A differential data pair 3:0 output (compliment): 245-800 MHz. 1.25 V±225 mV Channel B differential clock pair output (true): 245-800 MHz. 1.25 V±225 mV Channel B differential clock pair output (compliment): 245-800 MHz. 1.25 V±225 mV Channel B differential data pair 3:0 output (true): 245-800MHz. 1.25 V± 225 mV Channel B differential data pair 3:0 output (compliment): 245-800 MHz. DVOBBLANK# O DVO DVOBFLDSTL I DVO 81 8050D N/B Maintenance 5.2 Intel 855GM/GME North Bridge(8) DVOB and DVOC Port Common Signal Descriptions Name DVOBCINTR# ADDID[7:0] DVODETECT Type Description I DVO I DVO DVOBC Interrupt: This pin is used to signal an interrupt, typically used to indicate a hot plug or unplug of a digital display. ADDID[7:0]: These pins are used to communicate to the Video BIOS when an external device is interfaced to the DVO port. Note: Bit[7] needs to be strapped low when an on-board DVO device is present. The other pins should be left as NC. DVODETECT: This strapping signal indicates to the GMCH whether a DVO device is present or not. When a DVO device is connected, then DVODETECT = 0. I DVO Analog CRT Display Signal Descriptions Pin Name VSYNC HSYNC RED RED# GREEN GREEN# BLUE BLUE# Type O CMOS O CMOS O Analog O Analog O Analog O Analog O Analog O Analog Digital Video Output C (DVOC) Port Signal Descriptions Name DVOCD[11:0] Type Description O DVO DVOC Data: This data bus is used to drive 12-bit RGB data on each edge of the differential clock signals, DVOCCLK and DVOCCLK#. This provides 24-bits of data per clock period. In dual channel mode, this provides the upper 12-bits of pixel data. DVOCD[11:0] should be left as left as NC (“Not Connected”) if not used. Horizontal Sync: HSYNC signal for the DVOC interface. DVOCHSYNC should be left as left as NC (“Not Connected”) if not used. Vertical Sync: VSYNC signal for the DVOC interface. DVOCVSYNC should be left as left as NC (“Not Connected”) if the signal is NOT used when using internal graphics device. Flicker Blank or Border Period Indication: DVOCBLANK# is a programmable output pin driven by the GMCH. When programmed as a blank period indication, this pin indicates active pixels excluding the border. When programmed as a border period indication, this pin indicates active pixel including the border pixels. DVOCBLANK# should be left as left as NC (“Not Connected”) if not used. TV Field and Flat Panel Stall Signal. This input can be programmed to be either a TV Field input from the TV encoder or Stall input from the flat panel. DVOC TV Field Signal: When used as a Field input, it synchronizes the overlay field with the TV encoder field when the overlay is displaying an interleaved source. DVOC Flat Panel Stall Signal: When used as the Stall input, it indicates that the pixel pipeline should stall one horizontal line. The signal changes during horizontal blanking. The panel fitting logic, when expanding the image vertically, uses this. DVOCFLDSTL needs to be pulled down if not used. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C DVOCHSYNC O DVO DVOCVSYNC O DVO DVOCBLANK# O DVO DVOCFLDSTL I DVO Description CRT Vertical Synchronization: This signal is used as the vertical sync signal. CRT Horizontal Synchronization: This signal is used as the horizontal sync signal. Red (Analog Video Output): This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5-§Ù equivalent load on each pin (e.g., 75-§Ù resistor on the board, in parallel with the 75-§Ù CRT load). Red# (Analog Output): Tied to ground. Green (Analog Video Output): This signal is a CRT analog video output from the internal color palette DAC. The DAC is designed for a 37.5-§Ù equivalent load on each pin (e.g.,75-§Ù resistor on the board, in parallel with the 75- §Ù CRT load). Green# (Analog Output): Tied to ground. Blue (Analog Video Output) : This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5-§Ù equivalent load on each pin (e.g., 75ohm resistor on the board, in parallel with the 75-§Ù CRT load). Blue# (Analog Output): Tied to ground. 82 8050D N/B Maintenance 5.2 Intel 855GM/GME North Bridge(9) GPIO Signal Descriptions(Continued) GPIO Signal Descriptions GPIO I/F Total RSTIN# PWROK AGPBUSY# EXTTS_0 LCLKCTLA LCLKCTLB PANELVDDEN PANELBKLTE N PANELBKLTC TL DDCACLK DDCADATA DDCPCLK DDCPDATA Type I CMOS I CMOS O CMOS I CMOS O CMOS O CMOS O CMOS O CMOS O CMOS I/O CMOS I/O CMOS I/O CMOS I/O CMOS Comments Reset: Primary Reset, Connected to PCIRST# of ICH4-M. GPIO I/F Total Type MI2CCLK I/O DVO MI2CDATA I/O DVO Power OK: Indicates that power to GMCH is stable. AGPBUSY: Output of the GMCH IGD to the ICH4-M, which indicates that certain graphics activity is taking place. It will indicate to the ACPI software not to enter the C3 state. It will also cause a C3/C4 exit if C3/C4 was being entered, or was already entered when AGPBUSY# went active. Not active when the IGD is in any ACPI state other than D0. External Thermal Sensor Input: This signal is an active low input to the GMCH and is used to monitor the thermal condition around the system memory and is used for triggering a read throttle. The GMCH can be optionally programmed to send a SERR, SCI, or SMI message to the ICH4-M upon the triggering of this signal. SSC Chip Clock Control: Can be used to control an external clock chip with SSC control. SSC Chip Data Control: Can be used to control an external clock chip for SSC control. LVDS LCD Flat Panel Power Control: This signal is used enable power to the panel interface. LVDS LCD Flat Panel Backlight Enable: This signal is used to enable the backlight inverter (BLI) LVDS LCD Flat Panel Backlight Brightness Control: This signal is used as the Pulse Width Modulated (PWM) control signal to control the backlight inverter. CRT DDC Clock: This signal is used as the DDC clock signal between the CRT monitor and the GMCH. CRT DDC Data: This signal is used as the DDC data signal between the CRT monitor and the GMCH. Panel DDC Clock: This signal is used as the DDC clock signal between the LFP and the GMCH. Panel DDC Data: This signal is used as the DDC data signal between the LFP and the GMCH. Comments DVO I2C Clock: This signal is used as the I2C_CLK for a digital display (i.e. TV-Out Encoder, TMDS transmitter). This signal is tri-stated during a hard reset. DVO I2C Data: This signal is used as the I2C_DATA for a digital display (i.e. TV-Out Encoder, TMDS transmitter). This signal is tri-stated during a hard reset. DVI DDC Clock: This signal is used as the DDC clock for a digital display connector (i.e. primary digital monitor). This signal is tri-stated during a hard reset. DVI DDC Data: The signal is used as the DDC data for a digital display connector (i.e. primary digital monitor). This signal is tri-stated during a hard reset. DVI DDC Clock: The signal is used as the DDC data for a digital display connector (i.e. secondary digital monitor). This signal is tri-stated during a hard reset. DVI DDC Data: The signal is used as the DDC clock for a digital display connector (i.e. secondary digital monitor). This signal is tri-stated during a hard reset. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C MDVICLK I/O DVO MDVIDATA I/O DVO MDDCDATA I/O DVO MDDCCLK I/O DVO 83 8050D N/B Maintenance 5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(1) Hub Interface Signals Signal Name Firmware Hub Interface Signals Type Description HI[11:0] I/O Hub Interface Signals HI_STB/HI_STBS I/O HI_STB#/ HI_STBF I/O Hub Interface Strobe/ Hub Interface Strobe Second: One of two differential strobe signals used to transmit and receive data through the hub interface. Hub Interface 1.5 mode this signal is not differential and is the second of the two strobe signals. Hub Interface Strobe Complement / Hub Interface Strobe First: One of two differential strobe signals used to transmit and receive data through the hub interface. Hub Interface 1.5 mode this signal is not differential and is the first of the two strobe signals. Hub Interface Compensation: Used for hub interface buffer compensation. Hub Interface Voltage Swing: Analog input used to control the voltage swing and impedance strength of hub interface pins. HICOMP HI_VSWING I/O I LAN Connect Interface Signals Signal Name Type LAN_CLK I LAN_RXD[2:0] I LAN_TXD[2:0] O LAN_RSTSYNC O Type FWH[3:0]/ LAD[3:0] FWH[4]/ LFRAME# Type Description I/O Firmware Hub Signals. Muxed with LPC address signals. I/O LFRAME# Firmware Hub Signals. Muxed with LPC LFRAME# signal. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C PCI Interface Signals Signal Name Type AD[31:0] I/O C/BE[3:0]# I/O DEVSEL# I/O Description LAN I/F Clock: Driven by the LAN Connect component. Frequency range is 5 MHz to 50 MHz. Received Data: The LAN Connect component uses these signals to transfer data and control information to the integrated LAN Controller. These signals have integrated weak pull-up resistors. Transmit Data: The integrated LAN Controller uses these signals to transfer data and control information to the LAN Connect component. LAN Reset/Sync: The LAN Connect component’s Reset and Sync signals are multiplexed onto this pin. EEPROM Interface Signals Signal Name Signal Name Description EE_SHCLK O EEPROM Shift Clock: Serial shift clock output to the EEPROM. EE_DIN I EE_DOUT O EE_CS O EEPROM Data In: Transfers data from the EEPROM to the ICH3. This signal has an integrated pull-up resistor. EEPROM Data Out: Transfers data from the ICH3 to the EEPROM. EEPROM Chip Select: Chip select signal to the EEPROM. Description PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During subsequent clocks, AD[31:0] contain data. The ICH4 drives all 0s on AD[31:0] during the address phase of all PCI Special Cycles. Bus Command and Byte Enables: The command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase, C/BE[3:0]# define the Byte Enables. C/BE[3:0]# Command Type 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0110 Memory Read 0111 Memory Write 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1110 Memory Read Line 1111 Memory Write and Invalidate All command encodings not shown are reserved. The ICH4 does not decode reserved values, and therefore will not respond if a PCI master generates a cycle using one of the reserved values. Device Select: The ICH4 asserts DEVSEL# to claim a PCI transaction. As an output, the ICH4 asserts DEVSEL# when a PCI master peripheral attempts an access to an internal ICH4 address or an address destined for the hub interface (main memory or AGP). As an input, DEVSEL# indicates the response to an ICH4-initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated by the ICH4 until driven by a Target device. 84 8050D N/B Maintenance 5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(2) PCI Interface Signals (Continued) Signal Name FRAME# IRDY# TRDY# PAR PCI Interface Signals (Continued) Type Description I/O Cycle Frame: The current Initiator drives FRAME# to indicate the beginning and duration of a PCI transaction. While the Initiator asserts FRAME#, data transfers continue. When the Initiator negates FRAME#, the transaction is in the final data phase. FRAME# is an input to the ICH4 when the ICH4 is the Target, and FRAME# is an output from the ICH4 when the ICH4 is the Initiator. FRAME# remains tri- stated by the ICH4 until driven by an Initiator. Initiator Ready: IRDY# indicates the ICH4's ability, as an Initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock that both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates the ICH4 has valid data present on AD[31:0]. During a read, it indicates the ICH4 is prepared to latch data. IRDY# is an input to the ICH4 when the ICH4 is the Target and an output from the ICH4 when the ICH4 is an Initiator. IRDY# remains tri-stated by the ICH4 until driven by an Initiator. Target Ready: TRDY# indicates the ICH4's ability, as a Target, to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that the ICH4, as a Target, has placed valid data on AD[31:0]. During a write, TRDY# indicates that the ICH4, as a Target, is prepared to latch data. TRDY# is an input to the ICH4 when the ICH4 is the Initiator and an output from the ICH4 when the ICH4 is a Target. TRDY# is tri-stated from the leading edge of PCIRST#. TRDY# remains tri-stated by the ICH4 until driven by a target. Calculated/Checked Parity: PAR uses “even” parity calculated on 36 bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the ICH4 counts the number of 1s within the 36 bits plus PAR and the sum is always even. The ICH4 always calculates PAR on 36 bits regardless of the valid byte enables. The ICH4 generates PAR for address and data phases and only guarantees PAR to be valid one PCI clock after the corresponding address or data phase. The ICH4 drives and tri-states PAR identically to the AD[31:0] lines except that the ICH4 delays PAR by exactly one PCI clock. PAR is an output during the address phase (delayed one clock) for all ICH4 initiated transactions. PAR is an output during the data phase (delayed one clock) when the ICH4 is the Initiator of a PCI write transaction, and when it is the Target of a read transaction. ICH4 checks parity when it is the Target of a PCI write transaction. If a parity error is detected, the ICH4 will set the appropriate internal status bits, and has the option to generate an NMI# or SMI#. I/O I/O I/O Signal Name STOP# Type Description I/O Stop: STOP# indicates that the ICH4, as a Target, is requesting the Initiator to stop the current transaction. STOP# causes the ICH4, as an Initiator, to stop the current transaction. STOP# is an output when the ICH4 is a Target and an input when the ICH4 is an Initiator. STOP# is tri-stated from the leading edge of PCIRST#. STOP# remains tri-stated until driven by the ICH4. Parity Error: An external PCI device drives PERR# when it receives data that has a parity error. The ICH4 drives PERR# when it detects a parity error. The ICH4 can either generate an NMI# or SMI# upon detecting a parity error (either detected internally or reported via the PERR# signal). PCI Requests: The ICH4 supports up to 6 masters on the PCI bus. REQ[5]# is muxed with PC/PCI REQ[B]# (must choose one or the other, but not both). If not used for PCI or PC/PCI, REQ[5]#/REQ[B]# can instead be used as GPIO[1]. NOTE: REQ[0]# is programmable to have improved arbitration latency for for supporting PCI-based 1394 controllers. PCI Grants: The ICH4 supports up to 6 masters on the PCI bus. GNT[5]# is muxed with PC/PCI GNT[B]# (must choose one or the other, but not both). If not needed for PCI or PC/PCI, GNT[5]# can instead be used as a GPIO. Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail. GNT[B]#/GNT[5]#/GPIO[17] has an internal pull-up. PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all transactions on the PCI Bus. NOTE: This clock does not stop based on STP_PCI# signal. PCICLK only stops based on SLP_S1# or SLP_S3#. PCI Reset: ICH4 asserts PCIRST# to reset devices that reside on the PCI bus. The ICH4 asserts PCIRST# during power-up and when S/W initiates a hard reset sequence through the RC (CF9h) register. The ICH4 drives PCIRST# inactive a minimum of 1 ms after PWROK is driven active. The ICH4 drives PCIRST# active a minimum of 1 ms when initiated through the RC register. PCI Lock: This signal indicates an exclusive bus operation and may require multiple transactions to complete. ICH4 asserts PLOCK# when it performs non- exclusive transactions on the PCI bus. Devices on the PCI bus (other than the ICH4) are not permitted to assert the PLOCK# signal. System Error: SERR# can be pulsed active by any PCI device that detects a system error condition. Upon sampling SERR# active, the ICH4 has the ability to generate an NMI, SMI#, or interrupt. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C PERR# I/O REQ[4:0]# REQ[5]#/ REQ[B]#/ GPIO[1] I GNT[4:0]# GNT[5]#/ GNT[B]#/ GPIO[17] O PCICLK I PCIRST# O PLOCK# I/O SERR# I/OD 85 8050D N/B Maintenance 5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(3) PCI Interface Signals (Continued) Signal Name PME# IDE Interface Signals (Continued) Type Description I/OD PCI Power Management Event: PCI peripherals drive PME# to wake the system from low-power states S1-M–S5. PME# assertion can also be enabled to generate an SCI from the S0 state. In some cases the ICH4 may drive PME# active due to an internal wake event. The ICH4 will not drive PME# high, but it will be pulled up to VccSus3_3 by an internal pull-up resistor. PCI Clock Run: Used to support PCI Clock Run protocol. Connects to PCI devices that need to request clock re-start, or prevention of clock stopping. NOTE: An external pull-up to the core power plane is required. PC/PCI DMA Request [A:B]: This request serializes ISA-like DMA Requests for the purpose of running ISA-compatible DMA cycles over the PCI bus. This is used by devices such as PCI based Super I/O or audio codecs which need to perform legacy 8237 DMA but have no ISA bus. When not used for PC/PCI requests, these signals can be used as General Purpose Inputs. REQ[B]# can instead be used as the 6th PCI bus request. PC/PCI DMA Acknowledges [A: B]: This grant serializes an ISA-like DACK# for the purpose of running DMA/ISA Master cycles over the PCI bus. This is used by devices such as PCI based Super/IO or audio codecs which need to perform legacy 8237 DMA but have no ISA bus. When not used for PC/PCI, these signals can be used as General Purpose Outputs. GNTB# can also be used as the 6th PCI bus master grant output. These signal have internal pull-up resistors. CLKRUN# I/O REQ[A]#/ GPIO[0] REQ[B]#/ REQ[5]#/ GPIO[1] I GNT[A]#/ GPIO[16] GNT[B]#/ GNT[5]#/ GPIO[17] O IDE Interface Signals Signal Name Type PDCS1#, SDCS1# O PDCS3#, SDCS3# O PDA[2:0], SDA[2:0] O Signal Name Type Description PDD[15:0], SDD[15:0] I/O PDDREQ, SDDREQ I Primary and Secondary IDE Device Data: These signals directly drive the corresponding signals on the primary or secondary IDE connector. There is a weak internal pull-down resistor on PDD[7] and SDD[7]. Primary and Secondary IDE Device DMA Request: These input signals are directly driven from the DRQ signals on the primary or secondary IDE connector. It is asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function and are not associated with any AT compatible DMA channel. There is a weak internal pull-down resistor on these signals. Primary and Secondary IDE Device DMA Acknowledge: These signals directly drive the DAK# signals on the primary and secondary IDE connectors. Each is asserted by the ICH4 to indicate to IDE DMA slave devices that a given data transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function and are not associated with any AT-compatible DMA channel. Primary and Secondary Disk I/O Read (PIO and Non-Ultra DMA): This is the command to the IDE device that it may drive data onto the PDD or SDD lines. Data is latched by the ICH4 on the deassertion edge of PDIOR# or SDIOR#. The IDE device is selected either by the ATA register file chip selects (PDCS1# or SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA acknowledge (PDDAK# or SDDAK#). Primary and Secondary Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write strobe for writes to disk. When writing to disk, ICH4 drives valid data on rising and falling edges of PDWSTB or SDWSTB. Primary and Secondary Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA ready for reads from disk. When reading from disk, ICH4 deasserts PRDMARDY# or SRDMARDY# to pause burst data transfers. Primary and Secondary Disk I/O Write (PIO and Non-Ultra DMA): This is the command to the IDE device that it may latch data from the PDD or SDD lines. Data is latched by the IDE device on the deassertion edge of PDIOW# or SDIOW#. The IDE device is selected either by the ATA register file chip selects (PDCS1# or SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA acknowledge (PDDAK# or SDDAK#). Primary and Secondary Disk Stop (Ultra DMA): ICH4 asserts this signal to terminate a burst. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C PDDACK#, SDDACK# O PDIOR#/ (PDWSTB/PRDMA RDY#) O SDIOR#/ (SDWSTB/SRDMA RDY#) Description Primary and Secondary IDE Device Chip Selects for 100 Range: For ATA command register block. This output signal is connected to the corresponding signal on the primary or secondary IDE connector. Primary and Secondary IDE Device Chip Select for 300 Range: For ATA control register block. This output signal is connected to the corresponding signal on the primary or secondary IDE connector. Primary and Secondary IDE Device Address: These output signals are connected to the corresponding signals on the primary or secondary IDE connectors. They are used to indicate which byte in either the ATA command block or control block is being addressed. PDIOW#/ (PDSTOP) SDIOW#/ (SDSTOP) O 86 8050D N/B Maintenance 5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(4) LPC Interface Signals IDE Interface Signals (Continued) Signal Name Type Description PIORDY#/ (PDRSTB/PWDMA RDY#) I Primary and Secondary I/O Channel Ready (PIO): This signal will keep the strobe active (PDIOR# or SDIOR# on reads, PDIOW# or SDIOW# on writes) longer than the minimum width. It adds wait states to PIO transfers. Primary and Secondary Disk Read Strobe (Ultra DMA Reads from Disk): When reading from disk, the ICH4 latches data on rising and falling edges of this signal from the disk. Primary and Secondary Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk, this is de-asserted by the disk to pause burst data transfers. SIORDY#/ (SDRSTB/SWDMA RDY#) Signal Name LAD[3:0]/ FWH[3:0] LFRAME#/ FWH[4] LDRQ[1:0]# Type I/O O I Description LPC Multiplexed Command, Address, Data: For the LAD[3:0] signals, internal pull-ups are provided. LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort. LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or bus master access. These signals are typically connected to an external Super I/O device. An internal pull-up resistor is provided on these signals. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C USB Interface Signals Signal Name Interrupt Signals Signal Name SERIRQ PIRQ[D:A]# PIRQ[H:E]#/ GPIO[5:2] Type I/O I/OD I/OD IRQ[14:15] I APICCLK I APICD[1:0] I/OD Description Serial Interrupt Request: This pin implements the serial interrupt protocol. PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control Register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to IRQ17, PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. This frees the legacy interrupts. PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control Register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQ[E]# is connected to IRQ20, PIRQ[F]# to IRQ21, PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23. This frees the legacy interrupts. If not needed for interrupts, these signals can be used as GPIO. Interrupt Request 14:15: These interrupt inputs are connected to the IDE drives. IRQ14 is used by the drives connected to the Primary controller and IRQ15 is used by the drives connected to the Secondary controller. APIC Clock: This clock operates up to 33.33 MHz. APIC Data: These bi-directional open drain signals are used to send and receive data over the APIC bus. As inputs the data is valid on the rising edge of APICCLK. As outputs, new data is driven from the rising edge of the APICCLK. Type Description USBP0P, USBP0N, USBP1P, USBP1N I/O USBP2P, USBP2N, USBP3P, USBP3N I/O USBP4P, USBP4N, USBP5P, USBP4N I/O OC[5:0]# I/O USBRBIAS O USBRBIAS# I Universal Serial Bus Port 1:0 Differential: These differential pairs are used to transmit data/address/command signals for ports 0 and 1. These ports can be routed to USB UHCI Controller #1 or the USB EHCI Controller. NOTE: No external resistors are required on these signals. The ICH4 integrates 15 k . pull-downs and provides an output driver impedance of 45 . which requires no external series resistor Universal Serial Bus Port 3:2 Differential: These differential pairs are used to transmit data/address/command signals for ports 2 and 3. These ports can be routed to USB UHCI Controller #2 or the USB EHCI Controller. NOTE: No external resistors are required on these signals. The ICH4 integrates 15 k . pull-downs and provides an output driver impedance of 45 . which requires no external series resistor. Universal Serial Bus Port 5:4 Differential: These differential pairs are used to transmit data/address/command signals for ports 4 and 5. These ports can be routed to USB UHCI Controller #3 or the USB EHCI Controller NOTE: No external resistors are required on these signals. The ICH4 integrates 15 k . pull-downs and provides an output driver impedance of 45 . which requires no external series resistor Overcurrent Indicators: These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred. USB Resistor Bias: Analog connection point for an external resistor to ground. USBRBIAS should be connected to USBRBIAS# as close to the resistor as possible. USB Resistor Bias Complement: Analog connection point for an external resistor to ground. USBRBIAS# should be connected to USBRBIAS as close to the resistor as possible. 87 8050D N/B Maintenance 5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(5) Power Management Interface Signals (Continued) Power Management Interface Signals Signal Name Type THRM# I THRMTRIP# I SLP_S1# O SLP_S3# O SLP_S4# O SLP_S5# O PWROK PWRBTN# I I RI# I SYS_RESET# I RSMRST# I Description Thermal Alarm: This is an active low signal generated by external hardware to start the hardware clock throttling mode. The signal can also generate an SMI# or an SCI. Thermal Trip: When low, THRMTRIP# indicates that a thermal trip from the processor occurred; the ICH4 will immediately transition to a S5 state. The ICH4 will not wait for the processor stop grant cycle since the processor has overheated. S1 Sleep Control: SLP_S1# provides Clock Synthesizer or Power plane control. Optional use is to shut off power to non-critical systems when in the S1- M (Powered On Suspend), S3 (Suspend To RAM), S4 (Suspend to Disk) or S5 (Soft Off) states. S3 Sleep Control: SLP_S3# is for power plane control. It shuts off power to all non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk), or S5 (Soft Off) states. S4 Sleep Control: SLP_S4# is for power plane control. It shuts power to all non-critical systems when in the S4 (Suspend to Disk) or S5 (Soft Off) state. S5 Sleep Control: SLP_S5# is for power plane control. The signal is used to shut power off to all non-critical systems when in the S5 (Soft Off) states. Power OK: When asserted, PWROK is an indication to the ICH4 that core power and PCICLK have been stable for at least 1 ms. PWROK can be driven asynchronously. When PWROK is negated, the ICH4 asserts PCIRST#. NOTE: PWROK must deassert for a minimum of 3 RTC clock periods for the ICH4 to fully reset the power and properly generate the PCIRST# output Power Button: The Power Button causes SMI# or SCI to indicate a system request to go to a sleep state. If the system is already in a sleep state, this signal causes a wake event. If PWRBTN# is pressed for more than 4 seconds, this causes an unconditional transition (power button override) to the S5 state with only the PWRBTN# available as a wake event. Override occurs even if the system is in the S1-M–S4 states. This signal has an internal pull-up resistor. Ring Indicate: This signal is an input from the modem interface. It can be enabled as a wake event, and this is preserved across power failures. System Reset: This pin forces an internal reset after being debounced. The ICH4 will reset immediately if the SMBus is idle; otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle before forcing a reset on the system. Resume Well Reset: This signal is used for resetting the resume power plane logic. Signal Name Type Description LAN_RST# I SUS_STAT#/ LPCPD# O LAN Reset: This signal must be asserted at least 10 ms after the resume well power (VccLAN3_3 and VccLAN1_5 is valid. When deasserted, this signal is an indication that the resume well power is stable. Suspend Status: This signal is asserted by the ICH4 to indicate that the system will be entering a low power state soon. This can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. It can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered-off planes. This signal is called LPCPD# on the LPC I/F. C3_STAT#: This signal will typically be configured as C3_STAT#. It is used for indicating to an AGP device that a C3 state transition is beginning or ending. If C3_STAT# functionality is not required, this signal may be used as a GPO. NOTE: This signal will be asserted in S1-M on the ICH4-M. Suspend Clock: Output of the RTC generator circuit to use by other chips for refresh clock. AGP Bus Busy: To support the C3 state. This signal is an indication that the AGP device is busy. When this signal is asserted, the BM_STS bit will be set. If this functionality is not needed, this signal may be configured as a GPI. Stop PCI Clock: This signal is an output to the external clock generator for it to turn off the PCI clock. Used to support PCI CLKRUN# protocol. If this functionality is not needed, This signal can be configured as a GPO. Stop CPU Clock: Output to the external clock generator for it to turn off the processor clock. Used to support the C3 state. If this functionality is not needed, this signal can be configured as a GPO. Battery Low: This signal is an input from the battery to indicate that there is insufficient power to boot the system. Assertion will prevent wake from S1-M–S5 state. Can also be enabled to cause an SMI# when asserted. CPU Performance: CPUPERF# is used for Intel SpeedStep technology support. The signal selects which power state to put the processor in. SpeedStep Mux Select: SSMUXSEL is used for Intel SpeedStep technology support. The signal selects the voltage level for the processor. VGATE/VRM Power Good: VGATE/VRMPWRGD is used for Intel SpeedStep technology support. This is an output from the processor’s voltage regulator to indicate that the voltage is stable. This signal may go inactive during an Intel SpeedStep transition. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C C3_STAT# O SUSCLK O AGPBUSY# I STP_PCI# O STP_CPU# O BATLOW# I CPUPERF# OD SSMUXSEL O VGATE/ VRMPWRGD I 88 8050D N/B Maintenance 5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(6) Power Management Interface Signals (Continued) Signal Name DPRSLPVR Type Description O Deeper Sleep - Voltage Regulator: This signal is used to lower the voltage of VRM during C4 and S1-M states. When the signal is high, the voltage regulator outputs the lower “Deeper Sleep” voltage. When the signal is low (default), the voltage regulator outputs the higher “Normal” voltage. During PCIRST#, the output driver is disabled and an internal pull-down is enabled. This is needed for implementing a strap on the pin. When PCIRST# deasserts, the output driver is enabled. To guarantee no glitches on the DPRSLPVR pin, the pull-down is disabled after the output driver is fully enabled. NOTE: DPRSLPVR is sampled at the rising edge of PWROK as a functional strap. Processor Interface Signals Signal Name Type A20M# O CPUSLP# O FERR# INTR I O Processor Interface Signals (Continued) Signal Name IGNNE# Type Description O Ignore Numeric Error: This signal is connected to the ignore error pin on the processor. IGNNE# is only used if the ICH4 coprocessor error reporting function is enabled in the General Control Register (Device 31:Function 0, Offset D0, bit 13). If FERR# is active, indicating a coprocessor error, a write to the Coprocessor Error Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If FERR# is not asserted when the Coprocessor Error Register is written, the IGNNE# signal is not asserted. Speed Strap: During the reset sequence, ICH4 drives IGNNE# high if the corresponding bit is set in the FREQ_STRP register. Initialization: INIT# is asserted by the ICH4 for 16 PCI clocks to reset the processor. ICH4 can be configured to support CPU BIST. In that case, INIT# will be active when PCIRST# is active. Non-Maskable Interrupt: NMI is used to force a non-Maskable interrupt to the processor. The ICH4 can generate an NMI when either SERR# or IOCHK# is asserted. The processor detects an NMI when it detects a rising edge on NMI. NMI is reset by setting the corresponding NMI source enable/disable bit in the NMI Status and Control Register. Speed Strap: During the reset sequence, ICH4 drives NMI high if the corresponding bit is set in the FREQ_STRP register. System Management Interrupt: SMI# is an active low output synchronous to PCICLK. It is asserted by the ICH4 in response to one of many enabled hardware or software events. Stop Clock Request: STPCLK# is an active low output synchronous to PCICLK. It is asserted by the ICH4 in response to one of many hardware or software events. When the processor samples STPCLK# asserted, it responds by stopping its internal clock. Keyboard Controller Reset CPU: The keyboard controller can generate INIT# to the processor. This saves the external OR gate with the ICH4’s other sources of INIT#. When the ICH4 detects the assertion of this signal, INIT# is generated for 16 PCI clocks. NOTE: The ICH4 ignores RCIN# assertion during transitions to the S1-M, S3, S4 and S5 states. A20 Gate: A20GATE is from the keyboard controller. The signal acts as an alternative method to force the A20M# signal active. It saves the external OR gate needed with various other PCIsets. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C INIT# O NMI O SMI# O STPCLK# O RCIN# I A20GATE I Description Mask A20: A20M# will go active based on either setting the appropriate bit in the Port 92h register, or based on the A20GATE input being active. Speed Strap: During the reset sequence, ICH4 drives A20M# high if the corresponding bit is set in the FREQ_STRP register. CPU Sleep: This signal puts the processor into a state that saves substantial power compared to Stop-Grant state. However, during that time, no snoops occur. The ICH4 can optionally assert the CPUSLP# signal when going to the S1-M state. Numeric Coprocessor Error: This signal is tied to the coprocessor error signal on the processor. FERR# is only used if the ICH4 coprocessor error reporting function is enabled in the General Control Register (Device 31:Function 0, Offset D0, bit 13). If FERR# is asserted, the ICH4 generates an internal IRQ13 to its interrupt controller unit. It is also used to gate the IGNNE# signal to ensure that IGNNE# is not asserted to the processor unless FERR# is active. FERR# requires an external weak pull-up to ensure a high level when the coprocessor error function is disabled. NOTE: FERR# can be used in some states for notification by the processor of pending interrupt events. This functionality is independent of the General Control Register bit setting. CPU Interrupt: INTR is asserted by the ICH4 to signal the processor that an interrupt request is pending and needs to be serviced. It is an asynchronous output and normally driven low. Speed Strap: During the reset sequence, ICH4 drives INTR high if the corresponding bit is set in the FREQ_STRP register. 89 8050D N/B Maintenance 5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(7) Processor Interface Signals (Continued) Signal Name CPUPWRGD DPSLP# Description OD CPU Power Good: This signal should be connected to the processor’s PWRGOOD input. To allow for Intel ® SpeedStep™ technology support, this signal is kept high during an Intel SpeedStep technology state transition to prevent loss of processor context. This is an open-drain output signal (external pull-up resistor required) that represents a logical AND of the ICH4’s PWROK and VGATE / VRMPWRGD signals. Deeper Sleep: This signal is asserted by the ICH4 to the processor. When the signal is low, the processor enters the Deeper Sleep state by gating off the processor Core clock inside the processor. When the signal is high (default), the processor is not in the Deeper Sleep state. This signal behaves identically to the STP_CPU# signal, but at the processor voltage level. O SMBus Interface Signals Signal Name Real Time Clock Interface Signals Type Type Description I/OD SMBus Data: External pull-up is required. SMBCLK I/OD SMBus Clock: External pull-up is required. I Type INTRUDER# I SMLINK[1:0] I/OD Description RTCX1 Special Crystal Input 1: This signal is connected to the 32.768 kHz crystal. RTCX2 Special Crystal Input 2: This signal is connected to the 32.768 kHz crystal. Other Clock Signals Signal Name Type Description CLK14 I CLK48 I CLK66 I Oscillator Clock: Used for 8254 timers. It runs at 14.31818 MHz. This clock is permitted to stop during S1-M (or lower) states. 48 MHz Clock: This clock is used to run the USB controller. It runs at 48 MHz. This clock is permitted to stop during S1-M (or lower) states. 66 MHz Clock: This is used to run the hub interface. It runs at 66 MHz. This clock is permitted to stop during S1-M (or lower) states. Miscellaneous Signals Type Description SPKR Signal Name O RTCRST# I Speaker: The SPKR signal is the output of counter 2 and is internally “ANDed” with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external speaker driver device, which in turn drives the system speaker. Upon PCIRST#, its output state is 0. NOTE: SPKR is sampled at the rising edge of PWROK as a functional strap. RTC Reset: When asserted, this signal resets register bits in the RTC well and sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3 register). NOTES: 1. Clearing CMOS in an ICH4-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. 2. Unless entering the XOR Chain Test Mode, the RTCRST# input must always be high when all other RTC power planes are on. SMBus Alert: This signal is used to wake the system or generate SMI#. If not used for SMBALERT#, it can be used as a GPI. System Management Interface Signals Signal Name Type t t n e e r c m e u S c c Do a iT ial M t n e id f n o C SMBDATA SMBALERT#/ GPIO[11] Signal Name Description Intruder Detect: Can be set to disable system if box detected open. This signal’s status is readable, so it can be used like a GPI if the Intruder Detection is not needed. System Management Link: SMBus link to optional external system management ASIC or LAN controller. External pull-ups are required. Note that SMLINK[0] corresponds to an SMBus Clock signal, and SMLINK[1] corresponds to an SMBus Data signal. 90 8050D N/B Maintenance 5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)(8) AC’97 Link Signals Signal Name Power and Ground Signals Type Description AC ’97 Reset: This signal is a master hardware reset to external Codec(s). O AC ’97 Sync: This signal is a 48 kHz fixed rate sample sync to the AC_SYNC Codec(s). I AC97 Bit Clock: This signal is a 12.288 MHz serial data clock AC_BIT_CLK generated by the external Codec(s). This signal has an integrated pull-down resistor. O AC97 Serial Data Out: Serial TDM data output to the Codec(s). AC_SDOUT NOTE: AC_SDOUT is sampled at the rising edge of PWROK as a functional strap. I AC97 Serial Data In 2:0: These signals are Serial TDM data inputs AC_SDIN[1:0] from the three Codecs. NOTE: An integrated pull-down resistor on AC_BIT_CLK is enabled when either: The ACLINK Shutoff bit in the AC’97 Global Control Register is set to 1, or Both Function 5 and Function 6 of Device 31 are disabled. Otherwise, the integrated pull-down resistor is disabled. AC_RST# O Signal Name VCC3_3 VCC1_5 VCCHI Signal Name GPIO[43:32] GPIO[31:29] GPIO[28:27] GPIO[26] GPIO[25] GPIO[24:18] Type I/O O I/O I/O I/O I/O HIREF VCCSUS3_3 O Description Can be input or output. Main power well. Not implemented. Can be input or output. Resume power well. Unmuxed. Not implemented. Can be input or output. Resume power well. Unmuxed. Not Implemented in Mobile (Assign to native Functionality). Fixed as Output only. Main power well. Can be used instead as PC/PCI GNT[A:B]#. GPIO[17] can also alternatively be used for PCI GNT[5]#. Integrated pull-up resistor. I Not implemented. GPIO[15:14] I Fixed as Input only. Resume power well. Unmuxed. GPIO[13:12] I Fixed as Input only. Resume power well. Can be used instead as GPIO[11] SMBALERT#. I Not implemented. GPIO[10:9] Fixed as Input only. Resume power well. Unmuxed. I GPIO[8] Fixed as Input only. Main power well. Unmuxed. I GPIO[7] Not Implemented in Mobile (Assign to Native Functionality) I GPIO[6] I Fixed as Input only. Main power well. Can be used instead as GPIO[5:2] PIRQ[E:H]#. I Fixed as Input only. Main power well. Can be used instead as GPIO[1:0] PC/PCI REQ[A:B]#. GPIO[1] can also alternatively be used for PCI REQ[5]#. NOTE: Main power well GPIO are 5V tolerant, except for GPIO[43:32]. Resume power well GPIO are not 5V tolerant. GPIO[17:16] 3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5 or G3 states. 1.5 V supply for core well logic. This power may be shut off in S3, S4, S5 or G3 states. 1.5 V supply for Hub Interface 1.5 logic. 1.8 V supply for Hub Interface 1.0 logic. This power may be shut off in S3, S4, S5 or G3 states. Reference for 5 V tolerance on core well inputs. This power may be shut off in S3, S4, S5 or G3 states. Analog Input. Expected voltages are: • 0.9 V for HI 1.0 (Normal Hub Interface) Series Termination • 350 mV for HI 1.5 (Enhanced Hub Interface) Parallel Termination This power is shut off in S3, S4, S5, and G3 states. 3.3 V supply for resume well I/O buffers. This power is not expected to be shut off unless the main battery is removed or completely drained and AC power is not available. 1.5 V supply for resume well logic. This power is not expected to be shut off unless the main battery is removed or completely drained and AC power is not available. Reference for 5 V tolerance on resume well inputs. This power is not expected to be shut off unless the main battery is removed or completely drained and AC power is not available. 3.3 V supply for LAN Connect interface buffers. This is a separate power plane that may or may not be powered in S3–S5 states depending upon the presence or absence of AC power and network connectivity. This plane must be on in S0 and S1-M. 1.5 V supply for LAN Controller logic. This is a separate power plane that may or may not be powered in S3–S5 states depending upon the presence or absence of AC power and network connectivity. This plane must be on in S0 and S1-M. 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power is not expected to be shut off unless the RTC battery is removed or completely drained. NOTE: Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Clearing CMOS in an ICH4-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. 1.5 V supply for core well logic. This signal is used for the USB PLL. This power may be shut off in S3, S4, S5 or G3 states. RTC well bias voltage. The DC reference voltage applied to this pin sets a current that is mirrored throughout the oscillator and buffer circuitry. Powered by the same supply as the processor I/O voltage. This supply is used to drive the processor interface outputs. Grounds. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C V5REF VCCSUS1_5 General Purpose I/O Signals Description V5REF_SUS VCCLAN3_3 VCCLAN1_5 VCCRTC VCCPLL VBIAS V_CPU_IO VSS 91 8050D N/B Maintenance 6. System Block Diagram U713 INTEL BANIAS/DOTHAN Host 400MHZ J6 Card Reader Socket Mini PCI Card Socket IEEE 1394 HDD CD-ROM USB2.0 U727 PCMCIA CARD READER CB710 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C U714 DDR 266 U719 RTL8100CL North Bridge 855GME LVDS LCD U710 AGP J711 CRT RGB TV ATI-M10 66MHZ Amplifier TPA0212 MIC PCI BUS U715 AC 97 ICH4-M U726 AUDIO CODEC ALC655 Speaker U524 HP/OPT Jack Subwoofer Line In MDC RJ11 LPC BUS U15 FWH BIOS U16 Internal KB WINBOND W83L950D Touch Pad FAN 92 8050D N/B Maintenance 7. Maintenance Diagnostics 7.1 Introduction Each time the computer is turned on, the system BIOS runs a series of internal checks on the hardware. This power-on self test (post) allows the computer to detect problems as early as the power-on stage. Error messages of post can alert you to the problems of your computer.If an error is detected during these tests, you will see an error message displayed on the screen. If the error occurs before the display is initialized, then the screen cannot display the error message. Error codes or system beeps are used to identify a post error that occurs when the screen is not available. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C The value for the diagnostic port is written at the beginning of the test. Therefore, if the test failed, the user can determine where the problem occurred by reading the last value written to the port by the debug card plug at MINI PCI slot. 93 8050D N/B Maintenance 7.2 Diagnostic Tool for Mini PCI Slot : The Mini PCI DOG killer card is a single-step debug tool which utilizes Mini PCI interface (Type III A) and is able to hold a PCI bus cycle so that address, data and control bus states on PCI bus can be inspected. Especially, the tool can help an engineer trace address/data bus for BIOS read cycles as soon as power on and debug open or short circuit problems easily. Usually, this sort of problem will make a PC motherboard fail to boot. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C P/N:411906900001 Description: PWA-MPDOG;MINI PCI DOGKELLER CARD Note: Order it from MIC/TSSC 94 8050D N/B Maintenance 7.3 Error Codes - 1 Following is a list of error codes in sequent display on the debug board. POST (HEX) DESCRIPTION POST (HEX) DESCRIPTION 00h Boot started 17H Size Memory 01h Disable A20 through A20 18H Dispatch To RAM Test 02h Initialize CS 19H checksum the ROM 03h Test RAM 1AH Reset PIC's 04h Move BL into the RAM 1BH Initialize Video Adapter(s) 05h Execution in RAM 1CH Initialize Video (6845 Regs) 06h Check OVERRIDE option 1DH Initialize Color Adapter 07h Shadow System BIOS 1EH Initialize Monochrome Adapter 08h Checksum System BIOS ROM 1FH Test 8237A Page Registers 09h Proceed with Normal Boot 20H Test Keyboard 0Ah Proceed with Crisis Boot 21H Test Keyboard Controller 0Fh Fatal Error 22H Check If CMOS Ram Valid F0h .... - No RAM 23H Test Battery Fail & CMOS X-SUM F1h ..._ - RAM test failed 24H Test the DMA controllers 99h Resume SMRAM not Found 25H Initialize 8237A Controller 10H Some Type Of Long Reset 26H Initialize Int Vectors 11H Turn off FASTA20 for POST 27H RAM Quick Sizing 12H Signal Power On Reset 28H Protected mode entered safely 13H Initialize the Chipset 29H RAM test completed 14H Search For ISA Bus VGA Adapter 2AH Protected mode exit successful 15H Reset Counter/Timer 1 2BH Setup Shadow 16H user register config through CMOS 2CH Going To Initialize Video t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 95 8050D N/B Maintenance 7.3 Error Codes - 2 Following is a list of error codes in sequent display on the debug board. POST (HEX) DESCRIPTION POST (HEX) DESCRIPTION 2DH Search For Monochrome Adapter 42H Initialize the hard disk 2EH Search For Color Adapter 43H Initialize option ROMs 2FH Signon messages displayed 44H OEM's init of power management 30H special init of keyboard ctlr 45H Update NUMLOCK status 31H Test If Keyboard Present 46H Test For Coprocessor Installed 32H Test Keyboard Interrupt 47H OEM functions before boot 33H Test Keyboard Command Byte 48H Dispatch To Op. Sys. Boot 34H TEST, Blank and count all RAM 49H Jump Into Bootstrap Code 35H Protected mode entered safely (2). 50H ACPI INIT 36H RAM test complete 51H PM INIT & GEYSERVILLE CPU INIT 37H Protected mode exit successful 52H USB HC INIT 38H Update OUTPUT port F8H PXE BIOS decomp error 39H Setup Cache Controller F9H PCI BIOS decomp error 3AH Test If 18.2Hz Periodic Working FAH PNP BIOS decomp error 3BH test for RTC ticking FBH LOGO BIOS decomp error 3CH initialize the hardware vectors FCH LOGO Image decomp error 3DH Search and Init the Mouse FDH Energy Image decomp error 3EH Update NUMLOCK status FEH ROMDEBUG Image decomp error 3FH special init of COMM and LPT ports 88H PM code decomp error 40H Configure the COMM and LPT ports CAH CPU SMM remap code 41H Initialize the floppies CBH CPU SMM BASE remap Done t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 96 8050D N/B Maintenance 7.3 Error Codes - 3 Following is a list of error codes in sequent display on the debug board. POST (HEX) DESCRIPTION POST (HEX) DESCRIPTION D0H check rom signature, 1.x video E5H disable add-in rom card decode D1H enable RAM area in regs E6H PCI return(config and no video) D2H copy ROM to RAM in regs E7H look for PCI bridge device D3H update segment range attr E8H search IDE controllers on the PCI bus D4H configure memory registers E9H start of cardbus config D5H configure I/O registers A1H Enable/Verify R/W Status Runtime Data D6H configure IRQ assignments A2H Get/Verrify R/W Stattus NVRAM data area D7H turn on PCI device A3H Resolve System Nodes with the CMOS settings D8H 2.x video r/w segment A4H Init. var. in the PNP BIOS Runtime Data area D9H OEM defined, rom init A5H Hook INT 15 DAH disable add-in rom card decode A6H copy/setup $PnP Install Check in F0000 seg. DBH PCI return(config and no video) A7H Allow the OEM any Last Minute Hooks DCH enable RAM area in regs A8H Write protect RTData Area & NVRAM Copy Buffer DDH copy ROM to RAM in regs A9H return from pnp_init proc DEH update segment range attr DFH configure memory registers E0H configure I/O registers E1H configure IRQ assignments E2H turn on PCI device E3H 2.x video r/w segment E4H OEM defined, rom init t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 97 8050D N/B Maintenance 8. Trouble Shooting 8.1 No Power 8.9 CD-ROM Driver Test Error 8.2 Battery Can not Be Charged 8.10 Audio Failure t t n e 8.11eLAN Test Error 8.3 No Display r c m e S cu8.12 Modem Test Error 8.4 External Monitor No Display c o a D T l i a 8.5 Memory Test Error M 8.13 MINI-PCI Test Error i t n e 8.6 Keyboard/Touch pad Test Error 8.14 Card Bus&Reader Test Error d i f n o 8.7 USB Port Test 8.15 IEEE 1394 Failure CError 8.8 Hard Disk Drive Test Error 98 8050D N/B Maintenance 8.1 No Power When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up. P32 PF1 Power In PJ 701 P32 PD702 P25 U11 PWR_VDDIN PL1 PL2 PR701 VDD5 P25 F3,U13 P32 PQ701 PD704 P25 Q13 VDD5S Q48 P25 Q51,L71 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C VDD3_AVREF VDD3 P25 U6 VDD3S P25 VDD1.5 Q43 ADINP PF703 PL708 PU7 PQ707 P32 PD703 DVMAIN PL710 PD709 PD713 PQ704 P33 PD704 Charge P32 Battery Discharge JS704 PL703 PU2 PL701 PU702 PR711 P27 JS711,JS713,JS715 +3VS-P PR707 PU701 U707,Q701 +3VS L706,L707 L743 P27 PL702 P24 P24 +5VS_P JS718,JS719,JS721 U701 L701 U704,L70 3 L704,Q10 NOTE:. P27 Page on M/B board circuit diagram. PU3,PU9,PU10,PU11 PU12,PU13,PL711, PD718,PR740 L746 +3V P18 1394_AVCC P25 +PHYVDD P15 L702 +5VS U705,L708 P25 +VCC_USB_0 +VCC_USB_1 +VCC_USB_2 P25 U728 +5V P17 +CARD_VCC U18 P20 VA P31 +VCC_CORE To Next Page 99 8050D N/B Maintenance 8.1 No Power When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up. Continue To Previous Page P27 DVMAIN JS706,PL712 PU14 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C PU705,PL713,PR739 P29 JS71,JS717 +1.8V_P PU707,PL714,PR741 P29 JS72,JS722 +1.35V_P JS10,PL3 PU703 PU6,PL707,PR732 P28 P28 JS728,JS729,JS730 PU15 PU709,PL717,PR744 PU708,PL715,PR742 P26 +1.25V_DDR_P P26 +2.5VS_DDR_P P24 +VCCP JS72,JS725 +1.5V_P JS703,PL716 P5 +1.35V +1.05V_P PU4,PL706,PR719 P24 +1.8V P24 +1.5V JS1,JS12 JS708,JS709,JS710 P24 +1.25V_DDR P24 +2.5VS_DDR L732 P16 DVDD 100 8050D N/B Maintenance 8.1 No Power When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up. No power AC POWER Is the Notebook connected to power (Either AC adaptor or battery)? Yes t t n e e r c m e u S c c Do a iT ial M t n e id f n o C No Connect AC adaptor or battery Where From Power Source Problem(First use AC to power it) Please try another known good battery or AC adapter. Power OK? NO Check following parts and signals: Parts: Signals: Yes Please replace the faulty AC adaptor or Battery. PF1 ALWAYS PL1 DVMAIN PL2 ADEN# PD702 BATT_DEAD PQ701 BATTERY Check following parts and signals: Parts: Signals: J703 BATT PF702 PQ6 Board-level Troubleshooting PQ704 PL704 PL705 101 8050D N/B Maintenance 8.1 No Power(1) When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up. PL1 PJ701 PF1 7A/24VDC PL2 120Z/100M t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 120Z/100M PR701 PD702 BAV70LT1 PWR_VDDIN .01 PD701 RLZ24D PD704 BAV70LT1 To chapter 8.2 ADINP PQ701 AO4407 5 H8_I_LIMIT 23 LEARNING R428 P22 0 I_LIMIT PR1 10 6 P32 VCC RS- GND1 OUT GND0 3 2 PR702 470K G 1 2 D21 RLS4148 100K PR71 226K PQ704 G AO4407 D 8 7 6 5 14 PR720 PR703 100K PR705 1M WINBOND KBC DVMAIN 3 D PQ702 2N7002 U16 PD703 SBM1040 3 2 1 76 RS+ 1 S 4 S 3 2 1 PU1 8 7 6 5 PR45 33K BATT PQ6 2N7002 ADEN# PQ24 DTC144WK 102 8050D N/B Maintenance 8.1 No Power(2) When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up. PD704 BAV70LT1 VDD3S PF702 7A/24VDC t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 4 PL705 120Z/100M 3 2 1 8 7 6 5 BATT PQ704 AO4407 PWR_VDDIN PR720 100K DVMAIN PL704 120Z/100M PR20 4.99K P32 J703 BATTCONNECTOR 7 6 5 4 3 2 1 PR716 499K PC722 0.01U PR714 100K RP45 22*4 BAT_V 8 1 78 BAT_T 7 2 77 P22 U16 PR23 0 BAT_C 6 3 2 PR24 0 BAT_D 5 4 3 PR45 33K 14 ADEN# D21 RLS4148 PQ6 2N7002 WINBOND KBC PD2 BAV99 VDD3 PD3 BAV99 103 8050D N/B Maintenance 8.2 Battery Can not Be Charged There are problems in charging the battery. Battery can not Charge Is the notebook connected to power (AC adaptor)? t t n e e r c m e u S c c Do a iT ial M t n e id f n o C No Board-level Troubleshooting Connect AC adaptor. Check following parts and signals: Yes Replace Motherboard 1. Make sure that the battery is good. 2. Make sure that the battery is installed properly. Battery charge OK? Yes Please replace the faulty Battery. Parts PF703 PL708 PQ707 PL710 PD713 PD714 PD709 PQ13 PQ14 PU7 PQ15 PD5 PR65 Signal PR70 PQ11 PC33 PR63 PU5 PR74 PR75 PR76 PQ12 ADINP CHANGING BATT BAT_V BAT_T BAT_C BAT_D BATT_DEAD I_CTRL No 104 8050D N/B Maintenance 8.2 Battery Can not Be Charged There are problems in charging the battery. PQ707 AO4407 PL708 BEAD_120Z/100M 3 2 1 ADINP G PD713 EC31QS04 PR86 0 BATT PR88 4.7K PQ15 MMBT2222A PC39 1000P PD709 BZV55C15V PD714 EC31QS04 PR89 100K CHARGING PR76 249K PC48 0.01U CHARGING 11 10 U16 15 WINBOND KBC R483 0 I_CTRL C2 12 VCC 13 P22 PR78 0 PQ12 2N7002 From U16 PQ14 2N7002 PR79 124K 2 P33 C1 21IN+ PR75 20K PR74 13.7K PD5 BAS32L 26 Reference chapter 8.1(1) D t t n e e r c m e u S c c Do a iT ial M t n e id f n o C PR87 4.7K PQ13 DTA144WK PL709 3.0UH PL710 33UH 8 7 6 5 S PF703 TR/3216FF-3A From chapter 8.1(1) 8 16 21N+ PU7 TL594C BATT_DEAD# DVMAIN VDD5 Reference chapter 8.1(2) 78 77 2 3 PR69 100K BAT_V BAT_T BAT_C Q39 DTC144TKA =8.56V BATT_DEAD PC36 0.01U + 7 PU5 LMV393M BAT_D 8 - PR65 590K 5 PR70 3.3K 1.25V 6 PQ11 SCK431LCSK-.5 4 PR63 80.6K PC33 0.1U 105 8050D N/B Maintenance 8.3 No Display There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good. No Display Monitor or LCD module OK? No Yes Make sure that CPU module, DIMM memory are installed Properly. Display OK? Yes No t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Replace monitor or LCD. Replace Motherboard Correct it. 1.Try another known good CPU module, DIMM module and BIOS. 2.Remove all of I/O device (FDD, HDD, CD-ROM…….) from motherboard except LCD or monitor. Display OK? No Yes Board-level Troubleshooting Using debug card,depending on the error codes to make sure which parts maybe faulty Using circuit diagram ,check the faulty parts 1. Replace faulty part. 2. Connect the I/O device to the M/B one at a time to find out which part is causing the problem. 106 8050D N/B Maintenance 8.3 No Display(1) ****** System Clock Check ****** +3V 4.7K R860 +3V R863 8.2K L722 120Z/100M L726 120Z/100M L43 120Z/100M L718 120Z/100M 44,45 54 FS0 FS1 R863 4.7K 55 FS2 R894 4.7K 40 1,26,37 CLKANA CLK66 19,32 CLKCPU 46,50 CLKPCI 8,14 2 P11 ICS950810 C804 27P +3V 33*4 R816 33 39 R895 33 7 56 R821 0 0 HCLK_MCH HCLK_MCH# 28 VTT_PWRGD# 13 PCICLK_ICH R858 14M_ICH R859 33 33 VCCP_PWRGD PR717 P28 0 27 0 14M_CODEC P13 P14 001 FS1 FS0 CPU P20 U726 PCICLK_CARD P17 U727 PCICLK_LAN P16 U719 SMBCLK SMBDATA 16 R828 33 PCICLK_1394 10 R825 33 PCICLK_FWH PU703 LTC3728L x 0 1 100.00 0:00 1:3.3V 17 R817 33 MINI PCICK_KBC ICH4_M U715 AUDIO CODEC CARDBUS READER LAN P6 DDR J711 SODIMM IEEE P18 U724 1394 P23 U15 FS2 NB J713 -PCI 33 R827 CPU MINIPCI_SIO48M USBCLK_ICH 33 P5 P19 0 33 R826 P4 PCICLK_MINIPCI 33 R472 P3 U714 R824 29,30 PR57 48M_DREFCLK 66M_DEFSSCLK R831 10K PR715 100K PR59 1M R1137 P2 U713 R877 +3VS_P PQ8 2N7002 HCLK_CPU# C794 27P 12 CORE_CLKEN# R865 R872 R873 R878 11 Clock Generator 3 PR56 0 HCLK_CPU 43 X703 14.318MHZ PR731 2K 33*2 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 35,38 48,49 U712 +3V R874 R875 P22 U16 BIOS SYS WINBOND KBC UNIT:MHZ 107 8050D N/B Maintenance 8.3 No Display(2) ****** System Reset Check ****** U10 P25 MAX809 R7 1K +3VS 1 PWRBTN# 18 P26 P27 P31 H8_PWRON P22 U16 TC010-PSS11CET 3 MN RESET 4 2 H8_RESET# 25 WINBOND KBC VDD3 R531 10K U21 IMP811 P25 VCC +3V 3 VCC RESET# Convert 2 PWROK GND SW2 Power Module t t n e e r c m e u S c c Do a iT ial M t n e id f n o C ICH_PWRBTN HPWRGD +VCCP 1 Q31 Convert to R301 330 P13 RSMRST# P14 P4 8 Q42 FDV301N H8_RSMRST ICH_VGATE U715 VRMPWRGD J714 J708 CDROM HDD CONNECTOR CONNECTOR ICH_PWRBTN# 10K R492 Q49 Q41 DTC144TKA R909 0 5 ICH4_M SUSB# Convert to +3V U9A PCIRST#0 855GM /GME JL3 1 PCIRST# 3 74AHC08_V RSTDRV2# P18 92 1394_PCIRST# JL1 4 MINIPCI CONNECTOR 26 JL7 KBC_PCIRST# JL6 LAN_PCIRST# P22 64 5 MINIPCI_PCIRST# FWH_PCIRST# U16 WINBOND KBC +3V JL8 P16 U9C 2 JL9 9 7 8 27 U719 LAN Controller RTL8100CL 74AHC08_V P11 U2 TV_CARD CH7011A JL5 74AHC08_V P19 J713 P23 MCH_PCIRST# U9B 6 CARD_PCIRST# JL4 +3V U724 1394 VT6307L U727 CARDBUS READER SST49LFOO4A NORTH BRIDGE 2 P17 U15 BIOS R476 10K Q37 DTC144TKA P15 P5 U714 U9D +5V RSTDRV1# U713 BANIAS HPWRGD W83L950D 44 P3 +3V H8_SUSB P15 P2 PWROK LTC3728L 7 HCPURST# 13 TV_PCIRST# JL10 108 8050D N/B Maintenance 8.3 No Display(3) ****** VGA Controller Checking ****** AGP_ VREF R120 C146 10U C149 0.01U 1.02K R16 AGP_VDDQ 1M F1 2A +3V R110 1.02K t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Q9 SI4835DY 3 2 1 47K R104 10K S R140 +3V R19 10K G D 0 ENAVDD R20 0 2N7002 8 7 6 5 Q11 R752 C14 0.22U +3V P7 L15 120Z/100M 1,2,3 R11~R14 10K*4 6,7,10,14 PANEL_ID[0..3] U710 TXCLK-_ATI R160 0 TXCLK- 15 TXCLK+_ATI R161 0 TXCLK+ 13 TXOUT0-_ATI R153 0 TXOUT0- 28 TXOUT0+_ATI R154 0 TXOUT0+ 26 TXOUT1-_ATI R158 0 TXOUT1- 22 TXOUT1+_ATI R159 0 TXOUT1+ 20 TXOUT2-_ATI R794 0 TXOUT2- 27 TXOUT2+_ATI R795 0 TXOUT2+ 25 TXOUT3-_ATI R796 0 TXOUT3- 21 TXOUT3+_ATI R797 0 TXOUT3+ 19 R819 33 66M_AGP J2 LCD CONNECTOR ATI-M10 P12 P11 23 U712 CLK-GEN 109 8050D N/B Maintenance 8.3 No Display(4) ****** Back Light & Cover Switch Checking ****** +3V To U715 in this page R372 10K PWROK U714 855GM D15 BAT54 R386 DVMAIN VDD3S P22 11 H8_ENABKL BLADJ 35 BATT_R# 36 79 BATT_G# AC_POWER# R383 0 D16 BAT54 ENABKL_VGA R5 BATT_POWER# U16 R323 0 ENABKL_VGA_C 0 +3VS U703D 74AHC14_V L17 120Z/100M 1,2 L18 120Z/100M 3 P12 120Z/100M L10 4 J1 120Z/100M L9 6 8 1 8 7 6 2 3 9 10 5 4 R468 WINBOND KBC U710 ATI-M10 BAT54 R380 10K 27 P7 0 11 0 +3VS +3VS U703C 74AHC14_V U703B 74AHC14_V Q720 DTC114TKA Q719 DTC114TKA SUSB# P13 C947 4.7U R1152 13 BATT_LED# 1M Inverter t t n e e r c m e u S c c Do a iT ial M t n e id f n o C D2 +3V P4 R1140 U715 180K PWROK ICH4-M +3VS R373 470K 16 H8_LIDSW# R1152 1M SW1 R3 C385 0.1U 1K 30V/0.1A 110 8050D N/B Maintenance 8.3 No Display(5) CPU Core does not exist . DD_CPU DVMAIN PF2 7A/24VDC PL5 120Z/100M S1+ PL4 120Z/100M PR5 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C PR4 10K 31 G S S 4 P31 D 21 D PU12 FDS6694 G S PR44 VID2 PR40 VID3 PR34 VID4 PR33 VID5 PR31 0 13 0 14 0 15 0 17 0 18 0 19 VOS- PR28 1000P 576K PR30 100K LTC3734 22 +5VS_P PR29 PR38 10 S1- 30 2 S1+ 0.1U PC13 10U PQ9 MMBT3904L PR59 PR731 2K R831 10K U712 CLKGEN 6 28 R821 PR56 0 0 13.3K PC15 100P DVMAIN +2.5VS_DDR 1 P26 PR15 56.2k 8 PU15 PR16 1.3M 9 PR43 499K PR17 12.7K 11 PR57 +VCC_PWRGD 0 VOS- P28 TO PU703 LTC3728L PQ8 2N7002 S PD4 BAT54C 2 PR58 4.12K ICS950810 28 G D PC11 220P PR19 1M 0 +3V 3 P11 PR104 +3V 12 7 PC21 1000P PC12 PR729 249K From Left 13.3K PR37 10 PD718 EC31QS04-TE12L S PU3 +3VS PC18 PU11 FDS6694 3 2 1 PR52 VID1 3 2 1 U713 CPU BANIAS VID0 +VCC_CORE G S 3 2 1 P3 D PU13 FDS6694 G PR740 0.001 8 7 6 5 0 8 7 6 5 PR32 STOP_CPU# PL711 0.68UH 23 8 7 6 5 P13 U715 ICH4_M S1- 3 2 1 29 3 2 1 10 D G 24 +5VS_P PU10 FDS6694 8 7 6 5 8 7 6 5 PU9 FDS6694 D R251 220K PR60 43.2K VDD5 3 1 PQ10 MMBT3904L Q19 2N7002 PR49 100K +3VS PR61 0 PQ5 2N7002 PQ7 2N7002 PR50 1M PC28 3300P PWRON_SUSB# LTC3728L 10 RUN/SS To Pin12 111 8050D N/B Maintenance 8.4 External Monitor No Display There is no display or picture abnormal on CRT monitor, but LCD can normally display. External Monitor No Display 1. Confirm monitor is good and check the cable are connected properly. 2. Try another known good monitor. Display OK? Yes t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Board-level Troubleshooting Yes Re-soldering. No Check following parts and signals: Replace faulty monitor. Replace Motherboard No Check if J702 are cold solder? Parts: U715 R6 R10 R785 R138 R136 R137 R783 R135 R139 Q5 Q6 Q7 Q8 L12 L13 L11 L7 Signals: CRT_IN# DDCK DDDA HSYNC VCYNC RED GREEN BLUE 112 8050D N/B Maintenance 8.4 External Monitor No Display There is no display or picture abnormal on CRT monitor, but LCD can normally display. +5V_H ATI_CRT_DDCK R6 4.7K R10 4.7K t t n e e r c m e u S c c Do a iT ial M t n e id f n o C R785 R703 0 R1 0 +5V_H Q6 2N7002 0 L12 120Z/100M CHAGND GND +3V ATI_CRT_DDDA R138 Q5 2N7002 0 R804 8.2K P7 P13 +5V_H ATI_CRT_VSYNC U710 ATI_CRT_HSYNC ATI_M10 ATI_CRT_GREEN ATI_CRT_BLUE Q7 2N7002 0 CRT_IN# 0 R783 0 L58 220Z/100M R135 0 L59 220Z/100M R139 0 L60 220Z/100M 1K 14 J702 L7 120Z/100M L74 5 P12 L11 120Z/100M Q8 2N7002 R137 R9 13 1 2 3 12 120Z/100M CRT CONNECTOR ATI_CRT_RED R136 U715 ICH 15 L13 BEAD_600Z/100M 6,7,8,16,17 CHAGND 113 8050D N/B Maintenance 8.5 Memory Test Error Either on board or extend SDRAM is failure or system hangs up. Memory Test Error t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 1.If your system installed with expansion SO-DIMM module then check them for proper installation. 2.Make sure that your SO-DIMM sockets are OK. 3.Then try another known good SO-DIMM modules. Test OK? No Yes If your system host bus clock running at 100MHZ then make sure that SO-DIMM module meet require of DDR 333. Board-level Troubleshooting Replace the faulty SDRAM module. Replace Motherboard No Replace the faulty SDRAM module. Check following parts and signals Parts: Signals: U714 J711 J712 U712 R979 R1040 R1030 R1031 R1011 R1016 R948 R949 R950 R955 R340 C337 C346 MD[0..63] SMBCLK SMBDATA DQS[0..7] DM[0..7] MCB[0..7] MA0 MA3 MA[6..12] WE# CAS# RAS# BA[0,1] NB_DM8 NB_DQS8 CLK_DDR[0..5] CLK_DDR[0..5]# Yes 114 8050D N/B Maintenance 8.5 Memory Test Error Either on board or extend SDRAM is failure or system hangs up. +3V +1.25V_DDR R340 75 RP29~RP43 56*8 NB_MD[0..63] NB_DQS[0..7] NB_DM[0..7] P4 P5 NB_CB[0..7] NB_MA0 NB_MA3 NB_MA[6..12] U714 NB NB_WE# NB_RAS# NB_CAS# NB_BA[0,1] SMA [1,2] SMA[4,5] SMAB[1,2] SMAB [4,5] CKE [0~3] CS# [0,1] NB_DM8 NB_DQS8 NB_CLK_DDR[0..5] NB_CLK_DDR[0..5]# P11 29 U712 CLOCK GENERATOR 30 ICH4-M 10 MD[0..63] R1011,R1016.. 10 DQS[0..7] R950,R955.. 10 DM[0..7] R977,R978.. 10 R972~R975 R1032~R1036 R969~R971 R1030 R1031 10 10 WE# RAS# 10 R1040 10 10*12 SMB_DATA SMB_CLK R318 2.2K P6 MCB[0..7] MA0 MA[6..12] R979 R335~R338 R319 R359 R1103~R1106 R320 R360 R315 2.2K C346 0.1U R948,R949… VDD3S P13 U715 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C C337 0.01U MA3 J711 CAS# BA[0,1] & J712 NB_DM8 NB_DQS8 NB_CLK_DDR[0..5] NB_CLK_DDR[0..5]# SMBDATA 193 SMBCLK 195 DDR-SODIMM 855GM /GME 197 +2.5VS_DDR +3V Q21 2N7002 R316 10K Q22 2N7002 R317 10K 0.6MM/200P /H5.2 115 8050D N/B Maintenance 8.6 Keyboard (K/B) /Touch-Pad (T/P) Test Error Error message of keyboard or touch-pad failure is shown or any key does not work. Keyboard or Touch-Pad Test Error t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Check U16, J4,J5 for cold solder? Is K/B or T/P cable connected to notebook properly? No Yes Correct it. Board-level Troubleshooting Replace Motherboard No Re-soldering No Check following parts and signals: Try another known good Keyboard or Touch-pad. Test Ok? Yes Yes Replace the faulty Keyboard or Touch-Pad Parts Signals U16 U715 F701 L716 L36 L37 R132 R151 J4 J5 VDD3 VDD_AVREF KBC X+ KBC XH8/T_CLK H8/T_DATA KI[0:7] KO[0:15] PWRBTN# KBD_US/JP# 116 8050D N/B Maintenance 8.6 Keyboard (K/B) /Touch-Pad (T/P) Test Error Error message of keyboard or touch-pad failure is shown or any key does not work. VDD3_AVREF R414 F701 0.5A/POLYSW 72 0 +5V VDD3 6 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 71 C445 0.1U L716 120Z/100M C448 0.1U C449 10U 9 T_DATA L36 120Z/100M 5 6 T_CLK L37 120Z/100M 4 30 SW4 SW_LEFT R132 0 3 SW_RIGHT R151 0 2 P22 P11 17 PCICK_KBC U712 CLKGEN R817 33 PCICLK_KBC 70 SW5 GND VDD3 R392 8.2K P13 U9 LAD[0..3] 65~68 KBC_PCIRST# 64 LFRAME# H8_SUSB ICH4_M SUSB# RP44 4.7K*8 69 SERIRQ U715 WINBOND KBC Q49 DTC144TKA J4 1 U16 +3V P23 55~62 KI 0~7 39~54 KO 0~15 29 KBC_X- 28 KBC_X+ 1 C447 22P 1~16 P22 R404 1M 63 22 17~24 X1 8MHz J5 +3V 2 C450 22P R165 10K KBD_US/JP# 25 117 8050D N/B Maintenance 8.7 USB Port Test Error An error occurs when a USB I/O device is installed. USB Test Error Check if the USB device is installed properly. (Including charge board.) Test OK? Yes No t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Correct it Replace Motherboard Check following parts and signals: Parts: Replace another known good USB device. Re-test OK? Yes Replace the faulty part Board-level Troubleshooting U715 U705 U701 U712 J701 J706 L701 L702 L2 L5 L22 L708 R701 C701 R706 C713 C703 C709 Signals: +5VS USBOC0# USBP0+ +VCC_USB_0 USBP0- +VCC_USB_1 USBP1+ +VCC_USB_2 USBP1USBP2+ USBP2- No 118 8050D N/B Maintenance 8.7 USB Port Test Error An error occurs when a USB I/O device is installed. +5VS USBCLK_ICH R877 33 P11 39 U701 3 4 VOUT0 VIN1 USBP0USBP1+ U715 USBP1- ICH4_M + C701 150U L701 120Z/100M +VCC_USB_1 A1 J701 3 2 4 3 2 L5 90Z/100M U705 3 C709 1U 1 2 4 3 P15 L708 120Z/100M 1 VIN0 VOUT0 VIN1 VOUT1 5 GND 4 2 A3 A2 4 A4 USB/4PX2/DIP +VCC_USB_2 1 P15 + C713 150U R706 33K J706 3 1 2 4 3 2 4 GND1 USB Port Connector L22 90Z/100M USBP2+ USBP2- R701 33K L2 90Z/100M +5VS USB_OC1# P15 5 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 1 P14 1 +VCC_USB_0 USB Port Connector USBP0+ VOUT1 2 C703 1U USB_OC0# L702 120Z/100M 1 VIN0 GND U712 CLK-GEN P15 GND2 USB/4PX1 119 8050 N/B Maintenance 8.8 Hard Disk Drive Test Error Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing data to hard disk. Hard Driver Test Error t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 1.Check the BIOS setup 2.Replace another good hard driver or try again Board-level Troubleshooting Check following parts and signals: Re-boot OK? Yes Replace the faulty parts. No Check the system driver for proper installation. Re - Test OK? Yes Replace Motherboard Parts: Signals: U715 J714 Q37 Q41 L733 R476 R492 R1081 R1074 PCIRST#0 PIORDY PDD[0..15] PDA[0..2] PDIOR# PDIOW# PDDACK# PDCS1# PDCS3# PDDREQ IRQ14 +5V +5V_HDD End No 1 8050D N/B Maintenance 8.8 Hard Disk Drive Test Error Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing data to hard disk. +3V +5V_HDD R1074 8.2K +5V L733 120Z/100M 27~42 PD_D[0..15] P11 U715 PDIOW# 22 PDIOR# 20 PIORDY 18 PDDACK# 16 IRQ14 14 9,10,12 PDA[0.. 2] ICH4_M 3 8 PDCS1# 7 PDCS3# +5V PCIRST#0 R492 10K RSTDRV1# P15 J714 HDD CONNECT t t n e e r c m e u S c c Do a iT ial M t n e id f n o C R1081 4.7K 44 R476 10K Q41 DTC144TKA Q37 DTC144TKA 121 8050D N/B Maintenance 8.9 CD-ROM Test Error CD-ROM driver can’t run normally,maybe an error message is shown when reading data from CD-ROM. CD-ROM Driver Test Error Check the CD-ROM driver for proper installation. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Board-level Troubleshooting Check following parts and signals: Test OK? Yes No Try another known good compact disk. Re - Test OK? Yes Correct it Replace Motherboard Replace the faulty parts. Parts: Signals: U715 J708 Q37 Q41 R492 R476 R909 R833 R834 L723 CDROM_COMM PCIRST#0 RSTDRV2# SIORDY SDD[0..15] SDA[0..2] SDIOR# SDIOW# SDDACK# SDCS1# SDCS3# SDDREQ IRQ15 +5V +5V_CDROM CDROM_LEFT CDROM_RIGHT No 122 8050D N/B Maintenance 8.9 CD-ROM Test Error CD-ROM driver can’t run normally,maybe an error message is shown when reading data from CD-ROM. +3V +5V_CDROM L723 120Z/100M +5V 38~42 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C R833 4.7K R834 8.2K 6~21 SD_D[0..15] P11 U715 ICH4_M SDIOW# 25 SDIOR# 24 SIORDY 27 SDDACK# 28 IRQ15 29 35 36 +5V PCIRST#0 R492 10K R909 0 5 RSTDRV2# R476 10K Q41 DTC144TKA P20 Q37 DTC144TKA U726 AUDIO CODEC 18 C507 1U R538 6.8K CDROM_LEFT 1 20 C513 1U R547 6.8K CDROM_RIGHT 2 19 C515 0.22 R550 0 CDROM_COMM 3 R549 6.8K R546 6.8K CDROM CONNECT SDCS3# J708 31,33,34 SDA[0.. 2] SDCS1# P15 R537 6.8K 123 8050D N/B Maintenance 8.10 Audio Failure There is trouble with the sound from speaker or completely no sound Audio Failure t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 1. Check if speaker cables are connected properly. 2. Make sure all the drivers are installed properly. Board-level Troubleshooting Check following parts and signals: Parts: Test OK? Yes Correct it. No Try another known good speaker, CD-ROM. Re-test OK? Yes Replace Motherboard U18 U17 U524 U726 U715 U712 U19 U725 J3 J7 J705 J719 L741 D715 Q711 Q713 Q23 D17 D19 D22 U18 Signals: ROUT+ ROUTSBSPKR CARDSPK# PC_BEEP AVDD ACRST# ACSDOUT ACSDIN0 ACBITCLK 14M_CODEC MIC_VREF 2464_VREF AMP_LEFT AMP_RIGHT SUB_LEFT SUB_RIGHT AMP_SHUTDOWN ROUT+ ROUTLOUT+ LOUT- Replace the faulty parts. No 124 8050D N/B Maintenance 8.10 Audio Failure(Audio Codec) There is trouble with the sound from speaker or completely no sound J719 EXTERNAL MIC JACK +5V VA P20 U18 U17 5 OUT IN GND ADJ To U715 VCC 1 A C457 L734 0.1U Y 2 B C458 0.1U - CARDSPK# P17 C467 0.01U R438 10K L66 120Z/100M U727 CARD READER C456 1U 21 1,9 25,38 AVDD P20 U726 5 ACSDOUT U715 ACSDIN0 ICH4_M ACBITCLK 24 11 ACRST# R530 22 R812 0 L69 0 28 24 AUDIO CODEC C975 MIC 12 PC_BEEP P14 0 R1155 0 L744 BEAD_600Z/100M CB710 +3V SBSPKR R1150 L70 BEAD_600Z/100M NC7S32 MIC5205BM5 BEAD_600Z/100M + SBSPKR t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 4 EN INTERNAL MIC1 P20 C969 R535 0 R532 0 R519 1U C974 0 R324 1U 0 1U R1154 4.7K R1157 0 R1153 0 J721 Line/In Jack P20 2464_VREF To Next Page U19 L76 BEAD_600Z/100M L53 L751 120Z/100M BEAD_600Z/100M +5V L67 120Z/100M 7,18,19 8 ACSYNC 22 R498 10 ALC655 35 AOUT_L 0 R1130 R1135 0 AMP_LEFT 6 36 AOUT_R R1127 0 R1128 C484 1U 5 C480 1U 6 P21 U524 0 AMP_RIGHT C492 1U 20 C497 1U 23 AMP TPA0212_GND P11 U712 CLKGEN TO NEXT PAGE J720 56 R859 33 14M_CODEC R472 0 2 48 47 SPDIFOUT TO NEXT PAGE D22 EAPD TO NEXT PAGE U19 SUB_LEFT TO NEXT PAGE U19 SUB_RIGHT ICS950810 125 8050D N/B Maintenance 8.10 Audio Failure(Audio Amplifier & Subwoofer) There is trouble with the sound from speaker or completely no sound From Previous Page U726 SPDIFOUT 15,17 ROUT+ L52 16 ROUT- L50 600Z/100M 4 LOUT+ L14 600Z/100M 9 LOUT- L16 600Z/100M AUDIO AMP + C474 100U C474 + C489 100U 600Z/100M t t n e e r c m e u S c c Do a iT ial M t n e id f n o C R329 R528 TPA0212_GND R322 4.7K J7 Internal Speaker Connector AGND J3 HDR/MA-2 L80 L78 22 22 R1183 10K DECT_HP#OPT 600Z/100M 600Z/100M 600Z/100M L755 600Z/100M L55 600Z/100M L757 600Z/100M R1158 10K IC From Previous Page U726 D22 BAT54C EAPD R906 0 R905 8.2K 0 KBC_MUTE VA 80 D27 100 R463 22.1K 3 C482 0.15U R479 22.1K 2 OPT in 1 0 No this condition 1 1 No device DEVICE_DECT To U524 R510 22.1K 5 22.1K 6 Q23 DTC144TKA RLS4148 1 R509 HP in 1 C496 SUB_OUTR 0.22U C483 SUB_OUTL 0.22U R502 8.2K D17 RLS4148 R1125 0 C471 1000P R1122 2.1K 1 P21 5 R26 0 8 R27 0 6 L63 120Z/100M 8.2K 4 LM4871 Subwoofer Speaker Connector HDR/MA-2 U725 R496 P21 J705 R511 0.15U 0 0 D19 RLS4148 U19 LMV822 C490 0 R367 10K R477 Q38 7 SUB_LEFT +5V DEVICE_DECT# P2 SUB_RIGHT VA DECT_HP#/ OPT REMARK AMP_SHUTDOWN U715 ICH4_M From Previous Page U726 2464_VREF DEVICE_DECT# OPTIN# +3V U16 WINBOND KBC Q711 DTA144WK Q713 VDD3S R445 GP1FD310TP R1185 10K D715 BAW56 P13 LED Drive L758 600Z/100M +3V +5V P21 J720 L754 HP/OPT CONNECTOR 21 P21 U524 VA DEVICE_DECT +5V 126 8050D N/B Maintenance 8.11 LAN Test Error An error occurs when a LAN device is installed. LAN Test Error 1.Check if the driver is installed properly. 2.Check if the notebook connect with the LAN properly. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Board-level Troubleshooting Yes Test OK? No Check if BIOS setup is ok. Correct it. Replace Motherboard Re-test OK? Yes Correct it. Check following parts and signals: Parts: Signals: U719 U717 U723 J709 L732 L735 L737 L51 L49 Q709 X706 R1101 R1111 R1115 R907 R211 R212 EECK EEDI EEDO EECS PJRX+ PJRXPJTX1PJTX+ LAN_XTANL1 LAN_XTANL2 PCICLK_LAN LAN_WAKE PCI_AD[0..31] PCI_C/BR#[0..3] PCI_PAR LAN_PCIRST# PCI_STOP# AVDDL DVDD SB_PME# PCLKRUN# PCI_DEVSEL# PCI_FRAME# PCI_INTE# PCI_REQ3 PCI_IRDY# PCI_SERR No 127 8050D N/B Maintenance 8.11 LAN Test Error An error occurs when a LAN device is installed. +3VS 26,41,56,71 84,94,107 AVDDL +3VS t t n e e r c m e u S c c Do a iT ial M t n e id f n o C L737 L732 +2.5VS_DDR DVDD 120Z/100M 120Z/100M 3,7,16,20 24,32,45,54,64 78,99,110,116,126 L735 VDD3S +3VS R1110 12 120Z/100M 111 EECK 1 109 EEDI 2 108 EEDO 3 106 EECS 4 3.6K CS P16 R211,R212,R241… 8.2K*11 SB_PME# DI GND PCI_GNT3# PCI_INTE# PCI_IRDY# PCI_TRDY# PCI_SERR# PCI_PERR# PCI_STOP# MDI0+ 2 65,68,61,29,25 2 63,67,70,75,69 MDI0- L51 3 8 PMDI0+ 1 4 P16 7 PMDI0- U719 30 5 PCI_PAR U715 PCI_C/BE#[0..3] PCI_AD[0..31] 76 44,60.. 33,34… 2 LAN Controller 6 ICH4_M MDI1+ 27 LAN_PCIRST# +3VS 93C46 MDI1- L49 3 2 PMDI1+ 9 PJTX+ 1 10 PJTX1- 2 15 PJRX+ 3 16 PJRX- 6 MDO2+ 4 MD23- 5 MDO3+ 7 MDO3- 8 U717 11 MCT4 14 MCT3 PCI_AD18 R1111 0 R947 R152 75 1 4 1 PMDI1- RTL8100CL R1115 10K 5 DO R930 75 RP27 0*4 P16 J709 LAN CONNECTOR PCI_DEVSEL# PCLKRUN# PCI_FRAME# PCI_REQ3# C911 1U U723 31 1 P13 8 SK P16 R907 10K VCC LF-H80P 100 Q709 DTC144TKA LAN_WAKE 105 121 LAN_XTAL1 122 LAN_XTAL2 1M R1101 X706 1 P11 U712 13 PCICLK_LAN 28 C914 27P 2 25MHZ C915 27P ICS950810 128 8050D N/B Maintenance 8.12 Modem Test Error An error occurs when run the modem MODEM Test Error t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 1.Check if the driver is installed properly. 2.Check if the notebook connect with the phone LAN properly. Board-level Troubleshooting Check following parts and signals: Test OK? Yes No Replace a known good modem Re-test OK? Yes Correct it. Replace Motherboard Correct it. Parts: Signals: J717 J715 U726 R1132 C937 R498 L69 R1120 R1131 L724 F2 +5V +3VS +3V MONO_OUT ACSDOUT ACRST# ACSYNC ACBITCLK ACSDIN1 MODEMP MODEMN No 129 8050D N/B Maintenance 8.12 Modem Test Error An error occurs when run the modem 10,18 +5V 17 +3VS R1132 37 P20 5 U726 11 ALC555 10 6 C937 R498 P14 U715 ICH4_M J715 HDR/MA-2 P20 2 MONO_OUT 22 L69 0 R1131 22 2 3 1 L724 4 50UH R1120 22 MODEMP A2 MODEMN A1 C148 1000P C806 1000P P16 Lan Connector J709 Phone Lan Connector 0.1U 4.7K RJ11-2P /RJ45-8P P20 16 1 J717 ACSDOUT 23 ACRST# 25 ACSYNC 22 ACBITCLK 30 ACSDIN1 24 MODEM CONNECTOR t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 21 +3V JP, use 4pcs of 2kV 1000P cap US, use 2pcs of 2kV 1000P cap 1 F2 UK, use 4pcs of 3kV 1000P cap MINISMDC014-2 130 8050D N/B Maintenance 8.13 Mini PCI Test Error An error message is shown after Mini PCI device is installed or the Mini PCI device does’t work. Mini PCI Test Error 1.Please check if the Mini PCI device is installed properly. 2.Confirm Mini PCI device driver is installed ok. Test OK? Yes t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Board-level Troubleshooting Correct it Check following parts and signals: Parts: Signals U715 PCI_AD[0:31] CLKRUN# J509 PCI_C/BE# [0:3] PCI_PERR# PCI_REQ2# LAD [0:3] PCI_FRAME# LFRAME# PCI_IRDY# LRDQ0# PCI_TRDY# WIRELESS_PD# PCI_DEVSEL# MINIPCI_PME# PCI_STOP# SIO_48M PCI_INTD# PCICLK_MINIPCI U712 No Please try another known good Mini PCI device. Please replace Motherboard U9 Q704 R1137 R1079 R1007 Re-test OK? Yes Please change the faulty part then end. R1077 PCI_RESET# R1075 PCI_GNT2# R1091 PCI_SERR# No 131 8050D N/B Maintenance 8.14 CardBus & Reader Test Error An error occurs when a PC card device is installed. PC Card Slot Failure t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 1. Check if the PCMCIA CARD device is installed properly. 2. Confirm PCMCIA card driver is installed ok. Board-level Troubleshooting Check following parts and signals: Test OK? Yes No Try another known good PCMCIA card device. Re-test OK? No Yes Parts: Signals U727 J716 U728 J6 U9 R186 R180 R211 R212 R1121 R1129 R826 R1203 AD[0..31] PCIRST# C/BE# [0..3] P_GNT0# DEVSEL# PIRQA# FRAME# SUSB# RI# PCLK_CARD VCC5_EN# VCC3_EN# VPPD0 VPPD1 +VPPOUT +3V +5V Correct it Change the faulty part then end. Replace Motherboard IRDY# TRDY# STOP# PAR PERR# SERR# P_REQ0# SERIRQ 132 8050D N/B Maintenance 8.13 Mini PCI Test Error An error message is shown after Mini PCI device is installed or the Mini PCI device does’t work. +3V +5V R179 R211.. +3V R1007 13 10K t t n e e r c m e u S c c Do a iT ial M t n e id f n o C PCI_INTD# PCI_GNT2# PCI_REQ2# P13 18,97 P14 U715 R1068 PCI_PERR# PCLKRUN# PCI_STOP# PCI_DEVSE# PCI_IRDY# PCI_SERR# PCI_FRAM# PCI_TRDY# R1080 R1083 P19 WIRELESS_PD# 14,24 PCI_AD[0..31] ICH4_M PCI_C/BE#[0..3] LRDQ0# LAD[0..3] LFRAME# PCI_AD17 R1091 R1075 R1092 100 48 MINIPCI_LPCDRQ# J713 +3V 9 U9C 8 JL8 R1077 0 26 10 +3V Q704 SB_PME# R915 0 MINIPCI_PME# P11 39 R895 33 SIO_48M R1137 0 U712 ICS950810 11 R816 33 PCICLK_MINIPCI R1079 0 34 MINIPCI CONNECTOR PCIRST# 121 25 133 8050D N/B Maintenance 8.14 CardBus & Reader Test Error An error occurs when a PC card device is installed. +3V R1201 R1199 +3V R211, R212… 8.2K*7 10K*2 VCCD0# R180 R231 8.2k*2 R186 8.2k PCI_AD20 R1202 100 VCC5_EN# 1 VCC3_EN# 2 VPPD0 15 VPPD1 14 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C VCCD1# PCI_AD[0..31] VPPD0 P13 PCLKRUN# PCI_DEVSEL# PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_PERR# VPPD1 P17 +CARD_VCC 17,51 +VPPOUT 18,52 U728 P17 PCI_GNT0# U715 P17 PCI_REQ0# ICH4_M R1200 SUSB# 4.7K U9 10 8 9 PCI_SERR# U727 JL7 CARD_PCIRST# PCI_PAR 3,4 +3V SERIRQ R1121 10K R1129 10K TPS2211A 16 8 5,6 +5V J6 CardBus Reader PCI_C/BE#[0..3] CCBE[0..3]# CB710 CCD2# P11 U712 CLKGEN 12 R826 33 ICS950810 J716 MS Card MA/15PX2/ST SD Card P17 20,27,29 +SD_MSVDD 7 R1198 PCICLK_CARD 10 1,4,6 SD_CLK SDCD# SD_WP# 8~11 5 2,12,14 SD_CMD SD[0..3] R1203 10 MS_SCLK MS_INS# MS_BS CCD1# CAD[0..31] 7,12,21,61 36,67 2~6,8~11… CVS[1,2] 43,57 4732,40 R2_ A18 R2_ D2 R2_ D14 CBLOCK# CSTOP# CDEVSEL# CPAR CGNT# CTRDY# 13,15,53 CSERR# CAUDIO CSTSCHG 59,62,63 CPERR# CINT# CIRDY# 14,16,20 CFRAME# CRST# CREQ# 54,58,60 R1213 33 CCLK FM/34 PX2/1. 27MM 48~50 19 MS_SDIO 134 8050D N/B Maintenance 8.15 IEEE 1394 Test Failure An error occurs when a IEEE 1394 device is installed.. IEEE 1394 Fail 1. Check if the 1394 device is installed properly. 2. Confirm 1394 driver is installed ok. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Board-level Troubleshooting Test OK? Yes No Check if BIOS setup is ok. Correct it. Replace Motherboard Re-test OK? No Yes Correct it. Check following parts and signals: Parts: Signals U724 U722 J718 U9 U712 U715 L743 L746 L740 L83 R1117 R828 R1116 R1142 R1141 X707 PCI_AD[0..31] PCI_C/BE# [0..3] PC_DEVSEL# PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_PAR PCI_PERR# PCI_REQ1# PCI_PME# +3V,+3VS 1394_PCIRST# PCI_GNT1#EE CS_1394 EECK_1394 EEDI_1394 EEDO_1394 TPBIAS TPA+_6307 TPA-_6307 TPB+_6307 TPB-_6307 1394_AVCC XI XO +PHYVDD 135 8050D N/B Maintenance 8.15 IEEE 1394 Test Failure An error occurs when a IEEE 1394 device is installed.. +PHYVDD 1394_AVCC 24,8,20… +3V +3V L743 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 29 EECS_1394 1 5~28,97~120 32 EECK_1394 2 31 EEDI_1394 3 120Z/100M PCI_AD[0..31] R1117 PCI_AD21 P13 100 108 4,15,107,122 PCI_C/BE#[0..3] PCI_FRAME# PCI_GNT1# U715 PCI_DEVSEL# PCI_REQ1# PCI_TRDY# PCI_INTG# PCI_IRDY# PCI_STOP# P18 4 EEDO_1394 VCC CS P18 SK U722 DI 93C46 DO PCI_PERR# 3 U724 3 2 PCI_PME# 37 1394_PCIRST# 92 70 U9 1 JL2 R828 33 71 TPB+_6307 72 TPA-_6307 93 PCICLK_1394 73 XI R1116 1M XO TPA+_6307 P18 4 2 1 L740 120Z/100M 2 3 3 4 2 1 L83 120Z/100M 4 60 R1143 54.9 R1144 54.9 C965 270P R1148 4.99K 61 X707 R1142 54.9 J718 1394 CONNECTOR 16 1 TPB-_6307 3 VT6307L U712 ICS950810 30 123,126… PCI_PAR ICH4_M P11 8 62,65,75 76,89,90 L746 +3VS +3V 39,49 120Z/100M R211, R212, R218… 8.2K VCC0~7 VCCRAM R1141 54.9 24.576MHZ C939 10P C932 10P 74 TPBIAS 136 8050D N/B Maintenance 9. Spare Part List(1) Part Number Description Location(S) Part Number Description 221600020252 CARTON;BATTERY,CAIMAN,PWR 242600000439 LABEL;25*6,HI-TEMP,COMMON 221600050218 PARTITION;BATTERY,MARLIN,CAIMAN, 242600000452 LABEL;BLANK,7MM*7MM,PRC 221600050219 PARTITION;TOP/BTM,BATTERY,MARLIN 242600000452 LABEL;BLANK,7MM*7MM,PRC 221673120003 CARTON;N-B,8060 221673140001 BOX;AK,8060 221673150001 PARTITION;AK BOX,8060 221673150002 CARD BOARD;FRAME,PALLET,8060 221673150003 CARD BOARD;TOP/BTM,PALLET,8060 221673150004 PARTITION;PALLET,8060 222503220001 PE BUBBLE BAG;BATTERY,GRAMPUS 222670820003 PE BAG;L560*W345,7521N 224670830002 PALLET;1250*1080*130,7521N 225600000054 TAPE;INSULATING,POLYESTER FILM,1 225600000061 TAPE;ADHENSIVE,DOUBLE-FACE,W20,U t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Location(S) 242664800013 LABEL;CAUTION,INVERT BD,PITCHING 242668300028 LABEL;32*7MM,POLYESTER FILM,HOPE 242669600005 LABEL;LOT NUMBER,RACE 242669900009 LABEL;BLANK,60*80MM,7170 242670800113 BFM-WORLD MARK;WINXP,7521N 242678500005 CFM-INTEL;CENTRINO,NOTEBOOK,8081 242679900005 LABEL;BAR CODE,(25*10MM)*12pcs,8 242680900001 LABEL;AGENCY-GLOBAL,8050 242680900002 LABEL;BATT,11.1V/4.4AH,LI,SANYO, 242680900007 LABEL;17.3*5MM,BLANK,PWR 271002000301 RES;0 ,1/10W,5% ,0805,SMT L62,L65,L73,L88,R1,R123,R26,R2 271002472301 RES;4.7K ,1/10W,5% ,0805,SMT PR704,PR706 271002604011 RES;604 ,1/10W,1% ,0805,SMT R945,R946 271012000301 RES;0 ,1/8W,5% ,1206,SMT PR86 271035012711 RES;.012,1W,1%,2010,LR2010,IRC,S PR707,PR711,PR719,PR732,PR73 271044100101 RES;0.010,1.5W, 1%,2512,SMT;PWR R6 271045087101 RES;.008 ,1W ,1% ,2512,SMT PR742 242600000157 LABEL;BAR CODE,125*65,COMMON 271045107101 RES;.01 ,1W ,1% ,2512,SMT PR701 242600000232 LABEL;6*6MM,GAL,BLANK,COMMON 271045507103 RES;0.050,1W, 1%,2512,SMT, only R24A,R24B,R24C 242600000378 LABEL;27*7MM,HI-TEMP 260'C 271046017301 RES;.001,2W,5%,2512,CYNTEC,SMT PR740 242600000385 LABEL;27*10,LAN ID BAR CODE 271061000002 RES;0 ,1/16W,0402,SMT PR103,PR104,PR11,PR111,PR120 242600000433 LABEL;BLANK,11*5MM,COMMON 271061010101 RES;1,1/16W,1%,0402,SMT PR18 226600030332 SPONGE;320*290*10,CAIMAN,PWR 227680900002 PAD;LCD/KB,8050 227680900003 END CAP;NORMAL,L/R,8050 242600000001 LABEL;PAL,20*5MM,COMMON 242600000145 LABEL;10*10,BLANK,COMMON 242600000145 LABEL;10*10,BLANK,COMMON 137 8050D N/B Maintenance 9. Spare Part List(2) Part Number Description Location(S) Part Number Description Location(S) 271061100102 RES;10,1/16W,1%,0402,SMT PR37,PR38,PR5 271061180101 RES;18.2 ,1/16W,1% ,0402,SMT R838 271061100501 RES;10 ,1/16W,5% ,0402,SMT PR1,PR100,R1000,R1001,R1009,R 271061183102 RES;18K,1/16W,1%,0402,SMT PR718,R462,R507 271061101103 RES;100 ,1/16W,1% ,0402,SMT R1092,R1117,R1202,R208,R257,R 271061184302 RES;180K ,1/16W, 5%,0402,SMT R1140,R288 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C PR121,PR53,R1006,R141,R32,R32 271061196212 RES;1.96K,1/16W,1%,0402,SMT PR710 R110,R120 271061196213 RES;19.6K,1/16W,1%,0402,SMT PR36,PR97,PR99 R102,R1136,R1147,R155,R206,R2 271061201101 RES;200 ,1/16W, 1%,0402,SMT R280 R496,R502 271061202102 RES;2K ,1/16W,1% ,0402,SMT PR101,PR124,PR46,PR725,PR731 PR102,PR119,PR127,PR129,PR4,P 271061203102 RES;20K ,1/16W,1% ,0402,SMT PR117,PR21,PR41,PR722,PR726,R R1007,R104,R1098,R11,R1103,R1 271061203701 RES;20K ,1/16W,.1%,0402,SMT PR75 PR10,PR112,PR114,PR12,PR130,P 271061204102 RES;200K ,1/16W,1% ,0402,SMT PR54,PR55 PR69,PR703,PR720,PR83,PR89,R 271061205212 RES;20.5K,1/16W,1%,0402,SMT PR113 PR106,PR115,PR123,PR26,PR27,P 271061220102 RES;22,1/16W,1% ,0402,SMT R253 R296,R938 271061220501 RES;22 ,1/16W,5% ,0402,SMT R105,R1120,R1131,R306,R329,R4 PR35 271061221212 RES;2.21K,1/16W,1% ,0402,SMT R72,R79 PR116 271061221312 RES;22.1K,1/16W,1% ,0402,SMT R463,R479,R509,R510 PR79 271061221313 RES;220 ,1/16W, 5%,0402,SMT R552,R555,R556,R557 PR17 271061222101 RES;2.2K,1/16W,1%,0402,SMT PR6 PR96 271061222501 RES;2.2K ,1/16W,5% ,0402,SMT R315,R318 PR19,PR29 271061223102 RES;22K,1/16W,1% ,0402,SMT R325,R520 PR16,R1158 271061224501 RES;220K ,1/16W,5% ,0402,SMT R251 271061137371 RES;13.7K,1/16W,.1%,0402,SMT PR74 271061226311 RES;226K,1/16W,1%,0402,SMT PR71 271061151102 RES;150 ,1/16W, 1%,0402,SMT R220,R446,R772,R791,R850,R884 271061232111 RES;2.32K,1/16W,1%,0402,SMT PR39 271061152302 RES;15K ,1/16W,5% ,0402,SMT R1008 271061240302 RES;24,1/16W,5%,0402,SMT R106,R107,R108,R109,R29,R30,R3 271061152501 RES;1.5K ,1/16W,5% ,0402,SMT R1084 271061249211 RES;2.49K,1/16W,1% ,0402,SMT PR77 271061153102 RES;15K ,1/16W,1% ,0402,SMT PR105,PR107,PR122,PR727,PR72 271061249212 RES;24.9K,1/16W,1%,0402,SMT PR128,PR98 271061102105 RES;1K ,1/16W,1% ,0402,SMT 271061102211 RES;1.02K,1/16W,1% ,0402,SMT 271061102303 RES;1K ,1/16W,5% ,0402,SMT 271061102312 RES;10.2K,1/16W,1% ,0402,SMT 271061103102 RES;10K ,1/16W,1% ,0402,SMT 271061103501 RES;10K ,1/16W,5% ,0402,SMT 271061104102 RES;100K ,1/16W,1% ,0402,SMT 271061104501 RES;100K ,1/16W,5% ,0402,SMT 271061105501 RES;1M ,1/16W,5% ,0402,SMT 271061106501 RES;10M ,1/16W,5% ,0402,SMT 271061107411 RES;107K,1/16W,1%,0402,SMT 271061118211 RES;11.8K,1/16W,1%,0402,SMT 271061124312 RES;124K,1/16W,1%,0402,SMT 271061127212 RES;12.7K,1/16W,1%,0402,SMT 271061133101 RES;13.7K,1/16W,1%,0402,SMT 271061133311 RES;13.3K,1/16W,1%,0402,SMT 271061135101 RES;1.3M,1/16W,1%,0402,SMT 138 8050D N/B Maintenance 9. Spare Part List(3) Part Number Description Location(S) Part Number Description Location(S) 271061249312 RES;249K,1/16W,1%,0402,SMT PR729,PR76 271061562212 RES;56.2K,1/16W,1%,0402,SMT PR15 271061270102 RES;27.4 ,1/16W, 1%,0402,SMT R133,R213,R291 271061576411 RES;576K ,1/16W,1% ,0402,SMT PR28 271061272102 RES;2.7K ,1/16W,1% ,0402,SMT R448,R449 271061590411 RES;590K,1/16W,1%,0402,SMT PR65 271061301112 RES;301 ,1/16W,1% ,0402,SMT t t n e e r c m e u S c c Do a iT ial M t n e id f n o C R793,R855 271061604011 RES;60.4 ,1/16W,1% ,0402,SMT R923,R924 R1213,R77,R78,R816,R817,R818,R 271061619211 RES;6.19K,1/16W,1% ,0402,SMT PR81 R1073,R1089,R301 271061634211 RES;6.34K,1/16W,1% ,0402,SMT R1145 PR70 271061634214 RES;63.4K,1/16W,1%,0402,SMT PR42 PR45,R701,R706 271061649212 RES;6.49K,1/16W,1% ,0402,SMT PR721 R225 271061681501 RES;680 ,1/16W,5% ,0402,SMT R214 R876 271061682501 RES;6.8K ,1/16W,5% ,0402,SMT R537,R538,R546,R547 R119,R832 271061750501 RES;75 ,1/16W,5% ,0402,SMT R152,R271,R277,R767,R768,R769 PR58 271061752102 RES;7.5K,1/16W,1%,0402,SMT PR84 PR118,PR60,R1187,R1189,R1205, 271061753101 RES;75,1/16W,1%,0402,SMT R334,R340 R750 271061806311 RES;80.6K,1/16W,1% ,0402,SMT PR63,PR66 R1085,R553,R554,R558 271061822501 RES;8.2K ,1/16W,5% ,0402,SMT PR126,R1004,R1005,R1074,R1119 R10,R1081,R1132,R1154,R1200,R 271071000002 RES;0 ,1/16W,5% ,0603,SMT L69,L719,L728,L744,L747,L751,L R140,R442,R443,R702,R708,R929 271071101301 RES;100 ,1/16W,5% ,0603,SMT R11,R12,R14,R15,R16,R20,R21 PR702,R373 271071102302 RES;1K ,1/16W,5% ,0603,SMT R11 R1082,R1086,R1087,R1090,R209, 271071103302 RES;10K ,1/16W,5% ,0603,SMT R2 PR20,R1148 271071103302 RES;10K ,1/16W,5% ,0603,SMT R1122 271061499411 RES;499K ,1/16W,1% ,0402,SMT PR43,PR716 271071103302 RES;10K ,1/16W,5% ,0603,SMT R5,R7,R8 271061510303 RES;51, 1/16W, 5%,0402,SMT R224,R228,R238,R243,R289 271071104101 RES;100K ,1/16W,1% ,0603,SMT R18,R22,R23,R9 271061549011 RES;54.9 ,1/16W,1% ,0402,SMT R1141,R1142,R1143,R1144,R142, 271071104302 RES;100K ,1/16W,5% ,0603,SMT R7 271061560501 RES;56 ,1/16W,5% ,0402,SMT R198,R264,R269,R273,R42,R43,R7 271071105301 RES;1M ,1/16W,5% ,0603,SMT R10,R3 271061562102 RES;5.6K ,1/16W, 1%,0402,SMT R1099,R542 271071127011 RES;127 ,1/16W,1% ,0603,SMT R14A 271061330501 RES;33 ,1/16W,5% ,0402,SMT 271061331304 RES;330 ,1/16W,5% ,0402,SMT 271061332312 RES;3.3K,1/16W,5% ,0402,SMT 271061333501 RES;33K ,1/16W,5% ,0402,SMT 271061390501 RES;39, 1/16W, 5%,0402,SMT 271061391103 RES;390,1/16W,1% ,0402,SMT 271061402011 RES;40.2 ,1/16W,1% ,0402,SMT 271061412111 RES;4.12K,1/16W,1%,0402,SMT 271061432212 RES;43.2K,1/16W,1%,0402,SMT 271061470501 RES;47 ,1/16W,5% ,0402,SMT 271061471501 RES;470 ,1/16W,5% ,0402,SMT 271061472501 RES;4.7K ,1/16W,5% ,0402,SMT 271061473501 RES;47K ,1/16W,5% ,0402,SMT 271061474501 RES;470K ,1/16W,5% ,0402,SMT 271061499012 RES;49.9 ,1/16W,1% ,0402,SMT 271061499212 RES;4.99K,1/16W,1% ,0402,SMT 139 8050D N/B Maintenance 9. Spare Part List(4) Part Number Description Location(S) Part Number Description Location(S) 271071127011 RES;127 ,1/16W,1% ,0603,SMT R163 271071681813 RES;68.1,1/16W,1%,0603,SMT R903 271071131101 RES;130 ,1/16W,1% ,0603,SMT R911 271071684101 RES;680K ,1/16W,1% ,0603,SMT R5 271071152302 RES;1.5K ,1/16W,5% ,0603,SMT R17 271071713102 RES;715 ,1/16W,1% ,0603,SMT R762 271071152302 RES;1.5K ,1/16W,5% ,0603,SMT t t n e e r c m e u S c c Do a iT ial M t n e id f n o C R19 271071753301 RES;75K ,1/16W,5% ,0603,SMT R8 R777 271071822102 RES;8.2K ,1/16W,1% ,0603,SMT R14B R1A,R1B 271072287011 RES;287 ,1/10W,1% ,0603,SMT R914 R12 271072474101 RES;470K ,1/10W,1% ,0603,SMT R4 R1 271571000301 RP;0*8 ,16P ,1/16W,5% ,1606,SM RP14,RP15,RP6,RP8 R792,R839 271571560302 RP;56*8 ,16P,1/16W,5% ,1606,SMT RP29,RP30,RP31,RP32,RP33,RP3 R13,R3 271586026101 RES;.02 ,2W,1%,2512,SMT PR22 R16,R21,R22 271611000301 RP;0*4 ,8P ,1/16W,5% ,0612,SMT RP10,RP16,RP27,RP718 R18,R20,R23 271611103301 RP;10K*4 ,8P ,1/16W,5% ,0612,SMT RP719 C14 271611220301 RP;22*4 ,8P ,1/16W,5% ,0612,SMT RP45 R1110 271611240302 RP;24*4 ,8P ,1/16W,5% ,0612,SMT RP11,RP12,RP13,RP17,RP18,RP1 R898 271611750301 RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP2 R10 271621103302 RP;10K*8 ,10P,1/32W,5% ,1206,SMT RP46,RP715 R1 271621472302 RP;4.7K*8,10P,1/32W,5% ,1206,SMT RP44 PR87,PR88 272001105403 CAP;1U ,10%,10V ,0805,X7R,SMT PC3,PC46 PR108,PR109,PR110,PR2,PR3,PR 272001106702 CAP;10U,6.3V,+- 20%,0805,X5R,SMT C110,C112,C114,C121,C122,C127 R883 272001475701 CAP;4.7U ,CR,10V ,+80-20%,0805,Y C311,C517,C871,C941,C947 271071487811 RES;48.7 ,1/16W,1% ,0603,SMT R900 272002225701 CAP;2.2U ,CR,16V ,+80-20%,0805,Y C921,C961 271071499011 RES;499 ,1/16W,1% ,0603,SMT R764 272003105701 CAP;1U ,CR,25V ,+80%-20%,0805, PC701 271071499311 RES;499K ,1/16W,1% ,0603,SMT R17 272005104402 CAP;.1U ,50V,+/-10%,0805,X7R,SMT PC9 271071563101 RES;56K ,1/16W,1% ,0603,SMT R6 272005104404 CAP;.1U,CR,50V,10%,0805,SMT PC4,PC51,PC52,PC65,PC66,PC7,P 271071622303 RES;620,1/16W,5% ,0603,SMT R786 272005104705 CAP ;1U CR 50V +80-20% 0805 Y5V C14A,C14B,C4A,C4B 271071181101 RES;180 ,1/16W,1% ,0603,SMT 271071201301 RES;200 ,1/16W,5% ,0603,SMT 271071202301 RES;2K ,1/16W,5% ,0603,SMT 271071224301 RES;220K ,1/16W,5% ,0603,SMT 271071274811 RES;27.4 ,1/16W,1% ,0603,SMT 271071301311 RES;301K ,1/16W,1% ,0603,SMT 271071331301 RES;330 ,1/16W,5% ,0603,SMT 271071331301 RES;330 ,1/16W,5% ,0603,SMT 271071331301 RES;330 ,1/16W,5% ,0603,SMT 271071362101 RES;3.6K ,1/16W,1% ,0603,SMT 271071374812 RES;37.4 ,1/16W,1% ,0603,SMT 271071432111 RES;4.32K,1/16W,1% ,0603,SMT 271071432211 RES;43.2K,1/16W,1% ,0603,SMT 271071472302 RES;4.7K ,1/16W,5% ,0603,SMT 271071478101 RES;4.7 ,1/16W,1% ,0603,SMT 271071487011 RES;487 ,1/16W,1% ,0603,SMT,MUS 140 8050D N/B Maintenance 9. Spare Part List(5) Part Number Description 272010101301 CAP;100P,2KV,5%,1206,NPO,SMT,onl Location(S) C18 272010101302 CAP;100P,2KV,5%,1206,NPO,SMT,onl 272011106701 CAP;10U ,10V,+80-20%,1206,Y5V,S C166,C174,C238,C271,C355,C772 Part Number Description Location(S) 272075222401 CAP;2200P,50V ,10%,0603,X7R,SMT C15A 272075222401 CAP;2200P,50V ,10%,0603,X7R,SMT C5 272075223702 CAP; 0.22U CR 50V +80-20% 0603 C1,C2,C20A,C24,C25 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C C14A,C14B 272075471401 CAP;470P ,50V,10%,0603,X7R,SMT C15B C475 272075471409 CAP; 0.0047U CR 50V 10% 0603 X7 C4 PC703,PC704,PC705,PC721,PC73 272075473401 CAP;.047U,50V,10%,0603,X7R,SMT C313 C1 272102104401 CAP;.1U ,CR,10V,10%,0402,X5R,SM PC44,PC80 C19 272102105701 CAP;1U ,CR,6.3V ,80-20%,0402,Y C1002,C11,C160,C206,C210,C219 C148,C327,C806 272102224701 CAP;.22U ,10V ,+80-20%,0402,Y5V, C14,C483,C496,C515 C860,C908 272102334701 CAP;.33U ,CR,10V ,+80-20%,0402,Y C964 C10,C4 272102473402 CAP;.047uF ,16V ,+-10%,0402,X7R, C841 C482,C490 272103331401 CAP;33P ,25V ,+/-10%,0402,NPO,S C17,C19,C344 C1001,C151,C161,C239,C24,C283 272105100303 CAP;10P ,CR,50V ,5%,0402,NPO,SM C789,C790,C791,C795,C796,C797 C2 272105101401 CAP;100P ,50V ,5%,0402,COG,SMT C150,C18,C20,C503 C17 272105101402 CAP;100P ,50V ,+ -10%,0402,NPO,S C10,C330,C455,C498,C520,C521,C C12,C6 272105102408 CAP;1000P,CR,50V,10%,0402,X7R,SM C960,C962,PC14,PC17,PC18,PC19 C471 272105102501 CAP;1000P,50V ,+/-20%,0402,X7R,S C100,C1006,C1007,C1008,C101,C C16 272105103702 CAP;.01U ,50V,+80-20%,0402,SMT C106,C117,C120,C128,C132,C137 C22,C7 272105104701 CAP;.1U ,16V,+80-20%,0402,SMT C1000,C102,C103,C104,C105,C10 C9 272105181403 CAP;180P,50V,10%,0402,SMT PC24,PC25,PC61,PC63,PC738 272075101401 CAP;100P ,50V ,10%,0603,COG,SMT C20,C21 272105220402 CAP;22P ,50V ,+ -10%,0402,NPO,S C447,C450,C765,C766,C855,C861 272075101404 CAP; 0.001U CR 50V 10% 0603 X7R C13 272105221403 CAP;220P ,CR,50V ,10%,0402,X7R,S C165,PC11,PC73,PC734,PC75 272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S C13,C8 272105222501 CAP;2200P,50V ,+/-20%,0402,X7R,S C470,C494,C509,C728,C869 272075103401 CAP;.01U ,CR,50V ,10%,0603,X7R,S C11,C3 272105270303 CAP;27P ,50V ,5%,0402,COG,SMT C794,C804,C914,C915 272075103408 CAP ;0.1U CR 50V 10% 0603 X7R S C10,C11,C12,C15,C3,C5,C6,C7,C8 272105271403 CAP;270P ,50V,+-10%,0402,X7R,SMT C15,C21,C770,C782,C965 272012105401 CAP;1U ,CR,16V ,10%,1206,X7R,S 272021106501 CAP;10U ,10V ,20%,1210,X7R,SMT 272023106502 CAP;10U,25V,M,1210,T2.5MM,X5R,SM 272023475502 CAP;4.7U ,CR,25V ,20%,1210,X7R,S 272030050302 CAP;5P,3KV,5%,1808,NPO,SMT,only 272030102401 CAP;1000P,2KV,10%,1808,X7R,SMT 272070475701 CAP;4.7U,CR,6.3V,+80-20%,0603,Y5 272071105403 CAP;1U ,10V ,10%,0603,X5R,SMT 272071154401 CAP;.15U ,CR,10V,10%,0603,X7R,SM 272071225401 CAP;2.2U ,CR,6.3V ,10%,0603,X5R, 272071332401 CAP;.33U ,10V ,10%,0603,X7R,SMT 272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM 272072104402 CAP;.1U ,CR,16V,10%,0603,X7R,SM 272072223401 CAP;.022U,16V ,10%,0603,X7R,SMT 272072824401 CAP;.082U ,16V ,10%,0603,X7R,SMT 272073104401 CAP;.1U ,CR,25V,10%,0603,X7R,PR 272073223401 CAP;.022U,CR,25V ,10%,0603,X7R,S 141 8050D N/B Maintenance 9. Spare Part List(6) Part Number Description Location(S) Part Number Description Location(S) 272105332402 CAP;3300P,50V,10%,0402,SMT PC28,PC56 273000990127 INDUCTOR;IHLP5050CE-01-0.68uH,VI PL711 272105470402 CAP;47P ,50V ,+ -10%,0402,NPO,S C1,C143,C144,C154,C172,C2,C4,C 273000990184 INDUCTOR;3.0UH,30%,CDRH5D28,H3.0 PL717 272105471403 CAP;470P ,50V,10%,0402,X7R,SMT C41,C729,C742,C751 273000990185 INDUCTOR;3.9UH,30%,CDRH8D43,H4.5 PL706,PL707,PL715 272431157507 CAP;150U ,TPC,6.3V,20%,H1.9,7343 272431157512 CAP;150U,6.3V,+/-20%,H2.8,PT,NCC t t n e e r c m e u S c c Do a iT ial M t n e id f n o C C701,C713,C743,C768,PC712,PC7 273000990186 INDUCTOR;3.0UH,30%,CDRH6D28,H2.8 PL709,PL713,PL714 273001050039 XSFORMER;10/100 BASE,LF-H80P,SMT U717 PC775,PC778,PC781,PC784 273001050069 TRANSFORMER;10/100 BASE,NS0013,S PC729,PC749 273001050160 XFMR;CI8.5,25T/2150T,300mH,ONLY T1 PC787,PC788,PC811,PC815 274010800405 XTAL;8Mhz,30PPM,16PF,8*4.5,2P,SM X1 C466,C474,C489,C951 274011431414 XTAL;14.318MHZ,32PF,50PPM,8*4.5, X703 CP2 274012457406 XTAL;24.576MHZ,16PF,50PPM,8*4.5, X707 L19,L20,L38,L42,L43,L45,L56,L7 274012500415 XTAL;25MHZ,20PF,30PPM,8.0*4.5,SM X706 L13,L14,L16,L50,L52,L53,L55,L5 274012700406 XTAL;27MHZ,20PF,20PPM,8.0*4.5,SM X702 L58,L59,L60 274013276103 XTAL;32.768KHZ,20PPM,12.5PF,CM20 X704 L10,L11,L12,L36,L37,L7,L9 281101015001 IC;MP1015EM-Z,CCFL CTRL,TSSOP20, U1 L41,L732,L735,L737 282574008005 IC;74AHC08,QUAD 2-I/P AND,TSSOP, U9 L15,L17,L18,L24,L27,L46,L47,L5 282574014004 IC;74AHC14,HEX INVERTER,TSSOP,14 U703 L743,L746 282574132001 IC;74AHCT1G32,SINGLE OR GAT,SOT2 U17 L26,L28,L29,L30,L31,L32,L33,L3 283449004001 IC;FLASH,512*8,FWH/LPC,PM49FL004 L2,L22,L5 283450040001 IC;FLASH,512*8,FWH,M50FW040K1,PL PL719 283467490001 IC;FLASH,512K*8,FWH,SST49LF004A, 273000500115 CHOKE COIL;400uH MIN,120mΩ MAX; L724 283467490002 IC;FLASH,512K*8,FWH,W39V040FAP,P 273000610025 FERRITE ARRAY;120OHM/100MHZ,ONLY FA2 283467530001 IC;EEPROM,S24CC02A,2K,SO8,SMT,ON 273000620001 FERRITE ARRAY;600OHM/100MHZ,2520 L49,L51,L740,L83 283467540001 IC;EEPROM,M24C02-WMN6T,2K,SO8,SM IC2 273000990021 INDUCTOR;33uH,CDRH124,SUMIDA,SMT PL710 283467540002 IC;EEPROM,M93C46-WMN6T,64*16 BIT U722,U723 273000990054 INDUCTOR;10UH,D124C,+/-20%,TOKO, PL702,PL703 283767540001 IC;K4D263238E,DDR SDRAM,4MX32,BG U1,U3,U708,U709 272431227402 CAP;220U,2V,-35/+10%,H1.9,S,SP-C 272431227504 CAP;220U ,4V ,20%,7343,POSCAP,SM 272431337506 CAP;330U,4V,20%,7343,SMT 272601107506 EC;100U ,6.3V,M,9.3*3.6,-55~105' 272625470401 CP;47P*4 ,8P,50V ,10%,1206,NPO,S 273000130001 FERRITE CHIP;120OHM/100MHZ,1608, 273000130006 FERRITE CHIP;600OHM/100MHZ,.2A,1 273000130015 FERRITE CHIP;220OHM/100MHZ,1608, 273000130039 FERRITE CHIP;130OHM/100MHZ,1608, 273000150002 FERRIET CHIP;120OHM/100MHZ,2012, 273000150013 FERRITE CHIP;120OHM/100MHZ,2012, 273000150033 PHASEOUT;FERRITE CHIP,120OHM/100 273000150307 FERRITE BEAD;120 OHM/100MHZ,3A,0 273000150313 CHOKE COIL;90OHM/100MHZ,20%,2012 273000500092 CHOKE COIL;2.2UH ,20%,16A,3.5MM 142 8050D N/B Maintenance 9. Spare Part List(7) Part Number Description Location(S) Part Number Description Location(S) 283767540002 IC;EM6A9320BI-3.6M,DDR SDRAM,4MX 286301470001 IC;SC1470,PWM CTRL,TSSOP,14P,SMT PU16 283767630002 IC;HY8250128323,DDR SDRAM,4MX32, 286302211006 IC;CP2211,POWER DISTRI SW,REV.C1 U728 286302951015 IC;LP2951ACM,VOLTAGE REGULATOR,S U11 284500522001 IC;855GME GMCH,NORTH BRIDGE,BGA, 284500655003 IC;ALC655,AUDIO CODEC,LQFP,48P,S U714 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C U726 286303107001 IC;AMS3107C,3.3V,1%,VOL REGULATO U13 U710 286303728002 IC;LTC3728LX,PWM CTRL,LTC,5X5 QF PU14,PU15,PU2,PU703 U711 286303734001 IC;LTC3734,PWM CONTROLLER,32-QFN PU3 U724 286309167001 IC;RT9167-47CB,200MA LDO REGULAT U18 U706 286309701001 IC;RT9701,POWER DISTRI SW,SOT23- U701,U705 U719 286369229301 IC;G692L293T,RESET CIRCUIT,2.93V U21 U715 288100024002 DIODE;RLZ24D,ZENER,23.63V,5%,SMT PD701 288100032013 DIODE;BAS32L,VRRM75V,MELF,SOD-80 D24,D7,PD5 U712 288100054001 DIODE;BAT54,30V,200mA,SOT-23 D10,D11,D15,D16,D2 IC1 288100054002 DIODE;BAT54C,SCHOTTKY DIODE,SOT2 D22,PD4 U524 288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM D13 PU5 288100056005 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM ZD3,ZD4 U19 288100056017 DIODE;BAW56LT1,70V,215MA,SOT-23, D704,D715,PD1,PD6,PD7,PD705 PU1 288100070006 DIODE;BAV70LT1,70V,225MW,SOT-23, D12,D18,PD702,PD704 U725 288100099012 DIODE;BAV99LT1,70V,450MA,SOT-23, PD2,PD3 PQ11 288100140007 DIODE;B140,40V,1A,SMA,DIODES,SMT PD706,PD725 PU7 288100340008 DIODE;B340LA,40V,3A,SMA,DIODES,S PD713,PD714,PD718 286300690001 IC;GMT690B,RESET CIRCUIT,2.93V,S U10 288101040006 DIODE;SBM1040,10A,SCHOTTKY,POWER PD703 286300710002 IC;CB710,CARDBUS/CARD READER,LFG U727 288104148001 DIODE;RLS4148,200MA,500MW,MELF,S D17,D19,D21,D27,D703 286300812002 IC;S-812C,DECECTOR,SOT-89,PRC IC3 288105515001 DIODE;BZV55-C15,ZENER,5%,SOD-80, PD709 286301117021 IC;AMS1117,VOL REGULATOR,1A,SOT- U6 288110355001 DIODE;1SS355,80V,100mA,SOD-23,SM D2 286301414001 IC;MM1414,PROTECTION,TSOP-20A,PR IC4 288111544001 DIODE; 1SR-154-400 400V 1.0A D1 284501014001 IC;ATI MOBILITY M10-P,A14,AGP,BG 284502779001 IC;P2779A,EMI REDUCTION,SO8 284506307001 IC;VT6307L,PCI-1394,2PORT,LQFP,1 284507460002 IC;ADT7460,TEMPERATURE MTR,QSOP, 284508100009 IC;RTL8100CL,LAN CONTROLLER,LQFP 284582801044 IC;FW82801DBM,ICH4-M,BGA,421P 284583950002 IC;W83L950D-Ver.C,LPC_KBC,LQFP,8 284595081201 IC;ICS950812,CK408 CLOCK GEN,TSS 286002040001 IC;BQ2040,GAS GAUGE,SO,16P,SMT 286100212001 IC;TPA0212,AMPLIFIER,TSSOP,24P,S 286100393004 IC;LMV393,DUAL COMPARTOR,SSOP,8P 286100822002 IC;LMV822,OP AMP,DUAL,CMOS,MSOP, 286104173001 IC;MAX4173F,I-SENSE AMP,SOT23,6P 286104871002 IC;LM4871LD,AUDIO AMP,4Ohm,2.5W, 286300431014 IC;SC431LCSK-.5,.5%,ADJ REG,SOT2 286300594001 IC;TL594C,PWM CONTROL,SO,16P 143 8050D N/B Maintenance 9. Spare Part List(8) Part Number Description Location(S) Part Number Description 288200144008 TRANS;DTA144EKA,PNP,SMT Q1 291000013027 CON;HDR,MA,15P*2,ACES,88026-3000 288200301001 TRANS;FDV301N,N-CHANNEL,SOT23 Q42 291000020204 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM 288202215001 TRANS;MUN2215T1,N-MOSFET,SC59,SM Q719,Q720 291000020206 CON;HDR,MA,2P*1,1.25MM,H2.57,R/A t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Location(S) J716 J3,J7,J705,J715 288202222019 TRANS;MMBT2222ALT1,NPN,TO236AB,O PQ15 291000021105 CON;HDR,MA,11P*1,ACES,87213-1100 CN1 288202237002 TRANS;MUN2237T1,NPN,SOT-23,SMT,O PQ24,Q47 291000021105 CON;HDR,MA,11P*1,ACES,87213-1100 J1 Q12,Q23,Q26,Q27,Q29,Q31,Q32,Q 291000023008 CON;HDR,FM,15P*2,0.8MM.H5,R/A,SM J717 Q13,Q14,Q24,Q43,Q48,Q51 291000023011 CON;HDR,MA,15P*2,88031-3000,ACES J1 PQ10,PQ9,Q20,Q708,Q718 291000152603 CON;FPC/FFC,26P,1MM,R/A,KBD,SMT J5 PU10,PU9 291000251246 MINIPCI SOCKET;124P,R/A,0.8MM,H= J713 PQ701,PQ704,PQ707 291000256843 CON;IC CARD,68P,UP,STANDOFF 0.0 J6 Q3,Q5 291000614793 IC SOCKET;UPGA479M,479P,MOLEX U713 PU11,PU12,PU13,PU712 291000622007 CON;DIMM,R/A,200P,.6,H9.2,REVERS J711 Q9,U704,U707 291000811008 CON;PHONE JACK,2 IN 1,7.0MM,ALLT J709 PU710,U7 291000920605 CON;STEREO JACK,6P,W9.5,33184000 J719,J721 PU4,PU6,PU702,PU705,PU707,PU 294011200016 LED;GREEN,H0.8,0603,CL-190G,SMT D32,D33,D34,D35,D36,D37,D38 PU701 294011200034 LED;GREEN,H.8,0603,19-21VGC/TR,S LED4,LED5 PQ13,Q711 294011200034 LED;GREEN,H.8,0603,19-21VGC/TR,S LED3,LED6 PQ1,PQ12,PQ14,PQ16,PQ17,PQ1 294011200043 LED;RE/GR,H0.8,L1.9,W1.6,19-22SR LED1 J2 294011200043 LED;RE/GR,H0.8,L1.9,W1.6,19-22SR LED2 J2 294011200069 LED;GREEN,19-21VGC/TR8,LED_CL190 291000000706 CON;BATTERY,7P,MA,2.5MM,R/A,C103 J703 294011200069 LED;GREEN,19-21VGC/TR8,LED_CL190 291000010209 CON;HDR,MA,2P*1,1.25MM,H4.2,ST,S J710 295000010028 FUSE;0.14A/60V,POLY SWITCH,PTC,S F2 291000010303 CON;HDR,MA,3P*1,1.25MM,H4.2,ST,S J707 295000010048 FUSE;0.5A/15V,POLY SWITCH,SMD F701 291000010619 CON;HDR,MA,6P,ACES,87151-0607,SM J4 295000010114 FUSE;FAST,1.75A,63VDC,1206,SMT,P F1 291000013025 CON;HDR,MA,15P*2,ACES,88107-3000 J2 295000010140 FUSE;FAST,2A,63VDC,1206,SMT,0433 F1 288202240001 TRANS;MUN2240T1,NPN,SOT-23,ON 288202301001 TRANS;SI2301DS,P-MOSFET,SOT-23 288203904022 TRANS;MMBT3904L,NPN,Tr35NS,TO236 288204406001 TRANS;AO4406,N-MOS,.0165OHM,SO8 288204407001 TRANS;AO4407,P-MOS,.01OHM,SO8,SM 288204409001 TRANS;AO4409,P-MOSFET,SO-8P,MSL, 288204410010 TRANS;AO4410,N-MOSFET,ID=18A,0.0 288204435003 TRANS;FDS4435,P-MOSFET,35mOHM,SO 288204800001 TRANS;SI4800DY,N-MOS,.0185OHM,SO 288204900001 TRANS;AO4900,DUAL N-MOSFET WITH 288204914001 TRANS;AO4914,DUAL N-MOSFET,WITH 288221371002 TRANS;MUN2137T1,PNP,SMT,ON 288227002006 TRANS;2N7002LT1,N-CHANNEL FET,ES 291000000029 CON;MINI 4 IN 1 SOCKET CONNECTOR 291000000203 CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM 144 8050D N/B Maintenance 9. Spare Part List(9) Part Number Description Location(S) Part Number Description Location(S) 295000010141 FUSE;FAST,3A,32VDC,1206,SMT,0433 PF703 331870007007 CON;MINI DIN,7P,R/A,W/GROUND,330 J704 295000010163 FUSE;NORMAL,7A/24VDC,0433007,120 PF1,PF2,PF702 331910002006 CON;POWER JACK,2P,20VDC,5A,DIP PJ701 332110020165 WIRE ;#20AWG,UL1007,L=160mm,RED, CN1 295000010183 FUSE;FAST,1.75A,63VDC,1206,SMT,0 295000100004 FUSE;FAST,1A,63V,1206,THIN FILM 297004010001 SW;PUSH BUTTOM,5P,SPST,12VDC,50m 297120101007 SW;DIP,SPST,4P,24VDC,.025A,SMT 297140200003 SW;COVER SWITCH,0.1A,30V,4P,T-ME 310111103029 THERMISTOR;10K,1%,BN35-3H103F,18 316680900001 PCB;PWA-8050 M BD 316680900006 PCB;PWA-8050/BATT ,PR AND GA BD 316680900007 PCB;PWA-8050/Transition BD 316681300001 PCB;PWA-INVERTER BD (DA-1A08-A); 322680900001 CABLE FFC;TP,8050 323767720004 DDR SODIMM MODULE;256MB,77.10634 324180786388 IC,CPU,BANIAS,1.5GHZ,MICRO-FCPGA 331000000302 CON HOLDER;PCMCIA,UP,STANDOFF 0. t t n e e r c m e u S c c Do a iT ial M t n e id f n o C F3 332110020173 WIRE ;#20AWG,UL1007,L=256mm,BLAC CN4 SW2,SW4,SW5 332110026150 WIRE ;#26AWG,UL1007,L=208mm,BLUE CN2 SW701 332110026151 WIRE ;#26AWG,UL1007,L=142mm,YELL CN3 SW1 332810000034 PWR CORD;250V/2.5A,2P,BLK,EU,175 RT1 333050000117 SHRINK TUBE;UL,600V,105'C,ID2.5* R01 335152000026 CFM-BAT;FUSE,THERMAL,NEC,SF91E 335152000085 FUSE; 128 DC-7A/50V 139 ℃only UC R00 335152000097 FUSE;LR4-73X,POLY SWITCH,PWR R0F 338536010052 BATTERY;LI,3.7V/2.2AH,18650,SANY 339115000046 MICROPHONE;-60dB+-2dB,D6.0*H2.7, 340680900003 SPEAKER ASSY;R,8050 340680900004 COVER ASSY;8050 J718 340680900005 HOUSING ASSY;8050 CON1 340680900006 BRACKET ASSY;SYSTEM,8050 J701 340680900008 SHIELDING ASSY;COVER,8050 J714 340680900009 BRACKET ASSY;TP,8050 331040004024 CON;HDR,MA,4P*1,H=5.9,R/A,USB,DI J706 340680900010 COVER ASSY;HDD,8050 331040050018 CON;HDR,BTB R/A,0.8MM,S-TECH1507 J708 340680900011 HOUSEING ASSY;LCD,8050 331660020005 DIMM SOCKET;DDR SODIMM 200P, CA0 J712 340680900012 COVER ASSY;LCD,8050 331710015016 CON;D,FM,15P,3ROW,SUYIN,070912FR J702 340680900020 BEZEL ASSY;COMBO,QSI,SBW242,8050 331840010008 CON;STEREO JACK,10P,W/SPDIF,R/A, J720 340680900026 SHIELDING ASSY;HDD,8050 331000007025 CONNECTOR;7 PIN,DIP,ALLTOP,C1034 331000008033 CON;USB,FM,H15.64,R/A,4P*2,2522A 331030044019 CON;HDR,FM.22P*2,R/A,ST,ACE-1A2, MIC1 340680900002 SPEAKER ASSY;L,8050 J6 331000004009 CON;IEEE1394,MA,4P*1,0.8MM,R/A F1 145 8050D N/B Maintenance 9. Spare Part List(10) Part Number Description Location(S) Part Number Description 340680900027 WLEN ASSY;CABLE,8050 344680900048 DUMMY CARD;PCMCIA,8050 340680900028 WIRE ASSY;INVERTER,8050 344680900049 COVER;HINGE,L,8050 340680900029 COVER ASSY;MINIPCI,8050 345677000018 CONDUCTIVE TAPE;LCD,LYNX 340680900034 SPEAKER ASSY;WOOFER,NEW,8050 340680900035 HEATSINK ASSY;DESCRETE,UNP,8050 340683400029 HEATSINK ASSY;NORTHBRIDGE,8050F 341677000002 SPRING;SCREW,HEATSINK,LYNX 341680900001 SPC SCREW;#4-1/4,8050 342502900001 CONTACT PLATE;W4L27T0.15,7068 342502900001 CONTACT PLATE;W4L27T0.15,7068 342503200004 CONTACT PLATE;W4L63T0.15,1/4,T T 342672200010 BRACKET;CD-ROM,8500 342672400007 FINGER;EMI GROUNDING SMD FINGER 342677000014 SMT NUT;A40M20-50,EMI STOP,LYNX 342680900005 HINGE;R,8050 342680900006 HINGE;L,8050 342680900009 SMT NUT;A40M20-55,EMI STOP,8050 342683400005 SPRING;HEATSINK,VGA,8050F 344680900002 cover;battery,8050 344680900003 housing;battery,8050 Location(S) t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 345677300001 RUBBER;SILICONE RUBBER,T=1.5mm,D 346503100005 INSULATOR;5,BATTERY ASSY,7521Li 346503200202 INSULATOR;BATT ASSY,ONE ROUND,BL 346677000016 SPONGE;RTC,LYNX 346677300001 INSULATOR;FIBER,UL94V-0,D=17.5mm 346680900001 INSULATOR;MB,8050 346680900002 INSULATOR;CARD READER,8050 346680900005 INSULATOR;INVERTER,LCD,8050 346680900007 INSULATOR;PCB,ASSY,L105,W12T1.0 TP45,TP48,TP50 346680900009 INSULATOR;PCMCIA,8050 MTG701,MTG702 346680900010 INSULATOR;DDR,MINIPCI,8050 346680900011 MYLAR;COVER,LCD,8050 346680900017 INSULATOR;L16W8.5T0.05MM,DIALAMY MTG703,MTG704 346681800004 INSULATOR;BATT,ASSY,L129W15T0.25 347105015007 GASKET;1,05,015,007 347105030025 GASKET;1,05,030,025 347105035020 GASKET;1,05,035,020 344680900009 COVER;REAR,R,8050 347108030008 GASKET;1,08,030,008 344680900010 COVER;REAR,L,8050 347110003010 GASKET;1,10,003,010 344680900011 COVER;HINGE,R,8050 347110010010 GASKET;1,10,010,010 344680900015 COVER;CPU,8050 361200001018 CLEANNER;YC-336,LIQUID,STENCIL/P 344680900016 COVER;DDR,8050 361400003003 JET-MELT ADHESIVES;3478-Q,5/8in* 146 8050D N/B Maintenance 9. Spare Part List(11) Part Number Description Location(S) Part Number Description 361400003005 ADHESIVE;HEAT,TRANSFER,HTA-48(W) 411681300002 PWA;PWA-INVERTER BD,SMT,DA-1A08- 361400003021 SOLDER CREAM;NOCLEAN,P4020870980 411681300003 PWA;PWA-INVERTER BD,SMT TOP,DA-1 361400003021 SOLDER CREAM;NOCLEAN,P4020870980 411681300004 PWA;PWA-INVERTER BD,SMT BOT,DA-1 361400003030 ADHESIVE;ABS+PC PACK,G485,CEMIDA 365350000003 SOLDER WIRE;0.8MM,SN43/PB43/BI14 370102010201 SPC-SCREW;M2L2,NIW,K-HD,t=0.8,NL 370102010303 SPC-SCREW;M2L3,NIW,K-HD(+),NYLOK 370102010409 SPC-SCREW;M2L4,K-HD(t0.3),NIB/NL 370102010409 SPC-SCREW;M2L4,K-HD(t0.3),NIB/NL 370102010502 SPC-SCREW;M2 L5,NIB,K-HD,t0.8,NL 370102010607 SPC-SCREW;M2L6,K-HD(+),NIW/NLK,H 370102030301 SPC-SCREW;M2L3,K-HD,1,NIB/NLK 370102030301 SPC-SCREW;M2L3,K-HD,1,NIB/NLK 370102610401 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N 370102610401 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N 370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK 370102610603 SPC-SCREW;M2.6L6,K-HD,NIB/NLK 370102611601 SPC-SCREW;M2.6*L16,NIB,K-HD 370103010405 SPC-SCREW;M3L4,NIW,K-HD,T0.3 371102010252 SCREW;M2L2.5,K-HEAD(+),NIB/NLK t t n e e r c m e u S c c Do a iT ial M t n e id f n o C Location(S) 411681710001 PWA-PWA-BATT BD;LI,4.4Ah,2P3S,BL 411681710002 PWA-PWA-BATT BD;SMT,BL3244G095/8 411682700001 PWA;PWA-8050D,ATIM-A14-64M,MOTHE 411682700002 PWA;PWA-8050D,ATIM-A14-64M,MOTHE 411682700003 PWA;PWA-8050D,ATIM-A14-64M,MOTHE 412155600047 PCB ASSY;MDM,56K,UNIV,F-PACK,WO/ 412673400008 PCB ASSY;MINI-PCI,TYPE IIIB,INTE 412681300001 PCB ASSY;D/A BD,DA-1A08-A,PWR 413000020388 LCD;LTN154X1-L02,TFT15.4",XGA,SA 416268090002 LT PF;SAMSUNG,15.4",LTN154WX,805 422674300071 WIRE ASSY;MDC,E-NOTE 422677000008 WIRE ASSY;BATT TO MB,FOR LYNX,MO J710 422680900003 WIRE CABLE;SAM LTN154X1,8050 431680900004 CASE KIT;8050D,ATIM 441674800032 CONTACT PLATE ASSY;W4L27T0.15,S441680900031 LCD ASSY;SAMSUNG,XGA,15.4",LTN15 441681700001 BATT ASS'Y;11.1V,4.4Ah,LI,BL3244 371102010252 SCREW;M2L2.5,K-HEAD(+),NIB/NLK 441681700002 BATT ASSY;11.1V,4.4Ah,LI,CASE CL 371102610603 SCREW;M2.6L6,FLNG/PAN(+),NIW/NLK 441681700003 BATT ASSY;11.1V,4.4Ah,LI,CORE PA 373101712351 T-SCREW;B,M1.7,L2.35,K-HD,2,NIB 441681710031 CONTACT PLATE ASSY;W4L27T0.15,FU 411680900019 PWA;PWA-8050-4 in 1 TRANSITION B 442672600031 AC ADPT ASSY;19V,3.16A,DELTA,706 411681300001 PWA;PWA-INVERTER BD,DA-1A08-A,PW 442680900051 TOUCHPAD MODULE;SYNAPTICS,TM42PU 147 8050D N/B Maintenance 9. Spare Part List(12) Part Number Description Location(S) 451680900001 LABEL KIT;N-B,8050 451680900031 HDD ME KIT;8050 451680900051 LCD ME KIT;SAMSUNG,15.4",8050 451680900072 HOUSING KIT;8050,ATIM10/11 451680900093 HEATSINK ASSY DISCRETE;UNP,8050 451680900094 HEATSINK ASSY DISCRETE;MPT,8050 451680900151 ROM ME KIT;8050 451999900003 HEATSINK DISCRETE OPTION;8050 461680900006 PACKING KIT;N-B BOX,8050 481680900001 F/W ASSY;SYS/VGA BIOS,8050,ATIM 481680900002 F/W ASSY;KBD CTRL,8050 523402379038 HD DRIVE,40GB,2.5",MHT2040AT,FUJ 523430061010 DVD COMBO DRIVE;24X10X8X24,SBW-2 523468090002 HDD ASSY;40GB,MHT2040AT,FUJITSU, 523468090029 COMBO ASSY;SBW-242B,QSI,8050 526268270004 LTX;8050DA/5ACB/40H/9UI9/A5D3A/X 531020237777 KBD;88,UI,K011818A1,8050,BK 600100010009 SOLDER WIRE;63/37,0.8,CM,N/C,PRC 600100010009 SOLDER WIRE;63/37,0.8,CM,N/C,PRC 600100010009 SOLDER WIRE;63/37,0.8,CM,N/C,PRC t t n e e r c m e u S c c Do a iT ial M t n e id f n o C U15 U16 624200010140 LABEL;5*20,BLANK,COMMON P/N:526268270004 148 t t n e e r c m e u S c c Do a iT ial M t n e d i f n Co PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 5 4 3 2 1 REVISION 8050D R01 PROJECT CODE- G113 PRODUCT CODE- 6827 CHAGND TP46 TOUCHPAD_METAL10 TOUCHPAD_METAL10 IDSEL PCI_REQ3# / PCI_GNT3# PCI_REQ0# / PCI_GNT0# AD18 PCI_REQ1# / PCI_GNT1# AD21 PCI_REQ2# / PCI_GNT2# AD17 CARDBUS / CARDREADER PCI_INTB# / PCI_INTC# IEEE1394 PCI_INTG# PCI_INTD# R00 2003/8/26 R0A 2003/10/09 R0B TOUCHPAD_METAL5 TP48 2003/11/07 TP50 R01 TP47 TP51 TP52 TOUCHPAD_METAL10 TOUCHPAD_METAL10 TOUCHPAD_METAL10 342672400007 1 1 1 GND CHANGE CARDBUS/CARD READER CONTROLLER FROM R5C592 TO CB710 2. USE IEEE1394 CONTROLLER VT6307 INSTEAD OF R5C592 3. ADD SPDIF FUNCTION 4. CHANGE CARDBUS CONNENTOR PLACEMENT FORM COMPONENT SIDE TO SOLDER SIDE 5. CHANGE MDC AND MINIPCI CONNECTORS PLACEMENT FROM SOLDER SIDE TO COMPONENT SIDE 6. CHANGE LVDS ROUTING FAR AWAY POWER SWITCHING SIGNALS 1. CHANGE TV CONNECTOR 2. CHANGE BATTERY CONNECTOR 1. EXCHANGE TV CONNECTOR PIN 6 AND PIN 7 2. ADD POWER CONSUMPTION SAVING CIRCUIT BUT RESERVE 3. CHANGE SOME BEAD TO 0 OHM IN AUDIO REGION 4. CHANGE SOME RESISTOR AND CAPACITANCE TO INCREASE SUBWOOFER GAIN DELETE SOME COMPONENT AROUND TV ENCODER D 2003/12/16 342672400007 GND TP4 GND TOUCHPAD_METAL5 GND TP45 5. TOUCHPAD_METAL10 1 1 1 1. AD20 TOUCHPAD_METAL10 TOUCHPAD_METAL10 GND 1 GND HISTORY TP3 1 1 TOUCHPAD_METAL10 1 TOUCHPAD_METAL10 1 TP44 1 342672400007 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C GND GND GND GND CARDREADER MDC 342677000014 MTG702 MTG/ID1.2/OD4.6 342677000014 MTG701 MTG/ID1.2/OD4.6 MTG704 MTG/ID1.2/OD4.6 MTG703 MTG/ID1.2/OD4.6 1 1 C1007 50V 1 +/-20% 2 50V 1 +/-20% +5V ESD +1.35V C1008 1 1 JS702 1 C EC +3V 2 0402 1000P 2 0402 1000P TP722 TP723 TOUCHPAD_METAL10 TOUCHPAD_METAL10 +3V C357 50V 1 +/-20% 4 5 6 7 8 GND GND MTG8 ID3.0/OD11 MTG118NRD433_3016A 8050N 3 2 1 16 15 14 13 12 GND_45 1394_GND 4 5 6 7 8 16 15 14 13 12 TP58 RD080_051/NA TP59 RD080_051/NA B 1 16 15 14 13 12 GND_USB GND 1 4 5 6 7 8 2 0402 1000P GND GND 9 10 11 16 15 14 13 12 3 2 1 MTG7 ID3.0/OD11 MTG118NRD433_3016A 50V 1 +/-20% +5V 2 0402 1000P AGND MTG4 ID3.0/OD11 MTG118-RD433-N-30X16 +2.5V_M10 C1006 GND GND 1 SHORT-SMT4 GND 1 GND 9 10 11 4 5 6 7 8 TP43 GND 3 2 1 16 15 14 13 12 TP42 GND 9 10 11 4 5 6 7 8 9 10 11 B REQ/GNT PCI_INTE# EMI MTG2 ID3.0/OD11 MTG118-RD433-N-30X16 3 2 1 MTG1 ID3.0/OD11 MTG118NRD433_3016B INTERRUPT LAN MINIPCI 3 2 1 C PAGE 1 TITLE PAGE 2 CPU- BANIAS(1/2) PAGE 3 CPU-BANIAS(2/2) PAGE 4 NB-MONTARA-GME(1/2) PAGE 5 NB-MONTARA-GME(2/2) PAGE 6 DDR-DIMM PAGE 7 VGA-M10(1/4) PAGE 8 VGA-M10(2/4) PAGE 9 VGA-M10 (3/4) PAGE10 VGA-M10(4/4) PAGE11 CLOCK SYNTHERIZER/TV ENCODER PAGE12 CRT/LCD PAGE13 SOUTHBRIDGE-ICH4-M(1/2) PAGE14 SOUTHBRIDGE-ICH4-M(2/2) PAGE15 CDROM/HDD/USB CONNECTOR PAGE16 LAN RTL8100CL PAGE17 R5C811/841 PAGE18 IEEE1394 PAGE19 MINI-PCI PAGE20 AUDIO CODEC(ALC655) PAGE21 AUDIO AMPLIFIER/SUBWOOFER PAGE22 KBC(W83L950D) PAGE23 TOUCHP_PAD/FWH/LED PAGE24 PULL HIGH PAGE25 PERPHERIAL PAGE26 +2.5VS_DDR_P/+1.25V_DDR_P PAGE27 +3VS_P/+5VS_P PAGE28 +1.5V_P/+1.05V_P PAGE29 +1.8V_P/1.35V_P PAGE30 +1.2V/1.0V_M10 PAGE31 CPUCORE PAGE32 ADAPTER/VMAIN PAGE33 CHARGER/DISCHARGER 9 10 11 D PCB P/N 316680900001 ASSY P/N 411682700001 PCI DEVICE TAPEOUT DAY GND CPU GND MTG27 ID5.3/OD7.5 MTG28 ID5.3/OD7.5 MTG12 ID5.3/OD7.5 MTG32 ID5.3/OD7.5 CAGND MTG10 ID2.8/OD11 1 GND GND GND 3 2 1 3 2 1 3 2 1 FD704 FIDUCIAL-MARK 1 1 GND 1 1 MTG15 ID3.0/OD9.0 MTG118-RD354-N-30X12 1 MTG3 ID3.0/OD9.0 MTG118-RD354-N-30X12 FD3 FIDUCIAL-MARK MTG31 ID3.0/OD8.0/CP7.5X9.5 FD703 FIDUCIAL-MARK MTG6 ID3.0/OD9.0 MTG118-RD354-N-30X12 FD4 FIDUCIAL-MARK 1 MTG5 ID3.0/OD9.0 FD2 FIDUCIAL-MARK GND 1 MTG22 ID2.8/OD11 GND 1 GND 1 1 1 GND 光學定位點 FD1 FIDUCIAL-MARK 1 GND 1 3 2 1 MTG24 ID5.3/OD7.5 16 15 14 13 12 FD702 FIDUCIAL-MARK FD701 FIDUCIAL-MARK 1 GND_45 4 5 6 7 8 1 GND 16 15 14 13 12 1 4 5 6 7 8 MTG14 ID3.0/OD11 MTG118NRD433_3016B 9 10 11 3 2 1 16 15 14 13 12 9 10 11 4 5 6 7 8 9 10 11 16 15 14 13 12 9 10 11 4 5 6 7 8 MTG13 ID3.0/OD11 MTG118-RD433-N-30X16 3 2 1 MTG11 ID3.0/OD11 MTG118NRD433_3016A 3 2 1 MTG9 ID3.0/OD11 MTG118-RD433-N-30X16 A A 12 11 10 4 5 6 12 11 10 7 8 9 4 5 6 7 8 9 12 11 10 7 8 9 4 5 6 DRAWN DESIGN CHECK ISSUES GND GND 1394_GND Title 8050D MOTHER B/D Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 1 of 34 5 4 3 2 1 VCC : PROCESSOR CORE POWER SUPPLY. VCCA : ISOLATE POWER FOR INTERNAL PLL. CPU-BANIAS (1/2) VCCP : PROCESSOR I/O POWER SUPPLY. VCCQ : QUIET POWER SUPPLY FOR ON DIE COMP CKT. HA#[3..31] HADS# 4 4 HADSTB#0 HADSTB#1 4 4 4 4 HBR0# HBPRI# HBNR# HLOCK# +VCCP 31 PM_PS HRS#[0..2] HHIT# HHITM# HDEFER# HTRDY# HRS#[0..2] 13 14 4 HA20M# HFERR# HDPWR# 13 HSLP# 1 2 0/NA5% R292 13 13 13 HIGNNE# HSMI# HPWRGD 22 HPROCHOT# 13 4,13 B U3 AE5 HBR0# R264 56 1 4 4 4 4 4 N2 4 HSTPCLK# HDPSLP# 13 13 HINTR HNMI 13,23 4 HINIT# HCPURST# 11 CLK_ITP_CPU 11 CLK_ITP_CPU# 2 0402 5% HRS#0 HRS#1 HRS#2 HA20M# HDBR# HSLP# HPSI# N4 J3 L1 J2 A4 K3 K4 L4 M3 H1 K1 L2 C2 D3 C19 A7 A6 E1 HIGNNE# HSMI# HPWRGD A3 B4 E4 HPROCHOT# B17 HSTPCLK# HDPSLP# C6 B7 HINTR HNMI D1 D4 HINIT# B5 B11 A16 A15 REQ0# REQ1# REQ2# REQ3# REQ4# ADS# ADSTB0# ADSTB1# BR0# BPRI# BNR# LOCK# IERR# HIT# HITM# DEFER# TRDY# RS0# RS1# RS2# A20M# FERR# DPWR# DBR# SLP# PSI# IGNNE# SMI# PWRGOOD PROCHOT# STPCLK# DPSLP# LINT0 LINT1 INIT# RESET# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# DBSY# DRDY# THERMDA THERMDC ITP_CLK0 ITP_CLK1 THERMTRIP# HPROCHOT# R141 1K 0402 1% A13 C12 A12 C11 B13 B10 A10 AD26 E26 G1 AC1 Close to CPU as possible. < 0.5" C165 220P 0402 10% 50V C160 1U 0402 +80-20% 10V R134 2K 0402 1% HCOMP0 HCOMP1 HCOMP2 HCOMP3 P25 P26 AB2 AB1 GND AF7 HCOMP1 & HCOMP3 should be route with 5 mil width C14 C3 CPU_TEST1 CPU_TEST2 CPU_TEST3 TCK TDI TDO TMS TRST# PREQ# PRDY# C5 F23 C16 GTLREF0 GTLREF1 GTLREF2 GTLREF3 COMP0 COMP1 COMP2 COMP3 RSVD_0 RSVD_2 RSVD_3 TEST1 TEST2 TEST3 D6 D8 D18 D20 D22 E5 E7 E9 E17 E19 E21 F6 F8 F18 F20 F22 G5 G21 H6 H22 J5 J21 K22 U5 V6 V22 W5 W21 Y6 Y22 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AB6 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC9 AC11 AC13 AC15 AC17 AC19 AD8 AD10 AD12 AD14 AD16 AD18 AE9 D t t n e e r c m e u S c c Do a iT ial M t n e id f n o C HDINV#[0..3] 4 HDINV#[0..3] HDINV#0 HDINV#1 HDINV#2 HDINV#3 D25 J26 T24 AD20 DINV0# DINV1# DINV2# DINV3# +VCC_CORE AE11 AE13 AE15 AE17 AE19 AF8 AF10 AF12 AF14 AF16 AF18 HDSTBN#[0..3] HDBSY# HDRDY# CPU_THERMDA CPU_THERMDC VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 C BANIAS BGA479_SKT3 HDSTBN#[0..3] 4 HDSTBP#[0..3] M2 H2 B18 A18 1 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 +VCCP BPM0# BPM1# BPM2# BPM3# 2 C22 L24 W24 AE25 HTCLK HTDI HTDO HTMS HTRST# HPREQ# HPRDY# 1 HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 1 C23 K24 W25 AE24 C8 B8 2 0402 A9 2 0402 C9 1 1 VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 BCLK0 BCLK1 HDSTBP#[0..3] 4 4 4 CPU_THERMDA 22 CPU_THERMDC 22 C17 CPU_THRMTRIP_OUT# 14 BANIAS BGA479_SKT3 B +3V +VCCP 4 1 2 R243 51 0402 5% R219 51/NA 0402 5% R225 39 0402 1% R220 150 0402 1% HDBR# 1 R246 10K/NA 2 0402 R229 51/NA 0402 5% 1 R294 200/NA 1 R265 200/NA HINTR 1 R293 200/NA HNMI 1 R302 200/NA HSMI# 1 R268 200/NA HSTPCLK# 1 R249 200/NA HDPSLP# 1 R247 200/NA HSLP# 1 R248 200/NA HINIT# 1 R256 200/NA 2 0402 2 0402 2 0402 2 0402 2 0402 2 0402 2 0402 2 0402 2 0402 HIGNNE# HCPURST# 1 R214 680 0402 5% 2 2 1 HTRST# HTCLK GND 1 R133 27.4 1 R142 54.9 1 R291 27.4 1 R300 54.9 +VCCP HA20M# R213 27.4 0402 1% HCOMP0 & HCOMP2 should be route with 18 mil width 5% 2 R238 51 0402 5% 2 R228 51 0402 5% 2 HPREQ# HPRDY# HBPM#1 HBPM#0 HTDO HTMS HTDI 2 R224 51 0402 5% 1 1 1 1 +VCC_CORE 1 C R2 P3 T2 P1 T1 R198 56 0402 5% B15 B14 2 HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 U713B 11 HCLK_CPU 11 HCLK_CPU# HBPM#0 HBPM#1 R242 0 R237 0 +VCCP 1 HREQ#[0..4] +VCC_CORE 4 1 4 HREQ#[0..4] HD#[0..63] 2 HPWRGD HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 2 2 R301 330 0402 5% A19 A25 A22 B21 A24 B26 A21 B20 C20 B24 D24 E24 C26 B23 E23 C25 H23 G25 L23 M26 H24 F25 G24 J23 M23 J25 L26 N24 M25 H26 N25 K25 Y26 AA24 T25 U23 V23 R24 R26 R23 AA23 U26 V24 U25 V26 Y23 AA26 Y25 AB25 AC23 AB24 AC20 AC22 AC25 AD23 AE22 AF23 AD24 AF20 AE21 AD21 AF25 AF22 AF26 1 1 +VCCP D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# 2 HBR0# A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# 1 2 R289 51 0402 5% P4 U4 V3 R3 V2 W1 T4 W2 Y4 Y1 U1 AA3 Y3 AA2 AF4 AC4 AC7 AC3 AD3 AE4 AD2 AB4 AC6 AD5 AE2 AD6 AF3 AE1 AF1 2 1 +VCC_CORE D HD#[0..63] U713A HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 2 HA#[3..31] 2 4 5% 2 0402 2 0402 2 0402 2 0402 HCOMP0 1% HCOMP1 1% HCOMP2 1% HCOMP3 1% 5% GND 5% 1 R255 1K/NA 1 R143 1K/NA 1 R204 1K/NA 5% 5% 5% 2 CPU_TEST1 0402 5% 2 CPU_TEST2 0402 5% 2 CPU_TEST3 0402 5% 5% GND 5% Close to CPU as possible. 5% PLACEMENT MAX. 3" FROM CPU. GND Don't overlay by CHOKE or vibrating signals. Place close to CPU socket within 2". A A +1.5V R123 0 C163 0.1U 0402 10% 1 C316 0.1U 0402 10% 2 1 1 C162 0.1U 0402 10% 2 C161 2.2U 0603 +/-10% 2 1 1 C151 2.2U 0603 +/-10% 2 C323 2.2U 0603 +/-10% 2 1 1 C322 2.2U 0603 +/-10% 2 2 2 1 2 0805 2 1 R124 0/NA +VCCA 1 +1.8V C317 0.1U 0402 10% Title 0805 1.8V, 0.6A, 10uF and 10nF each VCCA pin. 1.5V for future support. 8050D MOTHER B/D GND Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 2 of 34 5 4 3 2 1 CPU-BANIAS (2/2) 1.180 0 0 0 0 1 0 1.676 1 0 0 0 1 0 1.164 0 0 0 0 1 1 1.660 1 0 0 0 1 1 1.148 0 0 0 1 0 0 1.644 1 0 0 1 0 0 1.132 0 0 0 1 0 1 1.628 1 0 0 1 0 1 1.116 0 0 0 1 1 0 1.612 1 0 0 1 1 0 1.100 0 0 0 1 1 1 1.596 1 0 0 1 1 1 1.084 0 0 1 0 0 0 1.580 1 0 1 0 0 0 1.068 0 0 1 0 0 1 1.564 1 0 1 0 0 1 1.052 0 0 1 0 1 0 1.548 1 0 1 0 1 0 1.036 0 0 1 0 1 1 1.532 1 0 1 0 1 1 1.020 1 1 1 2 1 1 1 GND +VCC_CORE C186 0.1U 0402 10% 16V C195 0.1U 0402 10% 16V C248 0.1U 0402 10% 16V C235 0.1U 0402 10% 16V C222 0.1U 0402 10% 16V C204 0.1U 0402 10% 16V GND C268 0.1U 0402 10% 16V C251 0.1U 0402 10% 16V C280 0.1U 0402 10% 16V C191 0.1U 0402 10% 16V C178 0.1U 0402 10% 16V C236 0.1U 0402 10% 16V 1 0 1 1 1 0 0.972 0 0 1 1 1 1 1.468 1 0 1 1 1 1 0.956 0 1 0 0 0 0 1.452 1 1 0 0 0 0 0.940 0 1 0 0 0 1 1.436 1 1 0 0 0 1 0.924 0 1 0 0 1 0 1.420 1 1 0 0 1 0 0.908 0 1 0 0 1 1 1.404 1 1 0 0 1 1 0.892 0 1 0 1 0 0 1.388 1 1 0 1 0 0 0.876 0 1 0 1 0 1 1.372 1 1 0 1 0 1 0.860 0 1 0 1 1 0 1.356 1 1 0 1 1 0 0.844 0 1 0 1 1 1 1.340 1 1 0 1 1 1 0.828 0 1 1 0 0 0 1.324 1 1 1 0 0 0 0.812 0 1 1 0 0 1 1.308 1 1 1 0 0 1 0.796 0 1 1 0 1 0 1.292 1 1 1 0 1 0 0.780 0 1 1 0 1 1 1.276 1 1 1 0 1 1 0.764 +1.5V 13,24 11,13,31 STOP_CPU# Q28 D Q45 S 2N7002/NA G 1 1 2 1 2 1 2 1 2 1 1 2 2 10K/NA 0402 5% +VCCP 120Z/100M 2012 GND 3 S L41 1 SI2301DS/NA D14 1 GND R400 B/CB# R401 1K/NA 0402 5% C196 0.1U 0402 10% 16V BAT54/NA +VCCP +VCCQ 2 D C237 10U 0805 6.3V C201 0.1U 0402 10% 16V C265 0.1U 0402 10% 16V C768 + 150U 7343 6.3V 1 1.484 C231 10U 0805 6.3V 2 0 C194 0.1U 0402 10% 16V 1 1 C242 0.1U 0402 10% 16V 2 1 1 1 C182 0.1U 0402 10% 16V 2 0 31 C259 0.1U 0402 10% 16V 1 0 VID5 2 0.988 1 1.004 1 2 0 0 1 0 1 2 1 1 C266 0.1U 0402 10% 16V 2 1 0 1 0 1 G 1 1.500 C181 0.1U 0402 10% 16V G 1.516 1 2 0 0 D 1 0 1 GND C258 10U 0805 6.3V GND GND S 1 1 C200 0.1U 0402 10% 16V G 1 0 D S 0 0 D S 0 C318 0.1U 0402 10% 16V C185 0.1U 0402 10% 16V B 2 1 C319 0.1U 0402 10% 16V 2 2 Q16 VID5 2 GND 1 0 C254 10U 0805 6.3V 2 C240 10U 0805 6.3V 2 C249 10U 0805 6.3V C831 10U 0805 6.3V 1 1 2 C158 10U 0805 6.3V +VCC_CORE 2N7002/NA D 2 2 1 1 1 C198 10U 0805 6.3V 2 2 C264 10U 0805 6.3V C157 10U 0805 6.3V 2 1 C156 10U 0805 6.3V 1 2 1 2 C155 10U 0805 6.3V +VCCP S 2 1 1 2 1 1 2 2 2 2 1 1 2 1 2 1 1 2 2 C1005 220U/NA 7343 4V GND R193 1 2 1 2 1 2 2 1 2 1 2 1 1 2 1 2 2 1 C 1 C1004 + 220U/NA + 7343 4V BANIAS BGA479_SKT3 CPUVID5 2 1 2 1 2 1 2 2 1 2 1 2 1 2 1 2 1 2 1 +VCC_CORE +VCC_CORE 1 1.196 1 C183 10U 0805 6.3V 2 VCC-Core 0 0 C177 10U 0805 6.3V 1 0 0 0 C241 10U 0805 6.3V C296 10U 0805 6.3V 2 1 0 0 C279 10U 0805 6.3V 1 2 0 0 C175 10U 0805 6.3V 2 3 0 1 C230 10U 0805 6.3V 1 4 1 1.692 C173 10U 0805 6.3V 2 5 1.708 1 GND C168 10U 0805 6.3V 1 VCC-Core 0 0 C807 10U 0805 6.3V C270 10U 0805 6.3V 2 0 0 0 C214 10U 0805 6.3V 1 1 0 0 C312 10U 0805 6.3V C179 10U 0805 6.3V 2 2 0 0 D C190 10U 0805 6.3V 1 3 0 0 C192 10U 0805 6.3V 2 4 0 C199 10U 0805 6.3V 1 5 C203 10U 0805 6.3V 2 B VID C321 10U 0805 6.3V 2 VID C189 10U 0805 6.3V +VCC_CORE C320 10U 0805 6.3V 2 R299 R298 RP28 1 8 VID0 4.7K*4/NA 7 VID1 2 1206 3 6 VID2 4 5 VID3 1 4.7K/NA 2 0402 VID4 1 4.7K/NA 2 0402 VID5 C250 10U 0805 6.3V 1 GND C267 10U 0805 6.3V 2 BANIAS BGA479_SKT3 GND C188 10U 0805 6.3V GND t t n e e r c m e u S c c Do a iT ial M t n e id f n o C +5V C193 10U 0805 6.3V 1 VSSENSE C180 10U 0805 6.3V 2 VCCSENSE C209 10U 0805 6.3V 1 AF6 1% C226 10U 0805 6.3V 2 AE7 1% C187 10U 0805 6.3V 0.844V ~ 1.356V, 32A 1 2 0402 2 0402 C220 10U 0805 6.3V GND 2 CPUVID5 1 R885 54.9 1 R899 54.9 C C257 10U 0805 6.3V +VCC_CORE 1 VID[0..4] VID[0..4] VID0 VID1 VID2 VID3 VID4 VID5 C256 10U 0805 6.3V 2 31 E2 F2 F3 G3 G4 H4 J22 J24 K2 K5 K21 K23 K26 L3 L6 L22 L25 M1 M4 M5 M21 M24 N3 N6 N22 N23 N26 P2 P5 P21 P24 R1 R4 R6 R22 R25 T3 T5 T21 T23 T26 U2 U6 U22 U24 V1 V4 V5 V21 V25 W3 W6 W22 W23 W26 Y2 Y5 Y21 Y24 AA1 AA4 AA6 AA8 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA25 AB3 AB5 AB7 AB9 AB11 AB13 AB15 AB17 1 VID0 VID1 VID2 VID3 VID4 VCCA0 VCCA1 VCCA2 VCCA3 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 2 F26 B1 N1 AC26 VCCQ0 VCCQ1 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 1 P23 W4 AB19 AB21 AB23 AB26 AC2 AC5 AC8 AC10 AC12 AC14 AC16 AC18 AC21 AC24 AD1 AD4 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AD22 AD25 AE3 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE23 AE26 AF2 AF5 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF24 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 2 +VCCQ VCCP_0 VCCP_1 VCCP_2 VCCP_3 VCCP_4 VCCP_5 VCCP_6 VCCP_7 VCCP_8 VCCP_9 VCCP_10 VCCP_11 VCCP_12 VCCP_13 VCCP_14 VCCP_15 VCCP_16 VCCP_17 VCCP_18 VCCP_19 VCCP_20 VCCP_21 VCCP_22 VCCP_23 VCCP_24 1 D +VCCA A2 A5 A8 A11 A14 A17 A20 A23 A26 B3 B6 B9 B12 B16 B19 B22 B25 C1 C4 C7 C10 C13 C15 C18 C21 C24 D2 D5 D7 D9 D11 D13 D15 D17 D19 D21 D23 D26 E3 E6 E8 E10 E12 E14 E16 E18 E20 E22 E25 F1 F4 F5 F7 F9 F11 F13 F15 F17 F19 F21 F24 G2 G6 G22 G23 G26 H3 H5 H21 H25 J1 J4 J6 U713D D10 D12 D14 D16 E11 E13 E15 F10 F12 F14 F16 K6 L5 L21 M6 M22 N5 N21 P6 P22 R5 R21 T6 T22 U21 2 +VCCP (1.05V) 1 1.05V, 2.4A +VCCP U713C GND 1 B/CB# GPIO16 A 0 1 1 1 0 0 1.260 1 1 1 1 0 0 0.748 0 1 1 1 0 1 1.244 1 1 1 1 0 1 0.732 0 1 1 1 1 0 1.228 1 1 1 1 1 0 0.716 0 1 1 1 1 1 1.212 1 1 1 1 1 1 0.700 Banias CPU 0 Celeron Banias CPU A power on default = 1 POWER CONSUMPTION SAVING CIRCUIT Title 8050D MOTHER B/D Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 3 of 34 5 4 3 2 1 NB-MONTARA-GME(1/2) AGPBUS AGP_AD[0..31] 855_DVOBHSYNC 855_DVOBVSYNC 855_DVOBD1 855_DVOBD0 855_DVOBD3 855_DVOBD2 855_DVOBD5 855_DVOBD4 855_DVOBD6 855_DVOBD9 855_DVOBD8 855_DVOBD11 855_DVOBD10 855_DVOBCCLKINT 855_DVOBFLDSTL 855_MDDCCDATA 855_DVOCVSYNC 855_DVOCHSYNC 855_DVOCBLANK# 855_DVOCD0 855_DVOCD1 855_DVOCD2 855_DVOCD3 855_DVOCD4 855_DVOCD7 855_DVOCD6 855_DVOCD9 855_DVOCD8 855_DVOCD11 855_DVOCD10 855_DVOBCINTR# 855_DVOCFLDSTL U714A HRS#0 HRS#1 HRS#2 2 HCPURST# 12,13,17,25,31 PWROK 1 0402 R217 2 0 L28 M25 N24 M28 N28 N27 P27 M23 N25 P28 M26 N23 P26 M27 F15 J11 ADS# HTRDY# DRDY# DEFER# HITM# HIT# HLOCK# BREQ0# BNR# BPRI# DBSY# RS[0]# RS[1]# RS[2]# CPURST# PWROK HDVREF[0] HDVREF[1] HDVREF[2] HAVREF HCCVREF 1 D 2 S 11 66M_MCH 11 DVOVREF R835 1 0/NA 0402 5% AGP_VREF 14 HUB_HI[0..10] +VCCP 2 HUB_HI0 HUB_HI1 HUB_HI2 HUB_HI3 HUB_HI4 HUB_HI5 HUB_HI6 HUB_HI7 HUB_HI8 HUB_HI9 HUB_HI10 C215 0.1U 0402 +80-20% 50V HUB_MCH_VREF HUB_RCOMP 13 MCH_PCIRST# R208 C216 100 0.1U 0402 0402 +80-20% 1% 50V C217 0.1U 0402 +80-20% 50V REFSET 855_DDDA 855_DDCK R790 1 10K R800 1 10K W1 T2 AD28 E8 G9 B6 2 0402 B4 2 0402 C5 +3V A7 A8 C8 D8 C9 D9 855_GREEN 855_BLUE 2 CHANGE TO 0402 GND J3 J2 855_DVOCCLK 855_DVOCCLK# K5 K1 K3 K2 J6 J5 H2 H1 H3 H4 H6 G3 855_DVOCD0 855_DVOCD1 855_DVOCD2 855_DVOCD3 855_DVOCD4 855_DVOCD5 855_DVOCD6 855_DVOCD7 855_DVOCD8 855_DVOCD9 855_DVOCD10 855_DVOCD11 DVODETECT DVORCOMP DVOCFLDSTL DVOCBLANK# L7 D1 H5 L3 855_DVODETECT R832 0402 1 40.2 2 855_DVOCFLDSTL 855_DVOCBLANK# DVOCHSYNC DVOCVSYNC HL[0] HL[1] HL[2] HL[3] HL[4] HL[5] HL[6] HL[7] HL[8] HL[9] HL[10] K6 L5 855_DVOCHSYNC 855_DVOCVSYNC LCLKCTLA LCLKCTLB H9 C6 04021 R210 04021 R799 LIBG MDDCCLK MDDCDATA MDVICLK MDVIDATA MI2CCLK MI2CDATA HLSTB HLSTB# HLVREF HLRCOMP PANELBKLTCTL PANELBKLTEN PANELVDDEN RSTIN# REFSET PSWING RCVENIN# RCVENOUT# DDCADATA DDCACLK DDCPCLK DDCPDATA B17 P7 T7 N7 M6 K7 N6 855_MDDCCLK 855_MDDCCDATA 855_MDVICLK 855_MDVIDATA 855_MI2CCLK 855_MI2CDATA G8 F8 A5 R202 1 0402 R203 1 0402 R801 1 0402 U2 AC16 AC15 MCH_PSWING RCVENIN# 1 0402 RCVENOUT# 2 0/NA 2 0/NA 2 0/NA BLADJ ENABKL_NB FPVDEN GND 1 1 C170 33P/NA 0402 +/-10% 25V C169 33P/NA 0402 +/-10% 25V 2 C775 33P/NA 0402 +/-10% 25V NC_0 NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 HSYNC VSYNC DREFSSCLK AJ29 AH29 B29 A29 AJ28 A28 AA9 AJ4 AJ2 A2 AH1 B1 R784 75/NA 0402 1% R145 75/NA 0402 1% 12 855_CRT_HSYNC 12 855_CRT_VSYNC 855_CRT_HSYNC 855_CRT_VSYNC 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 04021 R235 04021 R236 04021 R227 04021 R226 Less than 0.5" +VCCP R903 68.1 0603 1% +VCCP +VCCP MCH_PSWING GND R910 C837 100 1U/NA 0402 0402 +80-20% 1% 10V 2 1 2 2 C836 0.1U 0402 +80-20% 50V 1 1 C815 0.1U 0402 +80-20% 50V GND R850 150 0402 1% REFSET 1 127 1% 2 R163 2 2 R791 150 0402 1% 2 C784 0.1U 0402 +80-20% 50V 1 1 HYSWING 2 1 2 R913 C842 100 1U 0402 0402 +80-20% 1% 10V 2 1 2 2 C840 0.1U 0402 +80-20% 50V R855 301 0402 1% 1 2 HXSWING 1 GND 1 1 R257 C286 100 1U/NA 0402 0402 +80-20% 1% 10V 2 1 2 1 2 C287 0.1U 0402 +80-20% 50V R793 301 0402 1% 2 R902 49.9 0402 1% HCCVREF 2 HAVREF 1 1 1 R258 49.9 0402 1% A GND GND 0402 1 R1103 2 10K +1.5V 855_MI2CCLK 0402 1 R216 2 10K +1.5V 4 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 C R206 855_DVODETECT 1 2 +1.5V 1K 0402 5% 12,22 12 12 +1.5V R279 2 0/NA RDDP recommend 1K ohm resistor 8.2K/NA 8.2K/NA 8.2K/NA 8.2K/NA 8.2K/NA 8.2K/NA 8.2K/NA 8.2K/NA WHEN USE INTEGRATE VGA ADD R181 1R175 1R177 1R170 1R168 1R184 1R172 1R189 1R182 R59 1K 0402 5% DVOVREF R64 1K 0402 5% 04022 04022 04022 04022 04022 04022 04022 04022 855_ADDID0 855_ADDID1 855_ADDID2 855_ADDID3 855_ADDID4 855_ADDID5 855_ADDID6 855_ADDID7 330/NA 330/NA 330/NA 330/NA 330/NA 330/NA 330/NA 1K/NA 1 1 1 1 1 1 1 1 R174 R176 R169 R167 R183 R171 R188 R181 2 2 2 2 2 2 2 2 0402 0402 0402 0402 0402 0402 0402 0402 GND ADD ID : 0x7Fh B M10-P CONNECT TO NB WHEN USE INTEGRATE VGA DEL ALL RESISTOR R349 1 R350 1 R353 1 R357 1 R1176 1 R1177 1 R1178 1 R1179 1 IYAM0 IYAP0 IYAM1 IYAP1 IYAM2 IYAP2 IYAM3 IYAP3 GND 855_DVOCCLK 855_DVOCCLK# 855_DVOBCCLKINT 855_DVOBCINTR# 855_MI2CCLK 855_MI2CDATA 855_DVOCFLDSTL 855_DVOCHSYNC 855_DVOCVSYNC R114 R128 R147 R117 R162 R113 R150 R125 R157 1 1 1 1 1 1 1 1 1 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA 2 2 2 2 2 2 2 2 2 0402 0402 0402 0402 0402 0402 0402 0402 0402 855_DVOCD0 855_DVOCD1 855_DVOCD2 855_DVOCD3 855_DVOCD4 855_DVOCD5 855_DVOCD6 855_DVOCD7 855_DVOCD8 855_DVOCD9 855_DVOCD10 855_DVOCD11 R146 R111 R112 R126 R127 R148 R129 R149 R130 R115 R131 R116 1 1 1 1 1 1 1 1 1 1 1 1 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA 2 2 2 2 2 2 2 2 2 2 2 2 0402DVOCD0 0402DVOCD1 0402DVOCD2 0402DVOCD3 0402DVOCD4 0402DVOCD5 0402DVOCD6 0402DVOCD7 0402DVOCD8 0402DVOCD9 0402DVOCD10 0402DVOCD11 GND 3 AGP_SBSTBS AGP_SBSTBF AGP_WBF# AGP_RBF# AGP_ST0 AGP_ST1 AGP_ST2 AGP_GNT# AGP_REQ# WHEN USE INTEGRATE VGA DEL R206 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA DVOCCLK DVOCCLK# POUT/DET# DVOBCINTR# MI2CCLK MI2CDATA DVOCFLDSTL DVOCHSYNC DVOCVSYNC 2 2 2 2 2 2 2 2 0402 0402 0402 0402 0402 0402 0402 0402 R153 R154 R158 R159 R794 R795 R796 R797 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R361 1 0/NA R363 1 0/NA DVOCD[0..11] 0402 0402 0402 0402 0402 0402 0402 0402 2 0402 2 0402 TXOUT0-_ATI TXOUT0+_ATI TXOUT1-_ATI TXOUT1+_ATI TXOUT2-_ATI TXOUT2+_ATI TXOUT3-_ATI TXOUT3+_ATI 7 7 7 7 7 7 7 7 12 12 12 12 12 12 12 12 ICLKAM ICLKAP R160 1 0 R161 1 0 2 0402 2 0402 TXCLKTXCLK+ TXCLK-_ATI TXCLK+_ATI 7 7 12 12 A DVOCD[0..11] 11 Title 8050D MOTHER B/D Size C 2 2 2 2 2 2 2 2 2 TXOUT0TXOUT0+ TXOUT1TXOUT1+ TXOUT2TXOUT2+ TXOUT3TXOUT3+ 11 11 11 11 11 11 11 11 11 Date: 5 7 7 7 7 7 7 7 7 7 +1.5V 855_MI2CDATA WHEN USE INTEGRATE VGA ADD ALL RESISTOR +1.35V AGP_CBE#3 AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6 AGP_SBA7 D +1.5V NB CONNECT TO TV ENCORDER 1 +VCCP (1.05V) 2 10K 2 10K 2 10K 2 10K GND 2 Maximum length less than 0.5" from pin to voltage divider. GSBSTB# GSBSTB GWBF# GRBF# GST0 GST1 GST2 GGNT# GREQ# R144 75/NA 0402 1% Non SSC 0402GND R345 1 0/NA 2 855_HSYNC R348 1 0/NA 2 855_VSYNC 0402 7 7 7 7 7 7 7 7 7 7 7 7 5,7 855_DVOCD5 855_ADDID0 855_ADDID1 855_ADDID2 855_ADDID3 855_ADDID4 855_ADDID5 855_ADDID6 855_ADDID7 855_MDDCCLK 855_MDDCCDATA 855_MDVICLK 855_MDVIDATA GND GND AGP_PAR AGP_STOP# AGP_DEVSEL# AGP_TRDY# AGP_IRDY# AGP_FRAME# AGP_ADSTB0 AGP_ADSTB1 AGP_ADSTB0# AGP_ADSTB1# AGP_CBE#0 AGP_CBE#1 AGP_CBE#2 GCBE2# R1104 100K 0402 5% 2 10K/NA +3V 2 10K/NA A10 R798 1 1.5K/NA 2 0402 5% 855GM/GME GND BGA707_25 855_DDDA 855_DDCK 855_RED R1167 1 0/NA 2 0402 R343 1 0/NA 2 0402 855_GREEN R344 1 0/NA 2 0402 855_BLUE 2 C843 0.01U/NA 0402 +80-20% 50V 1 1 C844 0.1U 0402 +80-20% 50V RED RED# GEEN GREEN# BLUE BLUE# 5,7 WHEN USE INTEGRATE VGA ADD R798 DEL R857 R1104 GND AGP_AD[0..31] 7,24 855_DVODETECT 855_MDDCCLK 855_MI2CDATA 855_MDVICLK 855_MI2CCLK 855_MDVIDATA 855_DVOBCLK 855_DVOCCLK 855_DVOBCLK# 855_DVOCCLK# 855_DVOBD7 855_DVOBBLANK# 1 GND 2 0 HUB_MCH_VREF 1 R918 100 0402 1% HYRCOMP H10 J9 2 0402 2 0402 2 C810 0.1U 0402 +80-20% 50V HXRCOMP CHANGE TO 0402 12 855_CRT_DDDA 12 855_CRT_DDCK 12 855_CRT_RED 12 855_CRT_GREEN 12 855_CRT_BLUE CHANGE TO 0402 R914 287 0603 1% 1/10W 855_CRT_DDDA R331 1 0/NA 855_CRT_DDCK R1166 1 0/NA 855_CRT_RED 855_CRT_GREEN 855_CRT_BLUE 2 1 2 1 2 R839 27.4 2 1 2 R792 27.4 DVOVREF 1 Place near to GMCH. R789 1 0402 11 66M_DEFSSCLK SSC 2 Less than 0.5" 1 CHANGE TO 0402 W/ 2 1 37.4 0603 1% +1.35V 855_DVOBHSYNC 855_DVOBVSYNC GND +1.5V 855_RED GND Maximum length less than 0.5" from pin to voltage divider. HXRCOMP & HYRCOMP should be route with 18 mil width U7 U4 U3 V3 W2 W6 V6 W7 T3 V5 V4 W3 V2 855_HSYNC 855_VSYNC HUB_RCOMP EXTTS_0 GCLKIN GVREF HUB_HI[0..10] 14 HUB_STB 14 HUB_STB# R209 49.9 0402 1% +1.35V 2 T6 T5 1 R857 2 100K 0402 1 7 HAVREF HCCVREF Y22 Y28 855GM/GME BGA707_25 R898 ICLKAM ICLKAP ICLKBM ICLKBP 855_DVOBCCLKINT 855_DVOBCINTR# 855_DVOBFLDSTL 855_DVOBBLANK# 2 +3V B 1 DVOCD[0] DVOCD[1] DVOCD[2] DVOCD[3] DVOCD[4] DVOCD[5] DVOCD[6] DVOCD[7] DVOCD[8] DVOCD[9] DVOCD[10] DVOCD[11] M3 G2 M2 L2 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C TP27 TP30 HDVREF K21 J21 J17 DVOCCLK DVOCCLK# 855_DVOBD0 855_DVOBD1 855_DVOBD2 855_DVOBD3 855_DVOBD4 855_DVOBD5 855_DVOBD6 855_DVOBD7 855_DVOBD8 855_DVOBD9 855_DVOBD10 855_DVOBD11 AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31 1 2 HRS#[0..2] HADS# HTRDY# HDRDY# HDEFER# HHITM# HHIT# HLOCK# HBR0# HBNR# HBPRI# HDBSY# HRS#[0..2] ICLKAM D14 ICLKAP E13 1 ICLKBM E10 1 ICLKBP F10 0402 1 R166 2 D6 10K 5%Y3 DVOVREF F1 DVOBHSYNC DVOBVSYNC R3 R5 R6 R4 P6 P5 N5 P2 N2 N3 M1 M5 2 2 2 2 2 2 2 2 2 2 2 2 DINV[0]# DINV[1]# DINV[2]# DINV[3]# 1 1 1 1 1 1 1 1 IYAM[0] IYAM[1] IYAM[2] IYAM[3] IYAP[0] IYAP[1] IYAP[2] IYAP[3] IYBM[0] IYBM[1] IYBM[2] IYBM[3] IYBP[0] IYBP[1] IYBP[2] IYBP[3] 855_DVOBCLK 855_DVOBCLK# 1 J25 E25 B25 G19 TP38 TP26 TP21 TP32 TP31 TP22 TP20 TP36 G14 E15 C15 C13 F14 E14 C14 B13 H12 E12 C12 G11 G12 E11 C11 G10 P3 P4 2 HDINV#0 HDINV#1 HDINV#2 HDINV#3 HDINV#[0..3] 2 HDINV#[0..3] HDSTBN[0]# HDSTBN[1]# HDSTBN[2]# HDSTBN[3]# GND IYAM0 IYAM1 IYAM2 IYAM3 IYAP0 IYAP1 IYAP2 IYAP3 IYBM0 IYBM1 IYBM2 IYBM3 IYBP0 IYBP1 IYBP2 IYBP3 DVOBCCLKINT DVOBCINTR# DVOBFLDSTL DVOBBLANK# 1 J28 C27 E22 D18 G SUSCLK 2,13 HDPSLP# 2 855_DPMS 2 HDPWR# 0402 11 48M_DREFCLK Q15 2N7002 D S AGPBUSY# BCLK BCLK# DPMS DPSLP# DPWR# DREFCLK 2 HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBN#[0..3] 2 HDSTBN#[0..3] HDSTBP[0]# HDSTBP[1]# HDSTBP[2]# HDSTBP[3]# DVOBD[0] DVOBD[1] DVOBD[2] DVOBD[3] DVOBD[4] DVOBD[5] DVOBD[6] DVOBD[7] DVOBD[8] DVOBD[9] DVOBD[10] DVOBD[11] 1 K27 D26 E21 E18 DVOBCLK DVOBCLK# 2 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 13 F7 AE29 AD29 855_DPMS D5 Y23 AA22 B7 7,13,24 AGPBUSY# 11 HCLK_MCH 11 HCLK_MCH# 1 HDSTBP#[0..3] 2 HDSTBP#[0..3] R155 1K 0402 5% 1 0/NA R156 2 C HXRCOMP HXSWING HYRCOMP HYSWING +1.5V ADDID[0] ADDID[1] ADDID[2] ADDID[3] ADDID[4] ADDID[5] ADDID[6] ADDID[7] 1 B20 B18 H28 K28 CHECK E5 F5 E3 E2 G5 F4 G6 F6 2 HXRCOMP HXSWING HYRCOMP HYSWING 855_ADDID0 855_ADDID1 855_ADDID2 855_ADDID3 855_ADDID4 855_ADDID5 855_ADDID6 855_ADDID7 2 1 2 HADSTB#0 2 HADSTB#1 HREQ[0]# HREQ[1]# HREQ[2]# HREQ[3]# HREQ[4]# HADSTB[0]# HADSTB[1]# HD#[0..63] 2 R28 P25 R23 R25 T23 T26 AA26 HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 1 HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HREQ#[0..4] HD[0]# HD[1]# HD[2]# HD[3]# HD[4]# HD[5]# HD[6]# HD[7]# HD[8]# HD[9]# HD[10]# HD[11]# HD[12]# HD[13]# HD[14]# HD[15]# HD[16]# HD[17]# HD[18]# HD[19]# HD[20]# HD[21]# HD[22]# HD[23]# HD24]# HD[25]# HD[26]# HD[27]# HD[28]# HD[29]# HD[30]# HD[31]# HD[32]# HD[33]# HD[34]# HD[35]# HD[36]# HD[37]# HD[38]# HD[39]# HD[40]# HD[41]# HD[42]# HD[43]# HD[44]# HD[45]# HD[46]# HD[47]# HD[48]# HD[49]# HD[50]# HD[51]# HD[52]# HD[53]# HD[54]# HD[55]# HD[56]# HD[57]# HD[58]# HD[59]# HD[60]# HD[61]# HD[62]# HD[63]# HA[3]# HA[4]# HA[5]# HA[6]# HA[7]# HA[8]# HA[9]# HA[10]# HA[11]# HA[12]# HA[13]# HA[14]# HA[15]# HA[16]# HA[17]# HA[18]# HA[19]# HA[20]# HA[21]# HA[22]# HA[23]# HA[24]# HA[25]# HA[26]# HA[27]# HA[28]# HA[29]# HA[30]# HA[31]# K22 H27 K25 L24 J27 G28 L27 L23 L25 J24 H25 K23 G27 K26 J23 H26 F25 F26 B27 H23 E27 G25 F28 D27 G24 C28 B26 G22 C26 E26 G23 B28 B21 G21 C24 C23 D22 C25 E24 D24 G20 E23 B22 B23 F23 F21 C20 C21 G18 E19 E20 G17 D20 F19 C19 C17 F17 B19 G16 E16 C16 E17 D16 C18 2 P23 T25 T28 R27 U23 U24 R24 U28 V28 U27 T27 V27 U25 V26 Y24 V25 V23 W25 Y25 AA27 W24 W23 W27 Y27 AA28 W28 AB27 Y26 AB28 1 D 2 HREQ#[0..4] HD#[0..63] U714B HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 2 HA#[3..31] 2 HA#[3..31] Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 4 of 34 5 4 3 NB_MA3 6 NB_MA3 2 1 NB_MONTARA-GME(2/2) NB_MA0 6 NB_MA0 +1.35V +2.5VS_DDR U714E SDM[0] SDM[1] SDM[2] SDM[3] SDM[4] SDM[5] SDM[6] SDM[7] SDM[8] VCCADPLLA VCCADPLLB A6 B16 VCCAGPLL VCCAHPLL Y2 D29 A11 VCCASM_0 VCCASM_1 VCCGPIO_0 VCCGPIO_1 VCCQSM_0 VCCQSM_1 VCCADPLLA VCCADPLLB VCCAGPLL VCCAHPLL C777 0.1U 0402 +80-20% 50V C343 0.01U 0402 +80-20% 50V B11 VCCALVDS VSSALVDS B8 NB_DM[0..8] +1.5V 1 VCCADAC 2 L717 120Z/100M C779 0.1U 0402 +80-20% 50V C852 10U 16V 1206 1 2 2 1 2 1 2 1 2 1 2 C850 10U 16V 1206 1 2 1 2 1 2 1 2 C851 10U 0805 6.3V 10% C848 0.01U 0402 +80-20% 50V GND VCCADPLLA GND P16 J16 F16 AG15 AB15 U15 R15 N15 H15 D15 AC14 AA14 T14 P14 J14 AE13 AB13 U13 R13 N13 H13 F13 D13 A13 AJ12 AG12 AA12 J12 AJ11 AC11 AB11 H11 F11 D11 AJ10 AE10 AA10 C10 AG9 AB9 W9 U9 T9 R9 N9 L9 E9 AC8 Y8 V8 T8 P8 K8 H8 AJ7 AE7 AA7 R7 M7 J7 G7 E7 C7 AG6 Y6 L6 Y5 U5 B5 AE4 AC4 AA4 W4 T4 N4 K4 G4 D4 AJ3 AG3 R2 AJ1 AE1 AA1 U1 L1 G1 C1 J10 U26 D C B 855GM/GME BGA707_25 GND 1 1 2 C776 0.01U 0402 +80-20% 50V VCCADPLLB 2 L713 120Z/100M 2 C171 0.01U 0402 +80-20% 50V GND C772 10U 16V 1206 VTTHF_0 VTTHF_2 VTTHF_3 VTTHF_4 1 2 1 2 1 2 1 2 1 2 0402 +80-20% 0402 +80-20% 0402 +80-20% 0402 +80-20% 0402 +80-20% C832 C818 C814 C780 C781 C785 0.01U 0402 +80-20% 50V GND GND A GND C176 0.01U 0402 +80-20% 50V 1 VCCQSM 2 L729 120Z/100M 2 L730 120Z/100M/NA 1 1 +2.5V_M10 1 2 C227 10U 0805 6.3V 10% C860 4.7U 0603 6.3V +80-20% 2 VCCTXLVDS C174 10U 16V 1206 1 +2.5VS_DDR 1 2 L42 120Z/100M GND C859 0.01U 0402 +80-20% 50V Title 8050D MOTHER B/D Size C Date: 4 0.1U 50V 0.1U 50V 0.1U 50V 0.1U 50V 0.1U 50V VTTHF_1 +2.5VS_DDR 2 C846 0.1U/NA 0402 +80-20% 50V +1.35V 1 1 2 C166 10U 16V 1206 C783 10U 0805 6.3V 10% GND GND 5 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_126 VSS_125 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VCCGPIO 2 L715 120Z/100M C297 0.1U 0402 +80-20% 50V GND 1 2 1 R924 60.4 0402 1% 2 1 2 C858 0.1U 0402 +80-20% 50V 2 2 R946 604 0603 1% +3V 1 VCCAGPLL 2 C808 0.1U 0402 +80-20% 50V 2 L38 120Z/100M C847 0.1U 0402 +80-20% 50V MCH_SMRCOMP 1 2 1 2 CHANGE TO 0402 2 R923 60.4 0402 1% MCH_SMVSWINGH 1 GND VCCASM 2 L727 120Z/100M 2 +1.35V 1 L45 120Z/100M 2 1 1 2 : 400/200/133(100/133) 1 +1.35V C786 0.01U 0402 +80-20%VSSADAC 50V VCCAHPLL 2 L720 120Z/100M 2 : 400/200/200(100/200) 10 CHANGE TO 0402 1 1 1 2 1 01 2 00(def): 400/266/200(133/200) C238 10U 16V 1206 1 1 1 1 1 2 2 +1.35V R942 150 0402 1% MCH_SMVSWINGL C857 0.1U 0402 +80-20% 50V 1 6 +2.5VS_DDR CHANGE TO 0402 R941 150 0402 1% C271 C252 10U 0.1U 0402 16V +80-20% 1206 50V VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 GND R945 604 0603 1% CHANGE TO 0402 C202 0.1U 0402 +80-20% 50V VSSADAC 855GM/GME BGA707_25 VSSADAC AA29 W29 U29 N29 L29 J29 G29 E29 C29 AE28 AC28 E28 D28 AJ27 AG27 AC27 F27 A27 AJ26 AB26 W26 R26 N26 L26 J26 G26 AE25 AA25 D25 A25 AG24 AA24 V24 T24 P24 M24 K24 H24 F24 B24 AJ23 AC23 AA23 D23 A23 AE22 W22 U22 R22 N22 L22 J22 F22 C22 AG21 AB21 AA21 Y21 V21 T21 P21 M21 H21 D21 A21 AJ20 AC20 AA20 J20 F20 AE19 AB19 H19 D19 A19 AJ18 AG18 AA18 J18 F18 AC17 AB17 U17 R17 N17 H17 D17 A17 AE16 AA16 T16 GND +2.5VS_DDR PSB/Sys Mem Core/GFX Core(CL/CH) +VCCP 1 AJ8 AJ6 AB29 Y29 K29 F29 A26 V22 T22 P22 M22 H22 U21 R21 N21 L21 H20 A20 J19 H18 A18 H16 G15 VTTLF_0 VTTLF_1 VTTLF_2 VTTLF_3 VTTLF_4 VTTLF_5 VTTLF_6 VTTLF_7 VTTLF_8 VTTLF_9 VTTLF_10 VTTLF_11 VTTLF_12 VTTLF_13 VTTLF_14 VTTLF_15 VTTLF_16 VTTLF_17 VTTLF_18 VTTLF_19 VTTLF_20 2 VCCQSM VCCADAC_0 VCCADAC_1 GND +2.5VS_DDR Clock config bit GST[1,0] VTTHF_0 VTTHF_1 VTTHF_2 VTTHF_3 VTTHF_4 1 L714 120Z/100M 6 Place within 0.5" with 15-mil wide. A V29 M29 H29 A24 A22 2 A4 A3 VTTHF_0 VTTHF_1 VTTHF_2 VTTHF_3 VTTHF_4 1 AF1 AD1 VCCALVDS 2 GND NB_DM[0..8] +1.5V GST0 GST1 2 1 2 1 2 1 2 VCCASM VCCGPIO VCCDLVDS_0 VCCDLVDS_1 VCCDLVDS_2 VCCDLVDS_3 2 NB_DQS[0..8] 1 B9 A9 VCCADAC 6 +1.5V B15 B14 J13 G13 1 NB_CB[0..7] C197 0.1U 0402 +80-20% 50V GND R806 1K/NA 0402 5% C314 10U 0805 6.3V 10% GND 2 NB_CB[0..7] +1.35V R822 1K 0402 5% 1 2 2 1 2 1 2 1 2 1 C184 0.1U 0402 +80-20% 50V GND NB_DQS[0..8] 855GM/GME BGA707_25 +1.5V 2 1 1 1 2 1 2 NB_DM0 NB_DM1 NB_DM2 NB_DM3 NB_DM4 NB_DM5 NB_DM6 NB_DM7 NB_DM8 1 AE5 AE6 AE9 AH12 AD19 AD21 AD24 AH28 AH15 C281 10U 0805 6.3V 10% 1 RSVD_10 RSVD_11 B C300 0.1U 0402 +80-20% 50V 2 RSVD_8 RSVD_9 NB_DQS0 NB_DQS1 NB_DQS2 NB_DQS3 NB_DQS4 NB_DQS5 NB_DQS6 NB_DQS7 NB_DQS8 C291 0.1U 0402 +80-20% 50V 2 B2 B3 7 GGNT# 7 GREQ# RSVD_6 RSVD_7 AG2 AH5 AH8 AE12 AH17 AE21 AH24 AH27 AD15 C324 10U 0805 6.3V 10% GND 1 D3 D2 7 GRBF# 7 GWBF# SDQS[0] SDQS[1] SDQS[2] SDQS[3] SDQS[4] SDQS[5] SDQS[6] SDQS[7] SDQS[8] C299 0.1U 0402 +80-20% 50V 2 7 GSBSTB 7 GSBSTB# GST[0] GST[1] GST[2] C303 0.1U 0402 +80-20% 50V 1 F2 F3 C301 0.1U 0402 +80-20% 50V GND 2 C4 C3 C2 7 GST0 7 GST1 7 GST2 RSVD_5 C309 0.1U 0402 +80-20% 50V VCCTXLVDS 1 L4 7 GCBE2# RSVD_0 RSVD_1 RSVD_2 RSVD_3 RSVD_4 C325 10U 0805 6.3V 10% GND 1 F12 D12 B12 AA5 D7 C263 10U 0805 6.3V 10% 1 1 1 1 1 1 C302 0.1U 0402 +80-20% 50V A12 D10 B10 F9 2 TP40 TP35 TP703 TP41 TP25 SMRCOMP VCCTXLVDS_0 VCCTXLVDS_1 VCCTXLVDS_2 VCCTXLVDS_3 C290 0.1U 0402 +80-20% 50V t t n e e r c m e u S c c Do a iT ial M t n e id f n o C +1.5V 1 2 GND AB1 GND 2 SMVREF_0 1 AJ24 C328 MCH_SMRCOMP 0.1U 0402 +80-20% 50V C205 0.1U 0402 +80-20% 50V 2 +1.25V_DDR SMVSWINGH SMVSWINGL C232 0.1U 0402 +80-20% 50V VCCDVO_0 VCCDVO_1 VCCDVO_2 VCCDVO_3 VCCDVO_4 VCCDVO_5 VCCDVO_6 VCCDVO_7 VCCDVO_8 VCCDVO_9 VCCDVO_10 VCCDVO_11 VCCDVO_12 VCCDVO_13 VCCDVO_14 VCCDVO_15 1 AJ19 AJ22 P9 M9 K9 R8 N8 M8 L8 J8 H7 E6 M4 J4 E4 N1 J1 E1 2 MCH_SMVSWINGH MCH_SMVSWINGL SCK[0] SCK[0]# SCK[1] SCK[1]# SCK[2] SCK[2]# SCK[3] SCK[3]# SCK[4] SCK[4]# SCK[5] SCK[5]# C234 10U 0805 6.3V 10% 1 AB2 AA2 AC26 AB25 AC3 AD4 AC2 AD2 AB23 AB24 AA3 AB4 GND 2 NB_CLK_DDR0 NB_CLK_DDR0# NB_CLK_DDR1 NB_CLK_DDR1# NB_CLK_DDR2 NB_CLK_DDR2# NB_CLK_DDR3 NB_CLK_DDR3# NB_CLK_DDR4 NB_CLK_DDR4# NB_CLK_DDR5 NB_CLK_DDR5# C276 0.1U 0402 +80-20% 50V +1.5V 2 6 6 6 6 6 6 6 6 6 6 6 6 SCKE[0] SCKE[1] SCKE[2] SCKE[3] C247 0.1U 0402 +80-20% 50V 1 CKE0 CKE1 CKE2 CKE3 SCS[0]# SCS[1]# SCS[2]# SCS[3]# C272 10U 0805 6.3V 10% AG29 AF29 AC29 AF27 AJ25 AF24 AB22 AJ21 AF21 AB20 AF18 AB18 AJ17 AB16 AF15 AB14 AJ13 AA13 AF12 AB12 AA11 AB10 AJ9 AF9 Y9 AB8 AA8 Y7 AF6 AB6 AA6 AJ5 Y4 AF3 AB3 AG1 AC1 VCCSM_0 VCCSM_1 VCCSM_2 VCCSM_3 VCCSM_4 VCCSM_5 VCCSM_6 VCCSM_7 VCCSM_8 VCCSM_9 VCCSM_10 VCCSM_11 VCCSM_12 VCCSM_13 VCCSM_14 VCCSM_15 VCCSM_16 VCCSM_17 VCCSM_18 VCCSM_19 VCCSM_20 VCCSM_21 VCCSM_22 VCCSM_23 VCCSM_24 VCCSM_25 VCCSM_26 VCCSM_27 VCCSM_28 VCCSM_29 VCCSM_30 VCCSM_31 VCCSM_32 VCCSM_33 VCCSM_34 VCCSM_35 VCCSM_36 VCCHL_0 VCCHL_1 VCCHL_2 VCCHL_3 VCCHL_4 VCCHL_5 VCCHL_6 VCCHL_7 1 C AC7 AB7 AC9 AC10 6 6 6 6 SBA[0] SBA[1] V9 W8 U8 V7 U6 W5 Y1 V1 +1.35V 2 AD23 AD26 AC22 AC25 6 CS#0 6 CS#1 6 CS#2 6 CS#3 C273 0.1U 0402 +80-20% 50V VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 1 6 NB_BA0 6 NB_BA1 C293 0.1U 0402 +80-20% 50V GND 2 AD22 AD20 SWE# SCAS# SRAS# C255 0.1U 0402 +80-20% 50V 2 AD25 AC24 AC21 6 NB_WE# 6 NB_CAS# 6 NB_RAS# SMAB[1] SMAB[2] SMAB[4] SMAB[5] C218 0.1U 0402 +80-20% 50V 1 AD16 AC12 AF11 AD10 C282 0.1U 0402 +80-20% 50V C288 0.1U 0402 +80-20% 50V 2 SMAB1 SMAB2 SMAB4 SMAB5 C243 10U 0805 6.3V 10% 1 SMAB[4..5] 6 SMAB[4..5] NB_MD0 NB_MD1 NB_MD2 NB_MD3 NB_MD4 NB_MD5 NB_MD6 NB_MD7 NB_MD8 NB_MD9 NB_MD10 NB_MD11 NB_MD12 NB_MD13 NB_MD14 NB_MD15 NB_MD16 NB_MD17 NB_MD18 NB_MD19 NB_MD20 NB_MD21 NB_MD22 NB_MD23 NB_MD24 NB_MD25 NB_MD26 NB_MD27 NB_MD28 NB_MD29 NB_MD30 NB_MD31 NB_MD32 NB_MD33 NB_MD34 NB_MD35 NB_MD36 NB_MD37 NB_MD38 NB_MD39 NB_MD40 NB_MD41 NB_MD42 NB_MD43 NB_MD44 NB_MD45 NB_MD46 NB_MD47 NB_MD48 NB_MD49 NB_MD50 NB_MD51 NB_MD52 NB_MD53 NB_MD54 NB_MD55 NB_MD56 NB_MD57 NB_MD58 NB_MD59 NB_MD60 NB_MD61 NB_MD62 NB_MD63 NB_CB0 NB_CB1 NB_CB2 NB_CB3 NB_CB4 NB_CB5 NB_CB6 NB_CB7 2 6 NB_MA12 6 SMAB[1..2] AF2 AE3 AF4 AH2 AD3 AE2 AG4 AH3 AD6 AG5 AG7 AE8 AF5 AH4 AF7 AH6 AF8 AG8 AH9 AG10 AH7 AD9 AF10 AE11 AH10 AH11 AG13 AF14 AG11 AD12 AF13 AH13 AH16 AG17 AF19 AE20 AD18 AE18 AH18 AG19 AH20 AG20 AF22 AH22 AF20 AH19 AH21 AG22 AE23 AH23 AE24 AH25 AG23 AF23 AF25 AG25 AH26 AE26 AG28 AF28 AG26 AF26 AE27 AD27 AG14 AE14 AE17 AG16 AH14 AE15 AF16 AF17 1 D NB_MA6 NB_MA7 NB_MA8 NB_MA9 NB_MA10 NB_MA11 SMAB[1..2] SDQ[0] SDQ[1] SDQ[2] SDQ[3] SDQ[4] SDQ[5] SDQ[6] SDQ[7] SDQ[8] SDQ[9] SDQ[10] SDQ[11] SDQ[12] SDQ[13] SDQ[14] SDQ[15] SDQ[16] SDQ[17] SDQ[18] SDQ[19] SDQ[20] SDQ[21] SDQ[22] SDQ[23] SDQ[24] SDQ[25] SDQ[26] SDQ[27] SDQ[28] SDQ[29] SDQ[30] SDQ[31] SDQ[32] SDQ[33] SDQ[34] SDQ[35] SDQ[36] SDQ[37] SDQ[38] SDQ[39] SDQ[40] SDQ[41] SDQ[42] SDQ[43] SDQ[44] SDQ[45] SDQ[46] SDQ[47] SDQ[48] SDQ[49] SDQ[50] SDQ[51] SDQ[52] SDQ[53] SDQ[54] SDQ[55] SDQ[56] SDQ[57] SDQ[58] SDQ[59] SDQ[60] SDQ[61] SDQ[62] SDQ[63] SDQ[64] SDQ[65] SDQ[66] SDQ[67] SDQ[68] SDQ[69] SDQ[70] SDQ[71] SMA[0] SMA[1] SMA[2] SMA[3] SMA[4] SMA[5] SMA[6] SMA[7] SMA[8] SMA[9] SMA[10] SMA[11] SMA[12] 2 6 6 6 6 6 6 AC18 AD14 AD13 AD17 AD11 AC13 AD8 AD7 AC6 AC5 AC19 AD5 AB5 1 SMA[4..5] 6 SMA[4..5] NB_MA0 SMA1 SMA2 NB_MA3 SMA4 SMA5 NB_MA6 NB_MA7 NB_MA8 NB_MA9 NB_MA10 NB_MA11 NB_MA12 W21 AA19 AA17 T17 P17 U16 R16 N16 AA15 T15 P15 J15 U14 R14 N14 H14 T13 P13 6 2 SMA[1..2] 6 SMA[1..2] NB_MD[0..63] 1 U714D NB_MD[0..63] U714C 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 5 of 34 CKE1 MA12 MA9 MA7 SMA5 MA3 SMA1 +1.25V_DDR MD25 DQS3 MD26 MD27 MCB4 MCB5 MCB0 MCB1 DM8 MCB6 DQS8 MCB2 MCB7 MCB3 CKE1_S1 C425 0.01U 0402 +80-20% 50V MD32 MD33 C432 0.01U 0402 +80-20% 50V DQS4 MD34 MD35 MD40 1 1 C372 0.1U 0402 +80-20% 50V 2 1 C352 0.1U 0402 +80-20% 50V 2 C353 0.1U 0402 +80-20% 50V 2 C371 1U 0402 +80-20% 10V 2 1 C351 0.1U 0402 +80-20% 50V 1 2 1 C335 0.1U 0402 +80-20% 50V 2 1 C370 0.1U 0402 +80-20% 50V 2 1 C334 0.1U 0402 +80-20% 50V 2 C348 1U 0402 +80-20% 10V MD48 MD49 DQS6 MD50 C336 1U 0402 +80-20% 10V MD51 MD56 MD57 DQS7 GND MD58 MD59 SMBDATA SMBCLK 11,14 SMBDATA 11,14 SMBCLK +3V 5 5 5 5 5 5 5 5 5 5 5 5 NB_CLK_DDR0 NB_CLK_DDR0# NB_CLK_DDR1 NB_CLK_DDR1# NB_CLK_DDR2 NB_CLK_DDR2# NB_CLK_DDR3 NB_CLK_DDR3# NB_CLK_DDR4 NB_CLK_DDR4# NB_CLK_DDR5 NB_CLK_DDR5# R338 R337 R319 R320 R336 R335 R354 R352 R359 R360 R351 R347 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 2 2 2 2 2 2 2 2 2 2 2 2 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% CLK_DDR0 CLK_DDR0# CLK_DDR1 CLK_DDR1# CLK_DDR2 CLK_DDR2# CLK_DDR3 CLK_DDR3# CLK_DDR4 CLK_DDR4# CLK_DDR5 CLK_DDR5# MA6 SMA4 SMA2 MA0 NB_MA7 SMAB5 NB_MA3 SMAB1 BA1 RAS# CAS# CS#1 NB_MA10 NB_BA0 NB_WE# CS#2 MD36 MD37 MD32 MD33 DM4 MD38 DQS4 MD34 MD39 MD44 MD35 MD40 MD45 DM5 MD41 DQS5 MD46 MD47 MD42 MD43 CLK_DDR1# CLK_DDR1 MD52 MD53 MD48 MD49 DM6 MD54 DQS6 MD50 MD55 MD60 MD51 MD56 MD61 DM7 MD57 DQS7 MD62 MD63 MD58 MD59 +3V 0.6MM/200P/H9.2 QUASAR CA0145-200N01 GND +1.25V_DDR 1 C410 0.01U 0402 +80-20% 50V C421 0.01U 0402 +80-20% 50V C419 0.01U 0402 +80-20% 50V 2 R340 75 0402 1% 4 C337 0.01U 0402 +80-20% 50V C346 0.1U 0402 +80-20% 50V MCB7 CKE0_S1 C CKE2 NB_MA11 NB_MA8 NB_MA6 SMAB4 SMAB2 NB_MA0 NB_BA1 NB_RAS# NB_CAS# CS#3 CS#1_S1 MD36 MD37 DM4 MD38 MD39 MD44 MD45 DM5 MD46 MD47 CLK_DDR4# CLK_DDR4 B MD52 MD53 DM6 MD54 MD55 MD60 MD61 DM7 MD62 MD63 +3V R334 75 0402 1% C386 0.01U 0402 +80-20% 50V C366 0.1U 0402 +80-20% 50V C338 0.1U 0402 +80-20% 50V C422 0.1U 0402 +80-20% 50V C423 0.1U 0402 +80-20% 50V C424 0.1U 0402 +80-20% 50V C384 0.1U 0402 +80-20% 50V Title 8050D MOTHER B/D Size C Date: PDF created with FinePrint pdfFactory trial version http://www.fineprint.com C437 10U 0805 6.3V 10% GND GND GND 3 C436 10U 0805 6.3V 10% A +DDR_VREF 1 1 C402 0.01U 0402 +80-20% 50V 2 C420 0.01U 0402 +80-20% 50V C415 0.01U 0402 +80-20% 50V 2 C418 0.01U 0402 +80-20% 50V 1 1 1 C417 0.01U 0402 +80-20% 50V 2 1 1 C413 0.01U 0402 +80-20% 50V C401 0.01U 0402 +80-20% 50V 1 1 1 C416 0.01U 0402 +80-20% 50V 2 C411 0.01U 0402 +80-20% 50V 2 1 2 1 C399 0.01U 0402 +80-20% 50V 2 1 C398 0.01U 0402 +80-20% 50V 2 C395 0.01U 0402 +80-20% 50V 1 2 1 2 C396 0.01U 0402 +80-20% 50V 1 C414 0.01U 0402 +80-20% 50V 1 C408 0.01U 0402 +80-20% 50V DM8 MCB6 +1.25V_DDR +2.5VS_DDR C393 0.01U 0402 +80-20% 50V 2 1 C407 0.01U 0402 +80-20% 50V 2 1 C412 0.01U 0402 +80-20% 50V 2 1 C406 0.01U 0402 +80-20% 50V 2 1 C405 0.01U 0402 +80-20% 50V 2 1 C404 0.01U 0402 +80-20% 50V C391 0.01U 0402 +80-20% 50V 2 1 C409 0.01U 0402 +80-20% 50V 2 1 2 1 1 C403 0.01U 0402 +80-20% 50V 2 1 C400 0.01U 0402 +80-20% 50V 2 1 C397 0.01U 0402 +80-20% 50V 2 C394 0.01U 0402 +80-20% 50V 2 1 2 1 C392 0.01U 0402 +80-20% 50V 2 1 C390 0.01U 0402 +80-20% 50V 2 1 C389 0.01U 0402 +80-20% 50V 2 C388 0.01U 0402 +80-20% 50V 2 1 2 1 2 C387 0.01U 0402 +80-20% 50V MD30 MD31 MCB4 MCB5 0.6MM/200P/H5.2 QUASAR CA0115-200N01 +1.25V_DDR CKE0_S1 CKE1_S1 CS#0_S1 CS#1_S1 MD29 DM3 GND GND 5 SMBDATA SMBCLK DM2 MD22 MD23 MD28 1 C428 0.01U 0402 +80-20% 50V CKE3 CS#0_S1 NB_MA12 NB_MA9 CKE0 MD20 MD21 2 C430 0.01U 0402 +80-20% 50V MA11 MA8 MD14 MD15 1 C433 0.01U 0402 +80-20% 50V MA10 BA0 WE# CS#0 C426 0.01U 0402 +80-20% 50V CLK_DDR5 CLK_DDR5# D MD13 DM1 2 C429 0.01U 0402 +80-20% 50V MD42 MD43 1 5% 5% 5% 5% MD29 DM3 MD30 MD31 DM0 MD6 MD7 MD12 1 C431 0.01U 0402 +80-20% 50V +2.5VS_DDR 2 R976 1 0 0402 2 R1037 1 0 0402 2 R1029 1 0 0402 2 R968 1 0 0402 2 A MD19 MD24 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 MD4 MD5 2 C434 0.01U 0402 +80-20% 50V 2 RP35 56*8 RPX8 MD23 MD28 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 1 C427 0.01U 0402 +80-20% 50V 1 RP37 56*8 RPX8 DQS2 MD18 1 1 2 1 2 1 2 1 GND MD41 DQS5 RP34 56*8 RPX8 MD16 MD17 DM2 MD22 2 1 2 1 2 1 2 1 2 2 MCB3 1 SMA1 SMA2 SMA4 SMA5 SMAB1 SMAB2 SMAB4 SMAB5 CKE0 CKE1 CKE2 CKE3 CS#0 CS#1 CS#2 CS#3 R979 1 10 R1040 1 10 DQS8 MCB2 C332 0.1U 0402 +80-20% 50V 2 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 C350 0.1U 0402 +80-20% 50V CLK_DDR2 CLK_DDR2# 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 MD20 MD21 2 RP36 56*8 RPX8 CLK_DDR3 CLK_DDR3# 1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 MD10 MD11 2 SMAB4 SMAB2 SMA5 SMA2 NB_MA12 NB_MA11 NB_MA8 NB_MA9 NB_BA0 NB_WE# NB_CAS# NB_RAS# CS#1 CS#2 CS#3 CS#0 MCB3 MCB7 CKE1 CKE0 CKE2 CKE3 SMAB5 SMA4 NB_MA7 NB_MA6 NB_MA3 SMA1 SMAB1 NB_MA10 NB_MA0 NB_BA1 MD14 MD15 1 MA0 MA3 MA6 MA7 MA8 MA9 MA10 MA11 MA12 WE# CAS# RAS# BA0 BA1 SMA1 SMA2 SMA4 SMA5 SMAB1 SMAB2 SMAB4 SMAB5 CKE0 CKE1 CKE2 CKE3 CS#0 CS#1 CS#2 CS#3 DM8 2 0402 DQS8 2 0402 C349 0.1U 0402 +80-20% 50V GND 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 MD9 DQS1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 MD13 DM1 1 10 10 10 10 10 10 10 10 10 10 10 10 10 10 MD3 MD8 2 NB_MA0 R972 1 NB_MA3 R1033 1 NB_MA6 R973 1 NB_MA7 R1034 1 NB_MA8 R974 1 NB_MA9 R1035 1 NB_MA10 R1032 1 NB_MA11 R975 1 NB_MA12 R1036 1 NB_WE# R1030 1 NB_CAS#R969 1 NB_RAS#R970 1 NB_BA0 R1031 1 NB_BA1 R971 1 MD7 MD12 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 RP38 56*8 RPX8 DQS0 MD2 2 1 2 3 4 5 6 7 8 DM0 MD6 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 MCB1 MCB0 MCB4 MCB5 DQS8 DM8 MCB6 MCB2 MD0 MD1 2 MCB0 MCB1 MCB2 MCB3 MCB4 MCB5 MCB6 MCB7 MD4 MD5 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C C333 0.1U 0402 +80-20% 50V 2 0402 0402 0402 0402 0402 0402 0402 0402 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 2 2 2 2 2 2 2 2 2 MCB0 MCB1 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 2 10 10 10 10 10 10 10 10 MD26 MD27 C369 0.1U 0402 +80-20% 50V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 R1042 1 R1041 1 R1039 1 R1038 1 R981 1 R980 1 R978 1 R977 1 C347 0.1U 0402 +80-20% 50V J712 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 NB_CB0 NB_CB1 NB_CB2 NB_CB3 NB_CB4 NB_CB5 NB_CB6 NB_CB7 C331 0.1U 0402 +80-20% 50V 1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 MD25 DQS3 C868 0.1U 0402 +80-20% 50V 2 0402 0402 0402 0402 0402 0402 0402 0402 +2.5VS_DDR 1 2 2 2 2 2 2 2 2 MD19 MD24 2 10 10 10 10 10 10 10 10 DQS2 MD18 1 1 1 1 1 1 1 1 1 MD16 MD17 2 R999 R994 R989 R984 R965 R960 R955 R950 CLK_DDR0 CLK_DDR0# 1 NB_DM0 NB_DM1 NB_DM2 NB_DM3 NB_DM4 NB_DM5 NB_DM6 NB_DM7 RP29 56*8 RPX8 MD10 MD11 2 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 MD9 DQS1 1 0402 0402 0402 0402 0402 0402 0402 0402 MD3 MD8 2 2 2 2 2 2 2 2 2 DQS0 MD2 1 RP30 56*8 RPX8 10 10 10 10 10 10 10 10 J711 2 RP31 56*8 RPX8 +2.5VS_DDR +DDR_VREF MD0 MD1 1 RP32 56*8 RPX8 +2.5VS_DDR 2 RP33 56*8 RPX8 1 +DDR_VREF 1 RP39 56*8 RPX8 2 DDR -SODIMM 2 RP40 56*8 RPX8 3 +1.25V_DDR 1 RP41 56*8 RPX8 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 2 RP42 56*8 RPX8 R1060 1 R1055 1 R1050 1 R1045 1 R1026 1 R1021 1 R1016 1 R1011 1 NB_CB[0..7] 5 NB_DM8 5 NB_DQS8 RP43 56*8 RPX8 NB_DQS0 NB_DQS1 NB_DQS2 NB_DQS3 NB_DQS4 NB_DQS5 NB_DQS6 NB_DQS7 NB_DM[0..7] NB_MA0 NB_MA3 NB_MA6 NB_MA7 NB_MA8 NB_MA9 NB_MA10 NB_MA11 NB_MA12 NB_WE# NB_CAS# NB_RAS# NB_BA0 NB_BA1 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 NB_DQS[0..7] B 5 5 5 5 5 5 5 5 5 5 5 5 5 5 MD0 MD4 MD1 MD5 DQS0 DM0 MD2 MD6 MD3 MD7 MD8 MD12 MD9 MD13 DQS1 DM1 MD10 MD14 MD11 MD15 MD16 MD20 MD17 MD21 DQS2 DM2 MD18 MD22 MD19 MD23 MD24 MD28 MD25 MD29 DQS3 DM3 MD26 MD30 MD27 MD31 MD32 MD36 MD33 MD37 DQS4 DM4 MD34 MD38 MD35 MD39 MD40 MD44 MD41 MD45 DQS5 DM5 MD42 MD46 MD43 MD47 MD48 MD52 MD49 MD53 DQS6 DM6 MD50 MD54 MD51 MD55 MD56 MD60 MD57 MD61 DQS7 DM7 MD58 MD62 MD59 MD63 1 NB_CB[0..7] MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 2 NB_DM[0..7] 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 1 C 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 D NB_DQS[0..7] 4 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 2 5 NB_MD[0..63] NB_MD0 R1062 1 NB_MD1 R1061 1 NB_MD2 R1059 1 NB_MD3 R1058 1 NB_MD4 R1001 1 NB_MD5 R1000 1 NB_MD6 R998 1 NB_MD7 R997 1 NB_MD8 R1057 1 NB_MD9 R1056 1 NB_MD10R1054 1 NB_MD11R1053 1 NB_MD12R996 1 NB_MD13R995 1 NB_MD14R993 1 NB_MD15R992 1 NB_MD16R1052 1 NB_MD17R1051 1 NB_MD18R1049 1 NB_MD19R1048 1 NB_MD20R991 1 NB_MD21R990 1 NB_MD22R988 1 NB_MD23R987 1 NB_MD24R1047 1 NB_MD25R1046 1 NB_MD26R1044 1 NB_MD27R1043 1 NB_MD28R986 1 NB_MD29R985 1 NB_MD30R983 1 NB_MD31R982 1 NB_MD32R1028 1 NB_MD33R1027 1 NB_MD34R1025 1 NB_MD35R1024 1 NB_MD36R967 1 NB_MD37R966 1 NB_MD38R964 1 NB_MD39R963 1 NB_MD40R1023 1 NB_MD41R1022 1 NB_MD42R1020 1 NB_MD43R1019 1 NB_MD44R962 1 NB_MD45R961 1 NB_MD46R959 1 NB_MD47R958 1 NB_MD48R1018 1 NB_MD49R1017 1 NB_MD50R1015 1 NB_MD51R1014 1 NB_MD52R957 1 NB_MD53R956 1 NB_MD54R954 1 NB_MD55R953 1 NB_MD56R1013 1 NB_MD57R1012 1 NB_MD58R1010 1 NB_MD59R1009 1 NB_MD60R952 1 NB_MD61R951 1 NB_MD62R949 1 NB_MD63R948 1 5 NB_MD[0..63] 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 6 of 34 5 4 3 2 1 +3V M10_GPIO0 ATI M10-P(1/4) R743 1 10K Bus configuration straps 1.5V, AGP4X, ID=16 2 0402 M10_GPIO4 M10_GPIO5 M10_GPIO6 R742 1 10K/NA 2 0402 M10_GPIO1 R744 1 10K R61 1 10K R57 1 10K R735 1 10K 2 0402 2 0402 2 0402 2 0402 AGP_VDDQ GND R777 M10_GPIO2 11 ATI_TV_CRMA 11 ATI_TV_LUMA 11 ATI_TV_COMP AG23 AG24 +3V R770 1 0 2 0402 R773 1 0 2 0402 X1 R775 1 0/NA 2 0402 X2 R774 1 0/NA 2 0402 1 C72 0.1U 0402 +80-20% 50V R776 1 1M 2 0402 5% 1 C131 0.1U 0402 +80-20% 50V AK25 AJ25 TX0M TX0P TX1M TX1P TX2M TX2P TXCM TXCP AGPREF AGPTEST AGP8X_DET# R2SET C_R Y_G COMP_B H2SYNC V2SYNC DDC2CLK DDC2DATA HPD1 DDC3CLK DDC3DATA R G B HSYNC VSYNC SSIN SSOUT GND AJ29 1K 2 5% 0/NA 2 0402 AH27 AG26 C766 22P 0402 +/-10% 50V USE 22P 5% XTALIN TEST_MCLK TEST_YCLK XTALOUT DDC1DATA DDC1CLK AE12 AG12 AK27 AJ27 AJ26 AG25 AH25 AH26 14 7 1 1 1 2 2 R72 2.21K 0402 1% 4 4 4 4 4 4 4 4 4 4 ZV13 Reserve 64M Samsung 64M Infineon K4D263238E-GL36 HYB25D128323CL3.6 EM6A9320B1-3.6M 1 0 Reserve 64M EtroTech 0 1 Reserve 64M Hynix 1 1 Reserve 128M EtroTech H230904RAT309A LVDS CH2 ENAVDD ENABKL 12 12 +3V R764 1 0603 499 B 2 1% AF25 AF24 GND R771 0 0402 5% ATI_CRT_DDDA 12 ATI_CRT_DDCK 12 AF26 1 X1 X2 R786 2 620 C774 0603 0.1U 0402 10%5% 16V 1 ATI_CRT_RED ATI_CRT_GREEN ATI_CRT_BLUE GND C760 47P/NA 0402 +/-10% 25V C759 47P/NA 0402 +/-10% 25V R768 75 0402 5% R769 75 0402 5% R765 8.2K 0402 5% C757 1U 0402 +80-20% 10V C755 0.1U 0402 10% 16V U711 1 2 3 4 +3V 2 +3V L711 120Z/100M 2012 +3V GND XIN/CLKIN VDD XOUT REF PD# MODOUT LF VSS P2779A C770 SO8 270P 0402 +/-10% 50V GND 8 7 6 5 GND GND R772 1 150 2 0402 1% REF_OUT OSC_SPREAD R777 180 0603 1% GND A GND R767 75 0402 5% Title 8050D MOTHER B/D GND Size C GND Date: 5 4 C LVDS CH1 10K 0402 5% 2 0 +3V B6 E8 C761 47P/NA 0402 +/-10% 25V ZV12 0 GND R84 1 100K 2 0402 5% ATI_CRT_RED ATI_CRT_RED 12 ATI_CRT_GREEN GND ATI_CRT_GREEN 12 ATI_CRT_BLUE ATI_CRT_BLUE 12 ATI_CRT_HSYNC 12 ATI_CRT_VSYNC 12 +3V GND 2 0402 2 0402 R79 2.21K 0402 1% 2 GND R748 1 1K R749 1 1K 1 1 +3V R101 20K 0402 1% 4 3 HDS402 SW_HDS402 ZV11 I2C_DAT I2C_CLK R104 AUXWIN +3V SW701 1 2 GND C68 0.01U/NA 0402 +80-20% 50V GND TESTEN SUS_STAT# 0402 1 10K 2 ZV11 1 10K 2 ZV12 0402 +3V R86 10K 0402 5% AE13 AE14 AF12 TP1 TP2 2 0402 2 0402 2 0402 ZV11 2 25% ZV12 25% ZV13 5% 1 1 1 1 1 1 1 1 1 1 R752 DIGON 1 0 0402 2 5% BLON 1 0 ENABKL 2 R85 0402 5% AJ13 AH14 AJ14 AH15 AJ15 AK15 AH13 AK13 2 0402 GND TXOUT0-_ATI TXOUT0+_ATI TXOUT1-_ATI TXOUT1+_ATI TXOUT2-_ATI TXOUT2+_ATI TXOUT3-_ATI TXOUT3+_ATI TXCLK-_ATI TXCLK+_ATI TP8 TP7 TP6 TP10 TP9 TP11 TP13 TP15 TP12 TP14 MOBILITY-M10-P BGA644_64_1MM 2 R102 1 0402 R100 1 1 27MHZ C765 TXC8X4.5 22P 0402 +/-10% 50V SB_SUSST# AH28 1 2 1 2 1 2 1 2 A 13 2 2 1 AGP_VDDQ C120 0.01U 0402 +80-20% 50V GND X702 1 C122 10U 0805 6.3V 10% 1 DIGON BLON RSET GND C126 1000P 0402 +/-20% 50V TP702 1 C128 0.01U 0402 +80-20% 50V 2 1 C110 10U 0805 6.3V 10% 2 1 C123 1000P 0402 +/-20% 50V 2 2 1 REF_OUT 2 2 AK21 715 5% ATI_TV_CRMA AJ23 ATI_TV_LUMA AJ22 ATI_TV_COMP AK22 AJ24 AK24 SB_STBS AD_STBS0 AD_STBS1 1 1 1 33 5% 1 33 5% 10K 1 1 0 1 0 0402 1 0 0402 0402 RP718 8 0*4 7 1206 6 5 2 0402 1 1K/NA 1 R762 1 0603 ST0 ST1 ST2 TP53 TP54 TP55 1 1K/NA R62 2 GND M26 M27 AC25 SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 1 1 1 R83 1 AGP_VREF 2 0.1U 50V +80-20% TXOUT_L0N TXOUT_L0P TXOUT_L1N TXOUT_L1P TXOUT_L2N TXOUT_L2P TXOUT_L3N TXOUT_L3P TXCLK_LN TXCLK_LP TXOUT_U0N TXOUT_U0P TXOUT_U1N TXOUT_U1P TXOUT_U2N TXOUT_U2P TXOUT_U3N TXOUT_U3P TXCLK_UN TXCLK_UP STP_AGP# AGP_BUSY# RBF# AD_STBF0 AD_STBF1 SB_STBF AK16 AH16 AH17 AJ16 AH18 AJ17 AK19 AH19 AK18 AJ18 AG16 AF16 AG17 AF17 AF18 AE18 AH20 AG20 AF19 AG19 1 10K/NA 2 0402 1 AGP_VREF AGPTEST R140 1 47K 2 0402 5% R121 1 10K/NA 2 0402 5% 715 ohm is recommanded for R2SET. GND 4 C145 1 0402 C733 0.01U/NA 0402 +80-20% 50V 2 +3V AF29 AD27 AE28 AB28 M29 V26 5 AGP_SBSTBS 4 AGP_ADSTB0# 4 AGP_ADSTB1# B C734 0.01U/NA 0402 +80-20% 50V R82 R58 1 AGP_ST0 AGP_ST1 AGP_ST2 AD28 AD29 AC28 AC29 AA28 AA29 Y28 Y29 WBF# AJ10 1 AK102 AJ11 3 AH114 1 10K/NA 2 0402 R67 2 AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6 AGP_SBA7 AGP_ST0 AGP_ST1 AGP_ST2 C69 0.01U/NA 0402 +80-20% 50V 12,14,24 12,14,24 12,14,24 12,14,24 1 5 5 5 AH30 AH29 AE29 M28 V25 AB29 AGP_SBA[0..7] PANEL_ID0 PANEL_ID1 PANEL_ID2 PANEL_ID3 2 1% 0402 STP_AGP# AGPBUSY# AH6 AJ6 AK6 AH7 AK7 AJ7 AH8 AJ8 AH9 AJ9 AK9 AH10 AE6 AG6 AF6 AE7 AF7 AE8 AG8 R77 AF8 R78 AE9 R76 AF9 R405 AG10R406 AF10 R407 1 AGPTEST AC26 ZV_LCDCNTL0 ZV_LCDCNTL1 ZV_LCDCNTL2 ZV_LCDCNTL3 R66 GND 2 40.2 2 +3V GND 1 13,24 STP_AGP# 4,13,24 AGPBUSY# 5 AGP_RBF# 4 AGP_ADSTB0 4 AGP_ADSTB1 5 AGP_SBSTBF 4 AGP_SBA[0..7] R119 1 5% PCICLK RST# REQ# GNT# PAR STOP# DEVSEL# TRDY# IRDY# FRAME# INTA# GND 74AHC14_V TSSOP14 2 40R 5% 2 0402 1 0 2 0402 AG30 AG28 AF28 AD26 M25 N26 V29 V28 W29 W28 AE26 1206 ZV13 SW_1.5V/1.25V 30 1 M10 AGP_VDDQ 5% 22 2 5% D 2 49.9R 2 AF5 1 M9+ R794 2 0402 R105 1 0402 M10_GPIO11 M10_GPIO12 M10_GPIO9 M10_GPIO8 GND OSC_SPREAD 2 AGP MODE 2 0402 10K*8 For MEM_ID 1 1 5% 2 22P/NA R778 1 50V +/-10% 33/NA R779 1 0 11 66M_AGP 13 ATI_PCIRST# 5 AGP_REQ# 5 AGP_GNT# 4 AGP_PAR 4 AGP_STOP# 4 AGP_DEVSEL# 4 AGP_TRDY# 4 AGP_IRDY# 4 AGP_FRAME# R122 1 0 13,24 PCI_INTA# R118 5 AGP_WBF# C/BE#0 C/BE#1 C/BE#2 C/BE#3 10 9 8 7 6 R733 1 10K/NA 2 0402 U703A 2 C773 1 0402 GND N29 U28 P26 U26 1 2 3 4 5 R734 1 10K/NA 2 0402 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C AGP_CBE#0 AGP_CBE#1 AGP_CBE#2 AGP_CBE#3 FOR M10 C ZV_LCDDATA0 ZV_LCDDATA1 ZV_LCDDATA2 ZV_LCDDATA3 ZV_LCDDATA4 ZV_LCDDATA5 ZV_LCDDATA6 ZV_LCDDATA7 ZV_LCDDATA8 ZV_LCDDATA9 ZV_LCDDATA10 ZV_LCDDATA11 ZV_LCDDATA12 ZV_LCDDATA13 ZV_LCDDATA14 ZV_LCDDATA15 ZV_LCDDATA16 ZV_LCDDATA17 ZV_LCDDATA18 ZV_LCDDATA19 ZV_LCDDATA20 ZV_LCDDATA21 ZV_LCDDATA22 ZV_LCDDATA23 +3VS 2 AGP_CBE#[0..3] 4,5 AGP_CBE#[0..3] ROMCS# M10_GPIO3 2 GND AJ5 AH5 AJ4 AK4 AH4 AF4 AJ3 AK3 AH3 AJ2 AH2 AH1 AG3 AG1 AG2 AF3 AF2 1 2 0.01U 0402 50V 10% C146 10U 0805 6.3V 10% GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 2 2 2 C149 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 1 1 1 1 AGP_VREF R110 1.02K 0402 1% H29 H28 J29 J28 K29 K28 L29 L28 N28 P29 P28 R29 R28 T29 T28 U29 N25 R26 P25 R27 R25 T25 T26 U25 V27 W26 W25 Y26 Y25 AA26 AA25 AA27 M10_GPIO0 M10_GPIO1 M10_GPIO2 M10_GPIO3 M10_GPIO4 M10_GPIO5 M10_GPIO6 M10_GPIO7 M10_GPIO8 M10_GPIO9 M10_GPIO10 M10_GPIO11 M10_GPIO12 M10_GPIO13 M10_GPIO14 2 2 AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31 M10_GPIO13 M10_GPIO10 M10_GPIO7 M10_GPIO14 R738 1 10K/NA 2 0402 R737 1 10K/NA 2 0402 U710A 2 AGP_AD[0..31] 4,24 AGP_AD[0..31] 1 100 RP715 2 1.02K 324 1 1.02K AGP3.0(8X).35V 2 AGP2.0(4X).75V R739 1 10K/NA 2 0402 1 R120 1.02K 0402 1% D R779 2 1 AGP MODE 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 7 of 34 5 4 3 2 1 ATI M10-P(2/4) VGA_1.2/1.0 AVDD_1.8 AF22 AH24 VDDR4_0 VDDR4_1 VDDR4_2 VDDR4_3 VDDR4_4 A2VDD_0 A2VDD_1 A2VDDQ AVDD 1 1 2 1 1 2 2 1 2 1 1 2 2 1 2 1 1 1 1 1 1 2 1 2 1 2 1 2 1 2 2 1 1 2 1 2 1 0 0805 C55 10U 0805 6.3V 10% L30 1 C44 1000P 0402 +/-20% 50V GND 2 1 1 2 1 1 2 2 1 1 2 1 1 2 2 1 GND VDD_DAC2.5 C112 10U 0805 6.3V 10% 1 120Z/100M 2 2012 C116 0.1U 0402 +80-20% 50V C115 0.1U 0402 +80-20% 50V 120Z/100M 2 2012 AC10 AC9 AD10 AD9 AG7 2 1 2 L31 1 GND R55 C737 0.1U 0402 +80-20% 50V +2.5V_M10 +3V AC19 AC21 AC22 AC8 AD19 AD21 AD22 AD7 C738 0.1U 0402 +80-20% 50V 1 C84 10U 0805 6.3V 10% C736 10U 0805 6.3V 10% 2 2 2 1 1 C118 0.1U 0402 +80-20% 50V 2 2 1 2 1 2 2 2 1 C66 0.01U 0402 +80-20% 50V 2 2 1 2 1 2 2 1 1 VDD_MEMPLL1.8 2012 VDD_PNLIO2.5 C92 10U 0805 6.3V 10% C103 0.1U 0402 +80-20% 50V C102 0.1U 0402 +80-20% 50V VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS1DI VSS2DI VSSRH0 VSSRH1 TXVSSR_0 TXVSSR_1 TXVSSR_2 LVSSR_0 LVSSR_1 LVSSR_2 LVSSR_3 LPVSS MPVSS PVSS TPVSS VSS_123 A2VSSN_0 A2VSSN_1 A2VSSQ AVSSN AVSSQ N15 N16 N23 N24 N27 P15 P16 P4 R12 R13 R14 R15 R16 R17 R18 R23 R24 R30 R7 R8 T1 T13 T14 T15 T16 T17 T18 T19 T27 U15 U16 U4 U8 V15 V16 V30 W15 W23 W24 W27 W7 W8 Y4 C AE23 AE21 F19 M6 AG13 AG14 AH12 AE16 AE19 AF15 AF20 AJ19 A6 AJ28 AJ12 B U23 AH22 AJ21 AF23 AH23 AD24 MOBILITY-M10-P BGA644_64_1MM VDD_MEM_IO GND L26 1 120Z/100M 2 2012 VDD_MCLK2.5 2 MOBILITY-M10-P BGA644_64_1MM 1 2 2 2 2 1 C76 1000P 0402 +/-20% 50V C140 0.1U 0402 +80-20% 50V 1 LPVDD MPVDD PVDD TPVDD VDD_MEM_IO C139 0.1U 0402 +80-20% 50V 120Z/100M 2 GND C75 0.1U 0402 +80-20% 50V C141 10U 0805 6.3V 10% 2 VDDR3_0 VDDR3_1 VDDR3_2 VDDR3_3 VDDR3_4 VDDR3_5 VDDR3_6 VDDR3_7 LVDDR_25_0 LVDDR_25_1 VDDDI_1.8 2012 L709 1 C137 0.01U 0402 +80-20% 50V 120Z/100M 2 C58 0.01U 0402 +80-20% 50V 2 LVDDR_18_0 LVDDR_18_1 L35 1 C136 0.1U 0402 +80-20% 50V 1 TXVDDR_0 TXVDDR_1 AVDD_1.8 C138 10U 0805 6.3V 10% 2 VDD1DI VDD2DI C60 0.01U 0402 +80-20% 50V C130 0.1U 0402 +80-20% 50V 120Z/100M 2 1 VDDRH0 VDDRH1 GND C74 1000P 0402 +/-20% 50V C90 0.1U C78 0402 10U +80-20% 0805 50V 6.3V 10% C129 0.1U 0402 +80-20% 50V VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 +2.5V_M10 L27 1 L24 1 C50 10U 0805 6.3V 10% GND 1 A2VDDQ_1.8 AG21 AH21 C747 0.1U 0402 +80-20% 50V C54 0.1U 0402 +80-20% 50V C105 0.1U 0402 +80-20% 50V 2 VDD_DAC2.5 AJ20 A7 AK28 AK12 C746 0.1U 0402 +80-20% 50V 1 VDD_MEMPLL1.8 VDD_PLL1.8 VDD_PNLPLL1.8 AE17 AE20 C124 0.1U 0402 +80-20% 50V A2VDDQ_1.8 C127 10U 0805 6.3V 10% 2 AE15 AF21 CONNECT LVDDR_25 TO 1.8V FOR M9 VDD_PNLIO2.5 , TO 2.5V FOR M10 C86 0.1U 0402 +80-20% 50V 120Z/100M 2 2 AF13 AF14 C739 10U 0805 6.3V 10% 1 VDD_PNLIO1.8 B C98 10U 0805 6.3V 10% VDD_PNLPLL1.8 2 AE24 AE22 VDDR1_53 VDDR1_54 VDDR1_55 VDDR1_56 VSS_119 VSS_120 VSS_121 VSS_122 C77 0.01U 0402 +80-20% 50V 2 F18 N6 VDDDI_1.8 VDDCI_0 VDDCI_1 VDDCI_2 VDDCI_3 C87 1000P 0402 +/-20% 50V 2 VDD_MCLK2.5 VDDC15_0 VDDC15_1 VDDC15_2 VDDC15_3 VDDC15_4 VDDC15_5 VDDC15_6 VDDC15_7 A10 A16 A2 A22 A29 AA30 AB1 AB23 AB24 AB27 AB7 AB8 AC12 AC14 AC16 AC18 AC4 AD12 AD16 AD18 AD25 AD30 AE27 AG11 AG15 AG18 AG22 AG27 AG5 AG9 AJ1 AJ30 AK2 AK29 C1 C28 C3 C30 D12 D15 D18 D21 D24 D27 D4 D6 D9 F27 G12 G16 G18 G21 G24 G9 H12 H14 H16 H18 H21 H23 H27 H4 H8 H9 K1 K23 K24 K27 K30 K7 K8 L4 M16 M30 M7 M8 C764 0.1U 0402 +80-20% 50V 120Z/100M 2 2012 1 GND D13 D19 N4 T4 AB4 D10 D25 E4 C763 0.1U 0402 +80-20% 50V VDD_PNLIO1.8 2012 L34 1 U710E VDD_PLL1.8 C762 10U 0805 6.3V 10% VDD_MEM_IO 2 C113 0.1U 0402 VDD_MEM_IO +80-20% 50V 120Z/100M 2 2012 1 1 C96 0.01U 0402 +80-20% 50V 2 1 2 2 C79 10U 0805 6.3V 10% C97 1000P 0402 +/-20% 50V M15 R19 T12 W16 C153 0.1U 0402 +80-20% 50V 120Z/100M 2 L710 1 C758 10U 0805 6.3V 10% C81 0.1U 0402 +80-20% 50V GND 2 2 1 1 2 120Z/100M 2012 C117 0.01U 0402 +80-20% 50V 1 L28 AC11 AC20 H11 H20 L23 P8 Y23 Y8 C125 0.1U 0402 +80-20% 50V C152 0.1U 0402 +80-20% 50V t t n e e r c m e u S c c Do a iT ial M t n e id f n o C C99 1000P 0402 +/-20% 50V 2 2 L712 1 L32 1 1 0 C767 0.1U 0402 +80-20% 50V GND 2 R94 1 0805 C95 0.01U 0402 +80-20% 50V 1 1 VDD_CORE1.5 C147 1000P 0402 +/-20% 50V C167 10U 0805 6.3V 10% VDD_MEM_IO C108 1000P 0402 +/-20% 50V 2 VDD_CORE 1.8V for M9 , 1.5V for M10 VGA_1.2/1.0 VDD_CORE1.8 2012 1 GND C132 0.01U 0402 +80-20% 50V 120Z/100M 2 2012 L29 1 2 C83 0.1U 0402 +80-20% 50V C769 0.1U 0402 +80-20% 50V GND 1 C80 0.1U 0402 +80-20% 50V C164 10U 0805 6.3V 10% L39 1 2012 2 1 C119 0.1U 0402 +80-20% 50V 2 1 C 2 C111 0.1U 0402 +80-20% 50V 2 2 1 GND 1 VDD_CORE C114 10U 0805 6.3V 10% 1 C101 1000P 0402 +/-20% 50V AA23 AA24 AB30 AC23 AC27 AE30 AF27 J30 M23 M24 N30 P23 P27 T23 T24 T30 U27 V23 V24 W30 Y27 A15 A21 A28 A3 A9 AA1 AA4 AA7 AA8 AD4 B1 B30 D11 D14 D17 D20 D23 D26 D5 D8 E27 F4 G10 G13 G15 G19 G22 G27 G7 H10 H13 H15 H17 H19 H22 J1 J23 J24 J4 J7 J8 L27 L8 M4 N7 N8 R1 R4 T7 T8 V4 V7 V8 2 C109 0.1U 0402 +80-20% 50V VDDP_0 VDDP_1 VDDP_2 VDDP_3 VDDP_4 VDDP_5 VDDP_6 VDDP_7 VDDP_8 VDDP_9 VDDP_10 VDDP_11 VDDP_12 VDDP_13 VDDP_14 VDDP_15 VDDP_16 VDDP_17 VDDP_18 VDDP_19 VDDP_20 VDDR1_0 VDDR1_1 VDDR1_2 VDDR1_3 VDDR1_4 VDDR1_5 VDDR1_6 VDDR1_7 VDDR1_8 VDDR1_9 VDDR1_10 VDDR1_11 VDDR1_12 VDDR1_13 VDDR1_14 VDDR1_15 VDDR1_16 VDDR1_17 VDDR1_18 VDDR1_19 VDDR1_20 VDDR1_21 VDDR1_22 VDDR1_23 VDDR1_24 VDDR1_25 VDDR1_26 VDDR1_27 VDDR1_28 VDDR1_29 VDDR1_30 VDDR1_31 VDDR1_32 VDDR1_33 VDDR1_34 VDDR1_35 VDDR1_36 VDDR1_37 VDDR1_38 VDDR1_39 VDDR1_40 VDDR1_41 VDDR1_42 VDDR1_43 VDDR1_44 VDDR1_45 VDDR1_46 VDDR1_47 VDDR1_48 VDDR1_49 VDDR1_50 VDDR1_51 VDDR1_52 2 C91 0.01U 0402 +80-20% 50V 2 2 C106 0.01U 0402 +80-20% 50V VDDC_0 VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDDC_23 VDDC_24 VDDC_25 VDDC_26 VDDC_27 VDDC_28 VDDC_29 VDDC_30 VDDC_31 VDDC_32 VDDC_33 VDDC_34 VDDC_35 VDDC_36 VDDC_37 VDDC_38 VDDC_39 VDDC_40 1 1 1 1 2 C107 0.1U 0402 +80-20% 50V 2 1 2 C100 1000P 0402 +/-20% 50V 1 C85 0.01U 0402 +80-20% 50V 2 C89 10U 0805 6.3V 10% 2 1 2 C88 0.1U 0402 +80-20% 50V 1 C82 10U 0805 6.3V 10% 2 2 1 2 1 C743 + 150U 7343 2.5V 1 1 U710D AC13 AC15 AC17 AD13 AD15 M12 M13 M14 M17 M18 M19 N12 N13 N14 N17 N18 N19 P12 P13 P14 P17 P18 P19 U12 U13 U14 U17 U18 U19 V12 V13 V14 V17 V18 V19 W12 W13 W14 W17 W18 W19 D +1.8V AGP_VDDQ 1 D VDD_MEM_IO 120Z/100M 2 2012 120Z/100M 2 2012 GND +1.5V A A 120Z/100M 2 2 C121 10U 0805 6.3V 10% VDD_CORE1.5 1 2012 C134 0.1U 0402 +80-20% 50V 2 L33 1 1 120Z/100M/NA 2 2012 AGP_VDDQ 2 L705 1 120Z/100M 2 2012 1 L40 1 +1.8V C135 0.1U 0402 +80-20% 50V Title 8050D MOTHER B/D Size C GND Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 8 of 34 5 4 3 D C MEMA_MD0 MEMA_MD1 MEMA_MD2 MEMA_MD3 MEMA_MD4 MEMA_MD5 MEMA_MD6 MEMA_MD7 MEMA_MD8 MEMA_MD9 MEMA_MD10 MEMA_MD11 MEMA_MD12 MEMA_MD13 MEMA_MD14 MEMA_MD15 MEMA_MD16 MEMA_MD17 MEMA_MD18 MEMA_MD19 MEMA_MD20 MEMA_MD21 MEMA_MD22 MEMA_MD23 MEMA_MD24 MEMA_MD25 MEMA_MD26 MEMA_MD27 MEMA_MD28 MEMA_MD29 MEMA_MD30 MEMA_MD31 MEMA_MD32 MEMA_MD33 MEMA_MD34 MEMA_MD35 MEMA_MD36 MEMA_MD37 MEMA_MD38 MEMA_MD39 MEMA_MD40 MEMA_MD41 MEMA_MD42 MEMA_MD43 MEMA_MD44 MEMA_MD45 MEMA_MD46 MEMA_MD47 MEMA_MD48 MEMA_MD49 MEMA_MD50 MEMA_MD51 MEMA_MD52 MEMA_MD53 MEMA_MD54 MEMA_MD55 MEMA_MD56 MEMA_MD57 MEMA_MD58 MEMA_MD59 MEMA_MD60 MEMA_MD61 MEMA_MD62 MEMA_MD63 L25 L26 K25 K26 J26 H25 H26 G26 G30 D29 D28 E28 E29 G29 G28 F28 G25 F26 E26 F25 E24 F23 E23 D22 B29 C29 C25 C27 B28 B25 C26 B26 F17 E17 D16 F16 E15 F14 E14 F13 C17 B18 B17 B15 C13 B14 C14 C16 A13 A12 C12 B12 C10 C9 B9 B10 E13 E12 E10 F12 F11 E9 F9 F8 DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 DQA9 DQA10 DQA11 DQA12 DQA13 DQA14 DQA15 DQA16 DQA17 DQA18 DQA19 DQA20 DQA21 DQA22 DQA23 DQA24 DQA25 DQA26 DQA27 DQA28 DQA29 DQA30 DQA31 DQA32 DQA33 DQA34 DQA35 DQA36 DQA37 DQA38 DQA39 DQA40 DQA41 DQA42 DQA43 DQA44 DQA45 DQA46 DQA47 DQA48 DQA49 DQA50 DQA51 DQA52 DQA53 DQA54 DQA55 DQA56 DQA57 DQA58 DQA59 DQA60 DQA61 DQA62 DQA63 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 MAA14 DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7 RASA# CASA# WEA# CSA0# CSA1# CKEA CLKA0 CLKA0# CLKA1 CLKA1# DIMA_0 DIMA_1 PLLTEST RSTB_MSK VREFG DVOVMODE DMINUS DPLUS DBI_LO DBI_HI E22 B22 B23 B24 C23 C22 F22 F21 C21 A24 C24 A25 E21 B20 C19 MEMA_MA0 MEMA_MA1 MEMA_MA2 MEMA_MA3 MEMA_MA4 MEMA_MA5 MEMA_MA6 MEMA_MA7 MEMA_MA8 MEMA_MA9 MEMA_MA10 MEMA_MA11 MEMA_MA12 MEMA_MA13 J25 F29 E25 A27 F15 C15 C11 E11 MEMA_DQM#0 MEMA_DQM#1 MEMA_DQM#2 MEMA_DQM#3 MEMA_DQM#4 MEMA_DQM#5 MEMA_DQM#6 MEMA_DQM#7 J27 F30 F24 B27 E16 B16 B11 F10 MEMA_QSA0 MEMA_QSA1 MEMA_QSA2 MEMA_QSA3 MEMA_QSA4 MEMA_QSA5 MEMA_QSA6 MEMA_QSA7 E18 MEMA_CAS# E19 MEMA_WE# E20 MEMA_CS0# C751 1 2 470P 0402 50V 10% R758 1 56 2 2 0402 5% F20 MEMA_CS1# R760 1 56 0402 B19 MEMA_CKE B21 MEMA_CLK0 R761 1 10 C20 MEMA_CLK0# R759 1 10 5% 2 0402 5% 2 0402 C18 MEMA_CLK1 R757 1 10 A18 MEMA_CLK1# R755 1 10 5% 2 0402 5% 2 0402 DIMA_0 DIMA_1 AE25 R787 1 0 2 5% 0402G_DFS GND AG4 AE10 AE11 AF11 R81 VGA_THERMDC VGA_THERMDA AB26 AB25 R98 R97 MOBILITY-M10-P BGA644_64_1MM 1 0 2 0402 GND VGA_THERMDC 22 VGA_THERMDA 22 0 1 2 5% 0402G_DFS 0 1 2 5% 0402G_DFS AGP_VDDQ 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 RP23 24*4 1206 RP24 24*4 1206 RP18 24*4 1206 RP20 24*4 1206 RP19 24*4 1206 RP17 24*4 1206 RP21 24*4 1206 RP22 24*4 1206 RP706 24*4 1206 RP709 24*4 1206 RP716 24*4 1206 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 VMDA[0..63] VMDA0 VMDA1 VMDA2 VMDA3 VMDA4 VMDA5 VMDA6 VMDA7 VMDA8 VMDA9 VMDA10 VMDA11 VMDA12 VMDA13 VMDA14 VMDA15 VMDA16 VMDA17 VMDA18 VMDA19 VMDA20 VMDA21 VMDA22 VMDA23 VMDA24 VMDA25 VMDA26 VMDA27 VMDA28 VMDA29 VMDA30 VMDA31 VMDA32 VMDA33 VMDA34 VMDA35 VMDA36 VMDA37 VMDA38 VMDA39 VMDA40 VMDA41 VMDA42 VMDA43 VMDA44 VMDA45 VMDA46 VMDA47 VMDA48 VMDA49 VMDA50 VMDA51 VMDA52 VMDA53 VMDA54 VMDA55 VMDA56 VMDA57 VMDA58 VMDA59 VMDA60 VMDA61 VMDA62 VMDA63 VDQMA#[0..7] RASB# CASB# WEB# CSB0# CSB1# CKEB CLKB0 CLKB0# CLKB1 CLKB1# DIMB_0 DIMB_1 MVREFD MVREFS F6 B3 K6 G1 V5 W1 AC5 AD1 MEMB_QSA0 MEMB_QSA1 MEMB_QSA2 MEMB_QSA3 MEMB_QSA4 MEMB_QSA5 MEMB_QSA6 MEMB_QSA7 R2 MEMB_RAS# T5 MEMB_CAS# T6 MEMB_WE# R5 MEMB_CS0# R6 MEMB_CS1# R3 MEMB_CKE R754 1 56 2 5% 0402 5% C742 1 2 470P 0402 50V 10% VCLKA0 VCLKA#0 10 10 VCLKA1 VCLKA#1 10 10 2 R45 1 1K 1% 2 0402 R44 1 1K 1% 2 0402 GND +3V GND MEMTEST C729 1 2 470P 0402 50V 10% R725 1 56 2 2 0402 5% 5% GND N1 N2 R728 1 10 R727 1 10 5% 2 0402 5% 2 0402 VCLKB0 VCLKB#0 T2 T3 R50 R51 5% 2 0402 5% 2 0402 VCLKB1 VCLKB#1 1 10 1 10 R42 1 56 2 0402 5% C41 1 0402 DIMB_0 DIMB_1 E3 AA3 B7 0 B8 R747 1 2 5% 0402G_DFS C6 C7 C8 R750 47 0402 5% GND 5 R726 1 56 0402 1 MEMVMODE0 MEMVMODE1 MEMB_DQM#0 MEMB_DQM#1 MEMB_DQM#2 MEMB_DQM#3 MEMB_DQM#4 MEMB_DQM#5 MEMB_DQM#6 MEMB_DQM#7 R69 R74 R75 4.7K 0402 5% R43 1 56 2 0402 5% 2 470P 50V 10% GND VCLKB0 VCLKB#0 10 10 VCLKB1 VCLKB#1 10 10 VDD_MEM_IO 1 R740 2 R741 1K 0402 1% 2 VDD_MEM_IO 0402 1% 1 R736 2 R745 1K 0402 1% 2 0402 1% C732 1 2 0.1U GND 0402 50V +80-20% 1 2 0.1U GND 50V +80-20% C730 6.3V C731 6.3V 1 2 10U 0805 10% 1 2 10U 0805 10% 1 1K 1 VDD_CORE1.8 1K C735 0402 0402 5% 1 4.7K 2 1 4.7K/NA 2 0402 5% 1 QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7 E6 B2 J5 G3 W6 W2 AC6 AD2 2 DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 MEMB_MA0 MEMB_MA1 MEMB_MA2 MEMB_MA3 MEMB_MA4 MEMB_MA5 MEMB_MA6 MEMB_MA7 MEMB_MA8 MEMB_MA9 MEMB_MA10 MEMB_MA11 MEMB_MA12 MEMB_MA13 N5 M1 M3 L3 L2 M2 M5 P6 N3 K2 K3 J2 P5 P3 P2 2 MOBILITY-M10-P BGA644_64_1MM MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 MAB14 1 A DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 DQB9 DQB10 DQB11 DQB12 DQB13 DQB14 DQB15 DQB16 DQB17 DQB18 DQB19 DQB20 DQB21 DQB22 DQB23 DQB24 DQB25 DQB26 DQB27 DQB28 DQB29 DQB30 DQB31 DQB32 DQB33 DQB34 DQB35 DQB36 DQB37 DQB38 DQB39 DQB40 DQB41 DQB42 DQB43 DQB44 DQB45 DQB46 DQB47 DQB48 DQB49 DQB50 DQB51 DQB52 DQB53 DQB54 DQB55 DQB56 DQB57 DQB58 DQB59 DQB60 DQB61 DQB62 DQB63 2 B D7 F7 E7 G6 G5 F5 E5 C4 B5 C5 A4 B4 C2 D3 D1 D2 G4 H6 H5 J6 K5 K4 L6 L5 G2 F3 H2 E2 F2 J3 F1 H3 U6 U5 U3 V6 W5 W4 Y6 Y5 U2 V2 V1 V3 W3 Y2 Y3 AA2 AA6 AA5 AB6 AB5 AD6 AD5 AE5 AE4 AB2 AB3 AC2 AC3 AD3 AE1 AE2 AE3 MEMA_DQM#0 MEMA_DQM#1 MEMA_DQM#2 MEMA_DQM#3 MEMA_DQM#4 MEMA_DQM#5 MEMA_DQM#6 MEMA_DQM#7 R108 R93 R92 R107 R719 R729 R730 R718 1 1 1 1 1 1 1 1 24 24 24 24 24 24 24 24 5% 5% 5% 5% 5% 5% 5% 5% 2 2 2 2 2 2 2 2 0402 0402 0402 0402 0402 0402 0402 0402 VDQMA#0 VDQMA#1 VDQMA#2 VDQMA#3 VDQMA#4 VDQMA#5 VDQMA#6 VDQMA#7 MEMA_QSA0 MEMA_QSA1 MEMA_QSA2 MEMA_QSA3 MEMA_QSA4 MEMA_QSA5 MEMA_QSA6 MEMA_QSA7 R109 R91 R90 R106 R720 R731 R732 R717 1 1 1 1 1 1 1 1 24 24 24 24 24 24 24 24 5% 5% 5% 5% 5% 5% 5% 5% 2 2 2 2 2 2 2 2 0402 0402 0402 0402 0402 0402 0402 0402 VQSA0 VQSA1 VQSA2 VQSA3 VQSA4 VQSA5 VQSA6 VQSA7 RP713 24*4 1206 RP714 24*4 1206 RP717 24*4 1206 RP708 24*4 1206 RP705 24*4 1206 R70 4.7K/NAFOR 2.5V VDDR1 MEMVMODE=1.8V 0402 MEMVMODE1=GND 5% FOR 1.8V VDDR1(ELPIDA) MEMVMODE=GND MEMVMODE1=1.8V MEMB_MD0 MEMB_MD1 MEMB_MD2 MEMB_MD3 MEMB_MD4 MEMB_MD5 MEMB_MD6 MEMB_MD7 MEMB_MD8 MEMB_MD9 MEMB_MD10 MEMB_MD11 MEMB_MD12 MEMB_MD13 MEMB_MD14 MEMB_MD15 MEMB_MD16 MEMB_MD17 MEMB_MD18 MEMB_MD19 MEMB_MD20 MEMB_MD21 MEMB_MD22 MEMB_MD23 MEMB_MD24 MEMB_MD25 MEMB_MD26 MEMB_MD27 MEMB_MD28 MEMB_MD29 MEMB_MD30 MEMB_MD31 MEMB_MD32 MEMB_MD33 MEMB_MD34 MEMB_MD35 MEMB_MD36 MEMB_MD37 MEMB_MD38 MEMB_MD39 MEMB_MD40 MEMB_MD41 MEMB_MD42 MEMB_MD43 MEMB_MD44 MEMB_MD45 MEMB_MD46 MEMB_MD47 MEMB_MD48 MEMB_MD49 MEMB_MD50 MEMB_MD51 MEMB_MD52 MEMB_MD53 MEMB_MD54 MEMB_MD55 MEMB_MD56 MEMB_MD57 MEMB_MD58 MEMB_MD59 MEMB_MD60 MEMB_MD61 MEMB_MD62 MEMB_MD63 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 RP9 24*4 1206 RP11 24*4 1206 RP4 24*4 1206 RP3 24*4 1206 RP12 24*4 1206 RP13 24*4 1206 RP5 24*4 1206 RP7 24*4 1206 RP707 24*4 1206 RP712 24*4 1206 RP701 24*4 1206 RP702 24*4 1206 RP711 24*4 1206 RP710 24*4 1206 RP703 24*4 1206 RP704 24*4 1206 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 MEMA_CAS# MEMA_RAS# MEMA_CS0# MEMA_WE# 1 2 3 4 RP15 0*8 RPX8 VMDB0 VMDB1 VMDB2 VMDB3 VMDB4 VMDB5 VMDB6 VMDB7 VMDB8 VMDB9 VMDB10 VMDB11 VMDB12 VMDB13 VMDB14 VMDB15 VMDB16 VMDB17 VMDB18 VMDB19 VMDB20 VMDB21 VMDB22 VMDB23 VMDB24 VMDB25 VMDB26 VMDB27 VMDB28 VMDB29 VMDB30 VMDB31 VMDB32 VMDB33 VMDB34 VMDB35 VMDB36 VMDB37 VMDB38 VMDB39 VMDB40 VMDB41 VMDB42 VMDB43 VMDB44 VMDB45 VMDB46 VMDB47 VMDB48 VMDB49 VMDB50 VMDB51 VMDB52 VMDB53 VMDB54 VMDB55 VMDB56 VMDB57 VMDB58 VMDB59 VMDB60 VMDB61 VMDB62 VMDB63 VMDB[0..63] 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 RP14 0*8 RPX8 VCASA# VRASA# VCSA#0 VWEA# 0/NA 2 0402 0/NA 2 0402 0/NA 2 0402 VDIMA_0 VDIMA_1 VCSA#1 10 VMA[0..13] VCKEA 10 10 VCASA# VRASA# VCSA#0 VWEA# 10 10 10 10 VDIMA_0 VDIMA_1 VCSA#1 10 10 10 C VDQMB#[0..7] MEMB_DQM#0 MEMB_DQM#1 MEMB_DQM#2 MEMB_DQM#3 MEMB_DQM#4 MEMB_DQM#5 MEMB_DQM#6 MEMB_DQM#7 R40 R29 R38 R35 R724 R710 R722 R716 1 1 1 1 1 1 1 1 24 24 24 24 24 24 24 24 5% 5% 5% 5% 5% 5% 5% 5% 2 2 2 2 2 2 2 2 0402 0402 0402 0402 0402 0402 0402 0402 VDQMB#0 VDQMB#1 VDQMB#2 VDQMB#3 VDQMB#4 VDQMB#5 VDQMB#6 VDQMB#7 MEMB_QSA0 MEMB_QSA1 MEMB_QSA2 MEMB_QSA3 MEMB_QSA4 MEMB_QSA5 MEMB_QSA6 MEMB_QSA7 R41 R30 R39 R33 R723 R709 R721 R715 1 1 1 1 1 1 1 1 24 24 24 24 24 24 24 24 5% 5% 5% 5% 5% 5% 5% 5% 2 2 2 2 2 2 2 2 0402 0402 0402 0402 0402 0402 0402 0402 VQSB0 VQSB1 VQSB2 VQSB3 VQSB4 VQSB5 VQSB6 VQSB7 MEMB_MA12 MEMB_MA13 MEMB_MA0 MEMB_MA2 MEMB_MA1 MEMB_MA10 MEMB_MA3 MEMB_MA11 MEMB_MA4 MEMB_MA9 MEMB_MA6 MEMB_MA5 MEMB_MA7 MEMB_MA8 MEMB_CKE 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 MEMB_CAS# MEMB_RAS# MEMB_CS0# MEMB_WE# 1 2 3 4 DIMB_0 DIMB_1 MEMB_CS1# VQSB[0..7] 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 RP6 0*8 RPX8 R31 1 R711 1 R36 1 VMB12 VMB13 VMB0 VMB2 VMB1 VMB10 VMB3 VMB11 VMB4 VMB9 VMB6 VMB5 VMB7 VMB8 VCKEB 8 7 6 5 VCASB# VRASB# VCSB#0 VWEB# 0/NA 2 0402 0/NA 2 0402 0/NA 2 0402 VDIMB_0 VDIMB_1 VCSB#1 RP10 0*4 1206 VDQMB#[0..7] 10 VQSB[0..7] 10 B VMB[0..13] RP8 0*8 RPX8 VMB[0..13] VCKEB 10 10 VCASB# VRASB# VCSB#0 VWEB# 10 10 10 10 VDIMB_0 VDIMB_1 VCSB#1 10 10 10 A Title 8050D MOTHER B/D Date: PDF created with FinePrint pdfFactory trial version http://www.fineprint.com VQSA[0..7] 10 Size C 3 10 D VMA12 VMA13 VMA0 VMA2 VMA1 VMA10 VMA3 VMA11 VMA4 VMA9 VMA6 VMA5 VMA7 VMA8 VCKEA 8 7 6 5 RP16 0*4 1206 DIMA_0 R89 1 DIMA_1 R746 1 MEMA_CS1# R80 1 GND 4 VQSA[0..7] VDQMA#[0..7] VMA[0..13] 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 MEMA_MA12 MEMA_MA13 MEMA_MA0 MEMA_MA2 MEMA_MA1 MEMA_MA10 MEMA_MA3 MEMA_MA11 MEMA_MA4 MEMA_MA9 MEMA_MA6 MEMA_MA5 MEMA_MA7 MEMA_MA8 MEMA_CKE VMDB[0..63] U710C MEMB_MD0 MEMB_MD1 MEMB_MD2 MEMB_MD3 MEMB_MD4 MEMB_MD5 MEMB_MD6 MEMB_MD7 MEMB_MD8 MEMB_MD9 MEMB_MD10 MEMB_MD11 MEMB_MD12 MEMB_MD13 MEMB_MD14 MEMB_MD15 MEMB_MD16 MEMB_MD17 MEMB_MD18 MEMB_MD19 MEMB_MD20 MEMB_MD21 MEMB_MD22 MEMB_MD23 MEMB_MD24 MEMB_MD25 MEMB_MD26 MEMB_MD27 MEMB_MD28 MEMB_MD29 MEMB_MD30 MEMB_MD31 MEMB_MD32 MEMB_MD33 MEMB_MD34 MEMB_MD35 MEMB_MD36 MEMB_MD37 MEMB_MD38 MEMB_MD39 MEMB_MD40 MEMB_MD41 MEMB_MD42 MEMB_MD43 MEMB_MD44 MEMB_MD45 MEMB_MD46 MEMB_MD47 MEMB_MD48 MEMB_MD49 MEMB_MD50 MEMB_MD51 MEMB_MD52 MEMB_MD53 MEMB_MD54 MEMB_MD55 MEMB_MD56 MEMB_MD57 MEMB_MD58 MEMB_MD59 MEMB_MD60 MEMB_MD61 MEMB_MD62 MEMB_MD63 10 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C VCLKA1 VCLKA#1 TP17 1 AG29 GND 5% VCLKA0 VCLKA#0 R756 1 56 0402 1 VMDA[0..63] MEMA_MD0 MEMA_MD1 MEMA_MD2 MEMA_MD3 MEMA_MD4 MEMA_MD5 MEMA_MD6 MEMA_MD7 MEMA_MD8 MEMA_MD9 MEMA_MD10 MEMA_MD11 MEMA_MD12 MEMA_MD13 MEMA_MD14 MEMA_MD15 MEMA_MD16 MEMA_MD17 MEMA_MD18 MEMA_MD19 MEMA_MD20 MEMA_MD21 MEMA_MD22 MEMA_MD23 MEMA_MD24 MEMA_MD25 MEMA_MD26 MEMA_MD27 MEMA_MD28 MEMA_MD29 MEMA_MD30 MEMA_MD31 MEMA_MD32 MEMA_MD33 MEMA_MD34 MEMA_MD35 MEMA_MD36 MEMA_MD37 MEMA_MD38 MEMA_MD39 MEMA_MD40 MEMA_MD41 MEMA_MD42 MEMA_MD43 MEMA_MD44 MEMA_MD45 MEMA_MD46 MEMA_MD47 MEMA_MD48 MEMA_MD49 MEMA_MD50 MEMA_MD51 MEMA_MD52 MEMA_MD53 MEMA_MD54 MEMA_MD55 MEMA_MD56 MEMA_MD57 MEMA_MD58 MEMA_MD59 MEMA_MD60 MEMA_MD61 MEMA_MD62 MEMA_MD63 A19 MEMA_RAS# D30 B13 2 ATI M10-P(3/4) U710B 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 9 of 34 9 VMB[0..13] G7 G8 H5 H6 H7 H8 G5 G6 E5 E6 E7 E8 F5 F6 F7 F8 K8 L9 +2.5V_M10 VDD_MEM_IOREFM12 L12 M2 B3 GND B10 G3 G10 K11 VDIMB_1 K12 L2 VCSB#1 L3 VCSB#1 9 A12/RFU1 BA2/RFU2 9 G7 G8 H5 H6 H7 H8 G5 G6 E5 E6 E7 E8 F5 F6 F7 F8 K8 L9 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 D6 D7 D9 J5 J6 J7 J8 K4 K9 D4 C8 C9 C10 D5 D8 E4 E9 F4 F9 G4 G9 H4 H9 J4 J9 A3 C3 C4 C5 A10 C6 C7 D3 D10 K3 K6 K7 K10 VDD_MEM_IO B2 B4 B6 B7 B9 B11 D2 D11 E3 E10 F3 F10 H3 H10 J3 J10 HY5DU2832222F BGA144F_08MM_1 GND C727 0.01U 0402 +80-20% 50V C725 0.1U 0402 10% 16V 4 C37 10U 0805 6.3V 10% C30 1U 0402 +80-20% 10V C35 0.1U 0402 10% 16V GND VMDB56 VMDB57 VMDB58 VMDB59 VMDB60 VMDB61 VMDB62 VMDB63 VQSB7 K8 L9 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 C6 C7 D3 D10 K3 K6 K7 K10 VDD_MEM_IO B2 B4 B6 B7 B9 B11 D2 D11 E3 E10 F3 F10 H3 H10 J3 J10 B C33 0.01U 0402 +80-20% 50V GND 1 C29 0.1U 0402 10% 16V C34 0.01U 0402 +80-20% 50V GND 1 A R34 1K 0402 1% VDD_MEM_IOREF R32 1K 0402 1% 2 C722 10U 0805 6.3V 10% GND GND 1 1 C719 0.1U 0402 10% 16V 2 2 2 R712 1K 0402 1% 1 1 2 VDD_MEM_IOREF 2 1 D12 C12 C11 B12 A9 A8 B8 A7 A12 VDD_MEM_IO 1 5 2 1 2 GND C36 0.1U 0402 10% 16V 1 1 C726 0.01U 0402 +80-20% 50V 1 2 2 GND C57 10U 0805 6.3V 10% VMDB48 VMDB49 VMDB50 VMDB51 VMDB52 VMDB53 VMDB54 VMDB55 VQSB6 +2.5V_M10 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 2 C718 0.1U 0402 10% 16V 2 C721 1U 0402 +80-20% 10V 1 1 1 C716 10U 0805 6.3V 10% R713 1K 0402 1% C65 0.1U 0402 10% 16V C28 1U 0402 +80-20% 10V C27 0.1U 0402 10% 16V 2 C51 0.01U 0402 +80-20% 50V E2 E1 F2 F1 H2 H1 J1 J2 G1 D VDD_MEM_IO VDD_MEM_IO VDD_MEM_IOREF R60 1K 0402 1% C32 10U 0805 6.3V 10% GND C46 0.1U 0402 10% 16V VMDB40 VMDB41 VMDB42 VMDB43 VMDB44 VMDB45 VMDB46 VMDB47 VQSB5 1 1 1 C720 0.1U 0402 10% 16V 2 C723 1U 0402 +80-20% 10V 2 C63 0.1U 0402 10% 16V J12 J11 H12 H11 F12 F11 E12 E11 G12 C 1 C724 10U 0805 6.3V 10% 2 C48 1U 0402 +80-20% 10V A12/RFU1 BA2/RFU2 VMDB32 VMDB33 VMDB34 VMDB35 VMDB36 VMDB37 VMDB38 VMDB39 VQSB4 HY5DU2832222F BGA144F_08MM_1 2 C47 0.01U 0402 +80-20% 50V DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS3 A6 B5 A5 A4 B1 C2 C1 D1 A1 +2.5V_M10 1 C45 0.1U 0402 10% 16V DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS2 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 VSSQ_10 VSSQ_11 VSSQ_12 VSSQ_13 VSSQ_14 VSSQ_15 VSSQ_16 VSSQ_17 VSSQ_18 VSSQ_19 GND 2 C62 1U 0402 +80-20% 10V DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS1 VSS/TH1 VSS/TH2 VSS/TH3 VSS/TH4 VSS/TH5 VSS/TH6 VSS/TH7 VSS/TH8 VSS/TH9 VSS/TH10 VSS/TH11 VSS/TH12 VSS/TH13 VSS/TH14 VSS/TH15 VSS/TH16 +2.5V_M10 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 VSSQ_10 VSSQ_11 VSSQ_12 VSSQ_13 VSSQ_14 VSSQ_15 VSSQ_16 VSSQ_17 VSSQ_18 VSSQ_19 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS0 VREF MCL NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 1 VDD_MEM_IO B2 B4 B6 B7 B9 B11 D2 D11 E3 E10 F3 F10 H3 H10 J3 J10 2 2 C49 10U 0805 6.3V 10% A0 A1 A2 A3 A4 A5 A6 A7 A8/AP BA0 BA1 A9 A10 A11 DQM0 DQM1 DQM2 DQM3 RAS CAS WE CS CK CK# CKE 2 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 D6 D7 D9 J5 J6 J7 J8 K4 K9 D4 C8 C9 C10 D5 D8 E4 E9 F4 F9 G4 G9 H4 H9 J4 J9 A3 C3 C4 C5 A10 C6 C7 D3 D10 K3 K6 K7 K10 VSS/TH1 VSS/TH2 VSS/TH3 VSS/TH4 VSS/TH5 VSS/TH6 VSS/TH7 VSS/TH8 VSS/TH9 VSS/TH10 VSS/TH11 VSS/TH12 VSS/TH13 VSS/TH14 VSS/TH15 VSS/TH16 GND 1 2 1 2 C740 10U 0805 6.3V 10% VMDB24 VMDB25 VMDB26 VMDB27 VMDB28 VMDB29 VMDB30 VMDB31 VQSB3 VRASB# VCASB# VWEB# VCSB#0 VCLKB1 VCLKB#1 VCKEB M4 M5 L5 M6 M7 L8 M8 M9 M10 M3 L4 L7 K5 L6 A2 G11 G2 A11 L1 K1 K2 M1 L10 L11 M11 1 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 1 2 1 2 C741 0.1U 0402 10% 16V D12 C12 C11 B12 A9 A8 B8 A7 A12 9 9 9 9 9 9 9 2 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 VSSQ_10 VSSQ_11 VSSQ_12 VSSQ_13 VSSQ_14 VSSQ_15 VSSQ_16 VSSQ_17 VSSQ_18 VSSQ_19 1 1 9 R65 1K 0402 1% VDD_MEM_IOREF R753 1K 0402 1% VMDB16 VMDB17 VMDB18 VMDB19 VMDB20 VMDB21 VMDB22 VMDB23 VQSB2 U708 VMB0 VMB1 VMB2 VMB3 VMB4 VMB5 VMB6 VMB7 VMB8 VMB12 VMB13 VMB9 VMB10 VMB11 VDQMB#4 VDQMB#5 VDQMB#6 VDQMB#7 VRASB# VCASB# VWEB# VCSB#0 VCLKB1 VCLKB#1 VCKEB 2 A12/RFU1 BA2/RFU2 VDD_MEM_IO R751 1K 0402 1% E2 E1 F2 F1 H2 H1 J1 J2 G1 9 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C VSS/TH1 VSS/TH2 VSS/TH3 VSS/TH4 VSS/TH5 VSS/TH6 VSS/TH7 VSS/TH8 VSS/TH9 VSS/TH10 VSS/TH11 VSS/TH12 VSS/TH13 VSS/TH14 VSS/TH15 VSS/TH16 GND VDD_MEM_IO A VMDB8 VMDB9 VMDB10 VMDB11 VMDB12 VMDB13 VMDB14 VMDB15 VQSB1 9 VMB[0..13] VDD_MEM_IO 1 1 C749 0.01U 0402 +80-20% 50V 2 1 C752 0.1U 0402 10% 16V 2 1 2 2 2 1 1 1 2 C754 0.1U 0402 10% 16V DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS3 GND VDD_MEM_IO C748 1U 0402 +80-20% 10V VREF MCL NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 J12 J11 H12 H11 F12 F11 E12 E11 G12 9 VQSB[0..7] 1 C59 10U 0805 6.3V 10% GND VDD_MEM_IO C756 10U 0805 6.3V 10% DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS2 VMDB0 VMDB1 VMDB2 VMDB3 VMDB4 VMDB5 VMDB6 VMDB7 VQSB0 2 2 C745 0.01U 0402 +80-20% 50V DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS1 A6 B5 A5 A4 B1 C2 C1 D1 A1 9 VDQMB#[0..7] +2.5V_M10 1 1 C744 0.1U 0402 10% 16V 2 C753 1U 0402 +80-20% 10V 2 2 1 1 1 +2.5V_M10 C750 10U 0805 6.3V 10% 9 VDD_MEM_IOREFM12 L12 M2 B3 GND B10 G3 G10 K11 VDIMB_0 K12 L2 VCSB#1 L3 VCSB#1 HY5DU2832222F BGA144F_08MM_1 GND +2.5V_M10 VMDA56 VMDA57 VMDA58 VMDA59 VMDA60 VMDA61 VMDA62 VMDA63 VQSA7 VRASB# VCASB# VWEB# VCSB#0 VCLKB0 VCLKB#0 VCKEB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS0 2 HY5DU2832222F BGA144F_08MM_1 D12 C12 C11 B12 A9 A8 B8 A7 A12 9 9 9 9 9 9 9 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP BA0 BA1 A9 A10 A11 DQM0 DQM1 DQM2 DQM3 RAS CAS WE CS CK CK# CKE 2 VDD_MEM_IO B2 B4 B6 B7 B9 B11 D2 D11 E3 E10 F3 F10 H3 H10 J3 J10 VMDA48 VMDA49 VMDA50 VMDA51 VMDA52 VMDA53 VMDA54 VMDA55 VQSA6 1 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 D6 D7 D9 J5 J6 J7 J8 K4 K9 D4 C8 C9 C10 D5 D8 E4 E9 F4 F9 G4 G9 H4 H9 J4 J9 A3 C3 C4 C5 A10 C6 C7 D3 D10 K3 K6 K7 K10 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS3 E2 E1 F2 F1 H2 H1 J1 J2 G1 2 VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VREF MCL NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 VMDA40 VMDA41 VMDA42 VMDA43 VMDA44 VMDA45 VMDA46 VMDA47 VQSA5 M4 M5 L5 M6 M7 L8 M8 M9 M10 M3 L4 L7 K5 L6 A2 G11 G2 A11 L1 K1 K2 M1 L10 L11 M11 VMDB[0..63] 1 1 G7 G8 H5 H6 H7 H8 G5 G6 E5 E6 E7 E8 F5 F6 F7 F8 K8 L9 +2.5V_M10 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9 VSSQ_10 VSSQ_11 VSSQ_12 VSSQ_13 VSSQ_14 VSSQ_15 VSSQ_16 VSSQ_17 VSSQ_18 VSSQ_19 GND 2 9 9 VDD_MEM_IOREFM12 L12 M2 B3 GND B10 G3 G10 K11 VDIMA_1 K12 L2 VCSA#1 L3 VCSA#1 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS2 J12 J11 H12 H11 F12 F11 E12 E11 G12 U1 VMB0 VMB1 VMB2 VMB3 VMB4 VMB5 VMB6 VMB7 VMB8 VMB12 VMB13 VMB9 VMB10 VMB11 VDQMB#0 VDQMB#1 VDQMB#2 VDQMB#3 VRASB# VCASB# VWEB# VCSB#0 VCLKB0 VCLKB#0 VCKEB 1 VMDA24 VMDA25 VMDA26 VMDA27 VMDA28 VMDA29 VMDA30 VMDA31 VQSA3 VRASA# VCASA# VWEA# VCSA#0 VCLKA1 VCLKA#1 VCKEA1 VMDA32 VMDA33 VMDA34 VMDA35 VMDA36 VMDA37 VMDA38 VMDA39 VQSA4 2 D12 C12 C11 B12 A9 A8 B8 A7 A12 9 9 9 9 9 9 9 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS1 A6 B5 A5 A4 B1 C2 C1 D1 A1 1 VMDA16 VMDA17 VMDA18 VMDA19 VMDA20 VMDA21 VMDA22 VMDA23 VQSA2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS0 2 E2 E1 F2 F1 H2 H1 J1 J2 G1 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP BA0 BA1 A9 A10 A11 DQM0 DQM1 DQM2 DQM3 RAS CAS WE CS CK CK# CKE 1 VMDA8 VMDA9 VMDA10 VMDA11 VMDA12 VMDA13 VMDA14 VMDA15 VQSA1 U709 M4 M5 L5 M6 M7 L8 M8 M9 M10 M3 L4 L7 K5 L6 A2 G11 G2 A11 L1 K1 K2 M1 L10 L11 M11 2 J12 J11 H12 H11 F12 F11 E12 E11 G12 VMA0 VMA1 VMA2 VMA3 VMA4 VMA5 VMA6 VMA7 VMA8 VMA12 VMA13 VMA9 VMA10 VMA11 VDQMA#4 VDQMA#5 VDQMA#6 VDQMA#7 VRASA# VCASA# VWEA# VCSA#0 VCLKA1 VCLKA#1 VCKEA 1 A12/RFU1 BA2/RFU2 VMDA0 VMDA1 VMDA2 VMDA3 VMDA4 VMDA5 VMDA6 VMDA7 VQSA0 2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS3 VSS/TH1 VSS/TH2 VSS/TH3 VSS/TH4 VSS/TH5 VSS/TH6 VSS/TH7 VSS/TH8 VSS/TH9 VSS/TH10 VSS/TH11 VSS/TH12 VSS/TH13 VSS/TH14 VSS/TH15 VSS/TH16 D6 D7 D9 J5 J6 J7 J8 K4 K9 D4 C8 C9 C10 D5 D8 E4 E9 F4 F9 G4 G9 H4 H9 J4 J9 A3 C3 C4 C5 A10 B DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS2 VREF MCL NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 G7 G8 H5 H6 H7 H8 G5 G6 E5 E6 E7 E8 F5 F6 F7 F8 C DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS1 A6 B5 A5 A4 B1 C2 C1 D1 A1 1 VDD_MEM_IOREFM12 L12 M2 B3 GND B10 G3 G10 K11 9 VDIMA_0 K12 L2 VCSA#1 L3 VCSA#1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS0 1 A0 A1 A2 A3 A4 A5 A6 A7 A8/AP BA0 BA1 A9 A10 A11 DQM0 DQM1 DQM2 DQM3 RAS CAS WE CS CK CK# CKE 2 U3 M4 M5 L5 M6 M7 L8 M8 M9 M10 M3 L4 L7 K5 L6 A2 G11 G2 A11 L1 K1 K2 M1 L10 L11 M11 2 9 VMA0 VMA1 VMA2 VMA3 VMA4 VMA5 VMA6 VMA7 VMA8 VMA12 VMA13 VMA9 VMA10 VMA11 VDQMA#0 VDQMA#1 VDQMA#2 VDQMA#3 VRASA# VCASA# VWEA# VCSA#0 VCLKA0 VCLKA#0 VCKEA VDQMB#[0..7] VQSB[0..7] 1 VRASA# VCASA# VWEA# VCSA#0 VCLKA0 VCLKA#0 VCKEA VMA[0..13] 2 VMDB[0..63] VRAM 2 9 9 9 9 9 9 9 9 1 D 9 VQSA[0..7] 3 2 VMA[0..13] VDQMA#[0..7] 4 1 VQSA[0..7] 9 2 VDQMA#[0..7] VMDA[0..63] 2 5 VMDA[0..63] C25 10U 0805 6.3V 10% Title 8050D MOTHER B/D Size C Date: 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 10 of 34 2 0402 2 0402 2 0402 ITP_CPU# 1 HCLK_MCH# HCLK_CPU# R889 2 0402 0/NA 5% 10 11 12 13 16 17 18 R825 33 1 R816 33 1 R826 33 1 R827 33 1 PCICK_1394 PCICK_KBC 2 2 2 2 5 6 7 R824 33 1 2 0402 21 22 23 R829 33 R818 33 R819 33 1 1 1 2 0402 2 0402 2 0402 1 R876 C793 10P/NA 0402 +/-10% 50V C792 10P/NA 0402 +/-10% 50V 2 0402 5% R881 0 CLK_PCI_STOP# 4 14 7 C795 10P 0402 +/-10% 50V 2 0402 66M_DEFSSCLK 4 2 0402 PCICLK_1394 18 PCICK_KBC 33 2 0402 PCICLK_KBC 22 R817 1 C826 10P/NA 0402 +/-10% 50V C798 10P 0402 +/-10% 50V GND C791 10P 0402 +/-10% 50V XOUT 43 46 13 48 0/NA 2 0402855_TV_CRMA 1 R766 1 1 2 2 2 1 C811 2.2U 0603 +/-10% GND R63 0/NA 0805 RESET* C/HSYNC AS ISET BCO 2 DVOCD[0..11] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] D[10] D[11] GPIO[0] GPIO[1] DVOCD0 DVOCD1 DVOCD2 DVOCD3 DVOCD4 DVOCD5 DVOCD6 DVOCD7 DVOCD8 DVOCD9 DVOCD10 DVOCD11 63 62 61 60 59 58 55 54 53 52 51 50 8 7 NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 DVOCD[0..11] 4 B +3V +3V R53 8.2K/NA 0402 5% R56 1 0/NA 0402 5% C64 0.1U/NA 0402 +80-20% 50V 2 9 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2 GND R68 8.2K/NA 0402 5% C53 0.1U/NA 0402 +80-20% 50V R54 330/NA 0402 5% GND DVOBCINTR# 4 R71 330/NA 0402 5% GND GND Default NTSC CH7011A/NA PQFP64_0.5MM A GND +3V +3VA_TV L25 GND C39 10U/NA 6.3V 0805 10% 10U/NA 6.3V 0805 10% 1 1 1 2 120Z/100M/NA 2012 C73 2 C42 0.1U/NA 0402 +80-20% 50V 1 1 C71 0.1U/NA 0402 +80-20% 50V 2 1 C43 0.1U/NA 0402 +80-20% 50V 2 1 C70 0.1U/NA 0402 +80-20% 50V 2 10U/NA 6.3V 0805 10% GND 1 1 +3V C38 GND C40 0.1U/NA 0402 +80-20% 50V 2 +3V C61 0.1U/NA 0402 +80-20% 50V Title 8050D MOTHER B/D Size C Date: 4 C809 0.1U 0402 10% 16V GND 45 1 12 49 DVDD_0 DVDD_1 DVDD_2 18 44 33 VDD P-OUT GND 5 C803 0.1U 0402 10% 16V GND 2 GND XO R49 330/NA 0402 5% 5 6 7 8 0 TV_GND XI/FIN 2 2 4 R37 1 140/NA 2 R73 1 0/NA 2 DVOCFLDSTL 0402 5% 10 35 47 SPC SPD RP2 75*4 1206 C18 100P 0402 10% 50V C821 0.1U 0402 10% 16V 1 42 CVBS/B CVBS 34 40 2 0402855_TV_LUMA ATI_TV_CRMA 7 C20 100P 0402 10% 50V C812 0.1U 0402 10% 16V 2 2 15 14 XIN C/R Y/G DGND_0 DGND_1 DGND_2 1 TV_DDCK TV_DDDA H V AGND_0 AGND_1 AGND_2 1 1 2 2 0402855_TV_COMP 0/NA 1 R763 1 0/NA 1 R1240 2 R704 1 C56 20P/NA 0402 +/-10% 50V GND 4 POUT/DET# R47 8.2K/NA 13 TV_PCIRST# 0402 5% GND 1 C21 270P 0402 +/-10% 50V GND ATI_TV_LUMA 7 1 1 C15 270P 0402 +/-10% 50V TXC8X4.5 +3V ATI_TV_COMP 7 2 C782 270P 0402 +/-10% 50V 2 2 1 GND1 GND2 7P/RA SUYIN 33007S-07T1-C 331870007007 14.318MHZ/NA C52 20P/NA 0402 +/-10% 50V 2 1 C19 1 0402 855_TV_COMP39 CVBS1 36 2 2 33P 25V +/-10% 2 120Z/100M 2 33P 25V +/-10% 2 120Z/100M 2 120Z/100M 2 33P 25V +/-10% C17 1 0402 1 USE 20P 5% 4 3 2 1 L20 1 GND1 GND2 L19 2 A 1 2 3 4 5 6 7 GND WHEN USE INTEGRATE VGA ADD R763 R766 U2 R1240 1 J704 D Q712 2N7002/NA SOT23_FET 288227002006 C344 1 0402 L56 1 1 2 3 4 5 6 7 S 4 MI2CDATA D4 BAV99/NA 2 D3 TV_GND BAV99/NA 3 3 3 TV_GND BAV99/NA GND 10K/NA 0402 5%TV_DDDA D S TV_GND 1 G 1 2 1 2 2 1 R935 855_TV_CRMA 38 855_TV_LUMA 37 XOUT 1 1M/NA 2 5% X701 1 2 2 R52 0402 2 2 R46 75/NA 0402 5% XCLK XCLK* 6 11 64 1 R48 75/NA 0402 5% 4 5 4 DVOCHSYNC XIN 4 DVOCVSYNC VREF 16 17 41 4 DVOCCLK 4 DVOCCLK# 855_TV_COMP CVBS1 +3V 57 56 AVDD_0 AVDD_1 U2 3 4 DVOVREF TV_DDCK +3V +3V D719 +3VA_TV +3V GND_0 GND_1 1 10K/NA 0402 5% Q702 2N7002/NA SOT23_FET 288227002006 GND 1608 +1.5V +3V 1 2 4 MI2CCLK 2 120Z/100M GND +3V D +3VCLKANA C 33 D S B S C823 2.2U 0603 +/-10% GND L722 1 33 2 G 1 C67 0.1U 0402 +80-20% 50V C822 0.1U 0402 10% 16V +3V R865 1 R807 Place near to 7011. C802 0.1U 0402 10% 16V GND PCICK_1394 R828 1 TV ENCODER DVOVREF C827 0.1U 0402 10% 16V GND 390 0402 1% GND +3V 1608 1 5% 1 R887 0 C799 10P/NA 0402 +/-10% 50V GND ICS950810 TSSOP56 284595081201 2 2 0402 66M_MCH 66M_ICH 66M_AGP +3VCLK66 2 120Z/100M 2 13 STOP_PCI# CLK_CPU_STOP# 1 13 2 WHEN USE INTEGRATE VGA R887/NA 3,13,31 STOP_CPU# PCICLK_ICH C788 2.2U 0603 +/-10% 1 CLK_PD# 5% C800 0.1U 0402 10% 16V 2 2 0402 C801 0.1U 0402 10% 16V GND L726 1 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 42 IREF C778 0.1U 0402 10% 16V +3V 33 24 3V66_0 66MHZ_IN/3V66_5 1608 GND GND 1 1 R820 0 PCICLK_FWH 23 PCICLK_MINIPCI 19 PCICLK_CARD 17 PCICLK_LAN 16 C790 10P 0402 +/-10% 50V 2 120Z/100M 1 66MHZ_OUT0/3V66_2 66MHZ_OUT1/3V66_3 66MHZ_OUT2/3V66_4 GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 C797 10P 0402 +/-10% 50V +3VCLKPCI L718 1 2 VDDPCI0 VDDPCI1 C789 10P 0402 +/-10% 50V GND +3V 1 PCICLK_F0 PCICLK_F1 PCICLK_F2 DEFSSCLK 13 SUSA# 0402 0402 0402 0402 C796 10P 0402 +/-10% 50V GND CLK_ITP_CPU# 2 HCLK_MCH# 4 HCLK_CPU# 2 1 VDDCPU0 VDDCPU1 CLK_ITP_CPU 2 HCLK_MCH 4 HCLK_CPU 2 1 R862 33/NA 1 R873 33 1 R875 33 1 2 51 48 44 2 5% 1 ITP_CPU 1 R888 2 0402 0/NA HCLK_MCH HCLK_CPU 2 2 0402 2 0402 2 0402 C239 2.2U 0603 +/-10% 2 5% PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 VDDREF VDD48 VDDA VDD3V66_0 VDD3V66_1 R861 33/NA 1 R872 33 1 R874 33 1 1 MULTSEL0* VTT_PWRGD# D C819 0.1U 0402 10% 16V 1 R821 0 VTT_PWRGD# CPUCLKC0 CPUCLKC1 CPUCLKC2 52 49 45 C820 0.1U 0402 10% 16V 2 2 0402 CPUCLKT0 CPUCLKT1 CPUCLKT2 *PD# PCI_STOP# CPU_STOP#* GND 2 1 C262 0.1U 0402 10% 16V 20 13 1 1 R831 10K 0402 5% C FS0 FS1 FS2 4 9 15 20 27 31 36 41 47 +3V 14M_CODEC 14M_ICH 2 +3VCLKPCI 8 14 33 1 46 50 REF DEFSSCLK R859 1 1 R858 33 1608 2 +3VCLKCPU 56 2 120Z/100M 2 1 2 R869 4.7K/NA 0402 5% GND 31 CORE_CLKEN# +3VCLK66 1 37 26 19 32 +3VCLKANA 2 R848 4.7K 0402 5% 2 R894 4.7K 0402 5% 2 R860 4.7K 0402 5% 1 1 1 1 1 2 FS0 FS1 FS2 2 +3V R853 4.7K/NA 0402 5% 54 55 40 0402 CLK_PD# 1 R830 2 8.2K/NA 25 CLK_PCI_STOP# 34 1 R882 2 8.2K/NA CLK_CPU_STOP#53 0402 2 8.2K/NA 1 R886 0402 R863 8.2K 0402 43 1 2 +3V VTT_PWRGD# 28 5% GND R864 4.7K/NA 0402 5% SDATA SCLK 1 1 FS0 FS1 FS2 +3V 35 3V66_1/VCH_CLK 29 30 6,14 SMBDATA 6,14 SMBCLK +3VCLKCPU L43 GND 1 TXC8X4.5 C794 27P 0402 5% +3V SIO_48M 19 USBCLK_ICH 14 48M_DREFCLK 4 2 0402 50V +/-10% 2 14.318MHZ C825 1 10P/NA 2 0402 5% 2 0402 5% 1 C804 27P 0402 5% GND 10402 5% 10402 5% 10402 5% 2 Reserved UNIT: MHz X2 R895 2 33 R877 2 33 R878 2 33 2 Reserved 3 2 Reserved 1 1 2 1 2 39 38 48MHZ_USB 48MHZ_DOT 1 1 0:0V 1:3.3V X1 2 U712 X703 2 49.9/NA 0402 2 49.9 0402 1% 2 49.9 0402 1% GND 1 Reserved 1 1 1 1 TCLK/2 Reserved R870 R892 R890 2 TCLK/2 Reserved ITP_CPU HCLK_CPU HCLK_MCH 1 TCLK/2 0 2 49.9/NA 0402 2 49.9 0402 1% 2 49.9 0402 1% 1 1 1 2 0 Mid C833 1 10P/NA C830 1 10P/NA 1 1 1 1 Mid Layout note: Place crystal within 500 mils of CLK Gen. 2 Tristate R871 R893 R891 1 33.33 Tristate 2 66.66 Tristate DVDDV 133.33 0 1 1 0 2 1 1 X Mid 2 0402 50V +/-10% 2 0402 50V +/-10% 2 0402 50V +/-10% ITP_CPU# HCLK_CPU# HCLK_MCH# 2 C834 1 10P/NA 2 33.33 1 33.33 66.66 2 66.66 200.00 1 100.00 0 2 1 1 1 0 X 2 X 1 33.33 2 PCI* 1 66.66 2 166.66 1 CPU 0 2 FS0 0 1 FS1 X Mid 1 CLOCK SYNTHERIZER FS2 2 D 2 2 3V66[5:0] 3 1 001 4 2 5 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 11 of 34 5 4 3 2 1 Pannel ID 1 0 1 0 1 1 0 1 0 1 1 0 1 2 4 R370 0/NA 0402 5% G 1 2 3 +5V_H 2 2 C12 0.1U 0402 +80-20% 50V R20 1 0 0402 5% ENAVDD 2 S 1 1 WHEN USE INTEGRATE VGA ADD R22 DEL R20 ENABKL_VGA_C 3 2 R323 GND 2 +3V 2 C14 0.22U 0402 +80-20% 16V NEED USE X7R ? Q11 2N7002 SOT23_FET Q9 SI4835DY SO8 4 1 DTC144TKA/NA 288202240001 2 0402 GND R19 1 10K 0402 5% 1 10K/NA 0402 5% Q4 GND D 2 2 2 120Z/100M 2012 20K/NA 0402 1% ENABKL_VGA 7 R4 R399 MA/11PX1/RA ACES 87213-1100 2 FPVDEN D F1 1 2A FUSE_1206 1 R365 0/NA 0402 5% 10K/NA 0402 5% R16 1M 2 0402 5% 2 5 6 7 8 2 GND1 GND2 1 2 R398 FPVEDEN R22 1 0/NA 0402 5% D S 1 1 R1 L18 +3VS 1 FA2 8 7 6 5 +3V 1 120OHM/100MHZ 273000610025 1 2 3 4 +5V_H 1 1 2 3 4 5 6 7 8 9 10 11 C6 4.7U/NA 0805 +80-20% BATT_R# BATT_G# AC_POWER# BATT_POWER# PANEL TYPE J1 2 2 1 INVERTER C7 GND 0.1U 0402 +80-20% 50V 2 120Z/100M/NA L10 1 2 120Z/100M L9 1 2 1608 1608 120Z/100M GND VDD3S 2 1 C8 0.1U/NA 0402 +80-20% 50V 2012 Inverter 1 ENABKL_VGA_C 1 R5 2 0402 22,23 BATT_R# 22,23 BATT_G# 22,23 AC_POWER# 23 BATT_POWER# 1 1 L8 C340 1000P 0402 +/-20% 50V 2 2 BLADJ 0 LCD_ID2 0 G +5V_H 4,22 BLADJ LCD_ID1 0 D C339 0.01U 0402 +80-20% 50V L17 1 2 2012 120Z/100M DVMAIN D LCD_ID0 S 1 Display (CRT / LCD) 1 5% C11 1U 0402 +80-20% 10V L15 1 2 120Z/100M 2012 0 GND R383 H8_ENABKL 22 H8_ENABKL WHEN USE INTEGRATE VGA ADD R384 DEL R386 ENABKL 2 2 BAT54 5% 10K 0402 5% D16 1 3 1 2 1 22 H8_LIDSW# D15 3 4,13,17,25,31 PWROK R2 470K/NA 0402 R3 5% 1 1 7,14,24 PANEL_ID3 When inverter use +3V ADD R323 and DEL Q4,R398,R399,R4 4 TXCLK+ 4 TXCLK- 2 4 TXOUT3+ 4 TXOUT3- ESD0805A/NA 4 TXOUT2+ 4 TXOUT2- SW1 2 1K 0402 1 0/NA 0402 5% H8_LIDSW# BAT54 R372 2 2 +3V 10K 0402 5% t t n e e r c m e u S c c Do a iT ial M t n e id f n o C R373 470K 0402 5% R379 1 1 0 Cover Switch D1 1 R386 1 0402 +3V 2 7 +3VS R380 2 4 ENABKL_NB 1 ENABKL_VGA 3 1 C 0/NA 2 5% 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 When inverter use +5V ADD Q4,R398,R399,R4 and DEL R323 2 0 0402 5% +3V D2 R384 1 0402 1 J2 1 2 3 4 5% To SB PANEL_ID2 7,14,24 PANEL_ID1 7,14,24 PANEL_ID0 7,14,24 TXOUT1+ TXOUT1- 4 4 TXOUT0+ TXOUT0- 4 4 C GND1 GND2 30V/0.1A DT006-P11AA-A C385 0.1U 0402 +80-20% 50V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 MA/15PX2/ST ACES 88107-300X GND GND BAT54 GND Check Power Plane is 3VS or 5VS 2 D702 1 2N7002 D 2 L12 R703 3 4 2N7002 D 2 4.7K 2 5% 4.7K 2 5% +5V_H R785 S 1 0 2 0402 R138 S 1 0 2 0402 Q5 GND 8 1K 5% 2 J702 L7 CHAGND 2N7002 D 2 120Z/100M 1608 1 2N7002 D R136 S 4 3 2 1 CON_VSYNC CON_HSYNC CON_DDDA CON_BLUE CON_GREEN CHAGND 1 0 2 0402 R137 S 1 0 2 0402 1 1 1 1 1 0 2 0402 L58 CRT_GREEN R135 1 0 2 0402 2 220Z/100M 2 220Z/100M 2 220Z/100M 2 L74 1608 120Z/100M CRT_RED R783 1 0 2 0402 L59 L60 4 SMS05C/NA SSOT6 B Q2 3 CON_BLUE 855_CRT_VSYNC 4 ATI_CRT_VSYNC 7 2 ATI_CRT_HSYNC 7 855_CRT_HSYNC 4 CHAGND Q1 1 SLVU2.8/NA SOT23N 3 CON_GREEN 2 SLVU2.8/NA SOT23N CHAGND Q3 1 855_CRT_BLUE 4 ATI_CRT_BLUE 7 3 CON_RED 2 SLVU2.8/NA SOT23N ATI_CRT_GREEN 7 855_CRT_GREEN 4 CHAGND ATI_CRT_RED 7 855_CRT_RED 4 4 3 2 1 CON_RED R139 5 1 WHEN USE INTEGRATE VGA DEL R785 R138 R136 R137 R139 R135 R783 CRT_BLUE 6 2 CHAGND Q7 47PX4 1206 CON_DDCK 15 5 10 14 4 9 13 3 8 12 2 7 11 1 6 2 120Z/100M 1608 Q8 CP2 17 13,24 L11 1 1 3 ATI_CRT_DDDA 7 855_CRT_DDDA 4 G CRT_IN# 5 6 7 8 0402 5% 2 BEAD_600Z/100M 0603D C10 100P 0402 +/-10% 50V R8 0/NA 2 2 1 L13 1 1 R9 1 0402 CON_DDDA +5V_H ESD41A/NA D S 7 CHAGND G CHAGND 6 D S B 5 0 0805 U702 855_CRT_DDCK 4 ATI_CRT_DDCK 7 Q6 D S 1 2 120Z/100M 1608 1 G GND R6 1 0402 R10 1 0402 D S 0 0805 CHAGND G CRT R1 1 +5V_H 16 5 6 7 8 RP1 75*4/NA 1206 D701 3 5 CHAGND 2 CP1 47PX4/NA 1206 4 6 C1 47P C2 47P C4 47P 1 1 1 2 0402 25V +/-10% 2 0402 25V +/-10% 2 0402 25V +/-10% A 5 6 7 8 1 15P/3R-FM 7312S-15G2T-DC SUYIN 4 3 2 1 A GND 7 8 CHAGND GND ESD41A/NA CHAGND Title 8050D MOTHER B/D CLOSE TO CRT CONNECTOR Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 12 of 34 3 2 SLP_S5# 1 22P 0402 2 1 1 1 2 1 2 C225 0.1U 0402 10% 16V 2 C228 10U 0805 6.3V 10% R252 1K 0402 5% C298 1U 0402 10V GND SUSC# 22,26,27 D11 V5REF C207 0.1U 0402 10% 16V VDD3S R164 1K/NA 0402 5% D10 BAT54 C210 1U 0402 10V V5REF_SUS C221 0.1U 0402 10% 16V GND GND ICH_VGATE 13 74AHC08_V TSSOP14 22 0402 5% 10U 6.3V 0805 10% C277 0.1U 0402 10% 16V C245 1U 0402 10V C206 1U 0402 10V C213 0.1U 0402 10% 16V C306 0.1U 0402 10% 16V 1 1 C275 0.1U 0402 10% 16V 1 C305 0.1U 0402 10% 16V 1 C261 0.1U 0402 10% 16V C307 0.1U 0402 10% 16V 2 2 2 1 VDD3S 2 11 7 R397 1K 0402 5% BAT54 1 C233 R306 12 2 Spacing other signal 25 mils U9D C308 0.1U 0402 10% 16V GND A GND 2 +VHI_ICH 1 1 VDD1.5 R932 10K 0402 5% RTC_X2 2 +/-10% 22 A20GATE R931 1 A20_GATE 2 0 1 0805 C229 10U 6.3V 0805 10% GND C208 0.1U 0402 10% 16V C260 1U 0402 10V 1 +LAN_1.5V 2 R234 0 0805C_DFS 2 R245 0/NA 0805C C824 0.1U 0402 10% 16V 2 +1.5V +3V 2 0/NA 1 1 GND R311 1 2 RTC_X1 R938 X704 10M 0402 32.768KHZ 5% GND C269 0.1U 0402 10% 16V Title 8050D MOTHER B/D GND Size C Date: 5 VDD5 +3V GND 31 VRMPWRGD VDD5S 1 +3V 3 2 2 R233 0/NA 0805C 1 0805 +3VS +5V 5% +LAN_3V 2 R223 0 0805C_DFS B GND INTRUDER# 2 0402 BAW56 288100056017 1 4 +/-10% 3 2 C861 1 50V 22P 0402 2 1 50V GND 1 R287 10K C ICH4-M BGA360_25_36 +VCC_RTC R926 4.7K 0402 5% D704 SLP_S4# VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 2 C315 0.1U 0402 10% 16V R296 10M 0402 5% C855 1 14 14 14 14 24 14,20 11 +3V +3V PWROK GND SMLINK0 SMLINK1 SMB_DATA SMB_CLK SMBALERT# SBSPKR 14M_ICH 1 RTC_RST# RTC_VBIAS 1.25MM/ST/MA-2 ACES 85205-0200 A AC3 AB1 AB4 AC4 AA5 H23 J23 2 10K/NA SB_SUSST# 5% LDRQ1# 2 10K/NA 5% R939 1 0402 R270 1 0402 CPU_THRMTRIP# 14 SB_THRM# 22 VCCPLL D1 C23 C21 C19 C17 C15 C6 B22 B20 B18 B16 B12 B9 A22 A20 A18 A16 A4 A1 +3V 1 180K 0402 5% C841 0.047U 0402 10% 25V GND 2 C219 1U 0402 10V 1 1 2 DPRSLPVR DPSLP# SB_SUSST# ICH_VGATE 2 2 J710 SMILINK 0 SMLINK 1 SMBDATA SMBCLK SMBALERT#/GPIO 11 SPKR CLK14 ICH_RI# 16 ICH_PWRBTN# 22 ICH_SYS_RESET# 14 ICH_LAN_RST# 14 ICH_BATLOW# 14 SB_SUSST# 7 1 GND C856 1U 0402 +80-20% 10V 2 GND SUSCLK INTRUDER# RTCRST# PWROK RSMRST# VCCRTC VBIAS RTCX1 RTCX2 SLP_S4# SLP_S5# 1 R288 1 1 GND LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 Y4 Y2 AA2 Y1 AA1 Y3 Y5 AB2 AB3 V19 W20 V1 14 R917 1K 0402 5% 1 C311 4.7U 0805 +80-20% SLP_S3# SLP_S4# SLP_S5# RI# PWRBTN# SYS_RESET# LANRST# BATLOW#/TP[ 0 ] SUS_STAT#/LPCPD VGATE/VRMPWRGD THERMTRIP# THRM# V_CPU_IO V_CPU_IO V_CPU_IO C22 GND LFRAME#/FWH4 LDRQ0# LDRQ1# VDD3S 2 D12 BAV70LT1 288100070006 1 1 AME8800AEEV/NA SOT25 2 10U 6.3V 0805 10% SERIRQ 1 1 5 7,24 TP705 2 2 1 3 NC0 17,22,23,25 STP_AGP# ICH4-M BGA360_25_36 +VCC_RTC 4 NC1 2 C289 2.2U/NA 0603 +/-10% VOUT VIN GND0 2 2 1 3 2 1 SUSB# 1 1 U5 VDD5S 14,31 DPRSLPVR 2,4 HDPSLP# RTC_VBIAS RTC_X1 RTC_X2 R274 1 0 2 5% V20 0402G_DFS U23 16,17,19,24 21,24 24 24 C853 0.1U 0402 10% 16V V5REF_SUS P14 U18 AA23 +1.5V 2 1 VDD3S 24 PCLKRUN# SPK_OFF GPIO27 GPIO28 C304 0.1U 0402 10% 16V C274 V5REF1 V5REF2 1 4,12,17,25,31 PWROK 22,25 RSMRST# +VCC_RTC AA4 W6 W7 AB6 AA6 AB5 Y6 AC7 AC6 GPIO27 GPIO28 CPUPERF# E7 V6 E15 1 4 SUSCLK T2 R4 T4 U2 C3_STAT# VCCLAN1_5/VCCSUS1_5 VCCLAN1_5/VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 VCCSUS1_5 3 SUSCLK INTRUDER# RTC_RST# B R276 0 0805_DFS LAD0 LAD1 LAD2 LAD3 STOP_PCI# 11 SUSA# 11 STOP_CPU# 3,11,31 0402 1 2 R896 0 SUSA# V5REF V5REF_SUS +VCCP 1 LAD[0..3] 19,22,23 LAD[0..3] 22,24 22,24 2 MINIPCI_PME# 19 Y21 W18 W19 T3 Y20 J21 AC2 V2 W1 W4 SCI# WAKE_UP# 2 0 1 2 R915 0402G_DFS 5% 0/NA 2 R908 1 0402 STP_PCI/GPIO 18 SLP_S1#/GPIO 19 STP_CPU#/GPIO 20 C3_STAT#/GPIO 21 CPUPERF#/GPIO 22 SSMUXSEL/GPIO 23 CLKRUN#/GPIO 24 GPIO 25 GPIO 27 GPIO 28 V5 W3 GND 4,7,24 1 18 T5 U3 U4 GPIO 12 GPIO 13 AGPBUSY# 22,24 22,24 2 PCI_PME# LDRQ1# STPCLK# A20M# CPUSLP# CPUPWRGD INTR NMI SMI# IGNNE# A20GATE RCIN# FERR# INIT# KBD_US/JP# EXTSMI# 10U 6.3V 0805 10% C224 0.1U 0402 16V 1 19,22,23 LFRAME# 19 LRDQ0# AGPBUSY#/GPIO 6 GPIO 7 GPIO 8 0402 C212 0.1U 0402 16V 2 HSTPCLK# HSTPCLK# HA20M# HSLP# HPWRGD HINTR HNMI HSMI# HIGNNE# APICCLK APICD_0 APICD_1 2 R880 0 1 1 2 10K 5% R2 R3 V4 1 R222 1 0402 J19 H19 K20 2 0 C211 0.1U 0402 16V 2 C223 0.1U 0402 16V 1 2 Q704 2 V23 AB23 U21 1 R934 2 0 Y23 AB22 V21 W23 W21 A20_GATE Y22 U22 22 HRCIN# AA21 14 CPU_FERR# 0 1 2 V22 2,23 HINIT# R928 0402G_DFS 5% J22 14,17,19,22 SERIRQ R1 PCI_PME# 1 R240 1 F6 F7 E12 R6 T6 U6 G18 E13 F14 E20 11 1 TV_PCIRST# U715D DTC144TKA SOT23AN_1 288202240001 SB_PME# 3 2 +LAN_1.5V 1 1 2 JP_NET10 2 +3V +3V 1 R867 0/NA 0805C_DFS VDD1.5 2 74AHC08_V TSSOP14 GND GND 2 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 7 CARDBUS_PME# 17 2 1 FWH_PCIRST# 23 1 +1.5V 2 JL9 1 2 JP_NET10 +VHI_ICH 19 1 MINIPCI_PCIRST# VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCCHI0 VCCHI1 VCCHI2 VCCHI3 D 2 JL8 1 2 JP_NET10 U9C 9 JL10 2 2 2 2 2 2 2 2 K10 K12 K18 K22 P10 T18 V14 U19 L23 M14 P18 T22 1 CARD_PCIRST# 17 2 1 2 JP_NET10 1 16,17,18,19 2 PCI_C/BE#[0..3] VCCLAN3_3/VCCSUS3_3 VCCLAN3_3/VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 1 PCI_C/BE#3 PCI_C/BE#2 PCI_C/BE#1 PCI_C/BE#0 GND JL7 8 2 8.2K/NA 1 +1.5V +3V C285 0402 1 R904 2 1 LAN_PCIRST# 16 C244 0.1U 0402 16V GND 0/NA 2 R921 0402 C3_STAT# E9 F9 E11 F10 V9 V8 V7 F15 F16 F17 F18 K14 D22 AC23 AC18 AC14 AC10 AC5 AC1 AB20 AB7 AA22 AA16 AA12 AA9 AA3 Y19 Y7 W22 W8 W5 V17 V15 V3 U20 T23 T19 T1 R21 R18 R5 P22 P20 P13 P11 P3 N23 N21 N19 N14 N13 N12 N11 N10 N5 M13 M12 M11 M1 M22 L21 L14 L13 L12 L11 L10 K23 M20 K19 K13 K11 K3 J6 H1 G21 G19 G6 G3 F8 E22 E21 E19 E18 E17 E16 E14 E10 D23 D21 D19 D17 D15 D12 D8 D4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 2 JL6 1 2 JP_NET10 74AHC08_V TSSOP14 C253 0.1U 0402 16V 2 5 KBC_PCIRST# 22 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 +LAN_3V VDD3S 2 PCIRST# C SB_CARD_PME# 1 C246 0.1U 0402 16V MCH_PCIRST# 4 JL5 1 2 JP_NET10 6 10 CARDBUS_PME# 1 1 7 4 ICH4-M BGA360_25_36 PCI_PME# R920 1 0 2 5% 0402G_DFS C278 0.1U 0402 16V 1 SB_PME# PCIRST# 11 PCICLK_ICH JL4 1 2 JP_NET10 C294 0.1U 0402 16V U9B PCI_C/BE#[0..3] N4 M4 K4 J2 C/BE#3 C/BE#2 C/BE#1 C/BE#0 10U 6.3V 0805 10% 2 PCI_LOCK# FRAME# IRDY# TRDY# DEVSEL# STOP# PAR PERR# PLOCK# SERR# PME# PCIRST# PCICLK C292 GND +3V 1 F1 L5 F2 M3 F3 G1 L4 M2 K5 W2 U5 P5 +1.5V 74AHC08_V TSSOP14 2 PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_DEVSEL# PCI_STOP# PCI_PAR PCI_PERR# PCI_LOCK# PCI_SERR# SB_PME# 15,25 1 PCI_GNT0# TP34 1 R409 1 2 0/NA GNT# 4 GNT# 3 GNT# 2 GNT# 1 GNT# 0 GNTB#/GNT5#/GPIO 17 GNTA#/GPIO 16 PCIRST#0 2 D6 B7 A7 E6 C1 C5 E8 REQB#/REQ5#/GPIO 1 REQA#/GPIO 0 1 2 JP_NET10 2 PCI_GNT4# PCI_GNT4# PCI_GNT3# PCI_GNT2# PCI_GNT1# PCI_GNT0# B/CB# 16,17,18,19,24 16,17,18,19,24 16,17,18,19,24 16,17,18,19,24 16,17,18,19,24 16,17,18,19 16,17,18,19,24 24 16,17,19,24 14,16 A6 B5 3 2 2 3,24 SB_CARD_PME# CRT_IN# REQ# 4 REQ# 3 REQ# 2 REQ# 1 REQ# 0 U715A A5 B2 H6 J1 K6 M10 P6 U1 P12 V10 V16 V18 AC8 AC17 H18 J18 JL3 2 24 SB_CARD_PME# 12,24 CRT_IN# 24 16,24 19,24 18,24 17,24 PCI_REQ0# B6 C7 B3 A2 B1 1 2 PCI_REQ4# PCI_REQ4# PCI_REQ3# PCI_REQ2# PCI_REQ1# PCI_REQ0# PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 P4 D2 R1 D3 P2 E1 P1 E2 M5 E4 N3 E3 N2 E5 N1 F4 F5 L3 H2 L2 G4 L1 G2 K2 J5 H4 J4 G5 K1 H3 J3 H5 AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 +3V 1 24 16,24 19,24 18,24 17,24 PIRQA# PIRQB# PIRQC# PIRQD# PIRQE#/GPI0 2 PIRQF#/GPIO 3 PIRQG#/GPIO 4 PIRQH#/GPIO 5 14 D 5% D5 5% C2 5% B4 5% A3 5% C8 5% D7 5% C3 C4 7 U9A 16,17,18,19 7 PCI_INTA# R195 1 0 2 PCI_INTB# R854 10402G_DFS 0 2 PCI_INTC# R805 10402G_DFS 0 2 PCI_INTD# R823 10402G_DFS 0 2 PCI_INTE# R192 10402G_DFS 0 2 PCI_INTF# R199 10402G_DFS 0 2 PCI_INTG# R844 10402G_DFS 0 2 ICH_GPI50402G_DFS PCI_INTA# PCI_INTB# PCI_INTC# PCI_INTD# PCI_INTE# PCI_INTF# PCI_INTG# 24 ICH_GPI5 PCI_AD[0..31] 1394_PCIRST# 18 14 7,24 17,24 17,24 19,24 16,24 17,19,24 18,24 PCI_AD[0..31] ATI_PCIRST# JL2 1 2 JP_NET10 2 U715B +3V 1 1 SOUTHBRIDGE-ICH4-M(1/2) 2 JL1 1 2 JP_NET10 2 4 14 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 13 of 34 5 4 3 2 1 SOUTHBRIDGE-ICH4-M(2/2) +VCCP U715E CLK48 B23 ACSYNC ACSDOUT ACBITCLK ACRST# ACSDIN0 ACSDIN1 ACSDIN2 USBRBIAS# A23 1 USBRBIAS 1 2 R261 1 0 2 5% 0402G_DFS 5% VDD3S GND R812 0 0402 5% 1 2 1 D 20 20 20 20 20 ACSYNC 20 C787 10P/NA 0402 +/-10% 50V 2 Q20 288203904022 MMBT3904L R266 B 1 VDD3S CPU_THRMTRIP# 13 +VCCP R315 2.2K 0402 5% 2 13 1K 5% 0402 2 47K 5% 2 47K 5% SMLINK1 R933 1 0402 R310 1 0402 2 10K 5% 2 10K 5% ICH_BATLOW# SMLINK0 ICH_SYS_RESET# SMLINK1 13 SMLINK0 13 ICH_BATLOW# 13 ICH_SYS_RESET# 13 +3V R318 2.2K 0402 5% D SMB_DATA R316 10K 0402 5% S R317 10K 0402 5% SMBDATA 6,11 SMBCLK 6,11 1Q21 2 2N7002 R313 0/NA 0402 5% R290 0/NA 0402 5% t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 13 D SMB_CLK S 1 Q22 2 2N7002 R314 0/NA 0402 5% THERM_ERR# 22,25 GND R929 1 0402 R940 1 0402 R273 1 56 5% 0402 EE_DOUT ACSDOUT ACBITCLK ACRST# ACSDIN0 ACSDIN1 2 10K 5% 1 R269 56 0402 5% 11 2 CPU_THRMTRIP_OUT# R810 10 0402 5% GND 0402 +VCCP TP704 2 10K 5% C9 D9 B8 C13 D13 A13 B13 C R308 10K 1 66M_ICH R907 1 0402 13,16 SB_PME# 2 GND 4 4 HI_COMP HI_VSWING HI_VREF ICH4-M BGA360_25_36 2 5% 10K/NA 1 GND HUB_STB# HUB_STB 1 R811 1 0402 ICH_LAN_RST# 13 ICH_LAN_RST# 56 5% 0402 2 56 5% VDD3S 2 2 R838 18.2 0402 1% 271061180101 D11 D10 C12 A8 13 2 EE_DIN EE_CS EE_SHCLK EE_DOUT A10 A9 A11 B10 C10 A12 B11 C11 CPU_FERR# 2 F19 11 USBCLK_ICH LANRXD0 LANRXD1 LANRXD2 LANTXD0 LANTXD1 LANTXD2 LANRSTSYNC LANCLK 2 G GPIO43 GPIO 32 GPIO 33 GPIO 34 GPIO 35 GPIO 36 GPIO 37 GPIO 38 GPIO 39 GPIO 40 GPIO 41 GPIO 42 GPIO 43 R307 1 0402 R937 1 HFERR# D S MB_ID0 MB_ID1 J20 G22 F20 G20 F21 H20 F23 H22 G23 H21 F22 E23 2 2 8.2K 5% G RP26 8 0*4/NA 7 1206 6 5 MB_ID2 VDD3S R392 1 0402 13,17,19,22 SERIRQ R936 56 0402 5% N20 P21 R23 R22 M23 T21 +3V 4 D S 1 2 3 4 HI_COMP HIVSWING HIREF CLK66 HUB_HI[0..10] 1 WIRELESS_PD# PANEL_ID0 PANEL_ID1 PANEL_ID2 PANEL_ID3 MB_ID2 IDERST# MINIPCI_ACT# MB_ID0 MB_ID1 GPIO42 GPIO43 HI_STB#/HI_STBF HI_STB/HI_STBS HUB_HI0 HUB_HI1 HUB_HI2 HUB_HI3 HUB_HI4 HUB_HI5 HUB_HI6 HUB_HI7 HUB_HI8 HUB_HI9 HUB_HI10 R856 1 0402 2 19,24 7,12,24 7,12,24 7,12,24 7,12,24 24 15,24 19,24 24 24 24 24 OC#0 OC#1 OC#2 OC#3 OC#4 OC#5 L19 L20 M19 M21 P19 R19 T20 R20 P23 L22 N22 K21 1 USBOC4# USBOC5# B15 C14 A15 B14 A14 D14 HI 0 HI 1 HI 2 HI 3 HI 4 HI 5 HI 6 HI 7 HI 8 HI 9 HI 10 HI 11 2 USBOC1# WHEN USE INTEGRATE VGA ADD RP26 USBP_0 USBP_0# USBP_1 USBP_1# USBP_2 USBP_2# USBP_3 USBP_3# USBP_4 USBP_4# USBP_5 USBP_5# 1 USB_OC1# USBOC0# C20 D20 A21 B21 C18 D18 A19 B19 C16 D16 A17 B17 2 15 0402G_DFS 0402G_DFS 0402G_DFS 0402G_DFS 0402G_DFS 0402G_DFS C USB_OC0# 5% 5% 5% 5% 5% 5% 1 1 1 1 1 1 E 15 2 2 2 2 2 2 1 D 0/NA 0/NA 0/NA 0/NA 0/NA 0/NA TP23 TP29 TP33 TP37 TP24 TP28 2 1 1 1 1 1 1 1 R185 R190 R173 R178 R196 R205 USBP0+ USBP0USBP1+ USBP1USBP2+ USBP2- 2 15 15 15 15 15 15 HUB_HI[0..10] GND C 1 1 GPIO CHARACTERISTIC LIST NAME R809 10K 0402 5% POWER PLANE CURRENT DEFINE B5 GPI[0] I MAIN POWER WELL CRT_IN# A6 GPI[1] TYPE I MAIN POWER WELL SB_CARD_PME# C8 GPI[2] I MAIN POWER WELL PCI_INTE# D7 GPI[3] I MAIN POWER WELL PCI_INTF# C3 GPI[4] I MAIN POWER WELL PCI_INTG# C4 GPI[5] I MAIN POWER WELL ICH_GPI5 R2 GPI[6] I MAIN POWER WELL AGPBUSY# R3 GPI[7] I MAIN POWER WELL KBD_US/JP# V4 GPI[8] I RESUME POWER WELL EXTSMI# AA5 GPI[11] I RESUME POWER WELL SMBALERT#(Pull high only) V5 GPI[12] I RESUME POWER WELL SCI# W3 GPI[13] I RESUME POWER WELL WAKE_UP# E8 GPO[16] O MAIN POWER WELL C5 GPO[17] O MAIN POWER WELL Y21 GPO[18] O MAIN POWER WELL STOP_PCI# W18 GPO[19] O MAIN POWER WELL SUSA# W19 GPO[20] O MAIN POWER WELL STOP_CPU# T3 O MAIN POWER WELL C3_STAT# Y20 GPO[22] OD MAIN POWER WELL CPUPERF# J21 GPO[23] O MAIN POWER WELL AC2 GPIO[24] I/O RESUME POWER WELL PCLKRUN# V2 GPIO[25] I/O RESUME POWER WELL SPK_OFF W1 GPIO[27] I/O RESUME POWER WELL W4 GPIO[28] I/O RESUME POWER WELL J20 GPIO[32] I/O MAIN POWER WELL WIRELESS_PD# G22 GPIO[33] I/O MAIN POWER WELL PANEL_ID0 F20 GPIO[34] I/O MAIN POWER WELL PANEL_ID1 G20 GPIO[35] I/O MAIN POWER WELL PANEL_ID2 F21 GPIO[36] I/O MAIN POWER WELL PANEL_ID3 2 2 R197 10K 0402 5% USBOC4# USBOC5# +1.5V GND B 15 U715C PD_D[0..15] PD_D[0..15] PD_D15 PD_D14 PD_D13 PD_D12 PD_D11 PD_D10 PD_D9 PD_D8 PD_D7 PD_D6 PD_D5 PD_D4 PD_D3 PD_D2 PD_D1 PD_D0 15 15 15 15 15 PDIOW# PDDACK# PDDREQ PDIOR# PIORDY 15 15 15 PDA0 PDA1 PDA2 15 15 PDCS1# PDCS3# Y11 W11 W10 AB10 W9 AC9 Y9 AB9 AA8 Y8 AB8 AA7 AA10 Y10 AC11 AB11 W12 Y12 AA11 AC12 AB12 AA13 AB13 W13 Y13 AB14 PDD 15 PDD 14 PDD 13 PDD 12 PDD 11 PDD 10 PDD 9 PDD 8 PDD 7 PDD 6 PDD 5 PDD 4 PDD 3 PDD 2 PDD 1 PDD 0 PDIOW# PDDACK# PDDREQ PDIOR# PIORDY PDA0 PDA1 PDA2 PDCS1# PDCS3# SDIOW# SDDACK# SDDREQ SDIOR# SIORDY SDA2 SDA1 SDA0 SDCS1# SDCS3# IRQ14 IRQ15 A Y17 AA17 Y16 AB16 Y15 AA15 AC15 Y14 AA14 W14 AB15 W15 AC16 W16 AB17 W17 SD_D15 SD_D14 SD_D13 SD_D12 SD_D11 SD_D10 SD_D9 SD_D8 SD_D7 SD_D6 SD_D5 SD_D4 SD_D3 SD_D2 SD_D1 SD_D0 AA18 AB19 AB18 Y18 AC19 2 1 R912 150 0402 1% EE_DOUT 1 R813 4.7K/NA 0402 2 5% 2 0402 5% X GND X +VHI_ICH R275 1 4.7K/NA 1 15 R286 4.7K 0402 2 5% 2 0402 GPO[21] B 5% GND X +3V 13,20 15 15 15 15 15 SDA2 SDA1 SDA0 15 15 15 AB21 AC22 SDCS1# SDCS3# 15 15 AC13 AA19 IRQ14 IRQ15 15 15 ICH4-M BGA360_25_36 C839 0.1U 0402 10% 16V 13,31 DPRSLPVR SD_D[0..15] SDIOW# SDDACK# SDDREQ SDIOR# SIORDY AC21 AC20 AA20 R1113 ACSDOUT 1 4.7K/NA GND SD_D[0..15] SDD 15 SDD 14 SDD 13 SDD 12 SDD 11 SDD 10 SDD 9 SDD 8 SDD 7 SDD 6 SDD 5 SDD 4 SDD 3 SDD 2 SDD 1 SDD 0 C838 0.01U 0402 10% 50V 2 1 R884 150 0402 1% 2 C828 0.1U 0402 10% 16V 2 1 C829 0.01U 0402 10% 50V 2 1 2 48.7 +3V 1 1 2 HI_VSWING 1 1 HI_VREF 2 R900 HI_COMP R911 130 0603 1% R883 487 1% +1.5V STRAPPING 1 2 +1.5V SBSPKR R852 1 4.7K/NA 0402 2 5% STRAPPING AT RISING EDGE OF PWROK X X STRAPPING PINS FUNCTIONS H20 GPIO[37] I/O MAIN POWER WELL MB_ID2 ACSDOUT SAFE MODE F23 GPIO[38] I/O MAIN POWER WELL IDERST# EEDOUT RESERVED H22 GPIO[39] I/O MAIN POWER WELL MINIPCI_ACT# GNTA# OP-BLOCK SWAP OVERRIDE G23 GPIO[40] I/O MAIN POWER WELL MB_ID0 DPRSLPVR HUB INTERFACE TERMINATION SCHEME H21 GPIO[41] I/O MAIN POWER WELL MB_ID1 HUB_ICH_COMP HUB INTERFACE SCHEME(1.0 OR 1.5) F22 GPIO[42] I/O MAIN POWER WELL X SBSPKR NO REBOOT E23 GPIO[43] I/O MAIN POWER WELL X A Title 8050D MOTHER B/D Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 14 of 34 5 4 3 2 HDD- PRIMARY IDE CONNECTOR 1 CDROM- SECONDARY IDE CONNECTOR J714 2 3 1 +5V GND +5V_HDD 1 R492 10K 0402 5% R476 10K 0402 5% 2 R1 +3V GND C878 10U 0805C 10V GND 470/NA 0402 5% DTC144TKA 288202240001 GND 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 CDROM_RIGHT 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 CDROM_RIGHT 20 SD_D8 SD_D9 SD_D10 SD_D11 SD_D12 SD_D13 SD_D14 SD_D15 SDDREQ SDIOR# D SDDACK# TP706 1 SDA2 SDCS3# +5V_CDROM R/A-25PX2/0.8 SPEED K22-102-150X GND DTC144TKA 288202240001 14 14 14 14 14 14 14 14 14 14 14 GND SDDREQ SDIOW# SDIOR# SIORDY SDDACK# IRQ15 SDA1 SDA0 SDA2 SDCS1# SDCS3# SDDREQ SDIOW# SDIOR# SIORDY SDDACK# IRQ15 SDA1 SDA0 SDA2 SDCS1# SDCS3# R879 1 5.6K/NA 2 0402 5% +3V +5V_CDROM t t n e e r c m e u S c c Do a iT ial M t n e id f n o C R833 1 4.7K 0402 R834 1 8.2K 0402 2 5% 2 5% +3V C813 0.1U 0402 10% 16V GND C816 0.1U 0402 10% 16V GND +5V L723 1 +3V 1 1 1 GND C877 0.1U 0402 10% 16V 2 +3V 2 1 2 5% 2 5% 2 R1081 1 4.7K 0402 R1074 1 8.2K 0402 C872 0.1U 0402 10% 16V 2 120Z/100M 2012 2 Q37 L733 1 +3V +5V_CDROM 1 GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 C817 120Z/100M 10U 2012 0805C 10V 2 R295 1 5.6K/NA 2 0402 5% CD_LED# Q41 1 3 C PDDREQ PDIOW# PDIOR# PIORDY PDDACK# IRQ14 PDA1 PDA0 PDA2 PDCS1# PDCS3# 23 SDIOW# SIORDY IRQ15 SDA1 SDA0 SDCS1# CD_LED# R836 R1 +5V +5V_HDD PDDREQ PDIOW# PDIOR# PIORDY PDDACK# IRQ14 PDA1 PDA0 PDA2 PDCS1# PDCS3# PCIRST#0 PCIRST#0 2 RSTDRV1# 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 1 GND 2 Q705 DTC144TKA/NA 470 5% 0402 PDA2 PDCS3# 1 R1 2 IDERST# 13,25 14 14 14 14 14 14 14 14 14 14 14 SD_D0 SD_D1 SD_D2 SD_D3 SD_D4 SD_D5 SD_D6 SD_D7 SD_D8 SD_D9 SD_D10 SD_D11 SD_D12 SD_D13 SD_D14 SD_D15 0 0402 5% 1 1 14,24 HDR/FM/22PX2/2MM SPEED ACE-1A2-0216 GND GND SD_D[0..15] 2 +5V_HDD 14 SD_D[0..15] R927 110K/NA 0402 GND R909 2 J708 CDROM_LEFT CDROM_COM M RSTDRV2# SD_D7 2 5% SD_D6 SD_D5 SD_D4 SD_D3 SD_D2 SD_D1 SD_D0 20 CDROM_LEFT 20 CDROM_COM M R919 10K/NA 0402 Q703 5% DTC144TKA/NA R1 2 R1085 1 2 5% RSTDRV2# 3 HDD_LED# 1 R901 2 10K/NA 0402 5% 1 23 PDDREQ PDIOW# PDIOR# PIORDY PDDACK# IRQ14 PDA1 PDA0 PDCS1# HDD_LED# PD_D8 PD_D9 PD_D10 PD_D11 PD_D12 PD_D13 PD_D14 PD_D15 2 GND R922 1 10K 0402 GND 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 2 D PD_D0 PD_D1 PD_D2 PD_D3 PD_D4 PD_D5 PD_D6 PD_D7 PD_D8 PD_D9 PD_D10 PD_D11 PD_D12 PD_D13 PD_D14 PD_D15 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 3 PD_D[0..15] PD_D[0..15] 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 1 14 RSTDRV1# 2 PD_D7 PD_D6 PD_D5 10K/NA PD_D4 0402 PD_D3 5% PD_D2 PD_D1 PD_D0 +5V GND2 GND1 GND2 GND1 R436 1 GND C USB CONNECOTR +5VS 2 2 JO4 JO5 JO6 2 2 JO3 JO7 JO8 14 USBP2- A1 A2 A3 A4 GND1 GND2 1 2 2 L23 0603D GND1 GND2 1 2 3 4 GND1 GND2 BEAD/NA USB/4PX2/DIP SUYIN 2522A-08G1T-K VCC PP+ GND GND1 GND2 USB/4PX1 SUYIN 2545A-04GXT 2 A1 A2 A3 A4 J706 +VCC_USB_2 90Z/100M CHOKE_ACM2012 2 BEAD/NA 2 +VCC_USB_1 2 B BEAD/NA L22 1 2 3 4 4 1 2 3 4 1 +VCC_USB_0 2 4 R708 47K 0402 5% 2 3 2 1 C711 1000P 0402 +/-20% 50V 2 J701 L2 L1 0603D 1 1 2 1 2 2 1 GND_USB1 USB_OC1# 3 14 USBP2+ 90Z/100M CHOKE_ACM2012 C713 + 150U 7343 6.3V C31 0.1U 0402 +80-20% 50V 2 GND 14 USB_OC1# C3 0.1U 0402 +80-20% 50V GND_USB R706 33K 0402 5% RT9701-CBL SOT25 2 2 GND C709 1U 0402 +80-20% 10V +VCC_USB_2 2 120Z/100M 2012 1 GND 1 1 VOUT1 1 GND BEAD/NA 1 14 USBP0- 5 L21 0603D L3 0603D 14 USBP0+ VIN1 1 VOUT0 2 2 GND B VIN0 2 R702 47K 0402 5% 4 GND_USB +VCC_USB_1 2 120Z/100M 2012 1 1 2 C704 1000P 0402 +/-20% 50V L701 1 USB_OC0# 14 USB_OC0# 2 C702 + 150U/NA 7343 6.3V 3 C5 0.1U 0402 +80-20% 50V 1 2 GND 1 2 GND C701 + 150U 7343 6.3V 2 R701 33K 0402 5% RT9701-CBL SOT25 2 2 C703 1U 0402 +80-20% 10V 1 VOUT1 +VCC_USB_0 2 120Z/100M 2012 1 5 L708 U705 1 1 GND VIN1 1 VOUT0 1 4 VIN0 1 L702 U701 3 2 +5VS GND_USB1 JO16 JO15 JO14 L6 0603D BEAD/NA 1 1 1 1 1 1 3 2 1 2 1 1 GND_USB 1 14 USBP1+ JO13 4 1 L5 90Z/100M CHOKE_ACM2012 1 JO9 GND_USB GND_USB 1 2 A 1 14 USBP1- SHORT-SMT4 JO702 2 2 2 SHORT-SMT4 JO17 1 2 GND_USB1 A SHORT-SMT4 1 L4 0603D GND GND_USB1 SHORT-SMT4 BEAD/NA GND GND_USB Title 8050D MOTHER B/D Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 15 of 34 5 4 +2.5VS_DDR 3 2 120Z/100M 2012 1 1 1 2 1 2 XTAL1 XTAL2 RSET 125 8 CTRL18 127 1 1 MDI1- 0603 1 PMDI1- 2 R297 0/NA L48 MDI2- 0603 1 2 5.6K 0402 117 115 114 113 NC_15 AVDD25 NC_16 NC_17 11 12 72 74 DVDD 2 C889 GND 120Z/100M 2012 C845 0.01U/NA 2 0402 1 PMDI0+ 12 13 PJTX+ PMDI0- 11 14 PJTX1- V_DAC 10 15 MCT4 PMDI1+ 9 16 PJRX+ PMDI1- 8 17 PJRX- C835 0.1U 2 0402 1 V_DAC 7 18 MCT3 PMDI2+ 6 19 MDO2+ GND ADD if use RTL8110S C849 0.01U/NA 2 0402 GND 1 PMDI2- 5 20 V_DAC 4 21 MCT2 PMDI3+ 3 22 MDO3+ R944 1 0/NA 0805 V_DAC PMDI3- 2 23 MDO3- V_DAC 1 24 MCT1 GND Add thease caps when use RTL8110S, and C879 change to 0.01U 1 0/NA 0805 2 +3V 1 A A A A D710 3 LAN_WAKE 2 R1 1 R1109 510/NA 0402 1% 1K R1107 510/NA 0402 1% 1K R1102 510/NA 0402 1% 1K 1K R1097 510/NA 0402 1% 2 0 5% 0402 Q709 R1114 1 2 DTC144TKA 0/NA 288202240001 0402 5% 2 R1111 CL-190G/NA CL-190G/NACL-190G/NA ICH_RI# 13 KBC_RI# 22 PMDI0V_DAC PMDI0+ 7 6 8 PMDI1V_DAC PMDI1+ 1 3 2 4 5 TD+ TDC TD- TX+ TXC TX- RD+ RDC RD- RX+ RXC RX- NC0 NC1 NC2 NC3 16 14 15 MCT3 GND 1 1 2 2 MDO2MDO2+ PJRX+ PJTX1PJTX+ 20 20 MODEMP MODEMN MODEMP MODEMN MDO2- 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 8 7 6 5 4 3 2 1 RJ45 B A2 RJ11 A1 GND1 GND2 RJ11-2P/RJ45-8P C10037-102XX JO717 JO716 JO715 JO714 1 GND_45 GND_45 GND_45 1 GND_45 1 2 L728 0 0603 8 RP27MDO2+ 7 0*4 MDO26 1206MDO3+ MDO35 1 2 3 4 2 L719 0 0603 GND GND_45 A R271 1 2 R277 1 2 MCT4 R152 1 2 MCT3 R930 1 2 MCT2 R262 1 2 MCT1 R254 1 2 75 0402 75 0402 75 0402 75 0402 75/NA 0402 75/NA 0402 C327 1000P 2KV 1808 10% Title 8050D MOTHER B/D Size C Date: 4 A2 A1 GND1 GND2 GND GND_45 5 8 7 6 5 4 3 2 1 PJTX1PJTXPJTX+ PJRXPJRX+ 12 13 J709 JO721 MDO3MDO3+ H5007/NA H500X 2 2 2 2 MCT4 LF-H80P SOX16 Pull high at EC side. LED0 LED1 LED2 LED3 10 11 9 1 PJRX- U717 R1115 10K 0402 5% GND_45 1 JO720 2 Add AVDDL to V_DAC, when change to RTL8110S 1 A 1 1 1 2 C915 27P 0402 5% 2 1 0.01U/NA 2 0402 JO719 1 2 GND RTL8100CL PQFP128A_0.5MM JO718 1 2 U716 1 0.1U 0402 16V 10% 2 Use H1285 for RTL8100C L735 V_12P R943 D709 0603 LED0 LED1 LED2 LED3 It's should be NA when change to RTL8110S AVDDL 2 D708 R263 0/NA ADD if use RTL8110S 2 LED0 LED1 LED2 NC_14 1M 0402 1% X706 2 D707 C PMDI3- 2 GND +3VS CL-190G/NA 0603 1 R1099 C854 GND MDI3- 1% 1 GND 120Z/100M/NA CORE_ACM2520U PMDI2- 2 R278 0/NA L44 PMDI3+ Change to 2.49K when use RTL8110S DVDD C914 27P 0402 5% 2 120Z/100M/NA CORE_ACM2520U 4 120Z/100M CORE_ACM2520U PMDI0- 2 R272 0/NA 0603 MDI3+ 1 2 PMDI2+ 1 1 2 1 120Z/100M CORE_ACM2520U MDI0- L49 3 LAN_XTAL2 L51 4 LAN_XTAL1 122 2.Parallel and equal length 3.Not to use via 3 121 2 1.50/8/8/8/50 R285 0/NA 0603 MDI2+ 1 2 4 R303 0/NA 0603 PMDI1+ MDI1+ 1 2 PMDI0+ 2 MDI3+ MDI3- GND 3 18 19 R305 0/NA 0603 MDI0+ 1 2 R304 0/NA NC_13 CTRL25 GND 25MHZ TXC8X4.5 274012500415 1 2 MDI2+ MDI2- C884 0.01U/NA 0402 +80-20% 50V ADD if use RTL8110S 2 1 C882 0.01U/NA 0402 +80-20% 50V 2 14 15 R1066 49.9/NA 0402 1% 1 MDI1+ MDI1- 2 MDI0+ MDI0- 5 6 3 1 2 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C NC_11 NC_12 R1101 2 R1063 49.9/NA 0402 1% 1 EECK EEDI EEDO EECS GND LAN_XTAL2 1 1 10 120 NC_25 NC_26 3 7 16 20 26 41 56 71 84 94 107 AVDD33_0 AVDD33_1 NC_24 AVDD33(REG) 111 109 108 106 R1071 49.9/NA 0402 1% 1 2 VDD33_0 VDD33_1 VDD33_2 VDD33_3 VDD33_4 VDD33_5 VDD33_6 24 32 45 54 64 78 99 110 116 126 NC_18 VDD25_0 NC_19 VDD25_1 NC_20 VDD25_2 VDD25_3 NC_21 NC_22 NC_23 RX+ RX- GND LAN_XTAL1 R1067 49.9/NA 0402 1% GND GND NC_9 NC_10 R1070 1K/NA 0402 5% Crystal should be placed far away from I/O port and Tx,Rx,power,magnetics. MDI3+ MDI3- 2 B MDI2+ MDI2- GND 2 PCI_PERR# PCI_SERR# PCI_STOP# LAN_PCIRST# 2 0402 PCICLK CLKRUNB DEVSELB FRAMEB GNTB REQB IDSEL INTAB IRDYB TRDYB PAR NC_8 PERRB SERRB STOPB PCIRSTB GND C896 0.01U 0402 +80-20% 50V 1 13,17,18,19,24 13,17,19,24 13,17,18,19,24 13 100 28 65 68 61 29 30 46 25 63 67 76 88 70 75 69 27 EESK AUX/EEDI EEDO EECS TX+ TX- CBEB0 CBEB1 CBEB2 CBEB3 1 PCI_INTE# PCI_IRDY# PCI_TRDY# PCI_PAR 1 92 77 60 44 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C900 0.01U 0402 +80-20% 50V 1 PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3 PCICLK_LAN PCLKRUN# PCI_DEVSEL# PCI_FRAME# PCI_GNT3# PCI_REQ3# R947 13,24 13,17,18,19,24 13,17,18,19,24 13,17,18,19 104 103 102 98 97 96 95 93 90 89 87 86 85 83 82 79 59 58 57 55 53 50 49 47 43 42 40 39 37 36 34 33 C911 1U 0402 +80-20% 10V 2 11 13,17,19,24 13,17,18,19,24 13,17,18,19,24 13,24 13,24 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PMEB ISOLATEB LANWAKE 2 93C46 SO8 283467540002 1 13,17,18,19 PCI_C/BE#[0..3] 31 23 105 VCC NC1 NC0 GND 2 0402 CS SK DI DO D 1 AVDDH R1086 49.9 0402 1% 4 AVDDL R1082 49.9 0402 1% 2 +3VS 8 7 6 5 2 DVDD_A 2 1 2 3 4 R1090 49.9 0402 1% 1 U723 EECS EECK EEDI EEDO R1087 49.9 0402 1% 2 3.6K 0603 2 R1110 2 PCI_C/BE#[0..3] ISOLATEB LAN_WAKE 2 10K/NA 0402 1 R1100 1 +3VS MDI1+ MDI1- R1108 1 2 2 C906 0.1U 0402 10% 16V MDI0+ MDI01 USED IN 93C56 1 1 2 1 2 1 2 1 1 2 2 2 1 2 2 1 C891 0.1U 0402 10% 16V NC_6 GND_12 NC_7 GND_13 GND_14 GND_15 GND_16 2 C890 0.1U/NA 0402 10% 16V GND PCI_AD18 C886 0.1U 0402 10% 16V 13 17 9 4 123 124 128 1 C903 0.1U/NA 0402 10% 16V 2 1 2 ADD if use RTL8110S DVDD GND GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND L736 120Z/100M/NA 2012 C874 0.1U 0402 10% 16V GND 21 38 51 66 81 91 101 119 1 C883 0.1U 0402 10% 16V 2 1 1 C887 0.1U 0402 10% 16V AVDDH 1 C865 0.1U 0402 10% 16V ADD if use RTL8110S NC_0 GND_0 NC_1 GND_1 NC_2 NC_3 GND_2 GND_3 NC_4 NC_5 PCI_AD[0..31] 2 2 C893 0.1U 0402 10% 16V +3VS C 1 1 1 SB_PME# AVDDL C895 0.1U 0402 10% 16V 2 2 120Z/100M/NA 2012 C862 0.1U 0402 10% 16V 22 35 48 52 62 73 80 100 112 118 2 13,14 AVDDL 1 1 C876 0.1U 0402 10% 16V 1 U719 2 120Z/100M 2012 Change AVDDL to +2.5VS_DDR , when use RTL8110S C880 0.1U 0402 10% 16V R1006 1K 0402 R1008 15K 0402 2 1 L737 1 +3VS 0/NA 13,17,18,19 PCI_AD[0..31] +2.5VS_DDR L738 Close to RTL8100C C873 0.1U 0402 10% 16V +5V GND +3VS C866 0.1U 0402 10% 16V Change DVDD to +1.8VS, when use RTL8110S C867 0.1U 0402 16V 10% GND C879 0.1U 0402 10% 16V 1 C870 10U 16V 1206 2 2 2SB1188/NA 1 +1.8VS C905 0.1U 0402 10% 16V 2 2 Q707 B 1C CTRL18 E D C864 0.1U 0402 10% 16V 2 C863 0.1U 0402 10% 16V 2 1 +3VS 1 2 120Z/100M/NA 2012 C894 0.1U 0402 10% 16V 2 1 C904 0.1U 0402 10% 16V 2 L731 2 1 DVDD +1.8VS 1 1 LAN-RTL8100CL/RTL8110S DVDD L732 1 2 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 16 of 34 2 +CARD_VCC GND GND 1 1 1 2 2 2 2 2 2 2 2 0402 0402 0402 0402 0402 0402 1% 1% 1% SDCD# SD_WP# MS_INS# SM_CD# SM_WPD# SM_R/B# 1 C465 0.1U 0402 +80-20% 50V C463 10U 0805 6.3V 10% GND +SD_MSVDD B GND MA/15PX2/ST ACES 88025-3000 291000013027 GND +SD_MSVDD GND 1 CB710 BGA_GHK_209 MS_INS# SD_WP# SD_CMD SD0 SD2 MS_BS MS_SDIO GND1 GND2 GND3 GND4 GND5 GND6 1 1 +SD_MSVDD R431 1 0 5% 2 0402 R440 1 0 5% 2 0402 R435 1 0/NA5% 2 0402 R444 1 0/NA5% 2 0402 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 L54 120Z/100M 2012 273000150013 Q24 SI2301DS S +3V K R377 10K 0402 SD_PWREN# R1217 R378 1K 0402 5% MS_PWREN# (43K) G 4,12,13,25,31 PWROK +3V 2S 1 C341 0.1U 0402 10% 16V 2 R376 100K 0402 5% G CCLK R552 1 0402 2 5% 220 A D Q716 S 2N7002 1 D D36 CL-190G D R1213 33 0402 0 5% 0402G_DFS SD_LED# MS_LED# A +CARD_VCC +VPPOUT GND +3V GND C1002 1U 0402 +80-20% 10V 1 R388 1 R1233 1 R1234 2 0402 2 0402 2 0402 1% 1% 1% SD3 SD_CMD SD_CLK 43.2K 43.2K 43.2K 1 R1235 1 R389 1 R1237 2 0402 2 0402 2 0402 1% 1% 1% SD0 SD1 SD2 C993 0.1U 0402 10% 16V C994 0.1U 0402 10% 16V C995 0.1U 0402 10% 16V C996 0.1U 0402 10% 16V C997 0.1U 0402 10% 16V C998 0.1U 0402 10% 16V 1 43.2K 43.2K 43.2K/NA C999 0.1U 0402 10% 16V 2 1 +SD_MSVDD C1001 2.2U 0603 +/-10% GND C1000 0.1U 0402 10% 16V Title 8050D MOTHER B/D Size C GND Date: 5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 MS_SCLK SD_CLK SD1 SD3 1 R1224 R1225 R1226 R1228 R1230 R1231 1 2 MS_BS MS_SDIO MS_SCLK SM_LVD 2 VPPD0 VPPD1 286302211006 GND 0 5% 0402G_DFS J716 SDCD# MS_SCLK C988 10P 0402 5% 50V 2 2 1 SSOP16 16 15 14 13 12 11 10 9 1 1 1 1 1 1 GND 291000256843 GND 2 TPS2211A SHDN VDDP0 VDDP1 AVCCA AVCCB AVCCC AVPP 12V 2 C992 0.1U 0402 10% 16V VCCD0 VCCD1 3.3VA 3.3VB 5VA 5VB GND OC 43.2K 43.2K 43.2K 8.2K 8.2K 8.2K 1 1 C991 0.1U 0402 10% 16V 2 2 1 1 R1229 10K 0402 1 2 3 4 5 6 7 8 2 2 A U728 VCC5_EN# VCC3_EN# 1% 1% 1% 1% CCLKRUN# +3V +3V 0402 0402 0402 0402 2 2 2 2 1 CARD_ACT SM_W E# SM_RE# SM_CE# 1 RI# 1 4.7K/NA 2 0402 1% 1% 1% 2 1 4.7K/NA 2 0402 R1220 +3V R1208 R1209 R1210 R1211 2 0402 2 0402 2 0402 1 R1218 +5V 1 1 1 1 1 CARD_MF1 1 1 4.7K/NA 2 0402 C C987 10P 0402 5% 50V 2 10 0402 5% G R1216 R1221 10K 0402 +3V 43.2K 43.2K 43.2K 43.2K +VPPOUT GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND 1 R1205 1 R1206 1 R1207 D GND R1203 MS_CLK1 1 GND +SD_MSVDD 43.2K 43.2K 43.2K SHORT-SMT4 GND SD_CLK 2 10 0402 5% MS_PWREN# MS_CLK1 R1204 1 0 2 0402_DFS 5% MS_BS MS_LED# MS_INS# MS_SDIO R1214 +3VS SD_CLK1 1 D S Multi Function pin need pull up. G17 G18 H15 H14 N17 U11 V11 GND_C4 CTRDY# CFRAME# CAD17 CAD19 CVS2 CRST# CSERR# CREQ# CCBE3# CAUDIO CSTSCHG CAD28 CAD30 CAD31 CCD2# 2 H2 J1 H1 J3 J2 K1 J6 K3 K5 L1 L2 L6 M1 L5 M3 M2 M6 W4 U5 R6 V5 U6 V6 W6 V7 W7 R8 W10 V10 U10 R10 W11 RI# 2 0.1U/NA 0402 16V 10% 10K CCD1# CAD2 CAD4 CAD6 R2_D14 CAD8 CAD10 CVS1 CAD13 CAD15 CAD16 R2_A18 CBLOCK# CSTOP# CDEVSEL# R1198 2 1 R1201 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 GND +3V 2 0402 2 0402 2 1 Q714 DTC144WK/NA CAD0 CAD1 CAD2 CAD3 CAD4 CAD5 CAD6 CAD7 CAD8 CAD9 CAD10 CAD11 CAD12 CAD13 CAD14 CAD15 CAD16 CAD17 CAD18 CAD19 CAD20 CAD21 CAD22 CAD23 CAD24 CAD25 CAD26 CAD27 CAD28 CAD29 CAD30 CAD31 1 3 10K 1 1 2 2 D3/CAD0 D4/CAD1 D11/CAD2 D5/CAD3 D12/CAD4 D6/CAD5 D13/CAD6 D7/CAD7 D15/CAD8 A10/CAD9 CE2#/CAD10 OE#/CAD11 A11/CAD12 IORD#/CAD13 A9/CAD14 IOWR#/CAD15 A17/CAD16 A24/CAD17 A7/CAD18 A25/CAD19 A6/CAD20 A5/CAD21 A4/CAD22 A3/CAD23 A2/CAD24 A1/CAD25 A0/CAD26 D0/CAD27 D8/CAD28 D1/CAD29 D9/CAD30 D10/CAD31 +3VS P12 U12 W13 P11 R12 V12 R11 1 R1199 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 2 SHORT-SMT4 JS8 1 2 FM/34PX2/1.27MM ACECON MF-291000000008 2 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 IRQSER C989 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND_C1 GND_C3 2 MS_PWREN# MS_SCLK MS_CLKIN MS_BS MS_LED# MS_INS# MS_SDIO B R1212 10K/NA 0402 CCLK CIRDY# CCBE2# CAD18 CAD20 CAD21 CAD22 CAD23 CAD24 CAD25 CAD26 CAD27 CAD29 R2_D2 CCLKRUN# GND TP709 TP16 TP711 TP712 TP713 TP18 TP715 TP716 TP19 1 G14 GND 1 0402 TP708 2 SERIRQ 13,14,19,22 SERIRQ R1242 2 10K 1 2 PCLK SPKROUT RI_OUT#PME# SUSPEND# PRST# GNT# REQ# IDSEL FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR C/BE0# C/BE1# C/BE2# C/BE3# 2 13,16,18,19,24 PCI_FRAME# 13,16,18,19,24 PCI_IRDY# 13,16,18,19,24 PCI_TRDY# 13,16,18,19,24 PCI_DEVSEL# 13,16,18,19,24 PCI_STOP# 13,16,18,19,24 PCI_PERR# 13,16,19,24 PCI_SERR# 13,16,18,19 PCI_PAR 13,16,18,19 PCI_C/BE#0 13,16,18,19 PCI_C/BE#1 13,16,18,19 PCI_C/BE#2 13,16,18,19 PCI_C/BE#3 1 100 0402 5% A10 G15 C14 D19 A14 C13 B13 C10 F8 A7 B7 C7 F7 A6 B6 C6 E2 A5 C8 A15 1 0402 1 0402 TP707 SC_PWR5EN# 1 R1196 2 SC_PWR3EN# 1 10K/NA 20402 R1197 10K/NA 0402 1 13 CARD_PCIRST# 13,24 PCI_GNT0# 13,24 PCI_REQ0# R1202 2 0402 CARD_PCIRST# VCC_SC SC_PWR5EN# SC_PWR3EN# SC_CLK SC_IO SC_RST# SC_CD# SC_LED# SC_OC# SC_C8 SC_C4 2 1 4.7K R1192 2 10K R1241 2 10K C986 0.1U 0402 10% 16V GND_C2 GND_C4 N14 N15 P18 R17 T19 P15 P19 M14 N18 R19 R18 1 PCI_AD20 R1200 SM_PWR5EN# SM_PWR3EN# SM_WPD# SM_WP# 1 SM_CE# SM_RE# SM_LED# SM_CD# SM_R/B# SM_W E# SM_ALE 1 SM_LVD SM_CLE 1 SM_SD0 1 SM_SD1 1 SM_SD2 1 SM_SD3 1 SM_SD4 1 SM_SD5 1 SM_SD6 1 SM_SD7 1 C985 0.1U 0402 10% 16V t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 2 11 PCICLK_CARD 20 CARDSPK# 13 CARDBUS_PME# 13,22,23,25 SUSB# J15 H19 H18 K17 J14 J18 H17 N19 K14 K15 J19 K19 J17 L14 L17 L19 M18 M15 M19 L18 L15 +VPPOUT GND 2 0 PCI_INTC# 1 2 5% R1194 0402G_DFS CARD_MF1 PCI_INTF# 1 0/NA 2 0402 R1238 5% SERIRQ R1195 1 0/NA 2 0402 5% RI# CARD_ACT PCLKRUN# 13,16,19,24 PCLKRUN# VCC5_EN# VCC3_EN# PCI_INTC# 13,19,24 PCI_INTF# SD_CMD SD_WP# SDCD# SD_LED# SD0 SD1 SD2 SD3 SD_PWREN# R1191 1 0 2 5% SD_CLK1 0402G_DFS 1 0 PCI_INTB# R1193 1 2 5% 0402G_DFS SM_PWR5EN# SM_PWR3EN# SM_WPD# SM_WP# SM_CE# SM_RE# SM_LED# SM_CD# SM_R/B# SM_WE# SM_ALE SM_LVD SM_CLE SM_D0 SM_D1 SM_D2 SM_D3 SM_D4 SM_D5 SM_D6 SM_D7 V15 P13 V14 P14 R14 V13 U13 W14 W15 U14 W16 U15 CD1#/CCD1# CD2#/CCD2# VS1#/CVS1 VS2#/CVS2 CE1#/CCBE0# A8/CCBE1# A12/CCBE2# REG#/CCBE3# A18/RSVD (R_A18) D2/RSVD (R_D2) D14/RSVD (R_D14) A19/CBLOCK# A20/CSTOP# A21/CDEVSEL# A22/CTRDY# A13/CPAR WE#/CGNT# WP/CCLKRUN# BVD1/CSTSCHG BVD2/CAUDIO WAIT#/CSERR# READY/CINT# A15/CIRDY# A14/CPERR# INPACK/CREQ# RESET/CRST# A23/CFRAME# A16/CCLK 13,24 PCI_INTB# VCC_SD SD_PWREN# SD_CLKIN SD_CLK SD_CMD SD_WP SD_CD# SD_LED# SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 H3 R9 U8 P7 K6 N1 T1 P8 N2 P10 K2 N6 N5 R1 R2 N3 P3 U9 CSTSCHG V9 CAUDIO W9 CSERR# W8 CINT# V8 CIRDY# P5 CPERR# P1 CREQ# R7 CRST# W5 CFRAME# R3 2 P6 13,24 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 VCCD0# VCCD1# CCD1# CCD2# CVS1 CVS2 CCBE0# CCBE1# CCBE2# CCBE3# R2_A18 R2_D2 R2_D14 CBLOCK# CSTOP# CDEVSEL# CTRDY# CPAR CGNT# C H5 G1 G3 H6 F1 G5 F2 E1 G6 F5 E3 C12 A4 E6 B5 F6 B8 A8 E9 F9 B9 A9 F10 E10 F11 E13 C11 B11 A12 B12 E12 A13 F15 E17 A16 C15 E14 F13 B15 E19 F14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 2 E5 NC F18 F17 F19 VPPD0 VPPD1 VPPD2 M5 G2 J5 P2 P9 R13 P17 K18 E18 F12 B10 E8 C5 GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 CAD11 +SD_MSVDD PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 CAD0 CAD1 CAD3 CAD5 CAD7 CCBE0# CAD9 CAD11 CAD12 CAD14 CCBE1# CPAR CPERR# CGNT# CINT# PCI_AD[0..31] 13,16,18,19 PCI_AD[0..31] GND_C3 J6 U727 SHORT-SMT4 GND 1 GND CCLKRUN# 2 SHORT-SMT4 JS7 1 2 JS4 C983 0.1U 0402 10% 16V 2 R1189 43.2K 0402 1% 1 1 R1188 10K 0402 CRST# GND VCCA G_RST GND_C2 2 R1187 43.2K 0402 1% VPPD1 VPPD0 1 GND VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 A11 D1 F3 L3 U7 W12 M17 G19 B14 E11 C9 E7 2 R1190 1 0 2 5% 0402G_DFS GND_C1 2 +CARD_VCC CARD_PCIRST# 1 +CARD_VCC +3V C984 0.1U 0402 10% 16V 1 JS5 CardBus & Reader(CB710) CB710 IDSEL: AD20 PCI REQ0# PCI GNT0# PCI INTB# INTC# D 3 1 4 2 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 17 of 34 5 4 +3V +3VS 120Z/100M 2012 +3V C921 2.2U +80-20% 0805C 1 D 2 C961 2.2U +80-20% 0805C L739 120Z/100M/NA 2 2 120Z/100M/NA 2012 1 L742 1 2 1 +3VS 1 120Z/100M 2012 C925 0.1U 0402 +80-20% 50V 1 2 1 2 1 C922 0.1U 0402 +80-20% 50V 2 C923 0.1U 0402 +80-20% 50V L746 2 GND GND VCCRAM VCCSUS[0] VCCSUS[1] VCCATX0 VCCATX1 VCCATX2 62 76 90 VCCARX0 VCCARX1 VCCARX2 65 75 89 8 20 33 35 102 113 114 125 24 39 49 5% +3V 47 TPA-_6307 TPA+_6307 TPB+_6307 TPB-_6307 80 79 78 77 1 1 1 1 72 73 71 70 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 1 9 16 26 34 36 94 103 111 115 121 GND B 1394_AGND 2 2 2 2 1 1 1 2 2 2 C C964 0.33U 0402 +80-20% 16V GND GND XI XO 29 30 31 32 EECS_1394 EEDO_1394 EEDI_1394 EECK_1394 R1145 6.34K 0402 1% C958 47P 0402 +/-10% 50V R1146 1 GND 37 PCI_PME# 13 1K/NA 2 0402 5% +3V R1147 1K 0402 5% EECS_1394 EECK_1394 EEDI_1394 EEDO_1394 43 42 GND 38 40 44 45 51 56 57 67 XI +3V U722 1 2 3 4 CS SK DI DO VCC NC1 NC0 GND 8 7 6 5 1 60 61 93C46 SO8 283467540002 C907 1U 0402 +80-20% 10V GND R1116 XO 1 2 1M 0402 5% VT6307L PQFP128A_0.5MM Configuration Straps X707 1 GND 2 GND NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 C965 270P 0402 +/-10% 50V 2 PME# MODE0 MODE1 63 66 1 EECS/EEAUTO# EEDO EEDI/SDA EECK/SCL/EEFAST FRAME# DEVSEL# TRDY# IRDY# PGNT# PREQ# IDSEL INTA# PCICLK PCIRST# PAR PERR# STOP# PHYRST# R1142 54.9 0402 1% 2 XI XO R1141 54.9 0402 1% TPBIAS 1 XCPS XRES R1148 4.99K 0402 1% TPBIAS 74 81 88 2 XTPBIAS0 XTPBIAS1 XTPBIAS2 R1143 54.9 0402 1% 1 XTPA2P XTPA2M XTPB2P XTPB2M R1144 54.9 0402 1% 87 86 85 84 2 XTPA1P XTPA1M XTPB1P XTPB1M C928 0.1U 0402 +80-20% 50V 2 1 2 4.7K/NA 0402 I2CEEENA I2C EEPROM. I2CFAST 0: 4-wire EEPROM interface(Default) 1: 2-wire I2C EEPROM interface using SCL/SDA I2C EEPROM Fast Mode 2 24.576MHZ TXC8X4.5 274012457406 1 100 2 1% XTPA0M XTPA0P XTPB0P XTPB0M 46 48 C932 10P 0402 5% 50V 2 PCI_AD21 R1117 1 0402 52 1 PCI_INTG# PCICLK_1394 1394_PCIRST# PCI_PAR PCI_PERR# PCI_STOP# CARDBUSENA GNDATX0 GNDATX1 GNDATX2 GNDRAM GNDSUS[0] GNDSUS[1] 13,24 11 13 13,16,17,19 13,16,17,19,24 13,16,17,19,24 1394_AGND 54 55 53 R1112 CBE0# CBE1# CBE2# CBE3# 123 127 126 124 95 96 108 91 93 92 3 2 128 58 PHYCMC 12CEEENA I2CFAST 1 PCI_FRAME# PCI_DEVSEL# PCI_TRDY# PCI_IRDY# PCI_GNT1# PCI_REQ1# C955 0.1U 0402 +80-20% 50V GND PHYPC0 PHYPC1 PHYPC2 59 69 83 25 41 50 15 4 122 107 13,16,17,19 PCI_C/BE#0 13,16,17,19 PCI_C/BE#1 13,16,17,19 PCI_C/BE#2 13,16,17,19 PCI_C/BE#3 13,16,17,19,24 13,16,17,19,24 13,16,17,19,24 13,16,17,19,24 13,24 13,24 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 GNDARX0 GNDARX1 GNDARX2 C 28 27 23 22 21 19 18 17 14 13 12 11 10 7 6 5 120 119 118 117 116 112 110 109 106 105 104 101 100 99 98 97 64 68 82 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 U724 PCI_AD[0..31] GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 13,16,17,19 PCI_AD[0..31] 2 L743 1 GND 1394_AVCC +PHYVDD +3V C917 0.1U 0402 +80-20% 50V 2 +PHYVDD +PHYVDD 1 1 C918 0.1U 0402 +80-20% 50V 2 C919 0.1U 0402 +80-20% 50V 2 2 1 C916 0.1U 0402 +80-20% 50V 2 1 C920 0.1U 0402 +80-20% 50V 2 1 C924 0.1U 0402 +80-20% 50V 2 C954 0.1U 0402 +80-20% 50V 2 1 D C931 0.1U 0402 +80-20% 50V 1 ALL Capacator must close to power pin C936 0.1U 0402 +80-20% 50V 1 1 2 1 C957 0.1U 0402 +80-20% 50V 2 1 2 C956 0.1U 0402 +80-20% 50V GND 1 1 1394_AVCC +3V 2 2 IEEE1394(VT6307L) 1394_AVCC:Because of suspend then resume unknow, us suspend power VT6307L IDSEL: AD21 PCI REQ1# PCI GNT1# PCI INTG# 3 GND C929 10P 0402 5% 50V GND B 0: Disable (Default) 1: Enable CARDBUSENA CardBus Mode PHYCMC Programmable Contender / Bus Manager Capable 0: Disable (PCI)(Default) 1: Enable High specifies that the node is capable of being a bus manager. 2 0402 5% 4 L740 120Z/100M CORE_ACM2520U R1139 1 0/NA 2 0402 5% R543 1 0/NA 2 0402 J718 1 2 3 4 A ESD0805A/NA L747 1 1 A GND 2 120Z/100M 2012 R534 1 0/NA 2 0402 2 120Z/100M 2012 L87 K K GND0 GND1 4PX1/0.8MM-MA MOLEX 54030-0411 331000004009 1 1 1 K 120Z/100M CORE_ACM2520U 1 2 3 4 5 6 D706 ESD0805A/NA ESD0805A/NA ESD0805A/NA 1 1 2 D30 JO53 JO48 JO52 JO49 L83 A D711 K 3 TPA+_6307 4 D28 A A A 2 TPATPA+ TPA-_6307 2 5% 2 TPB+_6307 2 TPBTPB+ 1 TPB-_6307 2 1 0/NA 3 R1149 5% 1394_GND GND 1394_AGND Because of EMC notice, change L547 to 0 ohm 0805 1394_GND 1394_GND Title 8050D MOTHER B/D Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 18 of 34 5 4 3 2 1 MINI-PCI FROM LYNX-AMD +3V MINI-PCI J713 PCICLK_MINIPCI R1079 1 0 0402 2 5% C885 10P/NA 0402 +/-10% 50V 1 11 PCICLK_MINIPCI MINIPCI_LPCDRQ# 2 +3V 13,24 PCI_REQ2# R1083 1 0 0402 5% 2 MINI_REQ2# PCI_AD31 PCI_AD29 PCI_AD27 PCI_AD25 1 C898 0.1U 0402 +80-20% 50V MINIPCI_LPCFRAME# C901 0.1U 0402 +80-20% 50V PCI_CBE#3 PCI_AD23 13,16,17,18 PCI_C/BE#3 PCI_AD21 PCI_AD19 GND PCI_AD17 PCI_CBE#2 PCI_IRDY# 13,16,17,18 PCI_C/BE#2 13,16,17,18,24 PCI_IRDY# 1 C899 0.1U 0402 +80-20% 50V 2 1 C892 0.1U 0402 +80-20% 50V 2 1 C910 0.1U 0402 +80-20% 50V 2 2 1 +3V 2 1 C888 0.1U 0402 +80-20% 50V 2 1 C875 2.2U 0603 +/-10% 2 2 1 GND C909 0.1U 0402 +80-20% 50V 13,16,17,24 PCLKRUN# 13,16,17,24 PCI_SERR# 13,16,17,18,24 PCI_PERR# 13,16,17,18 PCI_C/BE#1 GND PCLKRUN# PCI_SERR# PCI_AD8 PCI_AD7 PCI_AD5 PCI_AD3 PCI_AD1 +5V 2 MINIPCI_LPCAD0 1 R1093 0/NA 0402 5% MINIPCI_SIO48M GND1 GND2 13 13,14,17,22 13,22,23 11 LRDQ0# SERIRQ LFRAME# SIO_48M R1096 R1065 R1069 R1088 1 1 1 1 0 0 0 0 2 2 2 2 0402 0402 0402 0402 5% 5% 5% 5% MINIPCI_LPCAD0 MINIPCI_LPCAD1 MINIPCI_LPCAD2 MINIPCI_LPCAD3 R1075 R1118 R1091 R1137 1 1 1 1 0 0 0 0 2 2 2 2 0402 0402 0402 0402 5% 5% 5% 5% MINIPCI_LPCDRQ# MINIPCI_PCISERIRQ MINIPCI_LPCFRAME# MINIPCI_SIO48M R1068 1 0 2 0402 5% R1077 1 0 R1078 1 0/NA 2 0402 2 0402 5% MINIPCI_PCIRST# 5% R1080 1 0 2 0402 5% PCI_INTD# PCI_GNT2# PCI_PME# TP721 TOUCHPAD_10 13,24 MINIPCI_PCIRST# 13 PCI_AD28 PCI_AD26 PCI_AD24 R1092 1 0402 PCI_AD22 PCI_AD20 PCI_PAR PCI_AD18 PCI_AD16 PCI_FRAME# PCI_TRDY# PCI_STOP# PCI_DEVSEL# 100 2 1% PCI_AD17 PCI_PAR 13,16,17,18 PCI_FRAME# PCI_TRDY# PCI_STOP# 13,16,17,18,24 13,16,17,18,24 13,16,17,18,24 +5V GND PCI_DEVSEL# 13,16,17,18,24 PCI_AD15 PCI_AD13 PCI_AD11 PCI_AD9 PCI_CBE#0 PCI_C/BE#0 R1095 R1094 1 0 5% 2 0402 MINIPCI_PD 1 0/NA R558 470 0402 5% D38 CL-190G LED_CL190 13,16,17,18 PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0 2 0402 C 5% 2 R1 Q710 DTC144TKA 288202240001 WIRELESS_PD# 14,24 MINIPCI_PCISERIRQ R1138 1 0 R1076 2 0402 1 0/NA 2 0402 5% R1072 1 0 2 5% 0402G_DFS GND1 GND2 124P/0.8MM/H6 SPEED MINIPCI_GPORESET# 13,24 MINIPCI_PME# 13 MINIPCI_LPCAD3 PCI_AD30 291000251246 SPEED-B27-101-0038 2 13,22,23 LAD0 13,22,23 LAD1 13,22,23 LAD2 13,22,23 LAD3 MINIPCI_LPCAD2 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C PCI_PERR# PCI_CBE#1 PCI_AD14 PCI_AD12 PCI_AD10 C D MINIPCI_LPCAD1 1 R1064 1 0/NA 2 0402 5% 13,17,24 PCI_INTF# +5V 1 2 5% 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 2A R1003 1 0 0402 RING TX+ TXPJ4 PJ5 LED2_YELP LED2_YELN RESERVED4 5V[1] INTA# RESERVED5 3.3VAUX[0] RST# 3.3V[4] GNT# GROUND9 PME# RESERVED6 AD[30] 3.3V[5] AD[28] AD[26] AD[24] IDSEL GROUND10 AD[22] AD[20] PAR AD[18] AD[16] GROUND11 FRAME# TRDY# STOP# 3.3V[6] DEVSEL# GROUND12 AD[15] AD[13] AD[11] GROUND13 AD[9] C/BE[0]# 3.3V[7] AD[6] AD[4] AD[2] AD[0] RESERVED_WIP4[0] RESERVED_WIP4[1] GROUND14 M66EN AC_SDATA_OUT AC_CODEC_ID0# AC_RESET# RESERVED7 GROUND15 SYS_AUDIO_IN SYS_AUDIO_IN_GND AUDIO_GND2 MPCIACT# 3.3VAUX[1] K MINIPCI_PD 2 TIP RX+ RXPJ7 PJ8 LED1_GRNP LED1_GRNN CHSGND INTB# 3.3V[0] RESERVED0 GROUND0 CLK GROUND1 REQ# 3.3V[1] AD[31] AD[29] GROUND2 AD[27] AD[25] RESERVED1 C/BE[3]# AD[23] GROUND3 AD[21] AD[19] GROUND4 AD[17] C/BE[2]# IRDY# 3.3V[2] CLKRUN# SERR# GROUND5 PERR# C/BE[1]# AD[14] GROUND6 AD[12] AD[10] GROUND7 AD[8] AD[7] 3.3V[3] AD[5] RESERVED2 AD[3] 5V[0] AD[1] GROUND8 AC_SYNC AC_SDATA_IN AC_BIT_CLK AC_CODEC_ID1# MOD_AUDIO_MON AUDIO_GND0 SYS_AUDIO_OUT SYS_AUDIO_OUT_GND AUDIO_GND1 RESERVED3 VCC5VA 3 R1007 1 10K 0402 5% 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 1 +3V 5% GND MINIPCI_ACT# 14,24 +3V +3VS 1 D PCI_AD[0..31] 13,16,17,18 PCI_AD[0..31] AD17 PCI_INTD# REQ2#/GNT2# GND C881 0.1U 0402 +80-20% 50V PIN24, 124 ARE AUX_POWER GND GND B B A A Title 8050D MOTHER B/D Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 19 of 34 5 4 3 2 1 AUDIO CODEC(ALC655) L66 120Z/100M 2012 +3V R452 470K/NA 0402 5% AGND 1 L741 S-OUT-L S-OUT-R AFILT1 1 5% VREFOUT 21 21 EAPD GND ALC655 PQFP48_0.5MM AGND 37 C939 +80-20% 0402 C940 41 +80-20% 0402 C962 29 0402 C960 30 0402 27 20mil 39 1 1 1 1 2 6.8K 0402 5% R542 5.6K 0402 5% AGND 10K/NA2 5% GND MODEM_SPK C933 1000P/NA 0402 10% 50V R560 1K/NA 0402 5% C518 0.1U/NA 0402 10% 16V AGND SUB_OUTL 21 SUB_OUTR AOUT_L AGND SUB_OUTR R1130 1 4.42K 2 0402 5% R1127 1 4.42K 2 0402 5% C966 1U AGND 0402 +80-20% 10V 1 0402 1 0402 0 2 0 2 MIC_VREF 5% 2464_VREF 5% 2464_VREF 21 2 120Z/100M 2012 AGND GND 0/NA 2 5% 0/NA 2 5% R1135 1 0402 R1128 1 0402 0 5% 0 5% 2 AMP_LEFT 21 2 AMP_RIGHT 21 SUB_LEFT SUB_RIGHT R1126 27K/NA 0402 5% 21 21 R1129 27K/NA 0402 5% B AGND 273000130006 1 5% 0 2 L53 0402 1 R519 2 L76 5% 0 0402 C499 100P/NA 0402 +/-10% 50V R520 22K 0402 1% 2 2 R325 22K 0402 1% 5 J721 4 3 6 2 1 BEAD_600Z/100M 0603D 1 2 1 R.CH L.CH 0603D 2 BEAD_600Z/100M 1 1 1 2 1 2 C159 100P/NA 0402 +/-10% 50V C498 100P 0402 +/-10% 50V J11 CAGND C330 100P 0402 J10 +/-10% 50V CAGND RA/D6/6P 2SJ-SB2014D3 CONN_JACK_SB2014 291000920605 L751 2 1 L725 2 GND GND GND A 1 J715 2 1 R1136 1K 0402 5% HDR/MA-2 ACES 85204-0200 291000020206 R849 560-2010/NA 0805 L724 50UH CHOKE_WLT04020201 L721 120Z/100M/NA 2 1 2012 1 F2 2 MINISMDC014-2 POLYSW_MINISMDC110 GND C148 1 2 1808 1000P 2KV 10% C806 1 2 1808 1000P 2KV 10% MODEMP MODEMN MODEMP MODEMN 16 16 GND_45 5 C912 10P/NA 0402 +/-10% 50V AGND 120Z/100M/NA 2 1 2012 14 2 5% 2 0402ACBITCLK ACSDIN1 3 R1120 1 22 ACSYNC ACSDIN1 2 R1131 1 22 5% 2 0402 R1121 1 22/NA 5% 2 0402 R1133 0/NA 0402 5% 120Z/100M 1608 CAGND C913 0.1U 0402 10% 10V GND CLOSE TO MDC JP, use 4pcs of 2kV 1000P cap Title 8050D MOTHER B/D US, use 2pcs of 2kV 1000P cap Size C UK, use 4pcs of 3kV 1000P cap Date: 5 R497 1 0402 R503 1 0402 SUB_OUTL 21 1 0402 2 5% 2 R1132 1 4.7K 291000023008 GND 1 AGND R535 1 FM/0.8MM/H2.4 AMP C-179373 MODEM_SPK 5% 1 C926 0.1U 0402 10% 10V 2 0402 2 1 2 2 C927 0.1U 0402 10% 10V 1 ACSDOUT ACRST# L62 2 120Z/100M 2012 AGND CAGND 1 A R1134 1 0/NA 2 +3VS L65 1 AGND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 1 +3V 2 120Z/100M 2012 AGND MONO_OUT MDC +5V 1 GND AGND LINE_IN/R +3V 2 120Z/100M 2012 AGND GND 0 0402 5% R324 J717 L88 1 R549 LINE_IN/L 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 L73 2 AGND R532 MONO_OUT C FOR EMI REQUEST CHANGE TO 0 OHM CDROM_COM M 15 AOUT_R C967 0.1U 0402 10% 16V CAGND CDROM_LEFT 15 CDROM_COM M 28 C963 1U 0402 +80-20% 10V ESD0805A/NA 0603B_0805C CDROM_RIGHT 15 CDROM_LEFT 5% 2 0 0402 R559 1 0402 2 1U 10V 2 1U 10V 2 1000P 50V 10% 2 1000P 50V 10% 1 R537 6.8K 0402 5% AGND 1 2 2 1 1 1 R546 6.8K 0402 5% CDROM_RIGHT 5% R550 1 2 0.1U/NA 16V 10% 2 0.1U 16V 10% AGND SPDIFOUT 2 2 C519 1 0402 C937 1 0402 13 2 B 0 0402 VREF R538 1 AOUT_R 36 1 GND R1124 2 JD0 AVSS1 AVSS2 1 5% 26 42 R1123 2 0/NA 0402 4 7 GND DVSS1 DVSS2 AFILT2 35 0402 1 MONO-OUT 1 2 6.8K 1 AGND PHONE FRONT-MIC1 NC_1 CEN-OUT LFE-OUT JD0/GPIO0 XTLSEL SPDIFI/EAPD SPDIFO 1 R547 1 2 40 43 44 45 46 47 48 LINE-OUT-L LINE-OUT-R 15 1 1 AGND 1 34 FRONT-MIC2 NC_0 14 1 AGND 2 0402 1 33 AUX-R 17 1 0 2 1 32 VRDA 16 1 1 5% 1 JD2 19 1 MIC 2 XTL-OUT PC-BEEP 18 1 1 SPARKGAP_6 2 D718 2 CD-GND 20 1 R1157 1 1 31 JO725 1% 1 CD-L XTL-IN 22 RA/D6/6P 2SJ-SB2014D3 CONN_JACK_SB2014 291000920605 CAGND 1 CD-R 21 LINE_IN/R 2 1 2 1U 10V +80-20% 2 1U 10V +80-20% 2 1U/NA 10V +80-20% 2 0.1U/NA 16V 10% BEAD_600Z/100M 0603D 2 1 R1164 2 22K/NA 0402 2 MIC2 1 2 L744 1 GND C504 22P/NA 0402 +/-10% 50V 1 AGND 2 GND C959 0402 C953 0402 C952 0402 C945 0402 2 1 2 MIC1 24 2 2 1 1 2 C477 22P/NA 0402 +/-10% 50V RESET# SDATA-OUT SDATA-IN SYNC BIT-CLK AUX-L 2 R1155 1 0 0603 C948 100P/NA 0402 +/-10% 50V t t n e e r c m e u S c c Do a iT ial M t n e id f n o C LINE-R JD1/GPIO1 X2 1 24.576MHZ/NA TXC8X4.5 274012457406 C971 0.1U/NA 0402 +80-20% 50V LINE_IN/L 2 1U 10V +80-20% 2 1U 10V +80-20% 2 1U 10V +80-20% 2 1U 10V +80-20% 2 1U 10V +80-20% 2 1U 10V +80-20% 2 0.22U 16V +80-20% 2 1U/NA 10V +80-20% 2 1U/NA 10V +80-20% 2 1U 10V +80-20% 2 1U 10V +80-20% AOUT_L 1 1 12 C974 0402 C969 0402 MIC1 C975 0402 MIC2 C970 0402 C513 0402 C507 0402 C515 0402 C979 0402 C980 0402 C976 0402 C516 0402 2 PC_BEEP 0402 5 J719 4 3 6 2 1 BEAD_600Z/100M 0603D 1 2 MIC_EXT AGND 23 1 2 0402 2 5% 0 C972 0.1U/NA 0402 +80-20% 50V 2 3 1 R516 1M/NA AGND LINE-L 1 2 1 C973 4.7U/NA 0603 6.3V +80-20% 2 2 22 5% 2 4.7K 0402 5% 1 1608 1 L57 MIC_INT 1 R498 1 0402 2 11 5 8 10 6 MIC_VREF 2 2 22 5% 2 5% 4.7/NA 1 L69 C509 2200P 0402 +/-20% 50V CAGND 2 DVDD1 DVDD2 R530 1 0402 1 0 2 R472 1 0 0402 5% 1 2 1 9 2 ACRST# ACSDOUT ACSDIN0 ACSYNC ACBITCLK 1 0402 R1153 R1154 C968 C938 0.1U 0.1U 0402 0402 +80-20% +80-20% 50V 50V AGND AGND GND U726 ACRST# ACSDOUT ACSDIN0 ACSYNC ACBITCLK 2 120Z/100M/NA CORE_ACM2520U 25 38 GND AVDD C481 0.1U 0402 10% 16V GND 14M_CODEC AGND 1 1 C501 0.1U 0402 10% 16V 2 2 C491 10U 0805 6.3V 10% AVDD1 AVDD2 GND 1 1 2 1 ACBITCLK C476 22P/NA 0402 +/-10% 50V 11 D R1150 1 0 0603 AGND R1151 C 1 C467 0.01U 0402 +80-20% 50V 2 GND 14 14 14 14 14 AGND 1 2 AGND 1 AGND 2 MIC5205BM5 SOT25 1 C455 100P 0402 +/-10% 50V C475 10U 1210 10V 2 PC_BEEP 2 1U 0402 10V +80-20% 1 2 3 1 R437 1K 0402 5% 2 NC7S32 SOT25 R443 47K 0402 5% 1 ADJ 1 2 10K 0402 5% 1 1 2 2 R442 47K 0402 5% C456 R438 5 4 2 VCC Y 1 1 A B GND 2 1 2 3 2 C458 0.1U 0402 16V 10% 1 CARDSPK#1 R484 180K/NA 0603 1% 4 4 2 CARDSPK# IN GND EN OUT 1 5 GND 2 16V MIC1 BEAD_600Z/100M L7341 0603D 2 1 + L70 1 0603D 2 2 BEAD_600Z/100M C942 47P/NA D5.8/H2.0 0402 EM147TK +/-10% 339115000046 50V JO724 D705 SPARKGAP_6 ESD0805A/NA 0603B_0805C 3 0402 U17 1 17 120Z/100M/NA 2 1 2012 VA U18 2 D 2 2 SBSPKR 13,14 SBSPKR 10% L64 1 2 +5V C460 0.1U 2 VA 10% 16V 0402 0.1U C457 1 2 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 20 of 34 4 1 1 DTC144TKA 288202240001 1 1 C949 0.1U 0402 10% 16V 1 2 GND HP in 0 1 OPT in 1 0 no this condition 1 1 on device VA 100U 6.3V L752 20% 1 2 120Z/100M 2012 R322 4.7K 0402 5% J7 1 2 R1183 10K 0402 2 GND D +5V 2 120Z/100M 2012 + C466 C934 0.1U 0402 10% 16V 2 AGND 600Z/100M 1608 1 2 20 L757 1 SPDIFOUT Drive IC LED 22 SPK_OFF# 1 12 13 24 + C474 2 1U 10V +80-20% HDR/MA-2 ACES 85204-0200 291000020206 + C489 100U 6.3V 20% 100U 6.3V 20% GND 1 0402 1 0402 5% 5% L80 L78 2 600Z/100M 2 600Z/100M 1 1 1608 1608 +3V 4 9 AGND AGND C354 100P/NA 0402 10% 50V C503 100P 0402 10% 50V C356 100P/NA 0402 10% 50V Q711 288221371002 AGND OPTIN# AGND DTA144WK 1 SOT23AN_1 AGND 3 CAGND C 1 C150 100P 0402 10% 50V 1 R328 1K 0402 1% 1 R529 1K 0402 1% 2 25 26 27 28 29 L759 600Z/100M 1608 1 R329 2 22 R528 2 22 2 G1 G2 G3 G4 G5 GP1FD310TP SHARP CONN_GP1FD310TP L758 600Z/100M 1608 AGND 1 LOUT+ LOUT- LIN G6 G7 G8 G9 G10 C1003 100P/NA 0402 +/-10% 50V 2 C485 1 0402 11 R1185 10K 0402 C978 AGND GND 1U/NA 0402 10V +80-20% Q713 DTC144TKA 288202240001 2 3 CAGND CAGND R1 DECT_HP#OPT 1 AGND 8 7 9 2 600Z/100M 2 19 TPA0212_GND TSSOP24_TPA0102 AGND CAGND 5 4 2 3 1 2 1608 2 GND0 GND1 GND2 GND3 LLINEIN LHPIN 30 31 32 33 34 2 1608 2 1608 2 HP/LINE 10 AGND 2 1 SHUTDOWN SEBTL 5 6 DTC144TKA 288202240001 1608 1608 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 2 1U 10V 2 1U 10V 2 1U 10V Q23 1 BYPASS 2 1 DEVICE_DECT 2 600Z/100M 2 600Z/100M 1 1 0 0402 J720 600Z/100M 1 2 GAIN0 GAIN1 1 2 C484 1 0402 C480 1 0402 C493 1 0402 3 R1 2 VDD 2 3 15 L55 J3 L14 L16 7 18 1 AMP_LEFT AMP_LEFT R367 10K 0402 DEVICE_DECT# PC-BEEP 17 20 PVDD0 PVDD1 L754 1 L755 1 DECT_HP#OPT 1 5% 5% 5% 5% ROUT+ ROUT- RIN 2 0402 0402 0402 0402 HDR/MA-2 ACES 85204-0200 291000020206 1 14 RHPIN RLINEIN 2 8 AGND VA C 2 1U 10V +80-20% 1608 1608 1 R1159 R1160 R1161 R391 2 600Z/100M 2 600Z/100M L50 ROUT+ ROUT- 21 16 1 1 C497 1 0402 1U 10V +80-20% 1U 10V +80-20% 1 2 100K 1 2 100K/NA 1 2 100K 1 2 100K/NA L52 U524 20 23 2 AMPVDD AMPVDD 1 CAGND 1 1 2 1U 10V +80-20% 2 C935 2 0402 C950 2 0402 AGND C492 1 0402 AMP_RIGHT AMP_RIGHT 2 20 R1302 1 600Z/100M DEVICE_DECT# AGND 1 GND Q52 AMPVDD 1 2 L67 C977 1U 0402 10V BAW56 288100056017 2 R1 REMARK 0 2 2 OPTIN# 1 AMP_OFF 1 K RLS4148 SPK_OFF# 2 A 2 3 D27 KBC_MUTE D715 3 2 22 D DTC144TKA 288202240001 R454 1K 0402 5% R1158 1.3M 0402 1% DECT_HP#/OPT 0 2 2 Q38 BAT54C DEVICE_DECT# 1 2 R1239 4.7K 0402 5% AMP_SHUTDOWN 3 1 +5V 1 SPK_OFF 1 2 2 2 13,24 3 AMP_OFF +5V 1 EAPD R477 100K 0402 5% R1 D22 1 20 3 AUDIO AMPLIFIER +5V 1 +3V 1 5 DEVICE_DECT# SUBWOOFER AMP(LM4871) +5VS_SUBAMP 2 1 2 22.1K 0402 2 4 R471 D 1M/NA S 0402 5% Q35 2N7002/NA G AMP_SHUTDOWN 2 R451 5% 1 0402 10K/NA DEVICE_DECT D17 A D19 RLS4148 A K R1125 1 K RLS4148 0 0402 2 1 R460 47K/NA 0402 5% SUB_OUTL VO1 VO2 VDD GND5 GND6 GND7 C941 4.7U +80-20% 0805 U19A LMV822 MSOP8 C462 0.1U/NA 0402 +80-20% 50V 1 2 AGND LM4871 LLP8A 2 C930 1U 0402 +80-20% 10V 2 22.1K 0402 0.15U 0603 2464VREF2 5 + RIN_2464 6 - 1% R26 R27 1 1 0 0 2 0805 2 0805 HDR/MA-2 ACES 85204-0200 291000020206 AGND AGND Q30 R1 TP49 2 1 DTC144TKA/NA 20 R511 R510 1 100 2 0402 1% 2 1 2 3K/NA 0402 5% 1U/NA 10V 0805 2464VREF1 2 22.1K 0402 1% R489 D 1M/NA S 0402 5% Q36 2N7002/NA G R459 AGND AGND 2 10U 6.3V 0805 10% 5% 1 0402 10K/NA R463 1 2464VREF2 2 A 22.1K 0402 1% 2 SUB_OUTR SUB_LEFT R491 1 0/NA 2 0402 5% SUB_OUTL SUB_RIGHT R512 1 0/NA 2 0402 5% SUB_OUTR AGND 7 1 1 2464_VREF SUB_OUTR SUB_OUTL 20 SUB_OUTR 20 AGND U19B LMV822 MSOP8 Title 8050D MOTHER B/D AGND Size C Date: 5 J705 1 2 S R462 18K 0402 1% 2 C470 2200P 0402 +/-20% 50V 8 R479 2 1 4 C482 1 ESD0603/NA C500 1 1 2 VA 1 2 D5 2 R461 1 1 2 A SUB_RIGHT 1 2 C479 D USE 2200P 10% 20 GND 2 JO10 USE 3K 1% 0 0402 1 AGND AGND R478 1 GND 6 13 14 15 B JO12 AGND 5 8 1 VA C345 1U/NA 0402 +80-20% 10V +IN -IN BYPASS SHDWN GND GND1 GND2 GND3 GND4 2 AGND 2 AGND - 1% 0.15U 0603 2 1U/NA 10V 0805 AGND 1 3 4 2 1 7 9 10 11 12 2 1 + 2 1 ESD0603/NA 1 1 3 SUB_LEFT 3 1 10.2K 1% 2 2 100U 6.3V 20% 1 20 2464VREF1 R509 R496 0402 1 1 2 8 C490 2 +80-20% 16V R1122 1 22.1K 0603 1% D6 + C951 2 0.22U 2 120Z/100M 2012 U725 1 1 2 3K/NA 0402 5% R507 18K 0402 1% SUB_OUTL C469 0.1U 0402 +80-20% 50V 1 10.2K 1% S C494 2200P 0402 +/-20% 50V R502 0402 C487 2 2 VA SUB_OUTL C483 1 0402 0.22U 2 +80-20% 16V 2 2 1 0 0402 1 R521 1 R506 C496 1 0402 2 USE 3K 1% USE 2200P 10% D B SUB_OUTR +5V L63 1 2 0603 10% 1 C471 1 1000P 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 21 of 34 5 4 3 2 1 J5 13 KBC_PCIRST# 13,19,23 LFRAME# FAN# 3V LEVEL D21 ADEN# FAN_SPEED 2 1 2 GND Processor Hot Protection 2 +VCC_CORE DTC144TKA 288202240001 HPROCHOT# 1 HPROCHOT# 17 15 14 23 22 19 BAT_DATA BAT_CLK 3 2 H8_ENABKL CHARGING 27 26 13 12 23 BATT_LED# 25 KBC_PWRON_VDD3S C133 0.1U 0402 +80-20% 50V 2 GND 2 D 1 2 R1 3 S 1 R381 0402 GP80/SD0 GP81/SD1 GP82/SD2 GP83/SD3 GP84/SD4 GP85/SD5 GP86/SD6 GP87/SD7 GP51/INT20#/S0 GP47/SRDY1#/S1 GP44/RXD GP45/TXD GP70/SIN2 P71/SOUT2 GP72/SCLK2 GP73/SRDY2#/INT21 GP74/INT31 GP75/INT41 GP50/A0 GP52/INT30#/R GP53/INT40#/W GP42/INT0/OBF00 GP43/INT1/OBF01 GP46/SCLK1/OBF1 GP20/FD0/LPCEN GP21/FD1 GP22/FD2/SDA1/RXD1 GP23/FD3/SCL1/TXD1 GP24/FD4 GP25/FD5 GP26/FD6 GP27/FD7 16 18 H8_LIDSW# H8_PWRON H8_PWRON 0 21 R439 1 0402 20 2 Q29 KO0 KO1 KO2 KO3 KO4 KO5 KO6 KO7 KO8 KO9 KO10 KO11 KO12 KO13 KO14 KO15 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 KI0 KI1 KI2 KI3 KI4 KI5 KI6 KI7 62 61 60 59 58 57 56 55 GP76/SDA GP77/SCL GP40/XOUT/PWM2 GP41/XCIN/PWM3 GP56/DA1/PWM01 GP57/DA2/PWM11 GP60/AN0/INT5 GP61/AN1/INT6 GP62/AN2/INT7 GP63/AN3/INT8 GP64/AN4/INT9 GP65/AN5/INT10 GP66/AN6/INT11 GP67/AN7/INT12 GP0/P3REF/FA0 GP1/FA1 GP2/FA2 GP3/FA3 GP4/FA4 GP5/FA5 GP6/FA6 GP7/FA7 GP10/FA8 GP11/FA9 GP12/FA10 GP13/FA11 GP14/FA12 GP15/FA13 GP16/FA14 GP17/FA15 RESET# T_DATA H8_RSMRST ICH_PWRBTN T_CLK 38 37 36 35 34 33 32 31 H8_THRM# H8_WAKE_UP# BATT_G# BATT_R# EXTSMI# CAP# NUM# SCROLL# XIN XOUT 11 10 BLADJ H8_I_CTR 1 80 79 78 77 76 75 74 PWRBTN# KBC_RI# AC_POWER# T_DATA 23 T_CLK 23 SUSC# 13,26,27 BATT_G# BATT_R# EXTSMI# CAP# NUM# SCROLL# AC_POWER# C454 0.1U 0402 +80-20% 50V H8AGND +KBC_CPUCORE H8_RESET# H8_RESET# 28 KBC_X+ 29 KBC_X- 72 R414 1 0 2 5% 0402G_DFS 25 VREF VCC VSS AVSS CNVSS 71 30 73 24 2 S BAT_DATA D G D S Q33 C449 0.1U 0402 +80-20% 50V C448 0.1U 0402 +80-20% 50V C445 10U 0805 6.3V 10% 2N7002 D BAT_CLK D S KBC_RI# Q40 R445 1 0 0402 2 KBC_RI# I_LIMIT I_CTRL R428 1 R483 1 0 0 R450 2 10K/NA 1 0402 2 0402 H8_I_LIMIT 2 0402 H8_I_CTR BLADJ L68 2 C478 0.1U 0402 +80-20% 50V GND 11 16 +3VS BEAD_600Z/100M 0603D 1 2 +3VS 10K*4 4 1206 3 2 1 RP719 TP718 1 TP719 1 FAN_SPEED 14,25 THERM_ERR# THERM_ERR# 6 7 4 9 PWM1 PWM2/SMBALERT PWM3/ADDRESS ENABLE TACH1 TACH2 TACH3 TACH4/ADDRESS SELECT/THERM D1+ D1D2+ D2GND 1 2 2 1 1 13 12 11 10 C869 2200P 0402 +/-20% C728 50V 2200P 0402 +/-20% 50V 2 15 5 8 3 1 FAN# 14 2 2 1 PWRBTN# 0 +2.5VIN/SMBALERT VCC TP720 ADT7460 QSOP16B C450 22P 0402 +/-10% 50V 8MHZ TXC8X4.5 2 1 2 3 4 C871 4.7U 0805 +80-20% CPU_THERMDA 2 32 32 32 32 22*4 RPSOA_8C VDD3 BAT_CLK BAT_DATA R448 1 2.7K R449 1 2.7K BAT_CLK BAT_DATA R419 1 2.7K/NA 2 1% 0402 R455 1 2.7K/NA 2 1% 0402 2 1% 0402 2 1% 0402 0/NA 0402 5% VDD5 R0A add Closed to KB CONN R390 0402 H8_ENABKL R425 0402 H8_THRM# ADD-->R0B +3V 1 10K/NA 2 5% 1 10K/NA 2 5% B +5V R482 2 10K 5% 1 0402 R481 2 10K 5% 1 0402 T_DATA T_CLK 10K 0402 5% KI5 R385 1 0/NA 0402 5% 2 0:for external flash GND H8_SCI R475 0402 1 10K 5% 2 VDD3 GND +3VS H8_PROCHOT# R413 R7 1 1K 0402 5% C9 1000P 0402 +/-20% 50V X7R 2 1 3 VDD3 H8_RSMRST H8_SUSB ICH_PWRBTN 1 H8_ADEN# 2 BATT_DEAD# 3 PWRBTN# 4 5 10 9 8 7 6 RP10KX8 RPSOE_10 RP44 2 4 5 VDD3 TC010-PSS11CET 297004010001 GND 2 10K 5% 1 0402 RP46 KI4 KI5 KI6 KI7 10 9 8 7 6 1 2 3 4 5 VDD3 KI0 KI1 KI2 KI3 A VDD3 GND 1206 4.7K*8 CPU_THERMDC 2 VGA_THERMDA 9 VGA_THERMDC 9 Title 8050D MOTHER B/D Size C 4 13,17,23,25 C BAT_V BAT_T BAT_C BAT_D 0:internal flash 1:external flash C447 22P 0402 +/-10% 50V GND 5 C459 0.1U 0402 +80-20% 50V H8AGND RP45 GND POWER BUTTON +3VS 1 SDA SCL 8 7 6 5 SW2 R1002 U706 16 1 BAT_VOLT BAT_TEMP BAT_CLK BAT_DATA +2.5VS_DDR 2 5 6 7 8 SUSB# GND GND THERMAL SENSOR / FAN CONTROLLER H8_THRM_DATA H8_THRM_CLK R404 1M 2 0402 5% X1 1 2 GND H8AGND A 1 1 I_LIMIT I_CTRL BLADJ 1 32 33 4,12 2 R430 KBC_X+ KBC_MUTE 21 1 S R1 R446 150 0402 1% 1 2 Q49 DTC144TKA SOT23AN_1 288202240001 VDD3 GND 2 0 0402 H8_SUSB D18 BAV70LT1 SOT23N 288100070006 R447 GND 2 R486 1 GND For External flash KBC_X- H8_THRM_CLK 2 ICH_PWRBTN DTC144TKA SOT23AN_1 288202240001 VDD3_AVREF VDD3 GP30/PWM0/FCTRL0 GP31/PWM10/FCTRL1 GP32/FCTRL2 GP33/FCTRL3# GP34/BANK0 GP35/BANK1 GP36/CE# GP37/OE# 2 0 0402 2N7002 13 2 G R473 1 1 12,23 KBC IC :284583950002 F/W ASSY:481677700002 +5VS A20GATE 12,23 12,23 13,24 23 23 23 H8_I_LIMIT H8_PROCHOT# C Version 284583950002 H8_THRM_DATA A A20GATE D20 H8_PWRON_SUSB# 25 25 Q31 R1 K RLS4148/NA PQFP80_0.5MM B 13 ICH_PWRBTN# 0/NA 2 5% 1 12 26,27 VDD3_AVREF GP54/CNTR0 GP55/CNTR1 10K 0402 5% H8_HRCIN# 2 9 8 7 6 5 4 W83L950D +5VS 1 H8_WAKE_UP# 3 13,24 WAKE_UP# 1 0/NA 2 5% 3 12 H8_ENABKL 33 CHARGING R99 R96 33 1M/NA 0402 0402 5% 5% 1 VDD3S R453 2 1 2 C Q26 DTC144TKA SOT23AN_1 288202240001 WAKE_UP# 3 H8_HRCIN# 1 Q706 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 1 R95 10K 0402 5% 1 GND R1 LEARNING 10MIL RLS4148 H8_PROCHOT# 3 SW_VDD3 BATT_DEAD# H8_ADEN# LEARNING H8_SUSB H8_SCI A RLS4148 K 32 +3V K LAD3 LAD2 LAD1 LAD0 R393 1 0 2 0402 SW_VDD3 3 1 25,32 25 HRCIN# DTC144TKA SOT23AN_1 288202240001 1 2 R87 0 0402 5% D GND 3 13,19,23 LAD[0..3] D703 A 1.25MM/ST/MA-3 ACES 85205-0300 291000010303 13 +3VS U16 70 69 68 67 66 65 64 63 LAD[0..3] 1 1 C104 0.1U 0402 +80-20% 50V 2 Q14 SI2301DS D 1 2 3 12 S 1 2 2 1 G R925 10K 0402 DTC144TKA SOT23AN_1 288202240001 R267 0402 11 PCICLK_KBC 13,14,17,19 SERIRQ R88 10K 0402 5% D S GND J707 FAN C94 0.1U 0402 +80-20% 50V 0/NA 2 0402 1 FPC/FFC/1MM/26P ACES 85202-26-00 291000152603 G C93 10U 16V 1206 R394 1 2 BATT_DEAD GND GND +3V GND Q39 13,24 GND +5V +3V Q42 FDV301N SOT23_FET DTC144TKA SOT23AN_1 288202240001 R1 33 R1 2 1 KBD_US/JP# Q27 2 1 SB_THRM# BATT_DEAD# D S H8_RSMRST G 2 H8_SCI H8_THRM# 1 2 1 13 2 13,25 Q32 R1 3 2 1 R424 1 22 0402 5% C453 0.1U 0402 +80-20% 50V GND RSMRST# SCI# 1 1 1 R395 10K 0402 +VCC_CORE +KBC_CPUCORE PULL HIGH at SB END 13,24 DTC144TKA SOT23AN_1 288202240001 2 1 1 +3V 1 1 1 +3V 2 1 1 WINBOND KBC 2 1 1 2 120Z/100M/NA 0805C R1 1 L61 1 1 1 1 Pull HIGH at Other End 2 1 1 VDD3_AVREF 1 1 1 20MIL VDD3 2 1 KO0 KO1 KO2 KO3 KO4 KO5 KO6 KO7 KO8 KO9 KO10 KO11 KO12 KO13 KO14 KO15 KI7 KI6 KI5 KI4 KI3 KI2 KI1 KI0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 1 3 1 C542 100P C540 100P C538 100P C536 100P C534 100P C532 100P C530 100P C528 100P C526 100P C524 100P C522 100P C520 100P 1 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 2 0402 50V 1 1 D C543 100P C541 100P C539 100P C537 100P C535 100P C533 100P C531 100P C529 100P C527 100P C525 100P C523 100P C521 100P 2 KO0 KO1 KO2 KO3 KO4 KO5 KO6 KO7 KO8 KO9 KO10 KO11 KO12 KO13 KO14 KO15 KI7 KI6 KI5 KI4 KI3 KI2 KI1 KI0 Date: 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 22 of 34 5 4 3 2 1 FWH TOUCH_PAD +3V D D 1 GND 0402 +80-20% TP_CLK 1 C902 0.1U 0402 10% 10V GND MODE GNDA VCCA GND VDD OE#/INIT# WE#/LFRAME# NC DQ7/RSV A7/RSV A6/RSV A5/RSV A4/RSV A3/RSV A2/RSV A1/RSV A0/RSV LAD0/DQ0 29 28 27 26 25 24 23 22 21 R364 GND 1 4.7K GND 2 0402 5% GND INIT# LFRAME# 13,19,22 2 SYS BIOS Vendor List: 2 GND ESD0805A/NA R1089 1 SST49LF004A R1084 1.5K 0402 5% R1073 GND 2,13 SST49LF004A : 283467490001 D23 2 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C LAD0 LAD1 LAD2 LAD3 LAD0 LAD1 LAD2 LAD3 HINIT# 1 2 330 0402 5% INIT# C Q718 MMBT3904L 288203904022 B Q708 MMBT3904L 288203904022 B 330 0402 5% C 1 JO21 2 2 JO19 13,19,22 13,19,22 13,19,22 13,19,22 C 2 JO20 GND E GND JO18 +3V DQ1/LAD1 DQ2/LAD2 GND DQ3/LAD3 DQ4/RSV DQ5/RSV DQ6/RSV 1 2 R403 1 8.2K 5% 2 0402 R412 1 8.2K 5% 2 0402 R418 1 8.2K 5% 2 0402 R423 1 8.2K 5% 2 0402 C897 0.1U 0402 10% 10V U15 14 15 16 17 18 19 20 1 1 1 2 5 6 7 8 9 10 11 12 13 C908 4.7U 0603 6.3V +80-20% GND TC010-PSS11CET 297004010001 1 R427 1 8.2K 5% 2 0402 R422 1 8.2K 5% 2 0402 R417 1 4.7K 5% 2 0402 R408 1 4.7K 5% 2 0402 HDR/MA-6 ACES 87151-0607 1 SW_RIGHT 2 4 5 +3V TP_RIGHT 2 SW5 2 C143 C144 C154 C172 47P 47P 47P 47P 0402 0402 0402 0402 +/-10% +/-10% +/-10% +/-10% 50V 50V 50V 50V ESD0805A/NA 1 3 1 2 4 5 TC010-PSS11CET 297004010001 D29 1 2 TP_LEFT R132 1 0 2 5% 0402G_DFS R151 1 0 2 5% 0402G_DFS J4 6 5 4 3 2 1 TP_DATA 2 120Z/100M 1608 2 1 3 SW_LEFT 1 GND TP_VDD 1 L37 SW4 GND 2 120Z/100M 1608 22 T_CLK C 1 1 L36 22 T_DATA miniSMDC050 0.1U 2 50V 4 3 2 1 32 31 30 0.5A/POLYSW C771 1 A8/RSV A9/RSV RESET# VPP VDD R-C#/CLK A10/GPI4 120Z/100M 2012 GND 1 R387 1 8.2K 5% 2 0402 2 E 1 2 F701 2 2 L716 R402 1 8.2K 5% 2 0402 R411 1 8.2K 5% 2 0402 2 +5V 1 11 PCICLK_FWH 13 FWH_PCIRST# GND J8 TP_RIGHT TP56 TP57 1 1 TP_LEFT TP_CLK TP_DATA TP_VDD 1 2 3 4 5 6 7 8 9 10 11 12 LED R415 AC_BATT_LED# 15 HDD_LED# 2 0402 K 15 0 R458 1 CD_LED# 12,22 2 0402 K A 0 R465 1 BATT_G# 2 0402 15 R553 1 0402 2 5% 470 R434 1 0402 2 220/NA 5% R554 1 0402 2 5% 470 A D32 CL-190G 15 When 8050N ADD J722 and DEL J4 B VDD3S 0/NA HDR/MA-12/NA ACES 87151-1207 291000141204 GND R433 1 0402 2 220/NA 5% 2 0402 1 R416 1 D721 CD_LED# HDD_LED# +5V 2 3 IDE_LED# 1 BAW56/NA VDD3S +5V D33 CL-190G 0/NA When 8050 ADD J4 and DEL J722 B D31 VG 4 12,22 R466 1 BATT_R# 2 0402 3 2 R467 1 0402 220/NA 1 0/NA 2 5% VDD3S SR 19-22SRVGC/TR8/NA R441 1 0402 2 5% 470/NA R420 22 NUM# NUM# 2 0402 1 K R555 1 0402 220 2 5% A R556 1 0402 220 2 5% A 0 IDE_LED# +5V +3V D34 CL-190G R421 22 CAP# 22 NUM# 22 SCROLL# 22 CAP# CAP# 2 0402 1 K 0 R426 1 2 0402 D35 CL-190G 0/NA R429 SCROLL# 2 0402 1 K A 0 R432 1 2 0402 2 5% 0/NA R457 AC_BATT_LED# A R557 1 0402 220 D37 CL-190G +3VS +3VS +3VS 2 0402 1 A 0/NA 3 2 R1 74AHC14_V TSSOP14 3 4 U703C 74AHC14_V TSSOP14 5 6 14 U703B U703D 74AHC14_V TSSOP14 9 1 R1152 1M 8 Q719 DTC114TKA 2 0402 5% 2 0402 GND 0/NA 2 1 GND GND 1 R1303 12,22 AC_POWER# 7 288202215001 7 BATT_LED# 1 22 BATT_LED# 7 1 13,17,22,25 SUSB# Q720 DTC114TKA 288202215001 R1 2 14 0 3 12 BATT_POWER# 2 0402 1 14 R468 BATT_POWER# C947 4.7U 0805 +80-20% Title 8050D MOTHER B/D Size C 1 R1140 180K 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 0402 Date: 5% 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 23 of 34 5 4 3 2 1 PULL -HIGH PCI PULL HIGH AGP PULL HIGH +3V 8.2K 8.2K 8.2K 8.2K D 1 1 1 1 R187 R847 R1119 R808 2 2 2 2 0402 0402 0402 0402 PCI_INTA# PCI_INTB# PCI_INTC# PCI_INTD# 7,13 13,17 13,17 13,19 PCI_INTE# PCI_INTF# PCI_INTG# PCI_LOCK# 13,16 13,17,19 13,18 13 GPIO PULL HIGH +3V +3V 8.2K 8.2K 8.2K 8.2K 1 R191 1 R194 1 R841 1 R868 2 0402 2 0402 2 0402 2 0402 12,13 1 1 1 1 1 13 ICH_GPI5 4,7,13 AGPBUSY# R180 R1005 R179 R814 R803 2 2 2 2 2 0402 0402 0402 0402 0402 R186 R207 R802 R201 R200 2 2 2 2 2 0402 0402 0402 0402 0402 PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3# PCI_REQ4# 13,17 13,18 13,19 13,16 13 PCI_GNT0# PCI_GNT1# PCI_GNT3# PCI_GNT4# PCI_GNT2# 13,17 13,18 13,16 13 13,19 CRT_IN# 13 SB_CARD_PME# +3V 8.2K 8.2K 8.2K 8.2K 8.2K CRT_IN# 13,22 KBD_US/JP# 7,13 STP_AGP# 3,13 0402 1 R804 2 8.2K 0402 1 R916 2 10K 5% 2 8.2K ICH_GPI5 0402 1 R815 AGPBUSY# 0402 2 R788 KBD_US/JP# 0402 1 R165 STP_AGP# 0402 2 R780 B/CB# +1.5V 1 20K 1% 2 10K 5% 1 20K/NA 1% 2 8.2K/NA 0402 1 R410 D WHEN USE INTEGRATE VGA DEL ALL RESISTOR VDD3S 100K 1 R837 2 0402 5% 100K 1 R866 2 0402 5% AGP_AD30 4,7 AGP_AD13 4,7 +3V 8.2K 8.2K 8.2K 8.2K 8.2K 1 1 1 1 1 13,22 13 SMBALERT# 2 10K 5% 1 10K 5% 2 10K 5% 2 10K 5% 0402 2 R309 SCI# 0402 1 R464 13,22 WAKE_UP# 0402 1 R382 13,22 +3V 0402 1 R396 EXTSMI# SMBALERT# GND +2.5VS_DDR +2.5VS_DDR_P JS708 1 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 1 1 1 1 1 1 1 R211 R231 R230 R241 R244 R212 R218 2 2 2 2 2 2 2 0402 0402 0402 0402 0402 0402 0402 PCI_FRAME# PCI_SERR# PCI_IRDY# PCI_PERR# PCI_DEVSEL# PCI_TRDY# PCI_STOP# 13,16,17,18,19 13,16,17,19 13,16,17,18,19 13,16,17,18,19 13,16,17,18,19 13,16,17,18,19 13,16,17,18,19 SHORT-SMT4 JS709 2 +VCCP 1 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 13 0402 1 R280 CPUPERF# 2 200 5% 2 8.2K 5% 0402 1 R1004 13,16,17,19 PCLKRUN# GPIO27 0402 1 R282 GPIO28 0402 1 R281 13 GPIO27 13 GPIO28 SPK_OFF 13,21 SPK_OFF R284 1 0 2 5% 0402G_DFS R283 1 0/NA 2 0402 2 8.2K 2 8.2K 0402 1 R905 SHORT-SMT4 JS710 2 1 +3V +3VS C 2 8.2K R897 1 R906 1 0/NA 2 0402 0 2 0402 2 SHORT-SMT4 +3VS_P C VDD3S +1.25V_DDR +1.25V_DDR_P JS711 +3V 1 JS11 2 1 SHORT-SMT4 JS713 2 +3VS VDD3S 2 SHORT-SMT4 JS12 1 2 1 SHORT-SMT4 JS715 2 SHORT-SMT4 1 +3V SHORT-SMT4 R1098 1 10K 0402 5% 14,19 WIRELESS_PD# +1.8V +3V +5VS 1 +5VS_P R843 R851 R840 R842 IDERST# MINIPCI_ACT# GPIO43 GPIO42 2 2 2 2 10K 10K 10K 10K 1 1 1 1 0402 0402 0402 0402 5% 5% 5% 5% 1 7,12,14 7,12,14 7,12,14 7,12,14 PANEL_ID0 PANEL_ID1 PANEL_ID2 PANEL_ID3 1 2 SHORT-SMT4 SHORT-SMT4 JS719 2 +1.35V 1 SHORT-SMT4 JS721 1 2 +3V PANEL_ID0 10K 1 PANEL_ID1 10K 1 PANEL_ID2 10K 1 PANEL_ID3 10K 1 R11 R12 R13 R14 2 2 2 2 0402 0402 0402 0402 2 SHORT-SMT4 JS717 2 JS718 14,15 14,19 14 14 +1.8V_P JS716 2 +1.35V_P JS720 1 2 SHORT-SMT4 JS722 2 SHORT-SMT4 1 SHORT-SMT4 +3V B +1.2V/1.0V_M10 R845 1 R232 1 R215 1 2 10K/NA 0402 0402 2 10K 2 10K/NA 0402 MB_ID0 R846 1 MB_ID1 R239 1 MB_ID2 R221 1 VGA_1.2/1.0 0402 2 10K 2 10K/NA 0402 0402 2 10K MB_ID0 MB_ID1 MB_ID2 1 2 2 SHORT-SMT4 JS725 2 SHORT-SMT4 JS726 2 GND B +1.5V_P JS723 JS724 1 14 14 14 +1.5V 1 1 SHORT-SMT4 SHORT-SMT4 JS727 2 +VCCP 1 +1.05V_P SHORT-SMT4 1.05V JS728 1 2 SHORT-SMT4 JS729 1 2 SHORT-SMT4 JS730 2 1 SHORT-SMT4 A A Title 8050D MOTHER B/D Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 24 of 34 5 4 3 2 1 POWER ON PERPHERIAL CIRCUIT VDD3_AVREF Q48 U14 6 1 5 4 SI2301DS VDD3 +3VS D GND U13 GND SW_VDD3 SW_VDD3 R523 1 0 AMS3107 SOT223 286303107001 13,15 R522 1 0/NA PCIRST#0 2 1 1 2 AME1117 SOT223 R259 1 1K 2 DTC144WK 288202237002 GND GND GND C295 2.2U 0603 +/-10% D GND 2 0402 1% GND GND R253 200 0402 1% 2 0402 5% 1 2 C355 10U 1206 10V 2 0402 5% 2 GND/ADJ 1 22 C342 10U 0805 6.3V 10% UDZ5.6B SOD323 VOUT 1 2 3 OUTPUT 1 2 3 Q47 INPUT C310 0.1U 0402 10% 10V 1 2 GND GND D13 LP2951-02 SO8 R321 10K 0402 5% GND VIN 2 GND 5VTAP OUT ERRGND 2 GND IN SENSE F/B SHUTDN A GND 3 6 1 5 4 1 2 A 2 R525 100K 0402 5% C517 4.7U 0805 +80-20% G D26 UDZS3.6B/NA SOD323 U6 VDD5 U11 8 2 7 3 K 1 1 G G D25 RLZ3.6B/NA MLL34B K K PWR_VDDIN C381 0.1U 0402 +80-20% 50V A 2 S G C383 10U 0805 6.3V 10% S D 1 VDD1.5 VDD3S D LP2951-3.3/NA SO8 R374 10K/NA 0402 5% Q43 SI2301DS 1 5VTAP OUT ERRGND 1 FUSE_1206 3216FF-1 1A-1206 IN SENSE F/B SHUTDN D S 8 2 7 3 1 2 D S F3 1 2 PWR_VDDIN GND GND GND +3V R551 1 0 2 5% 0402G_DFS C717 2.2U 0603 +/-10% C329 1U 0402 +80-20% 10V OD3 1 2 2 1 U7 SI4800DY SO8 1 GND 1 0 1 GND C283 2.2U 0603 +/-10% GND DVMAIN 2 R260 1 22K/NA 2 0402 1% D 2 1 Q17 D Q19 S 2N7002 G 2N7002/NA D S G PWRON_SUSB# S GND 2 S +3VS Q18 DTA144WK/NA SOT23AN_SC70_1 2 D R251 220K 0402 5% GND 0603 3 GND C708 0.1U 0402 +80-20% 50V R2501 1M 0402 5% PWRON_SUSB# R18 10U 6.3V 0805 10% S D C313 1 DVMAIN 5% PWRON_SUSB# C284 2 120Z/100M 2012 G SI2301DS/NA 1 OD3 2 L47 1 3 2 1 Q722 D S 0.047U G B 2 120Z/100M 2012 SI4788CY/NA SO8 8 7 6 5 VCC_ON +2.5V_M10 1 1 DRAIN3 DRAIN1 DRAIN2 GND GND 2N7002 2 2 0402 SOURCE3 SOURCE2 SOURCE1 VIN GND D S GND 1 0 1 1 VCC_ON 2 0402 5% L46 5 6 7 8 2 10U 6.3V 0805 10% R355 1 0/NA 3 For ATI VRAM 4 3 2 1 2 Q701 R17 GND 1 2 1 2 2 C715 R1249 0/NA 0805 R366 10K/NA 0402 5% DTC144TKA/NA U8 GND R707 1K 0402 5% D S C16 0.1U 0402 +80-20% 50V 2 1 2 2 4 C712 0.1U 0402 +80-20% 50V 2 GG GND 1 2 S R705 1 +2.5VS_DDR 1 D S SI2301DS/NA OD5 G 120Z/100M 2 2012 L706 120Z/100M 1 2 2012 2 Q721 2N7002 D S C710 1U 0402 +80-20% 10V 100K 0402 5% D D S GG Q10 +5VS Q25 PWRON_SUSB# 26,28,29,30,31 D GND +3VS S 2 1 GND GND 1 1 1 2 1 C705 10U 0805C 10V 2 1 2 4 2 R1248 0/NA 0805 GND R21 1K 0402 5% 2 100K 0402 5% 1 1 1 2 GND C13 0.1U 0402 +80-20% 50V GND L707 8 7 6 5 G 2 D G R15 1 C486 10U/NA 0805 6.3V 10% PWRON_SUSB# 1 PWRON_SUSB# +3V AO4403 SO8 3 2 1 S D S C706 1U 0402 +80-20% 10V U707 +3VS For Lan 120Z/100M 2 2012 L704 120Z/100M 1 2 2012 C707 2.2U 0603 +/-10% 1 1 +5V L703 8 7 6 5 22 GND R480 1 0 2 5% 0402G_DFS R548 1 0/NA 2 0402 5% 1 +5V_H AO4403 SO8 13,22 R1 U704 3 2 1 H8_RESET# R368 10K/NA 0402 5% 13,17,22,23 SUSB# +5VS C RSMRST# R474 294K/NA 0402 1% R508 100K 0402 5% R362 10K 0402 5% 22 H8_PWRON_SUSB# B GND DTC144TKA/NA H8_RESET# VDD3 1 GND GND 2 VDD3S GND GND 1 R312 100K 0402 5% 809S 2.93V 4 DTC144TKA 288202240001 IMP811 SOT143 C506 0.01U 0402 +80-20% 50V KBC_PWRON_VDD3S 22 2 1 GND 1 2 RESET VCC 4,12,13,17,31 R358 4.7K 0402 5% 2 1 3 1 DTC144TKA 288202240001 1 Q50 R1 0 1 2 5% 0402G_DFS MN PWROK 2 R25 2 2 4 2 3 +3VS Q12 R1 3 R456 4.7K/NA 0402 5% Q34 3 2 RESET# GND VDD3S 2 ADEN# U21 2 K BAS32L VDD3 0 0402 5% 1 22,32 Q44 VDD3 2 120Z/100M/NA 2012 THERM_ERR# 14,22 +3VS 1 ADEN# BAS32L 2 THERM_ERR# 1 2 2 2 A ADEN# K 1 +3VS VCC C326 0.1U 0402 10% 10V R501 1 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C C508 2.2U 0603 +/-10% R531 10K 0402 5% D24 2 2 D7 DTC144TKA 2882022400013 VDD3S R1 R375 10K 0402 5% A 3 4,12,13,17,31 1 G R561 100K 0402 5% 1 2 C24 2.2U 0603 +/-10% 2 120Z/100M 2012 L72 2 1 VDD5 1 G G G 1 1 1 D S D S C D D R1 L71 S R28 100K 0402 5% PWROK SI2301DS VDD5S SI2301DS S 1 VDD5 VDD3 2 Q51 Q13 1 H8 RESET# / RSMRST# PWROK U10 MAX809 SOT23N 286300690001 2 GND 2 0402 GND OD5 5% A A Title 8050D MOTHER B/D Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 25 of 34 5 4 3 2 1 +2.5VS_DDR_P/+1.25V_DDR_P DVMAIN PL716 JS703 1 2 2 1 SHORT-SMT4 D 2 D 1 2 2012 120Z/100M PC791 0.01U 0402 10% 50V 1 GND 1 PC66 0.1U 0805 10% 5 6 PU709A D t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 4 BOOST1 VIN BG1 EXTVCC INTVCC PGND BG2 BOOST2 24 23 22 21 20 19 18 17 G S 1 1 2 3 4 5 6 7 8 PC72 1 K BZV55C2V4/NA SENSE1.25- 1000P 0402 50V 10% 2 2 PR122 15K 0402 1% 1 1 PC76 PR116 100P 11.8K 0402 0402 +/-10% 1% 50V PR113 20.5K 0402 1% 2 PC69 1000P 0402 10% 50V JS6 2 2 PD724 PC798 + 150U 7243 6.3V SENSE1.25+ 2 2 2 2 1 PC75 220P 0402 10% 50V 1 1 2 PC73 220P 0402 10% 50V PR121 1K 0402 1% 2 2 PC74 47P 0402 10% 50V 1 PR124 2K 0402 1% PR117 20K 0402 1% 1 1 2 PR118 43.2K 0402 1% GND PC800 0.1U 0402 +80-20% 50V A S AO4900 SO8 PC797 10U 1210 10V 1 7 8 G 1 1 1 +1.25V_DDR_P .012 2010 1% 2 1 SENSE2.5- PU709B C 2 D 2 1 PC70 PC71 1000P 0402 1 2 10% 50V 1000P GND 0402 50V SENSE2.5+ 10% PR744 2 1.25V_2 1 3.0UH SPC-05703 30% 2 1 S PC790 0.1U 0402 +80-20% 50V PL717 1 2 2 NC1 SW2 TG2 RUN/SS2 SENSE2+ SENSE2NC0 VOSENSE2 1 AO4900 SO8 3 G SW1 TG1 PGOOD RUN/SS1 NC2 SENSE1+ SENSE1NC3 SGND1 SGND2 SGND3 SGND4 SGND5 16 15 14 13 12 11 10 9 VOSENSE1 PLLFLTR PLLIN FCB ITH1 SGND 3.3VOUT ITH2 AO4900 SO8 D 25 26 27 28 29 30 31 32 33 34 35 36 37 1 2 1 PU15 LTC3728L HVQFN32_1 2 2 PU708B 1 2 2 1 A 3.9UH SPC-08045 30% 2 PC787 + 330U 7343 4V 2 3 1 1 6 5 3 1 0.008 2512 1% 2 2 1 K PD723 1 PC789 + 330U/NA 7343 4V PC788 + 330U 7343 4V BZV55C3V3/NA PL715 2 8 7 PR742 1 GND 10U 16V 1206 PC68 0.1U 0402 +80-20% 50V GND S PC795 1000P 0402 10% 50V 2 4.7 0603 1% 2 2 1 1 2 4 GND +2.5VS_DDR_P PC65 0.1U 0805 10% G 1 BAW56 SOT23N PC67 INTVCC12 1 2 0 0402 5% AO4900 SO8 D 1 PD7 PR111 1 +5VS_P PU708A PR110 288100056017 2 2 1 PJL2 PC793 1000P 0402 10% 50V 2 GND GND PR109 4.7 0603 1% JP_NET20 JP_NET20 1 1 1 2 PC796 10U 1210 25V 20%/X5R GND C PC801 0.01U 0402 10% 50V 2 1 PC794 10U 1210 25V 20%/X5R 2 1 2 PC792 0.01U 0402 10% 50V PJL1 PC799 10U 1210 25V 20%/X5R 1 2 1 SHORT-SMT1 B GND PR120 0 0402 5% B 2 VDD5 SGND1 VDD5 1 PR112 100K 0402 1% PQ22 2N7002 R371 0402 1 0/NA 2 5% PR123 1M 0402 1% D S G 25,28,29,30,31 PWRON_SUSB# PQ20 2N7002 R356 0402 1 0 5% 2 SGND1 D S G PQ21 2N7002 C367 0.1U/NA 0402 +80-20% 50V PR115 1M 0402 1% 2 2 SGND1 1 1 S 2 2 C382 0.1U/NA 0402 +80-20% 50V PQ23 2N7002 D S G 1 2 D 0 5% S 1 1 22,27 H8_PWRON 13,22,27 SUSC# R369 0402 S D S 2 D S D 2 G INTVCC1 2 PR119 10K 0402 1% D 1 1 PR114 100K 0402 1% SGND1 A A Title 8050D MOTHER B/D Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 26 of 34 5 4 3 2 1 +3VS_P/+5VS_P DVMAIN PL701 JS704 1 2 1 2 2012 120Z/100M 2 1 SHORT-SMT4 D 2 D PC710 0.01U 0402 10% 50V 1 GND PC705 10U 1210 25V 20%/X5R 1 2 1 1 5 6 PU701A 24 23 22 21 20 19 18 17 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C AO4914 SO8 S 3 2 1 1 2 3 4 5 6 7 8 1 PC717 0.1U 0402 +80-20% 50V 1 1 2 PR36 19.6K 0402 1% 2 1 2 1 2 K SENSE5V- 1000P 0402 50V 10% 107K PC26 0402 47P 1% 0402 10% 50V 2 2 12 1 PR55 200K 0402 1% 2 2 2 PC23 47P 0402 10% 50V PC25 180P 0402 10% 50V PD707 BZV55B5V6/NA PC712 + 150U 7343 6.3V SENSE5V+ 2 2 1 1 1 PR46 2K 0402 1% PR41 20K 0402 1% PC24 180P 0402 10% 50V PR54 200K 0402 1% PC713 + 150U/NA 7343 6.3V PC721 10U 1210 10V A S PC19 2 PR42 63.4K 0402 5% GND 2 AO4914 SO8 G PR35 1 1 1 .012 2010 1% PU701B 2 1 SENSE3- +5VS_P 1 D C 2 2 PL702 10UH D124C 20% 2 1 PC17 PC20 1000P 0402 1 2 10% 50V 1000P GND 0402 50V SENSE3+ 10% PR707 2 5V_21 1 2 S PC737 0.1U 0402 +80-20% 50V NC1 SW2 TG2 RUN/SS2 SENSE2+ SENSE2NC0 VOSENSE2 1 1 1 2 SW1 TG1 PGOOD RUN/SS1 NC2 SENSE1+ SENSE1NC3 SGND1 SGND2 SGND3 SGND4 SGND5 16 15 14 13 12 11 10 9 1 AO4900 SO8 D 25 26 27 28 29 30 31 32 33 34 35 36 37 2 PU702B 8 7 PL703 10UH D124C 20% G 2 D G 4 BOOST1 VIN BG1 EXTVCC INTVCC PGND BG2 BOOST2 2 1 2 1 PC7 0.1U 0805 10% 7 8 1 .012 2010 1% K PU2 LTC3728L HVQFN32_1 VOSENSE1 PLLFLTR PLLIN FCB ITH1 SGND 3.3VOUT ITH2 2 +3VS_P A 2 3 1 1 2 3 2 GND PC725 + 150U/NA 7343 6.3V 10U 16V 1206 PC10 0.1U 0402 +80-20% 50V GND S GND 1 6 5 1 4 PR711 BZV55C4V3/NA PC4 0.1U 0805 10% G PC707 1000P 0402 10% 50V 2 4.7 0603 1% 2 2 1 2 5% AO4900 SO8 D 2 BAW56 SOT23N PC8 INTVCC02 1 PC706 1000P 0402 10% 50V 0 0402 PU702A JP_NET20 PD708 2 PD1 PR11 1 +5VS_P 1 1 4.7 0603 1% PJL4 PC719 + 150U 7343 6.3V JP_NET20 PR2 288100056017 2 2 1 1 PJL3 PC704 10U 1210 25V 20%/X5R GND GND PR3 GND C PC708 0.01U 0402 10% 50V 2 1 PC709 0.01U 0402 10% 50V 2 2 1 1 PC703 10U 1210 25V 20%/X5R PC14 1000P 0402 10% 50V JS1 1 2 1 1 SHORT-SMT1 D S G INTVCC0 D S G PQ4 2N7002 S S B SGND0 D PQ3 2N7002 GND PR48 0/NA 0402 5% 2 PR47 10K 0402 1% 2 D B VDD5 PR9 100K 0402 1% SGND0 1 1 VDD5 SGND0 2 2 PR10 100K 0402 1% 2 G 1 1 PR27 1M 0402 1% 2 PR26 1M 0402 1% 2 1 2 C23 0.1U/NA 0402 +80-20% 50V 2N7002 G 1 0 5% 2 1 D S PR25 0402 1 0 5% R23 0402 1 0/NA 2 5% 2 H8_PWRON 22,26 SUSC# 13,22,26 S R24 0402 PQ1 2N7002 S 22,26 H8_PWRON D D PQ2 D S C22 0.1U/NA 0402 +80-20% 50V SGND0 A A SGND0 Title 8050D MOTHER B/D Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 27 of 34 5 4 3 2 1 +1.5V_P/+1.05V_P DVMAIN PL3 JS10 2 1 SHORT-SMT4 1 1 2 D 2 2012 120Z/100M PC31 0.01U 0402 10% 50V D 1 2 GND SENSE1.5+ 2 1 K 2 1 2 2 1 2 PC724 1000P 0402 10% 50V JS701 1 B 2 GND 2 SGND3 1 2 INTVCC3 D PR724 10K 0402 1% D S PQ703 2N7002 S PQ706 2N7002 SGND3 S 1 1 PR730 1M 0402 1% 2 2 BZV55C2V4/NA SENSE1.05- PC735 100P 0402 +/-10% 50V PR722 20K PR727 15K 0402 0402 1% 1% PR723 0/NA 0402 5% D 1 2 D D S G C714 0.1U/NA 0402 +80-20% 50V PD716 PC742 + 220U/NA 7343 4V SENSE1.05+ 1 2 G 2 PC746 0.1U 0402 +80-20% 50V 1 PC734 220P 0402 10% 50V 1 PQ705 2N7002 S D S SGND3 PR733 100K 0402 1% 0 5% 1 5 6 2 AO4900 SO8 SHORT-SMT1 G 1 PC749 + 220U 7343 4V 1 2 1 12 1 2 2 2 VDD5 R714 0402 +1.05V_P S 2 2 PR717 0 0402 5% 25,26,29,30,31 PWRON_SUSB# 1 2 2 1 24 23 22 21 20 19 18 17 1 1 PC736 100P 0402 +/-10% 50V PC738 180P 0402 10% 25V PR728 15K 0402 1% 2 1 PR725 2K 0402 1% PR726 20K 0402 1% 31 VCCP_PWRGD PU6B 2 .012 2010 1% 2 PC727 1000P 0402 50V 10% PR721 6.49K 0402 1% 2 PR718 18K 0402 1% +3VS_P GND 1 3.9UH SPC-08045 30% 1 D 1000P GND 0402 50V 10% 1 B PR732 2 G 1 SENSE1.5- PL707 1 A 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1 1000P 0402 50V 10% NC1 SW2 TG2 RUN/SS2 SENSE2+ SENSE2NC0 VOSENSE2 1 2 PC731 PC726 1 1 2 S SW1 TG1 PGOOD RUN/SS1 NC2 SENSE1+ SENSE1NC3 SGND1 SGND2 SGND3 SGND4 SGND5 1 D PC730 0.1U 0402 +80-20% 50V PR715 100K 0402 1% AO4900 SO8 3 AO4900 SO8 25 26 27 28 29 30 31 32 33 34 35 36 37 C S 7 8 PU4B 1 2 1 K A 2 PC728 PC729 + 220U/NA + 220U 7343 7343 4V 4V 4 1 2 3.9UH SPC-08045 30% 2 PD710 PU6A D G 2 1 G BZV55C2V4/NA PC714 0.1U 0805 10% VOSENSE1 PLLFLTR PLLIN FCB ITH1 SGND 3.3VOUT ITH2 2 .012 2010 1% PU703 LTC3728L HVQFN32_1 BOOST1 VIN BG1 EXTVCC INTVCC PGND BG2 BOOST2 PL706 8 7 1 2 3 1 2 GND +1.5V_P 10U 16V 1206 PC718 0.1U 0402 +80-20% 50V GND 3 C PR719 PC715 0.1U 0805 10% 2 4 S GND t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 1 1 2 1 G PC30 1000P 0402 10% 50V 4.7 0603 1% 2 6 5 AO4900 SO8 2 1 2 2 0 0402 5% PU4A D 1 BAW56 SOT23N PC716 INTVCC32 1 PC40 1000P 0402 10% 50V 2 1 1 PD705 PR713 +5VS_P PR708 288100056017 2 4.7 0603 1% GND JP_NET20 JP_NET20 GND GND PR709 1 PJL6 PJL5 PC739 10U 1210 25V 20%/X5R 1 PC744 10U 1210 25V 20%/X5R 2 2 2 PC743 10U 1210 25V 20%/X5R 2 1 1 1 2 PC32 0.01U 0402 10% 50V PC38 0.01U 0402 10% 50V SGND3 A A Title 8050D MOTHER B/D Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 28 of 34 5 4 3 2 1 +1.8V_P/+1.35V_P DVMAIN PL712 JS706 2 1 2 2012 120Z/100M PC765 0.01U 0402 10% 50V 2 SHORT-SMT4 1 1 D D 2 GND 1 24 23 22 21 20 19 18 17 2 1 AO4900 SO8 PC780 0.1U 0402 +80-20% 50V 1 1 1 1 1 SENSE1.2- 1000P 0402 50V 10% 2 2 2 2 2 2 1 12 1 2 PR99 19.6K 0402 1% BZV55C2V4/NA PC782 + 150U 7343 6.3V SENSE1.2+ 2 2 PR96 13.7K 0402 PC62 1% 100P 0402 PR107 +/-10% 50V 15K 0402 PR97 1% 19.6K 0402 1% PC63 180P 0402 10% 50V K 1 2 PR101 2K 0402 1% PC60 100P 0402 +/-10% 50V PC61 180P 0402 10% 50V PR105 15K 0402 1% PD722 2 S PC55 1000P 0402 10% 50V JS3 1 2 B 1 GND PR103 0 0402 5% 2 1 2 SGND2 2 MCH_PG PC783 + 150U/NA 7343 6.3V SHORT-SMT1 PR94 31 5 6 2 1 2 3 4 5 6 7 8 1 2 2 1 PR93 100K 0402 1% B +1.35V_P PC57 2 PR98 24.9K 0402 1% +3VS_P 2 .012 2010 1% D 1 1 1 2 1.2V_2 1 3.0UH SPC-06703 30% PU707B C PR741 A 1 SENSE1.8- PL714 G 1 GND AO4900 SO8 1 2 2 BZV55C2V4/NA PC56 PC59 3300P 0402 1 2 10% 50V 1000P GND 0402 50V SENSE1.8+ 10% 16 15 14 13 12 11 10 9 1 1 1 1 K A 2 S PC767 0.1U 0402 +80-20% 50V NC1 SW2 TG2 RUN/SS2 SENSE2+ SENSE2NC0 VOSENSE2 2 AO4900 SO8 SW1 TG1 PGOOD RUN/SS1 NC2 SENSE1+ SENSE1NC3 SGND1 SGND2 SGND3 SGND4 SGND5 1 PU705B D 25 26 27 28 29 30 31 32 33 34 35 36 37 2 3.0UH SPC-06703 30% 2 PC770 + 150U 7343 6.3V S 3 2 G PD719 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C PU707A D G 4 7 8 1 .012 2010 1% PC52 0.1U 0805 10% VOSENSE1 PLLFLTR PLLIN FCB ITH1 SGND 3.3VOUT ITH2 2 PU14 LTC3728L HVQFN32_1 BOOST1 VIN BG1 EXTVCC INTVCC PGND BG2 BOOST2 3 PL713 1 8 7 PR739 +1.8V_P PC54 0.1U 0402 +80-20% 50V GND GND C PC51 0.1U 0805 10% 2 4 S GND 10U 16V 1206 1 6 5 1 1 2 1 G PC776 1000P 0402 10% 50V 2 4.7 0603 1% 1 2 AO4900 SO8 D 2 0 0402 5% PU705A 1 BAW56 SOT23N PC53 INTVCC22 1 PC777 1000P 0402 10% 50V 3 1 +5VS_P JP_NET20 1 PD6 PR92 PJL8 PR90 288100056017 2 4.7 0603 1% GND 1 GND PR91 1 JP_NET20 2 2 PC779 10U 1210 25V 20%/X5R 2 2 PC774 10U 1210 25V 20%/X5R 2 2 PC50 0.01U 0402 10% 50V 1 1 1 1 PJL7 PC766 0.01U 0402 10% 50V 0 0402 5% 1 2 INTVCC2 PR102 10K 0402 1% D VDD5 D S PQ17 2N7002 D S 1 G PR95 100K 0402 1% 2 SGND2 D S G PQ16 2N7002 A D S A 2 D S G PR106 1M 0402 1% SGND2 2 2 C142 0.1U/NA 0402 +80-20% 50V PQ18 2N7002 S 0 5% 1 1 1 25,26,28,30,31 PWRON_SUSB# R103 0402 Title 8050D MOTHER B/D SGND2 Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 29 of 34 5 4 3 2 1 +1.2V/1.0V_M10 DVMAIN PL718 D 2 PJL10 PC805 10U 1210 25V 20%/X5R 1 JP_NET20 2 PC804 10U 1210 25V 20%/X5R 1 PC803 10U 1210 25V 20%/X5R 1 1 1 2 GND PC806 0.01U 0402 10% 50V 2 1 GND PR72 1M 0402 5% GND A 2 PC64 4.7 0603 1% 10U 16V 1206 GND 2 5 6 7 8 4 14 13 12 11 10 9 8 PL719 PU712 AO4410 SO8 288204410010 G 4 2 2.2UH IHLP5050CE-01 20% PC814 + 330U/NA 7343 4V PC811 + 330U 7343 4V PC815 + 330U 7343 4V 2 PD727 EC31QS04-TE12L/NA DC2010 PD726 PC816 BZV55C2V4/NA 0.1U 0402 +80-20% 50V A K 1 2 3 2 S K D A 1 1 1 2 1 2 PC79 0.1U 0402 +80-20% 50V 2 PR126 8.2K 0402 5% 1 1 SC1470 TSSOP14 PC78 0.01U 0402 10% 50V +1.2V/1.0V_M10 S 1 2 3 BST DH LX ILIM VDDP DL PGND EN/PSV VIN VOUT VCCA FB PGOOD AGND 2 SGND7 SI4800DY SO8 G PU16 1 2 3 4 5 6 7 C PU710 D 1 PC77 0.1U/NA 0402 +80-20% 50V PC81 0.1U 0805 10% 5 6 7 8 2 1 1 1 PR125 0402 0 2 5% 2 2 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C PR108 GND 1 1 EC10QS04 2 2 1 PD725 PC37 0.1U 0402 +80-20% 50V K 2 10 0402 5% 25,26,28,29,31 PWRON_SUSB# GND +5VS_P PR100 1 C PC807 1000P 0402 10% 50V 1 2 2 2012 120Z/100M PC802 0.01U 0402 10% 50V 2 1 1 2 SHORT-SMT4 2 JS707 1 1 D JS9 1 2 SHORT-SMT1 B B GND SGND7 2 D S G 2 PR130 100K 0402 1% PQ19 2N7002 S 1 1 7 SW_1.5V/1.25V PR129 10K 0402 1% 2 PR127 10K 0402 1% 2 D 2 PR128 24.9K 0402 1% 1 1 1 PC80 0.1U 0402 10% 10V SGND7 SGND7 A A Title 8050D MOTHER B/D Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 30 of 34 5 4 3 +5VS_P 2 1 1 1 CPU_CORE MCH_PG 29 VRMPWRGD 13 2 PR5 10 0402 1% 2 PR4 10K 0402 1% PR6 1 2 1 1 2 2 1 2 3 5 6 7 8 S1- 4 S PR43 499K 0402 1% 2 1 1 2 2 S C CORE_CLKEN# 11 1 PR60 1 2 1 2 2 2 PWROK 4,12,13,17,25 PR73 0/NA 0402 5% E GND_A GND_A 1 PQ10 MMBT3904L 288203904022 B 43.2K 0402 1% PC35 1U 0402 +80-20% 10V GND_A A 1 PQ7 2N7002 SOT23_FET 2 PR56 0 0402 5% PR68 1.91K/NA 0402 1% 2 PR58 4.12K 0402 1% 1 PR50 1M 0402 1% S PQ5 2N7002 SOT23_FET 2 D S VCCP_PWRGD 28 S 1 PC27 100P 0402 +/-10% 50V 2 2 PR62 1M 0402 1% GND_A PC28 3300P 0402 10% 50V 2 C26 0.1U/NA 0402 +80-20% 50V PR66 80.6K 0402 1% 1 D 2 1 2 0 0402 5% D S G 1 2 PQ8 2N7002 SOT23_FET E 1 RUN/SS D PR61 1 D S PQ9 MMBT3904L 288203904022 B 1 VDD3 2 PR51 2K/NA 0402 1% PR59 1M 0402 1% G PR49 100K 0402 1% 2 PR57 0 0402 5% 2 C PR64 249K/NA 0402 1% 2 2 1 1 1 1 2 2 1 PR731 2K 0402 1% 1 1 2 1 PR729 249K 0402 1% VDD5 1 VDD3 VDD3 VID0 PC29 1000P 0402 10% 50V G 25,26,28,29,30 PWRON_SUSB# B +3V +3VS VID1 D 1 VID2 VID0 VID1 VID2 VID3 VID4 VID5 A VOS- 2 PR104 0 0402 5% GND VID3 GND_A VID[0..5] BZV55C2V4/NA 2 SHORT-SMT1 VID4 PR53 1K 0402 1% PC22 100P/NA 0402 +/-10% 50V PD720 PC781 + 220U 7243 2V PC775 + 220U 7243 2V JS2 1 VID5 2 2 2 PC12 0.1U 0402 +80-20% 50V A PC786 + 220U/NA 7243 2V 1 2 PC13 10U 1206 10V K EC31QS04-TE12L DC2010 PR34 0 0402 5% PR40 0 0402 5% RUN/SS 1 1 1 2 PR52 0 0402 5% PC784 + 220U 7243 2V PD718 1 1 2 3 S 1 2 3 S PR33 0 0402 5% 2 2 PC773 0.1U 0402 +80-20% 50V 2 1 PR44 0 0402 5% PC778 + 220U 7243 2V PC785 + 220U/NA 7243 2V K 4 S1+ PU11 FDS7788 SO8 D G 1 1 2 3 PU13 FDS7788 SO8 1 1 2 3 4 D G 1 PR31 0 0402 5% LTC3734 HVQFN32 PU12 FDS7788 SO8 C 2 2 1 D G 1 +VCC_CORE 2 2 0.68UH IHLP-5050CE 15% GND 17 1 PR16 1.3M 04021 1% PR17 12.7K 0402 1% 1 2 PC58 1000P 0402 +/-20% 50V PR740 .001 2512C 1% 1 S GND_A VID[0..5] 1 1 2 1 2 2 2 1 1 1 5 6 7 8 S A 2 S 1 18 2 2 56.2K 0402 1 1% 13.3K 0402 1% 3 PJL9 JP_NET20 2 19 2 2 PC751 0.01U 0402 10% 50V GND PL711 +5VS_P 1 2 1 PC752 10U 1210 25V 20% 1 20 1 PR19 PC757 10U 1210 25V 20% 2 21 NC 16 VID2 VID0 VID1 15 14 9 2 1 2 PC5 100K 1000P0402 0402 1% +80-20% 50V B PC753 10U 1210 25V 20% PU10 FDS6694 SO8 D G 1 2 3 VID3 PU8 FDS6694/NA SO8 4 5 6 7 8 RDPRSLP 22 5 6 7 8 VID4 4 23 PR15 2 GND_A PC754 10U 1210 25V 20% t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 24 GND_A PR12 5 6 7 8 5 6 7 8 BOOST PGOOD MCH_PG VFB SVCC VID5 SENSERDPSLP SENSE+ RBOOT 8 13 7 PGND PR39 2.32K 0402 1% 1 2 1 2 25 26 27 28 29 30 31 DPRSLPVR BG SGND 6 1 FREQSET STP_CPUB 5 PU9 D FDS6694 G SO8 4 D PVCC ITH 2 PR38 10 0402 1% 4 RUN/SS 1 2 1 PC750 10U 1210 25V 20% GND G TG 12 13.3K 0402 1% GND_A PC21 1000P 0402 10% 50V 2 PR37 10 0402 1% PC755 10U 1210 25V 20% GND SW OAOUT GND_A 1 2 PL4 120Z/100M 2012 PC41 1000P 0402 +/-20% 50V PU3 VOA- 3 11 2 C 1 1 1 A 1 2 PR29 1 32 33 2 2 GND_A PC11 220P 0402 10% 50V 1 VOA+ 10 1 PR28 576K 0402 1% PR18 1 0402 1% 2 2 PC18 1000P 0402 50V 2 +80-20% 1 2 PC9 0.1U 0805 X7R PR8 4.7 0603 1% 2 PSIB PR30 100K 0402 VOS-1% 1 EC10QS04 SGND1 2 2 7A/24VDC 1 DD_CPU 1 PF2 PD706 1 1 1 2 PR710 1.96K 0402 1% +3V 2 PR13 0 0402 5% K 1 1 PR32 0 0402 5% S1- +5VS_P PL5 120Z/100M 2012 1 3,11,13 STOP_CPU# S1+ DVMAIN 2 2 0 0402 5% 2 PM_PS PC15 100P 0402 +/-10% 50V PR712 0 0402 5% 2 1 13,14 DPRSLPVR 2 1U 0402 10V +80-20% 2 PR14 D PR7 0 0402 5% 2 GND_A 2 2.2K 0402 1% 2 1 1 1 PC6 D PD4 GND_A Title 8050D MOTHER B/D 2 3 Size C 1 BAT54C 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com Date: 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 31 of 34 5 4 3 2 VMAIN/DISCHARGE 1 PWR_VDDIN PD704 2 PD702 1 3 3 2 1 D PL1 120Z/100M 2012 PQ701 AO4407 SO8 DVMAIN 33 PD703 1 3 PR720 1 PR71 226K 0402 1% 2 GND 2 PC1 0.01U 0402 10% 50V G 1 3 2 1 2 1 2 1 2 2 1 2 1 33 DTC144WK 288202237002 PC733 0.01U 0402 +80-20% 50V PC732 1000P 0402 +/-20% 50V PL705 120Z/100M 2012 GND 1 PC3 1U 0805 10V B2 2 PC722 0.01U 0402 10% 50V 1 2 GND 3 + 2 - 4 PC723 0.1U 0402 +80-20% 50V 1 B PU5A LMV393M SSOP8 GND GND PR23 1 VDD5 22 8 BAT_V PR714 100K 0402 1% 22 PC16 0.1U 0402 +80-20% 50V 2 PR21 20K 0402 1% PR716 499K 0402 1% 2 2 BAT_T 1 B1 R/A-7P-2.5MM SUYIN 250233-MR007G123ZU GND 1 GND PR20 4.99K 0402 1% GNDB 33 2 PC720 0.01U 0402 10% 50V 2 7 6 5 4 3 2 1 BATT 1 J703 B3 1 PL704 120Z/100M 2012 1 1 2 VDD3S 1 1 7A/24VDC 2 1 2 PF702 1 2 2 1 22 2 PQ24 2 GND B BATT GND GND 7 6 5 4 3 2 1 C D PQ6 S 2N7002 SOT23_FET GND I_LIMIT 1 5 6 7 8 D 2 22,25 1 ADEN# 1 2 PR1 10 0402 5% OPEN-SMT4 2 2 1 PR45 33K 0402 5% PJO701 2 GND1 GND0 MAX4173FEUT-T SOT26 PC86 0.01U 0402 +80-20% 50V GND S OUT 3 1 2 3 1 2 1 6 VCC 1 RS+ RS- PQ702 2N7002 S PR705 1M 0402 5% PU1 4 5 D S G 1 GND PC740 0.01U 0402 10% 50V 4 GND D 1 1 C PQ704 AO4407 SO8 t t n e e r c m e u S c c Do a iT ial M t n e id f n o C LEARNING 22 LEARNING PC711 1000P 0402 +/-20% 50V 2 100K 0402 5% 1 2 SPARKGAP_6 PC85 1000P 0402 +/-20% 50V G 2 PR703 100K 0402 5% JO2 SPARKGAP_6 PC84 1000P 0402 +/-20% 50V D JO1 PC83 0.01U 0402 +80-20% 50V 2 1 PC82 0.01U 0402 +80-20% 50V 2 2 PR706 4.7K 0805 PR704 4.7K 0805 2 PC821 1000P 0402 +/-20% 50V 1 SBM1040 1 1 PC820 1000P 0402 +/-20% 50V 2 1 PC819 0.01U 0402 +80-20% 50V 2 PC818 0.01U 0402 +80-20% 50V 2 1 1 1 2 2 PR702 470K 0402 5% A PD701 RLZ24D MLL34B 1 K PR701 .01 2512 1% 1 1 2 3 4 PC702 0.01U 0402 10% 50V ADINP 8 7 6 5 G PC701 1U 0805 25V A4 2 D PL2 120Z/100M PC2 2012 0.01U 0402 10% 50V 1 3 2 1 S 2 A3 1 2 2 1 1 2 A1 7A/24VDC A2 2 2 1 OPEN-SMT4 PF1 1 JACK-2P 331910002006 2 4 PJ701 2DC-S107B200 JO701 1 S 2 D BAV70LT1 288100070006 BAV70LT1 288100070006 2 0 0402 5% PR24 1 2 PD2 0 0402 5% BAT_C 22 BAT_D 22 2 3 VDD3 1 PD3 BAV99 2 288100099012 3 VDD3 2 2 1 JO11 SPARKGAP_6 A BAV99 288100099012 JP1 SPARKGAP_6 A 1 1 GND GND GND GND Title 8050D MOTHER B/D Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 32 of 34 5 4 3 2 1 CHARGING PQ707 AO4407 SO8 PL709 32 K BZV55C15V PD711 RLZ20C/NA MLL34B 1 1 1 PC39 PR75 20K 1000P 0402 0402 0.1% 50V 10% 2IN+ A 2 A PC741 10U 1210 25V BATT EC31QS04 DC2010 PD709 EC31QS04 DC2010 E GND GND 2 PR82 10K 0402 1% PR84 7.5K 0402 5% 2 1 PR79 124K 0402 1% 1 2 2 PR81 1 2 1 2 1 PC47 1000P 0402 10% 50V 2 PC44 PC45 REF C 0.1U 0402 16V 10% 0.1U 0402 50V +80-20% PR77 2.49K 0402 1% 6.19K 0402 1% PR80 1 2 .02 2512 1% GND GNDB 2 63.4K/NA 0402 5% PJS1 2 PR78 1 22 I_CTRL B PR22 1 2 1 0.01U 0402 50V +80-20% OPEN-SMT4 1 PR83 100K 0402 5% 2 2 2 PC42 1 1 1 1 0.01U 0402 50V +80-20% PC46 1U 0805 10V G 1 1 22 CHARGING PR85 0 0402 5% PC43 TL594C SO16 2 PJ1 PQ12 D 2N7002 S SOT23_FET S 1 2 E1 C1 E2 GND C2 RT VCC CT OUTPUTCTRL DTC REF FEEDBACK 2IN1IN2IN+ 1IN+ 8 7 6 5 4 3 2 1 2 2IN+ GND t t n e e r c m e u S c c Do a iT ial M t n e id f n o C D PU7 9 10 11 12 13 14 15 16 PC48 0.01U 0402 10% 50V PR76 249K 0402 1% 2 1 3 2 PR74 13.7K 0402 0.1% PC49 0.01U/NA 0402 50V +80-20% 1 2 1 D C GND A BAS32L MLL34B PQ14 D 2N7002 S SOT23_FET S G K PQ13 DTA144WK SOT23AN_1 2 22 CHARGING 2 PR86 0 1206 5% 2 PD5 1 1 1 GND 3.0UH PC758 SPC-06703 0.01U 30% 0402 10% 50V 12.65V PD713 K A 2 PD714 2 PQ15 MMBT2222A 288202222019 B 2 K 1 PR89 100K 0402 5% PC756 10U 1210 25V 2 2 1 33UH CDRH124 1 K L5 2 1 1 A PL710 L4 4 1 PR88 4.7K 0603 2 PR87 4.7K 0603 C PC745 10U 1210 25V 2 2 PC748 0.01U 0402 10% 50V 1 1 1 1 2 D 8 7 6 5 G PC747 0.01U 0402 10% 50V D TR/3216FF-3A 3 2 1 L3 S 32 ADINP PL708 1 2 BEAD_120Z/100M 0805D L2 2 2 PF703 1 2 D 1 2 B SHORT-SMT3 0 0402 5% DVMAIN PR65 590K 0402 1% 2 8 PC33 0.1U 0402 +80-20% 50V 7 PU5B LMV393M SSOP8 PR63 80.6K 0402 5% BATT_DEAD 22 =8.56V 1 - PC36 0.01U 0402 10% 50V 2 2 3 SOT23N + 6 2 1 5 4 SCK431LCSK-.5 1 1 2 1.25V PQ11 PR69 100K 0402 5% 2 GND 1 1 PC34 0.01U 0402 10% 50V 2 2 PR70 3.3K 0402 5% 1 1 VDD5 A A GND GND Title 8050D MOTHER B/D Size C Date: 5 4 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 33 of 34 5 4 3 2 1 VGA_THRMDA/VGA_THRMDC 8050 BLOCK DIAGRAM CPU_THRMDA/CPU_THRMDC LCD PANEL (XGA) CLK_ITP_CPU+/- 100MHZ HCLK_CPU+/- 100MHZ SIO_48M (DEBUG CARD ONLY) CPU INTEL BANIAS/DOTHAN 14.318MHZ LVDS D D CLOCK GENERATOR HOST 400MHZ 14M_CODEC ICS950810 BATT-Adapter RGB +2.5V/+1.25V D/D Charger TL-594C 66M_MCH I-LIMIT OP D/D CPU Core LTC3734 DREFCLK_48MHZ MAX4173F LVDS/NA RGB/NA HCLK_NB+/- 100MHZ North Bridge DIMM1 DIMM0 CLK_DDR2+/- 855GME CLK_DDR1+/CLK_DDR0+/- AGP VGA_M10 PCICLK_FWH DDR 266 C TV +3V/+5V t t n e e r c m e u S c c Do a iT ial M t n e id f n o C 66M_ICH USB 0~2 66MHZ 66MHZ CDROM +1.5V/+1.05V C D/D Power LTC3728L +1.2V/1.0V +1.8V /+1.35V AC-Adapter D/D HDD PRIMARY IDE 14M_CODEC (CLK GEN) PCI AC97 B 24.576MHZ / NA 25MHZ PCICLK_LAN SMBUS D/D Power SC1470 VRAM 16MBx4 SECONDARY IDE ICH4-M PCICLK_MINIPCI 33MHZ 33MHZ PCI_1394_CLK PCI_CRAD_CLK LPC BUS D/D Power LTC3728L 32.768KHZ Sourth Bridge 33MHZ 14M_ICH x3 ADT7460 I -LIMIT 66M_AGP USBCLK_ICH 48MHZ PCICLK_ICH 33MHZ Fan D/D Power LTC3728L CH7011 27MHZ CLK_DDR3+/CLK_DDR4+/CLK_DDR5+/- B D/D Power LTC3728L CRT AUDIO CODEC ALC655 MDC MODULE RTL8100CL PH163112 Keyboard BIOS IEEE1394 SYSTEM BIOS WINBOND VIA VT6307L W83L950D 8MHZ PCMCIA CARD READER AMPLIFIER MINIPCI CP2211 TPA0212 EXT MIC. CB710 LINE IN INT MIC 512K KEY MATRIX PS/2 LM4871 A HP JACK NA PAD Internal Keyboard PCMCIA/ CARDBUS SLOT CardReader Transition Board Title 8050D MOTHER B/D Size C Date: 5 4 A SUB WOOFER CARD REARDER SOCKET CABLE TOUCH SPEAKER RJ45/ RJ11 24.576MHZ I -LIMIT SPEAKER 3 PDF created with FinePrint pdfFactory trial version http://www.fineprint.com 2 Document Number Rev R01 PCB 316680900001/ASSY 411682700001 Wednesday, December 31, 2003 1 Sheet 34 of 34 REFERENCE MATERIAL Intel Mobile Pentium-M Processor/BANIAS Processor Intel, INC. “Intel 855GME North Bridge” Intel, INC. “Intel ICH-4 South Bridge” Intel, INC. WINBOND KBC WINBOND, LTD. Clock Syntherizer ICS,INC VT6307L IEEE1394 Host Controller AMPRO Computers, INC System Explode View Technology Corp / MiTAC 8050D Hardware Specification Technology Corp / MiTAC SERVICE MANUAL FOR 8050D Sponsoring Editor : Jesse Jan Author : Grass Ren Assistant Editor : Ping.Xie Publisher : MiTAC International Corp. Address : 1, R&D Road 2, Hsinchu Science-Based Industrial, Hsinchu, Taiwan, R.O.C. Tel : 886-3-5779250 Fax : 886-3-5781245 First Edition : Mar.2004 E-mail : Willy.Chen @ mic.com.tw Web : http: //www.mitac.com http: //www.mitacservice.com